WEDC W3EG6432S403JD3

W3EG6432S-D3
-JD3
White Electronic Designs
PRELIMINARY*
256MB – 32Mx64 DDR SDRAM UNBUFFERED
FEATURES
DESCRIPTION
Double-data-rate architecture
DDR200, DDR266, DDR333 and DDR400
The W3EG6432S is a 32Mx64 Double Data Rate
SDRAM memory module based on 256Mb DDR SDRAM
components. The module consists of eight 32Mx8 DDR
SDRAMs in 66 pin TSOP packages mounted on a 184
pin FR4 substrate.
• JEDEC design specifications
Bi-directional data strobes (DQS)
Differential clock inputs (CK & CK#)
Programmable Read Latency 2,2.5 (clock)
Programmable Burst Length (2,4,8)
Programmable Burst type (sequential & interleave)
Edge aligned data output, center aligned data input.
Auto and self refresh
Serial presence detect
Power supply:
Synchronous design allows precise cycle control with the
use of system clock. Data I/O transactions are possible on
both edges and Burst Lengths allow the same device to be
useful for a variety of high bandwidth, high performance
memory system applications.
* This product is under development, is not qualified or characterized and is subject to
change without notice.
• VCC = VCCQ = +2.5V ±0.2V (100, 133 and
166MHz)
• VCC = VCCQ = +2.6V ±0.1V (200MHz)
JEDEC standard 184 pin DIMM package
• JD3 PCB height: 30.48 (1.20") max
NOTE: Consult factory for availability of:
• Lead-free products
• Vendor source control option
• Industrial temperature option
OPERATING FREQUENCIES
May 2005
Rev. 6
DDR400 @CL=3
DDR333 @CL=2.5
DDR266 @CL=2
DDR266 @CL=2
DDR266 @CL=2.5
DDR200 @CL=2
Clock Speed
200MHz
166MHz
133MHz
133MHz
133MHz
100MHz
CL-tRCD-tRP
3-3-3
2.5-3-3
2-2-2
2-3-3
2.5-3-3
2-2-2
1
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
W3EG6432S-D3
-JD3
White Electronic Designs
PRELIMINARY
PIN CONFIGURATION
PIN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
May 2005
Rev. 6
SYMBOL
VREF
DQ0
VSS
DQ1
DQS0
DQ2
VCC
DQ3
NC
NC
VSS
DQ8
DQ9
DQS1
VCCQ
CK1
CK1#
VSS
DQ10
DQ11
CKE0
VCCQ
DQ16
DQ17
DQS2
VSS
A9
DQ18
A7
VCCQ
DQ19
A5
DQ24
VSS
DQ25
DQS3
A4
VCC
DQ26
DQ27
A2
VSS
A1
NC
NC
VCC
PIN
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
SYMBOL
NC
A0
NC
VSS
NC
BA1
DQ32
VCCQ
DQ33
DQS4
DQ34
VSS
BA0
DQ35
DQ40
VCCQ
WE#
DQ41
CAS#
VSS
DQS5
DQ42
DQ43
VCC
NC
DQ48
DQ49
VSS
CK2#
CK2
VCCQ
DQS6
DQ50
DQ51
VSS
VCCID
DQ56
DQ57
VCC
DQS7
DQ58
DQ59
VSS
NC
SDA
SCL
PIN
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
SYMBOL
VSS
DQ4
DQ5
VCCQ
DQM0
DQ6
DQ7
VSS
NC
NC
NC
VCCQ
DQ12
DQ13
DQM1
VCC
DQ14
DQ15
NC
VCCQ
NC
DQ20
A12
VSS
DQ21
A11
DQM2
VCC
DQ22
A8
DQ23
VSS
A6
DQ28
DQ29
VCCQ
DQM3
A3
DQ30
VSS
DQ31
NC
NC
VCCQ
CK0
CK0#
PIN NAMES
PIN
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
A0-A12
BA0-BA1
DQ0-DQ63
DQS0-DQS7
CK0, CK1, CK2
CK0#, CK1#, CK2#
CKE0
CS0#
RAS#
CAS#
WE#
DQM0-DQM7
VCC
VCCQ
VSS
VREF
VCCSPD
SDA
SCL
SA0-SA2
VCCID
NC
SYMBOL
VSS
NC
A10
NC
VCCQ
NC
VSS
DQ36
DQ37
VCC
DQM4
DQ38
DQ39
VSS
DQ44
RAS#
DQ45
VCCQ
CS0#
NC
DQM5
VSS
DQ46
DQ47
NC
VCCQ
DQ52
DQ53
NC
VCC
DQM6
DQ54
DQ55
VCCQ
NC
DQ60
DQ61
VSS
DQM7
DQ62
DQ63
VCCQ
SA0
SA1
SA2
VCCSPD
2
Address input (Multiplexed)
Bank Select Address
Data Input/Output
Data Strobe Input/Output
Clock Input
Clock Input
Clock Enable input
Chip Select Input
Row Address Strobe
Column Address Strobe
Write Enable
Data-in-mask
Power Supply
Power Supply for DQS
Ground
Power Supply for Reference
Serial EEPROM Power Supply
Serial data I/O
Serial clock
Address in EEPROM
VCC Indentification Flag
No Connect
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
W3EG6432S-D3
-JD3
White Electronic Designs
PRELIMINARY
FUNCTIONAL BLOCK DIAGRAM
CS0#
DQS0
DQM0
DQS4
DQM4
DM
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
CS#
DQS
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQS1
DM
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
CS#
DQS
DM
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
CS#
DQS
DM
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
CS#
DQS
DM
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
CS#
DQS
DQS5
DQM1
DQM5
DM
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
CS#
DQS
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQS2
DQS6
DQM2
DQM6
DM
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
CS#
DQS
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQS3
DQS7
DQM3
DQM7
DM
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
CS#
DQS
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
RAS#
RAS#: DDR SDRAMs
CAS#
CAS#: DDR SDRAMs
SERIAL PD
BA0-BA1
SCL
WP
BA0-BA1: DDR SDRAMs
WE#
SDA
A0
A1
A2
SA0
SA1
SA2
WE#: DDR SDRAMs
A0-A12
A0-A12: DDR SDRAMs
CKE0
CKE0: DDR SDRAMs
VCCSPD
CLOCK INPUT
SPD
VCCQ
DDR SDRAMs
VCC
DDR SDRAMs
DDR SDRAMs
DDR SDRAMs
CK0, CK0#
2 SDRAMS
VREF
CK1, CK1#
3 SDRAMS
VSS
CK2, CK2#
3 SDRAMS
NOTE: All datalines are terminated through a 22 ohm series resistor.
May 2005
Rev. 6
3
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
W3EG6432S-D3
-JD3
White Electronic Designs
PRELIMINARY
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Value
Units
Voltage on any pin relative to VSS
VIN, VOUT
-0.5 to 3.6
V
Voltage on VCC supply relative to VSS
VCC, VCCQ
-1.0 to 3.6
V
TSTG
-55 to +150
°C
Storage Temperature
Power Dissipation
PD
8
W
Short Circuit Current
IOS
50
mA
Note:
Permanent device damage may occur if ‘ABSOLUTE MAXIMUM RATINGS’ are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability
DC CHARACTERISTICS
0°C ≤ TA ≤ 70°C, VCC = VCCQ = 2.5V ± 0.2V, VCC = VCCQ = 2.6V ± 0.1V (200MHz)
Parameter
Symbol
Min
Max
Unit
Supply Voltage
VCC
2.3
2.7
V
Supply Voltage
VCCQ
2.3
2.7
V
Reference Voltage
VREF
1.15
1.35
V
Termination Voltage
VTT
1.15
1.35
V
Input High Voltage
VIH
VREF + 0.15
VCCQ + 0.3
V
Input Low Voltage
VIL
-0.3
VREF -0.15
V
Output High Voltage
VOH
VTT + 0.76
—
V
Output Low Voltage
VOL
—
VTT-0.76
V
CAPACITANCE
TA = 25°C, f = 1MHz, VCC = VCCQ = 2.5V ± 0.2V, VCC = VCCQ = 2.6V ± 0.1V (200MHz)
Parameter
Symbol
Max
Unit
Input Capacitance (A0-A12)
CIN1
29
pF
Input Capacitance (RAS#,CAS#,WE#)
CIN2
29
pF
Input Capacitance (CKE0, CKE1)
CIN3
29
pF
Input Capacitance (CK0#,CK0)
CIN4
26
pF
Input Capacitance (CS0#, CS1#)
CIN5
29
pF
Input Capacitance (DQM0-DQM8)
CIN6
8
pF
Input Capacitance (BA0-BA1)
CIN7
29
pF
Data input/output capacitance (DQ0-DQ63)(DQS)
COUT
8
pF
May 2005
Rev. 6
4
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
W3EG6432S-D3
-JD3
White Electronic Designs
PRELIMINARY
IDD SPECIFICATIONS AND TEST CONDITIONS
0°C ≤ TA ≤ 70°C, VCC = VCCQ = 2.5V ± 0.2V, VCC = VCCQ = 2.6V ± 0.1V (200MHz)V
Includes DDR SDRAM component only
Parameter
Symbol
Conditions
DDR400@
CL=3
Max
DDR333@
CL=2.5-3-3
Max
DDR266@
CL=2
Max
DDR266@
CL=2.5
Max
DDR200@
CL=2
Max
Units
Operating Current
IDD0
One device bank; Active - Precharge;
tRC=tRC (MIN); tCK=tCK (MIN); DQ,DM
and DQS inputs changing once per
clock cycle; Address and control inputs
changing once every two cycles.
1080
1000
1000
1000
1000
mA
Operating Current
IDD1
One device bank; Active-ReadPrecharge Burst = 2; tRC=tRC (MIN);
tCK=tCK (MIN); lOUT = 0mA; Address
and control inputs changing once per
clock cycle.
1360
1360
1200
1200
1200
mA
Precharge PowerDown Standby
Current
IDD2P
All device banks idle; Power-down
mode; tCK=tCK (MIN); CKE=(low)
32
32
32
32
32
rnA
Idle Standby Current
IDD2F
CS# = High; All device banks idle;
tCK=tCK (MIN); CKE = high; Address
and other control inputs changing once
per clock cycle. VIN = VREF for DQ,
DQS and DM.
480
400
360
360
360
mA
Active Power-Down
Standby Current
IDD3P
One device bank active; Power-Down
mode; tCK (MIN); CKE=(low)
320
240
200
200
200
mA
Active Standby
Current
IDD3N
CS# = High; CKE = High; One device
bank; Active-Precharge; tRC=tRAS
(MAX); tCK=tCK (MIN); DQ, DM and
DQS inputs changing twice per clock
cycle; Address and other control inputs
changing once per clock cycle.
560
480
400
400
400
mA
Operating Current
IDD4R
Burst = 2; Reads; Continuous burst;
One device bank active; Address and
control inputs changing once per clock
cycle; TCK= TCK (MIN); lOUT = 0mA.
1600
1400
1200
1200
1200
mA
Operating Current
IDD4W
Burst = 2; Writes; Continuous burst;
One device bank active; Address and
control inputs changing once per clock
cycle; tCK=tCK (MIN); DQ,DM and DQS
inputs changing once per clock cycle.
1560
1400
1200
1200
1200
rnA
Auto Refresh Current
IDD5
tRC = tRC (MIN)
2080
2040
1880
1880
1880
mA
Self Refresh Current
IDD6
CKE ≤ 0.2V
Operating Current
IDD7A
Four bank interleaving Reads (BL=4)
with auto precharge with tRC=tRC (MIN);
tCK=tCK (MIN); Address and control
inputs change only during Active Read
or Write commands.
May 2005
Rev. 6
5
32
32
32
32
32
mA
3760
3280
2800
2800
2800
mA
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
W3EG6432S-D3
-JD3
White Electronic Designs
PRELIMINARY
DETAILED TEST CONDITIONS FOR DDR SDRAM IDD1 & IDD7A
IDD1 : OPERATING CURRENT : ONE BANK
IDD7A : OPERATING CURRENT : FOUR BANKS
1.
Typical Case : VCC=2.5V, T=25°C
1.
Typical Case : VCC=2.5V, T=25°C
2.
Worst Case : VCC=2.7V, T=10°C
2.
Worst Case : VCC=2.7V, T=10°C
3.
Only one bank is accessed with tRC (min), Burst
Mode, Address and Control inputs on NOP edge
are changing once per clock cycle. IOUT = 0mA
3.
Four banks are being interleaved with tRC (min),
Burst Mode, Address and Control inputs on NOP
edge are not changing. Iout=0mA
4.
Timing Patterns :
4.
Timing Patterns :
•
DDR200 (100 MHz, CL=2) : tCK=10ns, CL2,
BL=4, tRCD=2*tCK, tRAS=5*tCK
Read : A0 N R0 N N P0 N A0 N - repeat the
same timing with random address changing;
50% of data changing at every burst
•
DDR266 (133MHz, CL=2.5) : tCK=7.5ns,
CL=2.5, BL=4, tRCD=3*tCK, tRC=9*tCK, tRAS=5*tCK
Read : A0 N N R0 N P0 N N N A0 N - repeat
the same timing with random address
changing; 50% of data changing at every burst
•
DDR266 (133MHz, CL=2) : tCK=7.5ns, CL=2,
BL=4, tRCD=3*tCK, tRC=9*tCK, tRAS=5*tCK
Read : A0 N N R0 N P0 N N N A0 N - repeat
the same timing with random address
changing; 50% of data changing at every burst
•
DDR333 (166MHz, CL=2.5) : tCK=6ns, BL=4,
tRCD=10*tCK, tRAS=7*tCK
Read : A0 N N R0 N P0 N N N A0 N - repeat
the same timing with random address
changing; 50% of data changing at every burst
•
DDR400 (200MHz, CL=3) : tCK=5ns, BL=4,
tRCD=15*tCK, tRAS=7*tCK
Read : A0 N N R0 N P0 N N N A0 N - repeat
the same timing with random address
changing; 50% of data changing at every burst
Legend:
A = Activate, R = Read, W = Write, P = Precharge, N = NOP
A (0-3) = Activate Bank 0-3
•
DDR200 (100 MHz, CL=2) : tCK=10ns, CL2,
BL=4, tRRD=2*tCK, tRCD=3*tCK, Read with
Autoprecharge
Read : A0 N A1 R0 A2 R1 A3 R2 A0 R3 A1 R0
- repeat the same timing with random address
changing; 100% of data changing at every
burst
•
DDR266 (133MHz, CL=2.5) : tCK=7.5ns,
CL=2.5, BL=4, tRRD=3*tCK, tRCD=3*tCK
Read with Autoprecharge
Read : A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N
A1 R0 - repeat the same timing with random
address changing; 100% of data changing at
every burst
•
DDR266 (133MHz, CL=2) : tCK=7.5ns, CL2=2,
BL=4, tRRD=2*tCK, tRCD=2*tCK
Read : A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N
A1 R0 - repeat the same timing with random
address changing; 100% of data changing at
every burst
•
DDR333 (166MHz, CL=2.5) : tCK=6ns,
BL=4, tRRD=3*tCK, tRCD=3*tCK, Read with
Autoprecharge
Read : A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N
A1 R0 - repeat the same timing with random
address changing; 100% of data changing at
every burst
•
DDR400 (200MHz, CL=3) : tCK=5ns,
BL=4, tRRD=10*tCK, tRCD=15*tCK, Read with
Autoprecharge
Read : A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N
A1 R0 - repeat the same timing with random
address changing; 100% of data changing at
every burst
R (0-3) = Read Bank 0-3
May 2005
Rev. 6
6
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
W3EG6432S-D3
-JD3
White Electronic Designs
PRELIMINARY
DDR SDRAM COMPONENT ELECTRICAL CHARACTERISTICS AND
RECOMMENDED AC OPERATING CONDITIONS
AC CHARACTERISTICS
403
PARAMETER
335
262
263/265
MAX
MIN
MAX
202
SYMBOL
MIN
MAX
MIN
MAX
MIN
Access window of DQs from CK/CK#
tAC
-0.7
+0.7
-0.7
+0.7
-0.75 +0.75 -0.75 +0.75 -0.75 +0.75
MIN
MAX UNITS NOTES
ns
CK high-level width
tCH
0.45
0.55
0.45
0.55
0.45
0.55
0.45
0.55
0.45
0.55
tCK
26
CK low-level width
tCL
0.45
0.55
0.45
0.55
0.45
0.55
0.45
0.55
0.45
0.55
tCK
26
tCK (3)
5
7.5
ns
40, 45
CL = 2.5
tCK (2.5)
6
13
6
13
7.5
13
7.5
13
7.5
13
ns
40, 45
CL = 2
tCK (2)
7.5
13
7.5
13
7.5/10
13
7.5/10
13
7.5/10
13
ns
40, 45
DQ and DM input hold time relative to DQS
tDH
0.4
0.45
0.5
0.5
0.5
ns
23, 27
DQ and DM input setup time relative to DQS
tDS
0.4
0.45
0.5
0.5
0.5
ns
23, 27
DQ and DM input pulse width (for each input)
tDIPW
1.75
1.75
1.75
1.75
1.75
ns
27
Access window of DQS from CK/CK#
tDQSCK
-0.60 +0.60 -0.60 +0.60 -0.75 +0.75 -0.75 +0.75 -0.75 +0.75
ns
tCK
Clock cycle time
CL = 3
DQS input high pulse width
tDQSH
0.35
0.35
0.35
0.35
0.35
DQS input low pulse width
tDQSL
0.35
0.35
0.35
0.35
0.35
DQS-DQ skew, DQS to last DQ valid, per group, per
access
tDQSQ
0.40
1.25
0.75
1.25
tCK
0.2
0.2
0.2
0.2
0.2
tCK
DQS falling edge from CK rising - hold time
tDSH
0.2
0.2
0.2
0.2
0.2
tCK
Half clock period
tHP
Data-out high-impedance window from CK/CK#
tHZ
ns
16, 36
Data-out low-impedance window from CK/CK#
tLZ
-0.70
-0.70
-0.75
-0.75
-0.75
ns
16, 36
Address and control input hold time (fast slew rate)
tIHF
0.6
0.75
0.90
.90
.90
ns
12
Address and control input setup time (fast slew rate)
tISF
0.6
0.75
0.90
.90
.90
ns
12
Address and control input hold time (slow slew rate)
tIHS
0.6
0.80
1
1
1
ns
12
7
+0.70
0.75
22, 23
0.72
tCH,tCL
1.25
ns
tDSS
+0.70
0.75
tCK
0.5
tDQSS
tCH,tCL
1.25
0.5
Write command to first DQS latching transition
tCH,tCL
0.75
0.5
DQS falling edge to CK rising - setup time
May 2005
Rev. 6
1.28
0.45
tCH,tCL
+0.75
tCH,tCL
+0.75
+0.75
ns
30
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
W3EG6432S-D3
-JD3
White Electronic Designs
PRELIMINARY
DDR SDRAM COMPONENT ELECTRICAL CHARACTERISTICS AND
RECOMMENDED AC OPERATING CONDITIONS (continued)
AC CHARACTERISTICS
PARAMETER
403
335
MAX
MIN
262
MAX
MIN
263/265
MAX
MIN
MAX
202
SYMBOL
MIN
Address and control input setup time (slow slew rate)
tISS
0.6
0.80
1
1
MIN
1
MAX UNITS NOTES
ns
Address and Control input pulse width (for each
input)
tIPW
2.2
2.2
2.2
2.2
2.2
ns
LOAD MODE REGISTER command cycle time
tMRD
10
12
15
15
15
ns
DQ-DQS hold, DQS to first DQ to go non-valid, per
access
tQH
tHP
- tQHS
tHP
- tQHS
tHP
- tQHS
tHP
- tQHS
tHP
- tQHS
ns
Data hold skew factor
tQHS
ACTIVE to PRECHARGE command
tRAS
40
ACTIVE to READ with Auto precharge command
tRAP
15
ACTIVE to ACTIVE/AUTO REFRESH command
period
tRC
AUTO REFRESH command period
ACTIVE to READ or WRITE delay
PRECHARGE command period
0.50
70,000
0.55
42
70,000
0.75
0.75
0.75
12
22, 23
ns
40 120,000 40 120,000 40 120,000
ns
15
15
20
20
ns
55
60
60
65
65
ns
tRFC
70
72
75
75
75
ns
tRCD
15
15
15
20
20
ns
31, 48
43
tRP
15
DQS read preamble
tRPRE
0.9
1.1
0.9
1.1
0.9
1.1
0.9
1.1
0.9
1.1
tCK
37
DQS read postamble
tRPST
0.4
0.6
0.4
0.6
0.4
0.6
0.4
0.6
0.4
0.6
tCK
37
15
15
20
20
ns
ACTIVE bank a to ACTIVE bank b command
tRRD
10
12
15
15
15
ns
DQS write preamble
tWPRE
0.25
0.25
0.25
0.25
0.25
tCK
DQS write preamble setup time
tWPRES
0
DQS write postamble
tWPST
0.4
Write recovery time
tWR
15
15
15
15
15
ns
Internal WRITE to READ command delay
tWTR
2
1
1
1
1
tCK
Data valid output window
na
REFRESH to REFRESH command
tREFC
Average periodic refresh interval
tREFI
Terminating voltage delay to VCC
tVTD
0
0.6
tQH - tDQSQ
0.4
tQH - tDQSQ
70.3
0.4
0.4
0.4
7.8
0
0.6
tQH - tDQSQ
70.3
7.8
0
0
0.6
tQH - tDQSQ
70.3
7.8
0
0
0.6
tQH - tDQSQ
70.3
7.8
0
0
0.6
0
ns
18, 19
tCK
17
ns
22
70.3
µs
21
7.8
µs
21
ns
Exit SELF REFRESH to non-READ command
tXSNR
70
75
75
75
75
ns
Exit SELF REFRESH to READ command
tXSRD
200
200
200
200
200
tCK
May 2005
Rev. 6
8
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
White Electronic Designs
W3EG6432S-D3
-JD3
PRELIMINARY
Notes
1.
All voltages referenced to VSS.
2.
Tests for AC timing, IDD, and electrical AC and DC characteristics may
be conducted at nominal reference/supply voltage levels, but the related
specifications and device operation are guaranteed for the full voltage range
specified.
3.
Outputs measured with equivalent load:
16.
17.
VTT
Output
(VOUT)
18.
50Ω
Reference
Point
30pF
19.
20.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
15.
AC timing and IDD tests may use a VIL-to-VIH swing of up to 1.5V in the test
environment, but input timing is still referenced to VREF (or to the crossing point
for CK/CK#), and parameter specifications are guaranteed for the specified AC
input levels under normal use conditions. The mini-mum slew rate for the input
signals used to test the device is 1V/ns in the range between VIL (AC) and VIH
(AC).
The AC and DC input level specifications are as defined in the SSTL_2 Standard
(i.e., the receiver will effectively switch as a result of the signal crossing the AC
input level, and will remain in that state as long as the signal does not ring back
above [below] the DC input LOW [HIGH] level).
VREF is expected to equal VCCQ/2 of the transmitting device and to track variations
in the DC level of the same. Peak-to-peak noise (non-common mode) on VREF
may not exceed ±2 percent of the DC value. Thus, from VCCQ/2, VREF is allowed
±25mV for DC error and an additional ±25mV for AC noise. This measurement is
to be taken at the nearest VREF bypass capacitor.
VTT is not applied directly to the device. VTT is a system supply for signal
termination resistors, is expected to be set equal to VREF and must track
variations in the DC level of VREF.
IDD is dependent on output loading and cycle rates. Specified values are obtained
with mini-mum cycle time at CL = 2 for 262, and 262, CL = 2.5 for 335 and 265,
CL = for 403 with the outputs open.
Enables on-chip refresh and address counters.
IDD specifications are tested after the device is properly initialized, and is
averaged at the defined cycle rate.
This parameter is sampled. VCC = +2.5V ±0.2V, VCCQ = +2.5V ±0.2V, VREF = VSS,
f = 100 MHz, TA = 25°C, VOUT (DC) = VCCQ/2, VOUT (peak to peak) = 0.2V. DM
input is grouped with I/O pins, reflecting the fact that they are matched in loading.
For slew rates less than 1 V/ns and greater than or equal to 0.5 V/ns. If slew rate
is less than 0.5 V/ns, timing must be derated: tIS has an additional 50ps per each
100mV/ns reduction in slew rate from 500mV/ns, while tIH is unaffected. If slew
rate exceeds 4.5V/ns, functionality is uncertain.
The CK/CK# input reference level (for timing referenced to CK/CK#) is the point
at which CK and CK# cross; the input reference level for signals other than
CK/CK# is VREF.
Inputs are not recognized as valid until VREF stabilizes. Exception: during the
period before VREF stabilizes, CKE < 0.3 x VCCQ is recognized as LOW.
The output timing reference level, as measured at the timing reference point
indicated in Note 3, is VTT.
May 2005
Rev. 6
21.
22.
23.
24.
25.
26.
27.
28.
29.
30.
31.
32.
9
tHZ and tLZ transitions occur in the same access time windows as valid data
transitions. These parameters are not referenced to a specific voltage level, but
specify when the device output is no longer driving (HZ) or begins driving (LZ).
The intent of the Don’t Care state after completion of the postamble is the DQSdriven signal should either be high, low, or high-Z and that any signal transition
within the input switching region must follow valid input requirements. That is, if
DQS transitions high [above VIHDC (MIN)] then it must not transition low (below
VIHDC) prior to tDQSH (MIN).
This is not a device limit. The device will operate with a negative value, but
system performance could be degraded due to bus turnaround.
It is recommended that DQS be valid (HIGH or LOW) on or before the WRITE
command. The case shown (DQS going from High-Z to logic LOW) applies when
no WRITEs were previously in progress on the bus. If a previous WRITE was in
progress, DQS could be HIGH during this time, depending on tDQSS.
MIN (tRC or tRFC) for IDD measurements is the smallest multiple of tCK that meets
the minimum absolute value for the respective parameter. tRAS (MAX) for IDD
measurements is the largest multiple of tCK that meets the maximum absolute
value for tRAS.
The refresh period is 64ms. This equates to an average refresh rate of 7.8125µs.
However, an AUTO REFRESH command must be asserted at least once every
70.3µs; burst refreshing or posting by the DRAM controller greater than eight
refresh cycles is not allowed.
The valid data window is derived by achieving other specifications: tHP (tCK/2),
tDQSQ, and tQH (tQH = tHP - tQHS). The data valid window derates directly
porportional with the clock duty cycle and a practical data valid window can be
derived. The clock is allowed a maximum duty cycle variation of 45/55, beyond
which functionality is uncertain.
Each byte lane has a corresponding DQS: x8 = DQS with DQ0-DQ7.
This limit is actually a nominal value and does not result in a fail value. CKE is
HIGH during REFRESH command period (tRFC [MIN]) else CKE is LOW (i.e.,
during standby).
To maintain a valid level, the transitioning edge of the input must:
a. Sustain a constant slew rate from the current AC level through to the target
AC level, VIL (AC) or VIH (AC).
b. Reach at least the target AC level.
c. After the AC target level is reached, continue to maintain at least the target DC
level, VIL (DC) or VIH (DC).
JEDEC specifies CK and CK# input slew rate must be ≥ 1V/ns (2V/ns if
measured differentially).
DQ and DM input slew rates must not deviate from DQS by more than 10
percent. If the DQ/ DM/DQS slew rate is less than 0.5V/ns, timing must be
derated: 50ps must be added to tDS and tDH for each 100mv/ns reduction in slew
rate. If slew rate exceeds 4V/ns, functionality is uncertain.
VCC must not vary more than 4 percent if CKE is not active while any bank is
active.
The clock is allowed up to ±150ps of jitter. Each timing parameter is allowed to
vary by the same amount.
tHP min is the lesser of tCL minimum and tCH minimum actually applied to the
device CK and CK# inputs, collectively during bank active.
READs and WRITEs with auto precharge are not allowed to be issued until tRAS
(MIN) can be satisfied prior to the internal precharge command being issued.
Any positive glitch in the nominal voltage must be less than 1/3 of the clock and
not more than +400mV or 2.9V, whichever is less. Any negative glitch must be
less than 1/3 of the clock cycle and not exceed either 300mV or 2.2V, whichever
is more positive. However, the DC average cannot be below 2.3V minimum.
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
White Electronic Designs
W3EG6432S-D3
-JD3
PRELIMINARY
33.
34.
35.
36.
37.
38.
39.
40.
41.
42.
The voltage levels used are derived from a mini-mum VCC level and the
referenced test load. In practice, the voltage levels obtained from a properly
terminated bus will provide significantly different voltage values.
VIH overshoot: VIH (MAX) = VCCQ + 1.5V for a pulse width ≤ 3ns and the pulse
width can not be greater than 1/3 of the cycle rate. VIL undershoot: VIL (MIN) =
-1.5V for a pulse width ≤ 3ns and the pulse width can not be greater than 1/3 of
the cycle rate.
VCC and VCCQ must track each other.
tHZ (MAX) takes precedence over tDQSCK (MAX) + tRPST (MAX) condition. tLZ (MIN)
will prevail over tDQSCK (MIN) + tRPRE (MAX) condition.
tRPST end point and tRPRE begin point are not referenced to a specific voltage level
but specify when the device output is no longer driving (tRPST), or begins driving
(tRPRE).
During initialization, VCCQ, VTT, and VREF must be equal to or less than VCC +
0.3V. Alternatively, VTT may be 1.35V maximum during power up, even if VCC/
VCCQ are 0V, provided a minimum of 42Ω of series resistance is used between
the VTT supply and the input pin.
For 403, 335, 262, 263 and 265 speed grades, IDD3N is specified to be 35mA per
DDR SDRAM at 100 MHz.
The current part operates below the slowest JEDEC operating frequency of
83 MHz. As such, future die may not reflect this option.
May 2005
Rev. 6
43.
44.
45.
46.
47.
48.
10
Random addressing changing and 50 percent of data changing at every transfer.
Random addressing changing and 100 percent of data changing at every
transfer.
CKE must be active (high) during the entire time a refresh command is executed.
That is, from the time the AUTO REFRESH command is registered, CKE must be
active at each rising clock edge, until tREF has been satisfied.
IDD2N specifies the DQ, DQS, and DM to be driven to a valid high or low logic
level. IDD2Q is similar to IDD2F except IDD2Q specifies the address and control inputs
to remain stable. Although IDD2F, IDD2N, and IDD2Q are similar, IDD2F is “worst case.”
Whenever the operating frequency is altered, not including jitter, the DLL is
required to be reset. This is followed by 200 clock cycles.
Leakage number reflects the worst case leakage possible through the module
pin, not what each memory device contributes.
When an input signal is HIGH or LOW, it is defined as a steady state logic HIGH
or logic LOW.
The 403 speed grade will operate with tRAS (MIN) = 40ns and tRAS (MAX) =
120,000ns at any slower frequency.
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
W3EG6432S-D3
-JD3
White Electronic Designs
PRELIMINARY
ORDERING INFORMATION FOR JD3
Part Number
Speed
CAS Latency
tRCD
tRP
Height*
Temperature
W3EG6432S403JD3
200MHz/400Mb/s
3
3
3
30.48 (1.20")
0°C to 70°C
W3EG6432S335JD3
166MHz/333Mb/s
2.5
3
3
30.48 (1.20")
0°C to 70°C
W3EG6432S262JD3
133MHz/266Mb/s
2
2
2
30.48 (1.20")
0°C to 70°C
W3EG6432S263JD3
133MHz/266Mb/s
2
3
3
30.48 (1.20")
0°C to 70°C
W3EG6432S265JD3
133MHz/266Mb/s
2.5
3
3
30.48 (1.20")
0°C to 70°C
W3EG6432S202JD3
100MHz/200Mb/s
2
2
2
30.48 (1.20")
0°C to 70°C
NOTE:
1
* Consult Factory for availability of lead-free products. (F = Lead-Free, G = RoHS Compliant)
2
* Product specific part numbers are available for source control if needed, please consult factory for the correct part number if a specific component vendor is preferred.
3
* Consult factory for availability for industrial temperature (-40°C to 85°C) options
PACKAGE DIMENSIONS FOR JD3
133.48
(5.255" MAX.)
131.34
(5.171")
128.95
(5.077")
2.54
(0.100 MAX)
3.99
(0.157 (2x))
30.48
(1.20)
MAX
17.78
(0.700)
10.01
(0.394)
6.35
(0.250)
64.77
(2.550)
6.35
(0.250)
49.53
(1.950)
1.27
(0.050 TYP.)
1.78
(0.070)
3.99
(0.157)
(MIN)
2.31
(0.091)
(2x)
3.00
(0.118)
(4x)
1.27 ± 0.10
(0.050 ± 0.004)
* ALL DIMENSIONS ARE IN MILLIMETERS AND (INCHES)
May 2005
Rev. 6
11
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
W3EG6432S-D3
-JD3
White Electronic Designs
PRELIMINARY
ORDERING INFORMATION FOR D3
Part Number
Speed
CAS Latency
tRCD
tRP
Height*
Temperature
W3EG6432S403D3
200MHz/400Mb/s
3
3
3
30.48 (1.20")
0°C to 70°C
W3EG6432S335D3
166MHz/333Mb/s
2.5
3
3
30.48 (1.20")
0°C to 70°C
W3EG6432S262D3
133MHz/266Mb/s
2
2
2
30.48 (1.20")
0°C to 70°C
W3EG6432S263D3
133MHz/266Mb/s
2
3
3
30.48 (1.20")
0°C to 70°C
W3EG6432S265D3
133MHz/266Mb/s
2.5
3
3
30.48 (1.20")
0°C to 70°C
W3EG6432S202D3
100MHz/200Mb/s
2
2
2
30.48 (1.20")
0°C to 70°C
NOTE:
1
* Consult Factory for availability of lead-free products. (F = Lead-Free, G = RoHS Compliant)
2
* Product specific part numbers are available for source control if needed, please consult factory for the correct part number if a specific component vendor is preferred.
3
* Consult factory for availability for industrial temperature (-40°C to 85°C) options
PACKAGE DIMENSIONS FOR D3
133.48
(5.255" MAX.)
131.34
(5.171")
128.95
(5.077")
2.54
(0.100 MAX)
3.99
(0.157 (2x))
30.48
(1.20)
MAX
17.78
(0.700)
10.01
(0.394)
6.35
(0.250)
64.77
(2.550)
6.35
(0.250)
49.53
(1.950)
1.27
(0.050 TYP.)
1.78
(0.070)
3.99
(0.157)
(MIN)
2.31
(0.091)
(2x)
3.00
(0.118)
(4x)
1.27 ± 0.10
(0.050 ± 0.004)
* ALL DIMENSIONS ARE IN MILLIMETERS AND (INCHES)
May 2005
Rev. 6
12
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
W3EG6432S-D3
-JD3
White Electronic Designs
PRELIMINARY
Document Title
256MB – 32Mx64 DDR SDRAM UNBUFFERED
Revision History
Rev #
History
Release Date
Status
Rev 0
Initial Release
3-18-02
Advanced
Rev 1
Added DDR333
1-30-03
Advanced
Rev 2
2.1 Added document title page
4-14-04
Preliminary
Rev 3
Removed "ED" from part number
8-04
Preliminary
Rev 4
Corrected "MO" device count
9-04
Preliminary
Rev 5
5.1 Added DDR400
12-04
Preliminary
5-05
Preliminary
5.2 Added lead-free and RoHS compliant notes.
Rev 6
6.1 Added JEDEC standard PCB
6.2 D3 option "NOT RECOMMENDED FOR NEW DESIGNS"
May 2005
Rev. 6
13
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com