E2G0014-17-41 ¡ Semiconductor MSM511664C/CL ¡ Semiconductor This version: Jan. 1998 MSM511664C/CL Previous version: May 1997 65,536-Word ¥ 16-Bit DYNAMIC RAM : FAST PAGE MODE TYPE (BYTE WRITE) DESCRIPTION The MSM511664C/CL is a 65,536-word ¥ 16-bit dynamic RAM fabricated in Oki's silicon-gate CMOS technology. The MSM511664C/CL achieves high integration, high-speed operation, and low-power consumption because Oki manufactures the device in a quadruple-layer polysilicon/single-layer metal CMOS process. The MSM511664C/CL is available in a 40-pin plastic SOJ or 44/40-pin plastic TSOP. The MSM511664CL (the low-power version) is specially designed for lower-power applications. FEATURES • 65,536-word ¥ 16-bit configuration • Single 5 V power supply, ±10% tolerance • Input : TTL compatible, low input capacitance • Output : TTL compatible, 3-state • Refresh : 256 cycles/4 ms, 256 cycles/32 ms (L-version) • Byte write and fast page mode, read modify write capability • CAS before RAS refresh, hidden refresh, RAS-only refresh capability • Package options: 40-pin 400 mil plastic SOJ (SOJ40-P-400-1.27) (Product : MSM511664C/CL-xxJS) 44/40-pin 400 mil plastic TSOP (TSOPII44/40-P-400-0.80-K) (Product : MSM511664C/CL-xxTS-K) xx indicates speed rank. PRODUCT FAMILY Family Access Time (Max.) tRAC tAA tCAC tOEA Cycle Time Power Dissipation (Min.) Operating (Max.) Standby (Max.) MSM511664C/CL-60 60 ns 30 ns 20 ns 20 ns 110 ns 550 mW MSM511664C/CL-70 70 ns 40 ns 25 ns 25 ns 120 ns 495 mW MSM511664C/CL-80 80 ns 45 ns 30 ns 30 ns 135 ns 440 mW 5.5 mW/ 1.1 mW (L-version) 1/16 ¡ Semiconductor MSM511664C/CL PIN CONFIGURATION (TOP VIEW) VCC 1 40 VSS DQ1 2 39 DQ16 DQ2 3 38 DQ15 DQ3 4 37 DQ14 DQ4 5 36 DQ13 DQ5 6 35 DQ12 DQ6 7 34 DQ11 DQ7 8 33 DQ10 DQ8 9 32 DQ9 NC 10 31 NC VCC 11 30 VSS UWE 12 29 CAS LWE 13 28 OE RAS 14 27 NC A0 15 26 NC A1 16 25 NC A2 17 24 A7 A3 18 23 A6 A4 19 22 A5 VCC 20 21 VSS VCC DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 NC 1 2 3 4 5 6 7 8 9 10 44 43 42 41 40 39 38 37 36 35 VSS DQ16 DQ15 DQ14 DQ13 DQ12 DQ11 DQ10 DQ9 NC VCC UWE LWE RAS A0 A1 A2 A3 A4 VCC 13 14 15 16 17 18 19 20 21 22 32 31 30 29 28 27 26 25 24 23 VSS CAS OE NC NC NC A7 A6 A5 VSS 44/40-Pin Plastic TSOP (K Type) 40-Pin Plastic SOJ Pin Name A0 - A7 RAS Row Address Strobe CAS Column Address Strobe DQ1 - DQ16 Data Input/Data Output OE LWE Note : Function Address Input Output Enable Lower Byte Write Enable UWE Upper Byte Write Enable VCC Power Supply (5 V) VSS Ground (0 V) NC No Connection The same power supply voltage must be provided to every VCC pin, and the same GND voltage level must be provided to every VSS pin. 2/16 ¡ Semiconductor MSM511664C/CL BLOCK DIAGRAM Timing Generator RAS Timing Generator CAS Column Address Buffers 8 8 UWE LWE Write Clock Generator Column Decoders OE 16 Internal Address Counter A0 - A7 Refresh Control Clock Sense Amplifiers 16 I/O Selector Row Address Buffers Row Decoders 8 Word Drivers 16 16 16 16 8 Output Buffers Input Buffers DQ1 - DQ16 16 Memory Cells VCC On Chip VBB Generator VSS FUNCTION TABLE Input Pin DQ Pin Function Mode RAS CAS LWE UWE OE DQ1 - DQ8 DQ9 - DQ16 H * H * * * High-Z High-Z Standby L High-Z Refresh L L * L High-Z DOUT DOUT Word Read Lower Byte Write * H * H L L L H H DIN L L H L H Don't Care Don't Care DIN DIN Word Write High-Z — L L L L H DIN L L H H H High-Z Upper Byte Write *: "H" or "L" 3/16 ¡ Semiconductor MSM511664C/CL ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings Parameter Symbol Rating Unit VT –1.0 to 7.0 V Short Circuit Output Current IOS 50 mA Power Dissipation PD* 1 W Operating Temperature Topr 0 to 70 °C Storage Temperature Tstg –55 to 150 °C Voltage on Any Pin Relative to VSS *: Ta = 25°C Recommended Operating Conditions Parameter Power Supply Voltage (Ta = 0°C to 70°C) Symbol Min. Typ. Max. Unit VCC 4.5 5.0 5.5 V VSS 0 0 0 V Input High Voltage VIH 2.4 — 6.5 V Input Low Voltage VIL –1.0 — 0.8 V Capacitance Parameter Input Capacitance (A0 - A7) Input Capacitance (RAS, CAS, UWE, LWE, OE) Output Capacitance (DQ1 - DQ16) (VCC = 5 V ±10%, Ta = 25°C, f = 1 MHz) Symbol Typ. Max. Unit CIN1 — 7 pF CIN2 — 7 pF CI/O — 7 pF 4/16 ¡ Semiconductor MSM511664C/CL DC Characteristics Parameter (VCC = 5 V ±10%, Ta = 0°C to 70°C) Symbol Condition MSM511664 MSM511664 MSM511664 C/CL-70 C/CL-60 C/CL-80 Unit Note Min. Max. Min. Max. Min. Max. Output High Voltage VOH IOH = –2.5 mA 2.4 VCC 2.4 VCC 2.4 VCC V Output Low Voltage VOL IOL = 2.1 mA 0 0.4 0 0.4 0 0.4 V –10 10 –10 10 –10 10 mA –10 10 –10 10 –10 10 mA — 100 — 90 — 80 mA 1, 2 — 2 — 2 — 2 — 1 — 1 — 1 — 200 — 200 — — 100 — 90 — 5 — — 100 — — 0 V £ VI £ 6.5 V; Input Leakage Current ILI All other pins not under test = 0 V Output Leakage Current ILO Average Power Supply Current ICC1 (Operating) 0 V £ VO £ 5.5 V RAS, CAS cycling, tRC = Min. RAS, CAS = VIH Power Supply Current (Standby) ICC2 RAS, CAS ≥ VCC –0.2 V mA 1 200 mA 1, 5 — 80 mA 1, 2 5 — 5 mA — 90 — 80 mA 1, 2 95 — 85 — 75 mA 1, 3 300 — 300 — 300 mA RAS cycling, Average Power ICC3 CAS = VIH, Supply Current (RAS-only Refresh) tRC = Min. RAS = VIH, Power Supply Current (Standby) ICC5 CAS = VIL, Supply Current ICC6 (CAS before RAS Refresh) 1 DQ = enable Average Power RAS cycling, CAS before RAS RAS = VIL, Average Power ICC7 CAS cycling, Supply Current (Fast Page Mode) tPC = Min. tRC = 125 ms, Average Power ICC10 CAS before RAS, Supply Current (Battery Backup) Notes : 1. 2. 3. 4. 5. DQ disable tRAS £ 1 ms 1, 4, 5 ICC Max. is specified as ICC for output open condition. The address can be changed once or less while RAS = VIL. The address can be changed once or less while CAS = VIH. VCC – 0.2 V £ VIH £ 6.5 V, –1.0 V £ VIL £ 0.2 V. L-version. 5/16 ¡ Semiconductor MSM511664C/CL AC Characteristics (1/2) (VCC = 5 V ±10%, Ta = 0°C to 70°C) Note 1, 2, 3 Parameter MSM511664 MSM511664 MSM511664 C/CL-60 C/CL-70 C/CL-80 Symbol Unit Note Min. Max. Min. Max. Min. Max. tRC 110 — 120 — 135 — ns tRWC — — 170 — tPC 155 40 50 — 185 55 — — ns ns tPRWC 85 — 95 — 100 — ns Access Time from RAS tRAC — 60 — 70 — 80 ns 4, 5, 6 Access Time from CAS tCAC — 20 — 25 — 30 ns 4, 5 Access Time from Column Address Access Time from CAS Precharge tAA tCPA — — 30 35 — — 40 45 — — 45 50 ns ns 4, 6 4 Access Time from OE Output Low Impedance Time from CAS tOEA tCLZ — 0 20 — — 0 25 — — 0 30 — ns ns 4 4 CAS to Data Output Buffer Turn-off Delay Time tOFF 20 15 50 4 0 0 3 — 15 50 4 ns ns ns ms 7 15 50 4 0 0 3 — 20 tOEZ tT tREF 0 0 3 — 20 OE to Data Output Buffer Turn-off Delay Time Transition Time Refresh Period Refresh Period (L-version) tREF — 32 — 32 — 32 ms RAS Precharge Time tRP 40 — 40 — 45 — ns RAS Pulse Width tRAS 60 10,000 70 10,000 80 10,000 ns RAS Pulse Width (Fast Page Mode) tRASP 60 100,000 70 100,000 80 100,000 ns RAS Hold Time tRSH RAS Hold Time referenced to OE tROH 20 15 — — 25 15 — — 30 15 — — ns ns CAS Precharge Time (Fast Page Mode) tCP 10 — 10 — 10 — ns CAS Pulse Width tCAS 20 10,000 25 10,000 30 10,000 ns CAS Hold Time tCSH 60 — 80 — tCRP 5 — 70 5 — CAS to RAS Precharge Time — 5 — ns ns RAS Hold Time from CAS Precharge tRHCP RAS to CAS Delay Time tRCD 35 20 — 40 45 20 — 45 50 22 — 50 ns ns 5 RAS to Column Address Delay Time tRAD 15 30 15 30 17 35 ns 6 Random Read or Write Cycle Time Read Modify Write Cycle Time Fast Page Mode Cycle Time Fast Page Mode Read Modify Write Cycle Time 7 3 Row Address Set-up Time tASR 0 — 0 — 0 — ns Row Address Hold Time tRAH 10 — 10 — 12 — ns Column Address Set-up Time tASC 0 — 0 — 0 — ns Column Address Hold Time tCAH 10 — 10 — 15 — ns Column Address Hold Time from RAS Column Address to RAS Lead Time tAR tRAL 45 30 — — 45 40 — — 55 45 — — ns ns Read Command Set-up Time tRCS 0 — 0 — 0 — ns Read Command Hold Time tRCH 0 — 0 — 0 — ns 8 Read Command Hold Time referenced to RAS tRRH 0 — 0 — 0 — ns 8 6/16 ¡ Semiconductor MSM511664C/CL AC Characteristics (2/2) (VCC = 5 V ±10%, Ta = 0°C to 70°C) Note 1, 2, 3 Parameter Symbol MSM511664 MSM511664 MSM511664 C/CL-60 C/CL-70 C/CL-80 Unit Note Min. Max. Min. Max. Min. Max. Write Command Set-up Time tWCS 0 — 0 — 0 — ns Write Command Hold Time Write Command Hold Time from RAS tWCH tWCR 10 40 — — 10 45 — — 15 55 — — ns ns Write Command Pulse Width OE Command Hold Time tWP tOEH Write Command to RAS Lead Time Write Command to CAS Lead Time tRWL tCWL 10 10 20 20 — — — — — — 15 10 20 — 20 — — — — ns ns ns — 10 10 20 20 tDS 0 — 0 — 0 — ns 10 tDH — — — — — — 10 45 15 50 60 95 — — — — — — 15 55 15 55 70 ns ns ns ns ns ns 10 105 — — — — — — 9 Data-in Set-up Time Data-in Hold Time from RAS OE to Data-in Delay Time CAS to WE Delay Time Column Address to WE Delay Time tDHR tOED tCWD tAWD RAS to WE Delay Time tRWD 10 40 15 40 50 80 CAS Precharge WE Delay Time Data-in Hold Time 9 ns tCPWD 55 — 70 — 75 — ns CAS Active Delay Time from RAS Precharge tRPC 0 — 0 — 0 — ns RAS to CAS Set-up Time (CAS before RAS) RAS to CAS Hold Time (CAS before RAS) tCSR tCHR 5 10 — — 5 10 — — 5 10 — — ns ns 9 9 9 7/16 ¡ Semiconductor Notes: MSM511664C/CL 1. A start-up delay of 100 µs is required after power-up, followed by a minimum of eight initialization cycles (RAS-only refresh or CAS before RAS refresh) before proper device operation is achieved. 2. The AC characteristics assume tT = 5 ns. 3. VIH (Min.) and VIL (Max.) are reference levels for measuring input timing signals. Transition times (tT) are measured between VIH and VIL. 4. This parameter is measured with a load circuit equivalent to 1 TTL load and 50 pF. 5. Operation within the tRCD (Max.) limit ensures that tRAC (Max.) can be met. tRCD (Max.) is specified as a reference point only. If tRCD is greater than the specified tRCD (Max.) limit, then the access time is controlled by tCAC. 6. Operation within the tRAD (Max.) limit ensures that tRAC (Max.) can be met. tRAD (Max.) is specified as a reference point only. If tRAD is greater than the specified tRAD (Max.) limit, then the access time is controlled by tAA. 7. tOFF (Max.) and tOEZ (Max.) define the time at which the output achieves the open circuit condition and are not referenced to output voltage levels. 8. tRCH or tRRH must be satisfied for a read cycle. 9. tWCS, tCWD, tRWD, tAWD and tCPWD are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only. If tWCS ≥ tWCS (Min.), then the cycle is an early write cycle and the data out will remain open circuit (high impedance) throughout the entire cycle. If tCWD ≥ tCWD (Min.) , tRWD ≥ tRWD (Min.), tAWD ≥ tAWD (Min.) and tCPWD ≥ tCPWD (Min.), then the cycle is a read modify write cycle and data out will contain data read from the selected cell; if neither of the above sets of conditions is satisfied, then the condition of the data out (at access time) is indeterminate. 10. These parameters are referenced to the CAS leading edge in an early write cycle, and to the WE leading edge in an OE control write cycle, or a read modify write cycle. 8/16 E2G0092-17-41E ¡ Semiconductor MSM511664C/CL , ,, , ,,,, TIMING WAVEFORM Read Cycle tRC tRP tRAS RAS VIH – VIL – tAR tCSH tCRP tRCD VIH – CAS VIL – VIH – VIL – tRSH tCAS tRAD tASR Address tCRP tRAH tASC tRAL tCAH Column Row tRCS WE OE VIH – VIL – tAA tROH tOEA VIH – VIL – tCAC tRAC DQ tRCH tRRH VOH – tOEZ Open VOL – tOFF Valid Data-out tCLZ "H" or "L" Write Cycle (Early Write) tRC tRP tRAS RAS VIH – VIL – tAR tCRP CAS VIH – VIL – WE VIH – VIL – tCSH tRCD tRSH tCAS tRAD tRAH tASR Address tCRP tASC Row tCAH Column tWCS tWCH VIH – tRWL VIH – VIL – tDS DQ tCWL tWP VIL – tWCR OE tRAL VIH – VIL – tDHR tDH Valid Data-in Open "H" or "L" 9/16 , ,, ¡ Semiconductor MSM511664C/CL Read Modify Write Cycle tRWC tRAS RAS VIH – VIL – tRP tAR tCRP tCSH tCRP tRCD tRSH tCAS VIH – CAS VIL – tASR VIH – Address VIL – WE VIH – VIL – OE VIH – VIL – tRAH tASC tCAH Column Row tRAD tRWD tAA tAWD tRCS tOEA tOED tCAC tRAC DQ VI/OH– VI/OL– tCWL tRWL tWP tCWD tCLZ tOEZ Valid Data-out tOEH tDS tDH Valid Data-in "H" or "L" 10/16 ,,, , ,,, ¡ Semiconductor MSM511664C/CL Fast Page Mode Read Cycle tRASP VIH – RAS V – IL VIH – CAS VIL – Address WE VIH – VIL – tRP tAR tCRP tRHCP tPC tRCD tCP tASR tCP tCAS tCAS tRAD tRAH tASC tCSH tCAH tASC Column Row VIH – VIL – tCAC VOH – DQ VOL – Column tRCS tRCH tRRH tCPA tOEA tOFF tOEZ tRCH tAA tAA tCAC tOEA tOFF tCAC tOEZ tCLZ Valid Data-out tCLZ tRCS tCPA tOEA tRAC tRAL tCAH tASC Column tAA VIH – OE VIL – tCAS tCAH tRCH tRCS tCRP tRSH tCLZ tOFF tOEZ Valid Data-out Valid Data-out "H" or "L" Fast Page Mode Write Cycle (Early Write) tRASP tAR VIH – RAS V – IL tCRP VIH – CAS VIL – Address VIH – VIL – tRAH tASC Row tWCS tDS VIH – VIL – tCSH tCAH Column tCWL tWCH tWP tRAD tRHCP tRSH tRCD VIH – WE VIL – DQ tPC tCAS tASR tRP tWCR tDH Valid Data-in tDHR tCP tCRP tCP tCAS tASC tCAH tASC Column tCWL tWCS tWCH tWP tDS tDH Valid Data-in tCAS tCAH tRAL Column tRWL tCWL tWCS tWCH tWP tDS tDH Valid Data-in Note: OE = "H" or "L" "H" or "L" 11/16 ¡ Semiconductor MSM511664C/CL ,,, , ,, , Fast Page Mode Read Modify Write Cycle tRASP VIH – RAS VIL – tAR tRP tCSH tPRWC tRCD VIH – CAS VIL – tASC tCAH tRAH VIH – VIL – tCRP tCAS tASC tCAH tCAH Column Column tASC Column Row tRCS tCPWD tCWD tRWD tCWD tRCS V WE IH – VIL – tCWL tAWD tCWL tWP tDH VI/OH– VI/OL – Out tCLZ tOEA tOED tOEZ tCAC In tDH tDS tOEA tOEZ tCAC tWP tCPA tAA tOED VIH – OE V – IL tCWL tROH tWP tDH tDS tOEA tRWL tAWD tCPA tAA tAA tRAL tRCS tCPWD tCWD tAWD tDS tRAC DQ tCP tCAS tRAD tASR Address tCP tCAS tRSH Out tOED In tCLZ tOEZ tCAC Out In tCLZ "H" or "L" RAS-Only Refresh Cycle tRC RAS VIL – CAS Address VIH – VIL – VIH – VIL – tRP tRAS VIH – tCRP tASR tRPC tRAH Row tOFF DQ VOH – VOL – Open Note: WE, OE = "H" or "L" "H" or "L" 12/16 ,, , ,, ¡ Semiconductor MSM511664C/CL CAS before RAS Refresh Cycle tRC tRP RAS VIH – VIL – DQ tRP tRPC tRPC tCSR tCP CAS tRAS VIH – VIL – tCHR tOFF VOH – VOL – Open Note: WE, OE, Address = "H" or "L" "H" or "L" Hidden Refresh Read Cycle tRC tRAS RAS VIH – tRP tAR VIH – VIL – VIH – VIL – tRSH tRCD tRAD tASC tRAH tASR Address tRAS tRP VIL – tCRP CAS tRC Row tCHR tCAH Column tRCS tRAL VIH – WE V IL – tRRH tAA tROH tOEA VIH – OE V IL – tRAC DQ VOH – VOL – tCAC tCLZ tOFF tOEZ Valid Data-out "H" or "L" 13/16 , ,, , ¡ Semiconductor MSM511664C/CL Hidden Refresh Write Cycle tRC tRP tRAS RAS VIH – tRP tAR VIH – VIH – VIL – tRSH tRCD tRAD tASC tRAH VIL – tASR Address tRAS VIL – tCRP CAS tRC tCHR tCAH t RAL Column Row tWCS VIH – WE V IL – tWCH tWP tWCR VIH – OE V IL – tDS V – DQ IH VIL – tDH Valid Data-in tDHR "H" or "L" 14/16 ¡ Semiconductor MSM511664C/CL PACKAGE DIMENSIONS (Unit : mm) SOJ40-P-400-1.27 Mirror finish Package material Lead frame material Pin treatment Solder plate thickness Package weight (g) Epoxy resin 42 alloy Solder plating 5 mm or more 1.70 TYP. Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). 15/16 ¡ Semiconductor MSM511664C/CL (Unit : mm) TSOPII44/40-P-400-0.80-K Mirror finish Package material Lead frame material Pin treatment Solder plate thickness Package weight (g) Epoxy resin 42 alloy Solder plating 5 mm or more 0.49 TYP. Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). 16/16