OKI MSM512200L-80SJ

E2G0017-17-42
¡ Semiconductor
MSM512200/L
¡ Semiconductor
This version:
Jan. 1998
MSM512200/L
Previous version: May 1997
1,048,576-Word ¥ 2-Bit DYNAMIC RAM : FAST PAGE MODE TYPE
DESCRIPTION
The MSM512200/L is a 1,048,576-word ¥ 2-bit dynamic RAM fabricated in Oki's silicon-gate CMOS
technology. The MSM512200/L achieves high integration, high-speed operation, and low-power
consumption because Oki manufactures the device in a quadruple-layer polysilicon/single-layer
metal CMOS process. The MSM512200/L is available in a 26/20-pin plastic SOJ or 26/20-pin plastic
TSOP. The MSM512200L (the low-power version) is specially designed for lower-power applications.
FEATURES
• 1,048,576-word ¥ 2-bit configuration
• Single 5 V power supply, ±10% tolerance
• Input
: TTL compatible, low input capacitance
• Output : TTL compatible, 3-state
• Refresh : 1024 cycles/16 ms, 1024 cycles/128 ms (L-version)
• Fast page mode, read modify write capability
• CAS before RAS refresh, hidden refresh, RAS-only refresh capability
• Multi-bit test mode capability
• Package options:
26/20-pin 300 mil plastic SOJ (SOJ26/20-P-300-1.27) (Product : MSM512200/L-xxSJ)
26/20-pin 300 mil plastic TSOP (TSOPII26/20-P-300-1.27-K) (Product : MSM512200/L-xxTS-K)
xx indicates speed rank.
PRODUCT FAMILY
Family
Access Time (Max.)
tRAC
tAA
tCAC
tOEA
Cycle Time
Power Dissipation
(Min.)
Operating (Max.) Standby (Max.)
MSM512200/L-60
60 ns 30 ns 15 ns 15 ns
110 ns
440 mW
MSM512200/L-70
70 ns 35 ns 20 ns 20 ns
130 ns
385 mW
MSM512200/L-80
80 ns 40 ns 20 ns 20 ns
150 ns
330 mW
5.5 mW/
0.55 mW (L-version)
1/17
¡ Semiconductor
MSM512200/L
PIN CONFIGURATION (TOP VIEW)
DQ1 1
26 VSS
DQ1 1
26 VSS
DQ2 2
25 NC
DQ2 2
25 NC
WE 3
24 CAS1
WE 3
24 CAS1
RAS 4
23 CAS2
RAS 4
23 CAS2
A9 5
22 OE
A9 5
22 OE
A0 9
18 A8
A0 9
18 A8
A1 10
17 A7
A1 10
17 A7
A2 11
16 A6
A2 11
16 A6
A3 12
15 A5
A3 12
15 A5
VCC 13
14 A4
VCC 13
14 A4
26/20-Pin Plastic SOJ
Pin Name
A0 - A9
RAS
CAS1, CAS2
DQ1, DQ2
26/20-Pin Plastic TSOP
(K Type)
Function
Address Input
Row Address Strobe
Column Address Strobe
Data Input/Data Output
OE
Output Enable
WE
Write Enable
VCC
Power Supply (5 V)
VSS
Ground (0 V)
NC
No Connection
2/17
¡ Semiconductor
MSM512200/L
BLOCK DIAGRAM
RAS
Timing
Generator
Timing
Generator
CAS1
CAS2
10
Column
Address
Buffers
10
Write
Clock
Generator
Column
Decoders
WE
OE
2
Internal
Address
Counter
A0 - A9
Refresh
Control Clock
Sense
Amplifiers
2
I/O
Selector
Row
Address
Buffers
10
Row
Decoders
Word
Drivers
2
2
2
2
10
Output
Buffers
Input
Buffers
DQ1, DQ2
2
Memory
Cells
VCC
On Chip
VBB Generator
VSS
3/17
¡ Semiconductor
MSM512200/L
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
Parameter
Symbol
Rating
Unit
VT
–1.0 to 7.0
V
Short Circuit Output Current
IOS
50
mA
Power Dissipation
PD*
1
W
Operating Temperature
Topr
0 to 70
°C
Storage Temperature
Tstg
–55 to 150
°C
Voltage on Any Pin Relative to VSS
*: Ta = 25°C
Recommended Operating Conditions
Parameter
Power Supply Voltage
(Ta = 0°C to 70°C)
Symbol
Min.
Typ.
Max.
Unit
VCC
4.5
5.0
5.5
V
VSS
0
0
0
V
Input High Voltage
VIH
2.4
—
6.5
V
Input Low Voltage
VIL
–1.0
—
0.8
V
Capacitance
Parameter
Input Capacitance (A0 - A9)
Input Capacitance
(RAS, CAS1, CAS2, WE, OE)
Output Capacitance (DQ1, DQ2)
(VCC = 5 V ±10%, Ta = 25°C, f = 1 MHz)
Symbol
Typ.
Max.
Unit
CIN1
—
6
pF
CIN2
—
7
pF
CI/O
—
7
pF
4/17
¡ Semiconductor
MSM512200/L
DC Characteristics
Parameter
(VCC = 5 V ±10%, Ta = 0°C to 70°C)
Symbol
Condition
MSM512200 MSM512200 MSM512200
/L-60
/L-70
/L-80
Unit Note
Min.
Max.
Min.
Max.
Min.
Max.
Output High Voltage
VOH IOH = –5.0 mA
2.4
VCC
2.4
VCC
2.4
VCC
V
Output Low Voltage
VOL IOL = 4.2 mA
0
0.4
0
0.4
0
0.4
V
Input Leakage Current
ILI
–10
10
–10
10
–10
10
mA
–10
10
–10
10
–10
10
mA
—
80
—
70
—
60
mA 1, 2
0 V £ VI £ 6.5 V;
All other pins not
under test = 0 V
Output Leakage Current
ILO
DQ disable
0 V £ VO £ 5.5 V
RAS, CAS1, CAS2
Average Power
ICC1 cycling,
Supply Current
(Operating)
tRC = Min.
RAS, CAS1, CAS2 = VIH
Power Supply
Current (Standby)
—
2
—
2
—
2
ICC2 RAS, CAS1, CAS2
—
1
—
1
—
1
≥ VCC –0.2 V
—
100
—
100
—
—
80
—
70
—
5
—
—
80
—
—
Average Power
RAS cycling,
Supply Current
ICC3 CAS1, CAS2 = VIH,
(RAS-only Refresh)
1
100
mA
1, 5
—
60
mA 1, 2
5
—
5
mA
—
70
—
60
mA 1, 2
60
—
55
—
50
mA 1, 3
200
—
200
—
200
mA
tRC = Min.
RAS = VIH,
Power Supply
Current (Standby)
ICC5 CAS1, CAS2 = VIL,
RAS cycling,
Supply Current
ICC6 CAS1, CAS2
(CAS before RAS Refresh)
before RAS
Average Power
RAS = VIL,
ICC7 CAS1, CAS2 cycling,
Supply Current
1
DQ = enable
Average Power
(Fast Page Mode)
tPC = Min.
tRC = 125 ms,
Average Power
ICC10
Supply Current
(Battery Backup)
Notes : 1.
2.
3.
4.
5.
mA
CAS1, CAS2
before RAS,
1, 4,
5
tRAS £ 1 ms
ICC Max. is specified as ICC for output open condition.
The address can be changed once or less while RAS = VIL.
The address can be changed once or less while CAS1, CAS2 = VIH.
VCC – 0.2 V £ VIH £ 6.5 V, –1.0 V £ VIL £ 0.2 V.
L-version.
5/17
¡ Semiconductor
MSM512200/L
AC Characteristics (1/2)
(VCC = 5 V ±10%, Ta = 0°C to 70°C) Note 1, 2, 3, 11, 12
Parameter
MSM512200 MSM512200 MSM512200
/L-70
/L-80
/L-60
Unit Note
Symbol
Min. Max. Min. Max. Min. Max.
tRC
110
—
130
—
150
—
ns
tRWC
150
—
180
—
200
—
ns
tPC
40
—
45
—
50
—
ns
tPRWC
80
—
95
—
100
—
ns
Access Time from RAS
tRAC
—
60
—
70
—
80
ns
4, 5, 6
Access Time from CAS
tCAC
—
15
—
20
—
20
ns
4, 5
Access Time from Column Address
tAA
—
30
—
35
—
40
ns
4, 6
Access Time from CAS Precharge
tCPA
—
35
—
40
—
45
ns
4, 14
Access Time from OE
tOEA
—
15
—
20
—
20
ns
4
Output Low Impedance Time from CAS
tCLZ
0
—
0
—
0
—
ns
4
CAS to Data Output Buffer Turn-off Delay Time
tOFF
0
15
0
20
0
20
ns
7
OE to Data Output Buffer Turn-off Delay Time
Random Read or Write Cycle Time
Read Modify Write Cycle Time
Fast Page Mode Cycle Time
Fast Page Mode Read Modify Write
Cycle Time
tOEZ
0
15
0
20
0
20
ns
7
Transition Time
tT
3
50
3
50
3
50
ns
3
Refresh Period
tREF
—
16
—
16
—
16
ms
Refresh Period (L-version)
tREF
—
128
—
128
—
128
ms
RAS Precharge Time
tRP
40
—
50
—
60
—
ns
RAS Pulse Width
tRAS
60
10,000
70
10,000
80
10,000
ns
RAS Pulse Width (Fast Page Mode)
tRASP
60
100,000
70
100,000
80
100,000 ns
RAS Hold Time
tRSH
15
—
20
—
20
—
ns
RAS Hold Time referenced to OE
tROH
15
—
20
—
20
—
ns
CAS Precharge Time (Fast Page Mode)
tCP
10
—
10
—
10
—
ns
CAS Pulse Width
tCAS
15
10,000
20
10,000
20
10,000
ns
CAS Hold Time
tCSH
60
—
70
—
80
—
ns
CAS to RAS Precharge Time
tCRP
5
—
5
—
5
—
ns
RAS Hold Time from CAS Precharge
tRHCP
35
—
40
—
45
—
ns
RAS to CAS Delay Time
tRCD
20
45
20
50
20
60
ns
5
RAS to Column Address Delay Time
tRAD
15
30
15
35
15
40
ns
6
Row Address Set-up Time
tASR
0
—
0
—
0
—
ns
Row Address Hold Time
tRAH
10
—
10
—
10
—
ns
16
14
Column Address Set-up Time
tASC
0
—
0
—
0
—
ns
13
Column Address Hold Time
tCAH
15
—
15
—
15
—
ns
13
Column Address Hold Time from RAS
tAR
50
—
55
—
60
—
ns
Column Address to RAS Lead Time
tRAL
30
—
35
—
40
—
ns
6/17
¡ Semiconductor
MSM512200/L
AC Characteristics (2/2)
(VCC = 5 V ±10%, Ta = 0°C to 70°C) Note 1, 2, 3, 11, 12
Parameter
Symbol
MSM512200 MSM512200 MSM512200
/L-70
/L-80
/L-60
Unit Note
Min.
Max.
Min.
Max.
Min.
Max.
Read Command Set-up Time
tRCS
0
—
0
—
0
—
ns
13
Read Command Hold Time
tRCH
0
—
0
—
0
—
ns
8, 13
Read Command Hold Time referenced to RAS
tRRH
0
—
0
—
0
—
ns
8
Write Command Set-up Time
tWCS
0
—
0
—
0
—
ns
9, 13
Write Command Hold Time
tWCH
10
—
10
—
10
—
ns
13
Write Command Hold Time from RAS
tWCR
45
—
50
—
60
—
ns
Write Command Pulse Width
tWP
10
—
10
—
10
—
ns
OE Command Hold Time
tOEH
15
—
20
—
20
—
ns
Write Command to RAS Lead Time
tRWL
15
—
20
—
20
—
ns
Write Command to CAS Lead Time
tCWL
15
—
20
—
20
—
ns
15
Data-in Set-up Time
tDS
0
—
0
—
0
—
ns
10, 13
Data-in Hold Time
tDH
15
—
15
—
15
—
ns
10, 13
Data-in Hold Time from RAS
tDHR
50
—
55
—
60
—
ns
OE to Data-in Delay Time
tOED
15
—
20
—
20
—
ns
CAS to WE Delay Time
tCWD
35
—
45
—
45
—
ns
9
Column Address to WE Delay Time
tAWD
50
—
60
—
65
—
ns
9
RAS to WE Delay Time
tRWD
80
—
95
—
105
—
ns
9
CAS Precharge WE Delay Time
tCPWD
55
—
65
—
70
—
ns
9, 14
tRPC
5
—
5
—
5
—
ns
13
CAS Active Delay Time from RAS Precharge
RAS to CAS Set-up Time (CAS before RAS)
tCSR
5
—
5
—
5
—
ns
13
RAS to CAS Hold Time (CAS before RAS)
tCHR
10
—
10
—
10
—
ns
14
WE to RAS Precharge Time (CAS before RAS) tWRP
10
—
10
—
10
—
ns
WE Hold Time from RAS (CAS before RAS) tWRH
10
—
10
—
10
—
ns
RAS to WE Set-up Time (Test Mode)
tWTS
10
—
10
—
10
—
ns
RAS to WE Hold Time (Test Mode)
tWTH
10
—
10
—
10
—
ns
7/17
¡ Semiconductor
Notes:
MSM512200/L
1. A start-up delay of 200 µs is required after power-up, followed by a minimum of eight
initialization cycles (RAS-only refresh or CAS before RAS refresh) before proper device
operation is achieved.
2. The AC characteristics assume tT = 5 ns.
3. VIH (Min.) and VIL (Max.) are reference levels for measuring input timing signals.
Transition times (tT) are measured between VIH and VIL.
4. This parameter is measured with a load circuit equivalent to 2 TTL loads and 100 pF.
5. Operation within the tRCD (Max.) limit ensures that tRAC (Max.) can be met.
tRCD (Max.) is specified as a reference point only. If tRCD is greater than the specified
tRCD (Max.) limit, then the access time is controlled by tCAC.
6. Operation within the tRAD (Max.) limit ensures that tRAC (Max.) can be met.
tRAD (Max.) is specified as a reference point only. If tRAD is greater than the specified
tRAD (Max.) limit, then the access time is controlled by tAA.
7. tOFF (Max.) and tOEZ (Max.) define the time at which the output achieves the open
circuit condition and are not referenced to output voltage levels.
8. tRCH or tRRH must be satisfied for a read cycle.
9. tWCS, tCWD, tRWD, tAWD and tCPWD are not restrictive operating parameters. They are
included in the data sheet as electrical characteristics only. If tWCS ≥ tWCS (Min.), then
the cycle is an early write cycle and the data out will remain open circuit (high
impedance) throughout the entire cycle. If tCWD ≥ tCWD (Min.) , tRWD ≥ tRWD (Min.),
tAWD ≥ tAWD (Min.) and tCPWD ≥ tCPWD (Min.), then the cycle is a read modify write
cycle and data out will contain data read from the selected cell; if neither of the above
sets of conditions is satisfied, then the condition of the data out (at access time) is
indeterminate.
10. These parameters are referenced to the CAS leading edge in an early write cycle, and
to the WE leading edge in an OE control write cycle, or a read modify write cycle.
11. The test mode is initiated by performing a WE and CAS before RAS refresh cycle.
This mode is latched and remains in effect until the exit cycle is generated.
The test mode specified in this data sheet is a 2-bit parallel test function. CA0 is not
used. In a read cycle, if all internal bits are equal, the DQ pin will indicate a high
level. If any internal bits are not equal, the DQ pin will indicate a low level.
The test mode is cleared and the memory device returned to its normal operating
state by performing a RAS-only refresh cycle or a CAS before RAS refresh cycle.
12. In a test mode read cycle, the value of access time parameters is delayed for 5 ns for the
specified value. These parameters should be specified in test mode cycle by adding the
above value to the specified value in this data sheet.
13. These parameters are determined by the falling edge of either CAS1 or CAS2,
whichever is earlier.
14. These parameters are determined by the rising edge of either CAS1 or CAS2,
whichever is later.
15. tCWL, tDH and tDS should be satisfied by both CAS1 and CAS2.
16. tCP is determined by the time both CAS1 and CAS2 are high.
8/17
¡ Semiconductor
MSM512200/L
Notes concerning CAS1 and CAS2 control
Overlap the active-low timings of CAS1 and CAS2. Skew between CAS1 and CAS2 is allowed
under the following conditions:
(1) The timing specification for CAS1 and CAS2 should be met individually.
(2) Different operation modes for CAS1/CAS2 are not allowed (as shown below).
RAS
CAS1
Delayed write
CAS2
Early write
WE
(3) Closely separated CAS1/CAS2 control is not allowed. However, when the condition
(tCP ≤ tUL) is satisfied, fast page mode can be performed.
RAS
CAS1
CAS2
tUL
9/17
E2G0094-17-41G
,,,
,
,,,,
¡ Semiconductor
MSM512200/L
TIMING WAVEFORM
Read Cycle
tRC
tRP
tRAS
VIH –
RAS
VIL –
tAR
tCSH
tCRP
CAS
tRCD
VIH –
VIL –
Address
VIL –
tRSH
tCAS
tRAD
tASR
VIH –
tCRP
tRAH tASC
tRAL
tCAH
Column
Row
tRCS
WE
OE
VIH –
VIL –
tAA
tROH
tOEA
VIH –
VIL –
tCAC
tRAC
DQ
tRCH
tRRH
VOH –
tOEZ
Open
VOL –
tOFF
Valid Data-out
tCLZ
"H" or "L"
Write Cycle (Early Write)
tRC
tRP
tRAS
RAS
VIH –
VIL –
tAR
tCRP
VIH –
CAS
VIL –
WE
VIH –
VIL –
tCSH
tRCD
tRSH
tCAS
tRAD
tRAH
tASR
Address
tCRP
tASC
Row
tCAH
Column
tWCS
tWCH
VIH –
tRWL
VIH –
VIL –
tDS
DQ
tCWL
tWP
VIL –
tWCR
OE
tRAL
VIH –
VIL –
tDHR
tDH
Valid Data-in
Open
"H" or "L"
10/17
,,,
¡ Semiconductor
MSM512200/L
Read Modify Write Cycle
tRWC
tRAS
RAS
VIH –
VIL –
tRP
tAR
tCRP
tCSH
tCRP
tRCD
tRSH
tCAS
VIH –
CAS
VIL –
tASR
VIH –
Address
VIL –
WE
VIH –
VIL –
OE
VIH –
VIL –
tRAH
tASC
tCAH
Column
Row
tRAD
tRWD
tAA
tAWD
tRCS
tOEA
tOED
tCAC
tRAC
DQ
VI/OH–
VI/OL–
tCWL
tRWL
tWP
tCWD
tCLZ
tOEZ
Valid
Data-out
tOEH
tDS
tDH
Valid
Data-in
"H" or "L"
11/17
¡ Semiconductor
MSM512200/L
,,,
,,,
Fast Page Mode Read Cycle
tRASP
VIH –
RAS V –
IL
VIH –
CAS
VIL –
Address
WE
VIH –
VIL –
tRP
tAR
tCRP
tRHCP
tPC
tRCD
tCP
tASR
tCP
tCAS
tCAS
tRAD
tRAH tASC
tCSH
tCAH
tASC
Column
Row
VIH –
VIL –
tCAC
VOH –
DQ
VOL –
Column
tRCS
tRCH
tRRH
tCPA
tOEA
tOFF
tOEZ
tRCH
tAA
tAA
tCAC
tOEA
tOFF
tCAC
tOEZ
tCLZ
Valid
Data-out
tCLZ
tRCS
tCPA
tOEA
tRAC
tRAL
tCAH
tASC
Column
tAA
VIH –
OE
VIL –
tCAS
tCAH
tRCH
tRCS
tCRP
tRSH
tCLZ
tOFF
tOEZ
Valid
Data-out
Valid
Data-out
"H" or "L"
Fast Page Mode Write Cycle (Early Write)
tRASP
tAR
VIH –
RAS V –
IL
tCRP
VIH –
CAS
VIL –
Address
VIH –
VIL –
tRAH tASC
Row
VIH –
VIL –
tDS
DQ
VIH –
VIL –
tCSH
tCAH
Column
tCWL
tWCH
tWP
tRAD
tRHCP
tRSH
tRCD
tWCS
WE
tPC
tCAS
tASR
tRP
tWCR
tDH
Valid Data-in
tDHR
tCP
tCRP
tCP
tCAS
tASC
tCAH
tASC
Column
tCWL
tWCS
tWCH
tWP
tDS
tDH
Valid
Data-in
tCAS
tCAH
tRAL
Column
tRWL
tCWL
tWCS
tWCH
tWP
tDS
tDH
Valid
Data-in
Note: OE = "H" or "L"
"H" or "L"
12/17
¡ Semiconductor
MSM512200/L
,
,
,,
,
,
,
Fast Page Mode Read Modify Write Cycle
tRASP
VIH –
RAS
VIL –
tAR
tRP
tCSH
tPRWC
tRCD
VIH –
CAS
VIL –
tASC
tCAH
tRAH
VIH –
VIL –
tCRP
tCAS
tASC
tCAH
tCAH
Column
Column
tASC
Column
Row
tRCS
tCPWD
tCWD
tRWD
tCWD
tRCS
V
WE IH –
VIL –
tCWL
tAWD
tCWL
tWP
tDH
VI/OH–
VI/OL –
Out
tCLZ
tOEA
tOED
tOEZ
tCAC
In
tDH
tDS
tOEA
tOEZ
tCAC
tWP
tCPA
tAA
tOED
VIH –
OE V –
IL
tCWL
tROH
tWP
tDH
tDS
tOEA
tRWL
tAWD
tCPA
tAA
tAA
tRAL
tRCS
tCPWD
tCWD
tAWD
tDS
tRAC
DQ
tCP
tCAS
tRAD
tASR
Address
tCP
tCAS
tRSH
Out
tOED
In
tCLZ
tOEZ
tCAC
Out
In
tCLZ
"H" or "L"
RAS-Only Refresh Cycle
tRC
RAS
VIL –
CAS
Address
VIH –
VIL –
VIH –
VIL –
tRP
tRAS
VIH –
tCRP
tASR
tRPC
tRAH
Row
tOFF
DQ
VOH –
VOL –
Open
Note: WE, OE = "H" or "L"
"H" or "L"
13/17
M
L
K
^
]
\
S
R
Q
P
¡ Semiconductor
MSM512200/L
CAS before RAS Refresh Cycle
tRC
tRP
RAS
tRP
tRAS
VIH –
VIL –
tRPC
tRPC
tCP
CAS
tCSR
tCHR
tWRP
tWRH
VIH –
VIL –
tWRP
,
,,
WE
VIH –
VIL –
DQ
VOH –
VOL –
tOFF
Open
Note: OE, Address = "H" or "L"
"H" or "L"
Hidden Refresh Read Cycle
tRC
tRAS
RAS
VIH –
tRP
tAR
VIH –
VIL –
VIH –
VIL –
tRSH
tRCD
tRAD
tASC
tRAH
tASR
Address
tRAS
tRP
VIL –
tCRP
CAS
tRC
Row
tCHR
tCAH
Column
tRCS
tRAL
VIH –
WE V
IL –
tRRH
tAA
tROH
tOEA
VIH –
OE V
IL –
tRAC
DQ
VOH –
VOL –
tCAC
tCLZ
tOFF
tOEZ
Valid Data-out
"H" or "L"
14/17
¡ Semiconductor
MSM512200/L
Hidden Refresh Write Cycle
tRC
tRAS
RAS
CAS
Address
VIH –
VIL –
tRP
tAR
,
,,,,
,
VIH –
VIL –
VIH –
VIL –
tCRP
tASR
tRCD
tRSH
tRAD
tASC
tCAH
tRAH
Row
WE
VIH –
VIL –
OE
VIH –
VIL –
tCHR
tRAL
Column
tWCH
tWP
tWCS
tDS
DQ
tRC
tRAS
tRP
VIH –
VIL –
tWRP
tWRH
tDH
Valid Data-in
tDHR
"H" or "L"
Test Mode Initiate Cycle
tRC
tRP
RAS
VIH –
VIL –
tRPC
tCP
CAS
tRAS
tCSR
VIH –
VIL –
tWTS
WE
tCHR
tWTH
VIH –
VIL –
tOFF
DQ
VOH –
VOL –
Open
Note: OE, Address = "H" or "L"
"H" or "L"
15/17
¡ Semiconductor
MSM512200/L
PACKAGE DIMENSIONS
(Unit : mm)
SOJ26/20-P-300-1.27
Mirror finish
Package material
Lead frame material
Pin treatment
Solder plate thickness
Package weight (g)
Epoxy resin
42 alloy
Solder plating
5 mm or more
0.80 TYP.
Notes for Mounting the Surface Mount Type Package
The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which
are very susceptible to heat in reflow mounting and humidity absorbed in storage.
Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the
product name, package name, pin number, package code and desired mounting conditions
(reflow method, temperature and times).
16/17
¡ Semiconductor
MSM512200/L
(Unit : mm)
TSOPII26/20-P-300-1.27-K
Mirror finish
Package material
Lead frame material
Pin treatment
Solder plate thickness
Package weight (g)
Epoxy resin
42 alloy
Solder plating
5 mm or more
0.38 TYP.
Notes for Mounting the Surface Mount Type Package
The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which
are very susceptible to heat in reflow mounting and humidity absorbed in storage.
Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the
product name, package name, pin number, package code and desired mounting conditions
(reflow method, temperature and times).
17/17