Si 5 32 P R E L I M I N A R Y D A TA S H E E T D U A L F R E Q U E N C Y X O ( 1 0 M H Z T O 1 . 4 GH Z ) Features Available with any-rate output frequencies from 10 to 945 MHz and selected frequencies to 1.4 GHz Two selectable output frequencies Industry standard 7x5 mm package Available CMOS, LVPECL, LVDS & CML outputs 3.3, 2.5, and 1.8 V supply options 3x better frequency stability than SAW based oscillators Si5602 3rd generation DSPLL® with superior jitter performance Internal fixed crystal frequency ensures high reliability and low aging Lead-free/RoHS-compliant Applications Ordering Information: SONET/SDH xDSL 10 GbE LAN/WAN Low jitter clock generation Optical modules Test and measurement See page 7. Description The Si532 dual frequency XO utilizes Silicon Laboratories advanced DSPLL® circuitry to provide a very low jitter clock for all output frequencies. The Si532 is available with any-rate output frequency from 10 to 945 MHz and selected frequencies to 1400 MHz. Unlike traditional XOs where a different crystal is required for each output frequency, the Si532 uses one fixed crystal frequency to provide a wide range of output frequencies. This IC based approach allows the crystal resonator to be optimized for superior frequency, stability, and reliability. In addition, DSPLL clock synthesis provides superior supply noise rejection, simplifying the task of generating low jitter clocks in noisy environments often found in communication systems. The Si532 IC based XO is factory configurable for a wide variety of user specifications including frequency, supply voltage, and output format. Specific configurations are factory programmed into the Si532 at the time of shipment, thereby eliminating the long lead times associated with custom oscillators. Functional Block Diagram V DD Fixed Frequency XO FS Preliminary Rev. 0.3 12/05 CLK– CLK+ Any-rate 10–1400 MHz DSPLL® Clock Synthesis OE GND Copyright © 2005 by Silicon Laboratories Si532 This information applies to a product under development. Its characteristics and specifications are subject to change without notice. Si5 32 1. Electrical Specifications Table 1. Si532 Electrical Specifications Parameter Min Typ Max Units Notes Frequency Nominal Frequency LVDS/CML/LVPECL CMOS 10 10 — — 945 160 Initial Accuracy –1.5 — 1.5 Temperature Stability –20 –50 — — +20 +50 — — ±10 Aging MHz Specified at time of order by P/N. Also available in bands from 970 to 1134 MHz and 1213 to 1417 MHz. ppm Measured at +25 °C at time of shipping ppm Selectable option by P/N. See Section 4. "Ordering Information" on page 7. ppm Frequency drift over projected 15 year life Outputs Symmetry 45 — 55 % LVPECL: LVDS: CMOS: RMS Jitter for FOUT > 500 MHz 12 kHz to 20 MHz 50 kHz to 80 MHz — — 0.27 0.30 — — ps FOUT > 500 MHz Differential Modes: LVPECL/LVDS/CML RMS Jitter for FOUT of 125 to 500 MHz 12 kHz to 20 MHz — 0.5 — VDD – 1.3 V (differential) 1.25 V (differential) VDD/2 ps 125 < FOUT < 500 MHz Differential Modes: LVPECL/LVDS/CML Any output N = 1000 cycles Period Jitter for FOUT <160 MHz Peak-to-Peak RMS — — 5 1 — — ps LVPECL Output Option mid-level swing (diff) swing (single-ended) VDD – 1.42 1.1 0.50 — — — VDD – 1.25 1.9 0.93 V VPP VPP LVDS Output Option mid-level swing (diff) 1.125 0.32 1.2 0.40 1.275 0.50 V VPP Rterm = 100 Ω (differential) CML Output Option mid-level swing — 0.70 VDD – 0.75 0.95 — 1.20 V VPP Rterm = 100 Ω (differential) 2 Preliminary Rev. 0.3 50 Ω to VDD – 2.0 V Si532 Table 1. Si532 Electrical Specifications (Continued) Parameter CMOS Output Option VOH VOL Rise/Fall time Min Typ Max Units Notes 0.8xVDD — — — VDD 0.4 V CL = 15 pF — — — 1 350 — ps ns CML/LVPECL/LVDS at 20% / 80% CMOS with CL = 15 pF Inputs Voltage (VDD) 3.3 V option 2.5 V option 1.8 V option 2.97 2.25 1.71 3.3 2.5 1.8 3.63 2.75 1.89 — — 90 60 — — mA Frequency Select (FS) VIH VIL 0.75 x VDD 0 — — VDD 0.5 V Output Enable VIH VIL 0.75 x VDD — — — VDD 0.5 V Current Output enabled TriState mode V Optional parameter specified by P/N FS = “0” selects F0 FS = “1” selects F1 Table 2. Absolute Maximum Ratings Parameter Supply Voltage Storage Temperature Symbol Rating Units VDD –0.5 to +3.8 V TS –55 to +125 °C Preliminary Rev. 0.3 3 Si5 32 Table 3. Environmental Conditions Parameter Conditions/Test Method Operating Temperature –40 to +85 °C Mechanical Shock MIL-STD-883F, Method 2002.3 B Mechanical Vibration MIL-STD-883F, Method 2007.3 A Solderability MIL-STD-883F, Method 203.8 Gross & Fine Leak MIL-STD-883F, Method 1014.7 Resistance to Solvents MIL-STD-883F, Method 2016 Table 4. Pinout 4 Pin Symbol Function 1 FS Frequency Select 2 OE Output Enable 3 GND Ground 4 CLK+ Oscillator Output 5 CLK– (N/A for CMOS) Complementary Output (N/C for CMOS) 6 VDD Power Suppy Voltage Preliminary Rev. 0.3 Si532 2. Outline Diagram and Suggested Pad Layout Figure 1 illustrates the package details for the Si532. Table 5 lists the values for the dimensions shown in the illustration. Figure 1. Si532 Outline Diagram Table 5. Package Diagram Dimensions (mm) Dimension Min Nom Max A 1.45 1.65 1.85 b 1.2 1.4 1.6 c 0.60 TYP. D 7.00 BSC. D1 6.10 6.2 e 2.54 BSC. E 5.00 BSC. 6.30 E1 4.30 4.40 4.50 L 1.07 1.27 1.47 S 1.815 BSC. R 0.7 REF. aaa — — 0.15 bbb — — 0.15 ccc — — 0.10 ddd — — 0.10 Preliminary Rev. 0.3 5 Si5 32 3. 6-Pin PCB Land Pattern Figure 2 illustrates the 6-pin PCB land pattern for the Si532. Table 6 lists the values for the dimensions shown in the illustration. Figure 2. Si530 PCB Land Pattern Table 6. PCB Land Pattern Dimensions (mm) Dimension Min Max D2 5.08 REF e 2.54 BSC E2 4.15 REF GD 0.84 — GE 2.00 — VD 8.20 REF VE 7.30 REF X 1.70 TYP Y 2.15 REF ZD — 6.78 ZE — 6.30 Notes: 1. Dimensioning and tolerancing per the ANSI Y14.5M-1994 specification. 2. Land pattern design based on IPC-7351 guidelines. 3. All dimensions shown are at maximum material condition (MMC). 4. Controlling dimension is in millimeters (mm). 6 Preliminary Rev. 0.3 Si532 4. Ordering Information The Si532 was designed to support a variety of options including frequency, tuning slope, output format, and VDD. Specific device configurations are programmed into the Si532 at time of shipment. A unique part number associated with these options and frequencies will be assigned. The Si532 XO series is supplied in an industrystandard, 7x5 mm package. Part numbers for the Si532 Dual Frequency XO are determined by following configuration tables. Silicon Labs provides a web browser-based part number configuration tool to simplify this process. Refer to www.silabs.com/ VCXO to access this tool and for further ordering instructions. X 532 X XXXXXX B G R Tape & Reel Packaging 532 XO Product Family Operating Temp Range (°C) G -40 to +85°C Part Revision Letter Frequency Designator Code Two unique frequencies can be specified within the following bands of frequencies: 10 to 945 MHz 970 to 1134 MHz 1213 to 1417 MHz A six digit code will be assigned by SiLabs for the specified combination of frequencies. Note: Six digit codes > 000100 refer to dual XOs programmed with the lower frequency value selected when FS = 0, and the higher value when FS = 1; six digit codes < 000100 refer to dual XOs programmed with the higher frequency value selected when FS = 0, and the lower value when FS = 1. 1 st Option Code A B C D E F G H J K V DD 3.3 3.3 3.3 3.3 2.5 2.5 2.5 2.5 1.8 1.8 Output Format LVPECL LVDS CMOS CML LVPECL LVDS CMOS CML CMOS CML Note: CMOS available to 160 MHz. 2 nd Option Code Temp Stability (ppm, max, ±) A B 50 20 Figure 3. Part Number Convention Preliminary Rev. 0.3 7 Si5 32 DOCUMENT CHANGE LIST Revision 0.2 to Revision 0.3 Updated the “Features” section. Updated Table 1, “Si532 Electrical Specifications,” on page 2. Updated LVDS, CML, and CMOS electric specifications. Updated Figure 1, “Si532 Outline Diagram,” on page 5. Updated 4. "Ordering Information" on page 7. Updated Figure 3, “Part Number Convention,” on page 7. 8 Preliminary Rev. 0.3 Si532 NOTES: Preliminary Rev. 0.3 9 Si5 32 CONTACT INFORMATION Silicon Laboratories Inc. 4635 Boston Lane Austin, TX 78735 Tel: 1+(512) 416-8500 Fax: 1+(512) 416-9669 Toll Free: 1+(877) 444-3032 Email:[email protected] Internet: www.silabs.com The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. Silicon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from the use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed features or parameters. Silicon Laboratories reserves the right to make changes without further notice. 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Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders. 10 Preliminary Rev. 0.3