S i 5 3 5 / 5 36 REVISION D U L T R A L O W J ITTER C RYSTAL O SCILLATOR (XO) Features Si5602 Available with select frequencies from Available with LVPECL and 100 MHz to 312.5 MHz LVDS outputs 3rd generation DSPLL® with superior 3.3 and 2.5 V supply options Industry-standard 5 x 7 mm jitter performance and high-power package and pinout supply noise rejection Pb-free/RoHS-compliant 3x better frequency stability than SAW-based oscillators Ordering Information: Applications See page 7. 10/40/100G data centers 10G Ethernet switches/routers Fibre channel/SAS/storage Enterprise servers Networking Telecommunications Description The Si535/536 XO utilizes Silicon Laboratories’ advanced DSPLL® circuitry to provide an ultra low jitter clock at high-speed differential frequencies. Unlike a traditional XO, where a different crystal is required for each output frequency, the Si535/536 uses one fixed crystal to provide a wide range of output frequencies. This IC based approach allows the crystal resonator to provide exceptional frequency stability and reliability. In addition, DSPLL clock synthesis provides superior supply noise rejection, simplifying the task of generating low jitter clocks in noisy environments typically found in communication systems. The Si535/536 IC based XO is factory programmed at time of shipment, thereby eliminating long lead times associated with custom oscillators. Pin Assignments: See page 6. (Top View) NC 1 6 VDD OE 2 5 CLK– GND 3 4 CLK+ Si535 Functional Block Diagram VDD CLK– CLK+ OE 1 6 VDD NC 2 5 CLK– GND 3 4 CLK+ Si536 Fixed Frequency XO OE Preliminary Rev. 0.6 7/13 100–312.5 MHz DSPLL® Clock Synthesis GND Copyright © 2013 by Silicon Laboratories Si535/536 This information applies to a product under development. Its characteristics and specifications are subject to change without notice. Si535/536 1. Electrical Specifications Table 1. Recommended Operating Conditions Parameter Supply Voltage1 Supply Current Symbol Test Condition Min Typ Max Unit VDD 3.3 V option 2.97 3.3 3.63 V 2.5 V option 2.25 2.5 2.75 V Output enabled LVPECL LVDS — — 111 90 121 98 mA Tristate mode — 60 75 mA VIH 0.75 x VDD — — V VIL — — 0.5 V –40 — 85 °C IDD Output Enable (OE)2 Operating Temperature Range TA Notes: 1. Selectable parameter specified by part number. See Section 3. "Ordering Information" on page 7 for further details. 2. OE pin includes a 17 k pullup resistor to VDD. Table 2. CLK± Output Frequency Characteristics Parameter Nominal Frequency1 Initial Accuracy Symbol Test Condition Min Typ Max Unit fO LVPECL/LVDS 100 — 312.5 MHz fi Measured at +25 °C at time of shipping — ±1.5 — ppm –7 –20 — — +7 +20 ppm Frequency drift over first year — — ±3 ppm Frequency drift over 20 year life — — ±10 ppm Temp stability = ±20 ppm — — ±31.5 Temp stability = ±7 ppm — — 20 — — 10 Temperature Stability1,2 Aging fa Total Stability2 ppm Powerup Time3 tOSC Notes: 1. See Section 3. "Ordering Information" on page 7 for the list of available frequencies. 2. Selectable parameter specified by part number. 3. Time from powerup or tristate mode to fO. 2 Preliminary Rev. 0.6 ms Si535/536 Table 3. CLK± Output Levels and Symmetry Parameter Symbol Test Condition Min Typ Max Unit VO Mid-level VDD – 1.42 — VDD – 1.25 V VOD Swing (diff) 1.1 — 1.9 VPP VSE Swing (Single-ended) 0.55 — 0.95 VPP VO Mid-level 1.125 1.20 1.275 V VOD Swing (diff) 0.5 0.7 0.9 VPP — — 350 ps 45 — 55 % LVPECL Output Option1 LVDS Output Option 2 Rise/Fall time (20/80%) tR, tF Symmetry (duty cycle) SYM Differential Notes: 1. 50 to VDD – 2.0 V. 2. Rterm = 100 (differential). Preliminary Rev. 0.6 3 Si535/536 Table 4. CLK± Output Phase Jitter Parameter LVPECL/LVDS Phase Jitter* (RMS) Symbol Test Condition Min Typ Max Unit J 10 kHz to 1 MHz (data center) — 0.19 — ps 12 kHz to 20 MHz (OC-48) — 0.25 — ps Symbol Test Condition Min Typ Max Unit JPER RMS — 2 — ps Peak-to-Peak — 14 — ps *Note: Applies to output frequencies: 156.25 MHz. Table 5. CLK± Output Period Jitter Parameter LVPECL/LVDS Period Jitter* *Note: N = 1000 cycles. Figure 1. Si535/536 Typical Phase Noise at 156.25 MHz 4 Preliminary Rev. 0.6 Si535/536 Table 6. Environmental Compliance The Si535/536 meets the following qualification test requirements. Parameter Conditions/Test Method Mechanical Shock MIL-STD-883, Method 2002 Mechanical Vibration MIL-STD-883, Method 2007 Solderability MIL-STD-883, Method 2003 Gross & Fine Leak MIL-STD-883, Method 1014 Resistance to Solder Heat MIL-STD-883, Method 2036 Moisture Sensitivity Level J-STD-020, MSL1 Gold over Nickel Contact Pads Table 7. Thermal Characteristics (Typical values TA = 25 ºC, VDD = 3.3 V) Parameter Symbol Test Condition Min Typ Max Unit Thermal Resistance Junction to Ambient JA Still Air — 84.6 — °C/W Thermal Resistance Junction to Case JC Still Air — 38.8 — °C/W Ambient Temperature TA –40 — 85 °C Junction Temperature TJ — — 125 °C Table 8. Absolute Maximum Ratings1 Parameter Symbol Rating Unit Maximum Operating Temperature TAMAX 85 °C Supply Voltage, 2.5/3.3 V Option VDD –0.5 to +3.8 V Input Voltage (any input pin) VI –0.5 to VDD + 0.3 V Storage Temperature TS –55 to +125 °C ESD 2500 V TPEAK 260 °C tP 20–40 seconds ESD Sensitivity (HBM, per JESD22-A114) Soldering Temperature (Pb-free profile)2 Soldering Temperature Time @ TPEAK (Pb-free profile)2 Notes: 1. Stresses beyond those listed in Absolute Maximum Ratings may cause permanent damage to the device. Functional operation or specification compliance is not implied at these conditions. Exposure to maximum rating conditions for extended periods may affect device reliability. 2. The device is compliant with JEDEC J-STD-020C. Refer to Si5xx Packaging FAQ available for download at www.silabs.com/VCXO for further information, including soldering profiles. Preliminary Rev. 0.6 5 Si535/536 2. Pin Descriptions (Top View) NC 1 6 VDD OE 1 6 VDD OE 2 5 CLK– NC 2 5 CLK– GND 3 4 CLK+ GND 3 4 CLK+ Si536 Si535 Table 9. Pinout for Si535 Series Pin Symbol Function 1 NC No connection 2 OE Output enable 0 = clock output disabled (outputs tristated) 1 = clock output enabled 3 GND Electrical and Case Ground 4 CLK+ Oscillator Output 5 CLK– Complementary Output 6 VDD Power Supply Voltage *Note: OE includes a 17 k pullup resistor to VDD. Table 10. Pinout for Si536 Series Pin Symbol Function 1 OE Output enable 0 = clock output disabled (outputs tristated) 1 = clock output enabled 2 No connection No connection 3 GND Electrical and Case Ground 4 CLK+ Oscillator Output 5 CLK– Complementary output 6 VDD Power Supply Voltage *Note: OE includes a 17 k pullup resistor to VDD. 6 Preliminary Rev. 0.6 Si535/536 3. Ordering Information The Si535/536 XO supports a variety of options including frequency, temperature stability, output format, and VDD. The Si535 and Si536 XO series are supplied in an industry-standard, RoHS compliant, 6-pad, 5 x 7 mm package. The Si536 Series supports an alternate OE pinout (pin #1) for the LVPECL and LVDS output formats. See Tables 9 and 10 for the pinout differences between the Si535 and Si536 series. 53x D evice 535 536 X X XXXM XXX G D Tape & Reel Packaging Blank = Trays O utput Enable pin 2 pin 1 O perating Tem p R ange (°C ) G -40 to +85 °C Part R evision Letter 1 st O ption C ode A B E F V DD 3.3 3.3 2.5 2.5 R O utput Form at O utput Enable Polarity LVPEC L H igh LVDS H igh LVPEC L H igh LVDS H igh Frequency (e.g., 156M 250 is 156.250 M H z) Select frequencies available in the frequency range 100 to 312.5 M Hz are listed below . Frequencies requiring greater than 6 digit resolution are assigned a six digit code. Available Fre quencie s Fre que ncy Orde r Code 106.250 MHz 106M250 125.000 MHz 125M000 150.000 MHz 150M000 155.520 MHz 155M520 156.250 MHz 156M250 156.2578 MHz 000305 156.2539 MHz 000335 159.375 MHz 159M375 161.1328 MHz 000174 166.6286 MHz 000118 167.3316 MHz 000119 212.500 MHz 212M500 312.500 MHz 312M500 2 nd O ption C ode C ode B C Tem perature Stability (ppm , m ax, ±) 20 7 Total Stablility (ppm , m ax, ±) 31 .5 20 Exam ple P/N : 535AB156M 250D G R is a 5 x 7 XO in a 6 pad package. The frequency is 156.250 M H z, with a 3.3 V supply, LVPEC L output, and O utput Enable active high polarity. Tem perature stability is specifed as ±20 ppm . The part is specified for –40 to +85 °C am bient tem perature range operation and is shipped in tape and reel form at. Figure 2. Part Number Convention Preliminary Rev. 0.6 7 Si535/536 4. Package Outline Figure 3 illustrates the package details for the Si535/536. Table 11 lists the values for the dimensions shown in the illustration. Figure 3. Si535/536 Outline Diagram Table 11. Package Diagram Dimensions (mm) Dimension A b c D D1 e E E1 H L p R aaa bbb ccc ddd eee 8 Min 1.50 1.30 0.50 4.30 6.10 0.55 1.17 1.80 Nom 1.65 1.40 0.60 5.00 BSC 4.40 2.54 BSC 7.00 BSC 6.20 0.65 1.27 — 0.70 REF 0.15 0.15 0.10 0.10 0.05 Preliminary Rev. 0.6 Max 1.80 1.50 0.70 4.50 6.30 0.75 1.37 2.60 Si535/536 5. 6-Pin PCB Land Pattern Figure 4 illustrates the 6-pin PCB land pattern for the Si535/536. Table 12 lists the values for the dimensions shown in the illustration. Figure 4. Si535/536 PCB Land Pattern Table 12. PCB Land Pattern Dimensions (mm) Dimension Min C1 4.20 E 2.54 X1 1.55 Y1 1.95 Notes: General 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing is per the ANSI Y14.5M-1994 specification. 3. This Land Pattern Design is based on the IPC-7351 guidelines. 4. All dimensions shown are at Maximum Material Condition (MMC). Least Material Condition (LMC) is calculated based on a Fabrication Allowance of 0.05 mm. Solder Mask Design 1. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad is to be 60 µm minimum, all the way around the pad. Stencil Design 1. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release. 2. The stencil thickness should be 0.125 mm (5 mils). 3. The ratio of stencil aperture to land pad size should be 1:1. Card Assembly 1. A No-Clean, Type-3 solder paste is recommended. 2. The recommended card reflow profile is per the JEDEC/IPC J-STD-020D specification for Small Body Components. Preliminary Rev. 0.6 9 Si535/536 6. Si535/Si536 Mark Specification Figure 5 illustrates the mark specification for the Si535/Si536. Table 13 lists the line information. Figure 5. Mark Specification Table 13. Si53x Top Mark Description Line Position Description 1 1–10 “SiLabs"+ Part Family Number, 53x (First 3 characters in part number where x = 5 indicates a 535 device and x = 6 indicates a 536 device). 2 1–10 Si535, Si536: Option1 + Option2 + Freq(7) + Temp Si535/Si536 w/ 8-digit resolution: Option1 + Option2 + ConfigNum(6) + Temp 3 10 Trace Code Position 1 Pin 1 orientation mark (dot) Position 2 Product Revision (D) Position 3–6 Tiny Trace Code (4 alphanumeric characters per assembly release instructions) Position 7 Year (least significant year digit), to be assigned by assembly site (ex: 2013 = 3) Position 8–9 Calendar Work Week number (1–53), to be assigned by assembly site Position 10 “+” to indicate Pb-Free and RoHS-compliant Preliminary Rev. 0.6 Si535/536 DOCUMENT CHANGE LIST Revision 0.2 to Revision 0.3 Updated Table 7 on page 5. Revision 0.3 to Revision 0.5 Updated Note 1 in Table 2 on page 2. Updated Symmetry Test Condition in Table 3 on page 3. Updated Table 4 on page 4. Updated Table 5 on page 4. Updated XXXMXXX text in Figure 2 on page 7. Updated 4. "Package Outline" on page 8. Revision 0.5 to Revision 0.6 Updated Figure 2 on page 7. Updated Land Pattern information on page 10. 11 Preliminary Rev. 0.6 Si535/536 CONTACT INFORMATION Silicon Laboratories Inc. 400 West Cesar Chavez Austin, TX 78701 Tel: 1+(512) 416-8500 Fax: 1+(512) 416-9669 Toll Free: 1+(877) 444-3032 Please visit the Silicon Labs Technical Support web page: https://www.silabs.com/support/pages/contacttechnicalsupport.aspx and register to submit a technical support request. Patent Notice Silicon Labs invests in research and development to help our customers differentiate in the market with innovative low-power, small size, analogintensive mixed-signal solutions. Silicon Labs' extensive patent portfolio is a testament to our unique approach and world-class engineering team. The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. Silicon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from the use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed features or parameters. Silicon Laboratories reserves the right to make changes without further notice. Silicon Laboratories makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Silicon Laboratories assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. 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