19-1553; Rev 0; 9/99 MAX3831/MAX3832 Evaluation Kits Features ♦ +3.3V Single Supply ♦ On-Board Clock and Data Recovery (CDR) ♦ Fully Assembled and Tested Surface-Mount Board ♦ Loss-of-Frame/Loss-of-Lock Monitors Ordering Information Component Suppliers PHONE FAX PART TEMP. RANGE IC PACKAGE Coilcraft 847-639-6400 847-639-1469 MAX3831EVKIT 0°C to +85°C 64 TQFP-EP* Sprague 207-324-4140 603-224-1430 MAX3832EVKIT 0°C to +85°C 64 TQFP-EP* SUPPLIER Note: Please indicate that you are using the MAX3831 or MAX3832 when contacting these component suppliers. *Exposed paddle Component List DESIGNATION QTY C1 C2–C5, C7–C14, C18, C22, C24–C28, C31–C33, C35, C36, C43–C47, C52–C56, C59–C62 1 38 DESCRIPTION 0.33µF ±10%, 16V min ceramic capacitor (0805) 0.1µF ±10%, 25V min ceramic capacitors (0603) C23 1 1.0µF ±10%, 16V min ceramic capacitor (0805) C29 1 33µF ±10%, 10V min tantalum cap Sprague 293D336X0016D2 C30 1 2.2µF ±10%, 10V min ceramic capacitor (1206) R4, R60 2 390Ω ±5% resistors R30, R33, R36, R39, R71 0 100Ω ±1% resistor (0603)— not placed R28, R29 2 4.99kΩ ±1% resistors DESIGNATION QTY DESCRIPTION R61, R62 0 49.9Ω ±1% resistor (0603)— not placed L1, L2, L4, L5, L6 5 56nH inductors Coilcraft 0805CS-560XKBC D2, D3 2 LEDs J1, J2, J33–J36 6 SMA connectors (PC mount) J7, J8, J15–J32 20 SMB connectors (PC mount) J38 1 2x12 header (0.1in centers) JP3 1 3-pin header (0.1in centers) JP4, JU2, JU3, JU7 4 2-pin headers (0.1in centers) +3.3V, GND 2 Test points U1 1 MAX3831UCBor MAX3832UCB 64-pin TQFP-EP U2 1 MAX3876EHJ (32-pin TQFP) U3 1 74HCT04 None 2 Shunts for JP3 and J38 None 1 MAX3831/MAX3832 PC board None 1 MAX3831/MAX3832 data sheet ________________________________________________________________ Maxim Integrated Products 1 For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800. For small orders, phone 1-800-835-8769. Evaluate: MAX3831/MAX3832 General Description The MAX3831/MAX3832 evaluation kits (EV kits) simplify evaluation of the MAX3831/MAX3832 2.488Gbps interconnect mux/demux ICs with clock generator. The EV kits require only a +3.3V single supply and include all the external components necessary to interface with 3.3V CML and LVDS logic. A parallel data generator or stimulus system can be used with an oscilloscope to evaluate the chip’s complete functionality. A built-in system test (BIST) function allows a system high-speed test. The MAX3831/MAX3832 EV kits contain an on-board clock and data recovery IC (MAX3876EHJ) that is used to generate 2.488Gbps clock and data inputs to the high-speed, CML-compatible serial-input ports. Evaluate: MAX3831/MAX3832 MAX3831/MAX3832 Evaluation Kits Quick Start 1) Apply 3.3V to the +3.3V pin. Connect power-supply ground to GND. 2) Short TEST to ground by tying pins 9 and 10 of J38 together. This places the chip into test mode, with PRBS data transmitted to the serial- and paralleldata output ports. 3) Reset the elastic store buffer by shorting pins 5 and 6 of J38. 4) Remove the jumper from pins 5 and 6 of J38; the LOF indicator (D3) should turn off. 5) Use a high-speed, 50Ω input oscilloscope to monitor PDO_± and SDO± for a proper eye diagram. 50Ω probe, balance the circuit by connecting the other output with a 50Ω terminator to ground. Connecting LVDS Outputs to High-Impedance Oscilloscope Inputs To monitor an LVDS signal with a high-impedance oscilloscope probe, install a 100Ω differential load resistor between the complementary outputs (see R30, R33, R36, R39, R71 in the Component List). Connecting CML Outputs to High-Impedance Oscilloscope Inputs To monitor a CML signal with a high-impedance instrument, install 49.9Ω ±1% pull-up resistors (see R61 and R62 in the Component List) between the respective output lines and VCC. Detailed Description Connecting LVDS Outputs to 50Ω Oscilloscope Inputs To monitor an LVDS signal with a 50Ω oscilloscope probe, leave the coupling capacitors in series with the outputs. If you are observing only one output with a Exposed-Paddle Package The exposed-paddle (EP), 64-pin TQFP incorporates features that provide a very low thermal resistance path for heat removal from the IC. The paddle is electrical ground on the MAX3831/MAX3832 and should be soldered to the circuit board for proper thermal and electrical performance. Table 1. Controls, Test Points, and LEDs NAME TYPE PIN JU2 2-pin header 1, 2 RCLKI± common-mode bias connection. Shorting JU2 to ground sets VCM = 0 (allows a single-ended RCLK± input). JU3 2-pin header 1, 2 LOF test point (before buffering). Do not short. JU7 2-pin header 1, 2 LOF test point (after buffering). Do not short. JP4 2-pin header 1, 2 Loss-of-Lock (LOL) test point. Do not short. 1, 2 Short to enable system-loopback input to CDR. 2, 3 Short to enable serial-data input to CDR. 1, 2 TRIEN—short to enable tristate mode. 3, 4 PLBEN—short to enable parallel-system-loopback mode. 5, 6 RSETES—short to reset elastic store buffers. 7, 8 LBEN—short to enable serial-line-loopback mode. 9, 10 TEST—short to enable BIST mode. 11, 12 N/A 13, 14 N/A 15, 16 RSETFR—short to reset frame-sync circuitry. 17, 18 LOF test point. Do not short. 19, 20 N/A 21, 22 N/A 23, 24 N/A JP3 J38 D2 3-pin header 24-pin header LED 1, 2 DESCRIPTION LOL indicator* LOF indicator *LOL indicates serial data is not locked. Note that the LOL monitor is only valid when a data stream is present on the inputs of the MAX3876. D3 2 LED 1, 2 ________________________________________________________________________________________ J2 SDO+ +3.3V 10 12 14 16 18 20 22 24 9 11 13 15 17 19 21 23 R62 49.9Ω = OPTIONAL COMPONENT J8 PCLKO+ J7 PCLKO- C8 0.1µF 8 7 J1 C47 SDO0.1µF 6 5 R71 100Ω C45 0.1µF SCLK+ SCLK- SDVCC TEST_N SD+ LBEN_N VCCOUT VCCOUT VCC R61 49.9Ω LOF_N RSETFR_N TEST_N LBEN_N RSETES_N PLBEN_N TRIEN_N C44 0.1µF C3 0.1µF 4 3 +3.3V 2 1 1 GND 2 VCC 3 SDO4 SDO+ 5 VCC 6 LBEN 7 TEST 8 SDI+ 9 SDI10 VCC 11 SCLKI+ 12 SCLKI13 VCC 14 PCLKO15 PCLKO+ 16 GND VCC VCC C61 0.1µF R28 4.99k C59 0.1µF C1 0.33µF R29 4.99k C60 0.1µF JU2 J31 RCLKI- VCCPLL J32 RCLKI+ J30 PDI1+ VCC PLBEN_N RSETES_N J29 PDI1- MAX3832 U1 VCC 48 47 RSETFR_N JU3 PDI3+ 46 PDI345 PDI4+ 44 PDI443 GND 42 PDO1+ 41 PDO140 PDO2+ 39 PDO238 VCC 37 PDO3+ 36 PDO335 PDO4+ 34 PDO433 TRIEN J28 PDI2+ VCC 64 GND 63 FIL+ 62 FIL61 GND 60 V CC 59 RSETES 58 RCLKI+ 57 RCLKI56 VCC 55 PLBEN 54 PDI1+ 53 PDI152 PDI2+ 51 PDI250 GND 49 17 VCC 18 N.C. 19 N.C. 20 N.C. 21 N.C. 22 N.C. 23 N.C. 24 VCC 25 GND 26 N.C. 27 N.C. 28 GND 29 GND 30 RSETFR 31 LOF 32 GND 1 2 74HCT04 U3A J26 PDI3+ 13 74HCT04 12 R30 100Ω 1% R39 100Ω 1% U3F LOF_N VCC TRIEN_N J27 PDI2- 0.1µF C13 R36 100Ω 1% J24 PDI4+ JU7 0.1µF C14 J18 PDO3- R33 100Ω C12 1% 0.1µF R4 390Ω J16 PDO4- J15 PDO4+ J17 PDO3+ J20 PDO2- J19 PDO2+ J22 PDO1- J21 PDO1+ C10 0.1µF C9 0.1µF C7 0.1µF C4 0.1µF C5 0.1µF J25 PDI3- D3 J23 PDI4- +3.3V Evaluate: MAX3831/MAX3832 2x12HEADER J38 MAX3831/MAX3832 Evaluation Kits Figure 1. MAX3831/MAX3832 EV Kits Schematic _______________________________________________________________________________________ 3 J34 J33 SDI- SDI+ GND +3.3V +3.3V J50 J49 C11 0.1µF C2 0.1µF 1 C29 2 33µF C32 0.1µF Figure 2. MAX3831/MAX3832 EV Kits Schematic (continued) _______________________________________________________________________________________ J36 J35 GND GND VCC SDI+ SDIVCC SIS GND MAX3876 U2 C22 0.1µF SLBI+ SLBI- JP3 C55 0.1µF VCC SDO+ SDOVCC VCC SCLKO+ SCLKOVCC GND 24 23 22 21 20 19 18 17 VCCCDR C54 0.1µF C43 0.1µF VCCOUT C28 0.1µF 32 31 30 29 28 27 26 25 C27 0.1µF C53 0.1µF VCCVCO VCCPLL C26 0.1µF 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 C52 0.1µF C46 0.1µF C23 1µF C36 0.1µF C35 0.1µF C33 0.1µF C31 0.1µF C25 0.1µF SLBI ENABLE VCCCDR VCCCDR L2 56nH L6 56nH L5 56nH SDI ENABLE C18 0.1µF VCCCDR C30 2.2µF L4 56nH C24 0.1µF 2 VCCCDR GND GND VCC SLBI+ SLBIVCC VCCCDR 1 3 GND FIL+ FILGND PHADJ+ PHADJGND LOL VCC GND VCCCDR 4 L1 56nH ALL DECOUPLING CAPS WILL BE LOCATED NEAR THEIR OUT PINS. VCCCDR VCCCDR VCCCDR R60 390Ω D2 VCCCDR C56 0.1µF JP4 VCC VCCCDR C62 0.1µF SCLK+ SD+ SCLK- SD- Evaluate: MAX3831/MAX3832 MAX3831/MAX3832 Evaluation Kits MAX3831/MAX3832 Evaluation Kits Evaluate: MAX3831/MAX3832 1.0" Figure 3. MAX3831/MAX3832 EV Kits Component Placement Guide—Component Side ________________________________________________________________________________________ 5 Evaluate: MAX3831/MAX3832 MAX3831/MAX3832 Evaluation Kits 1.0" Figure 4. MAX3831/MAX3832 EV Kits PC Board Layout—Component Side 6 _______________________________________________________________________________________ MAX3831/MAX3832 Evaluation Kits Evaluate: MAX3831/MAX3832 1.0" Figure 5. MAX3831/MAX3832 EV Kits PC Board Layout—Solder Side _______________________________________________________________________________________ 7 Evaluate: MAX3831/MAX3832 MAX3831/MAX3832 Evaluation Kits 1.0" Figure 6. MAX3831/MAX3832 EV Kits PC Board Layout—Power Plane 8 _______________________________________________________________________________________ MAX3831/MAX3832 Evaluation Kits Evaluate: MAX3831/MAX3832 1.0" Figure 7. MAX3831/MAX3832 EV Kits PC Board Layout—Ground Plane _______________________________________________________________________________________ 9 Evaluate: MAX3831/MAX3832 MAX3831/MAX3832 Evaluation Kits 1.0" Figure 8. MAX3831/MAX3832 EV Kits Component Placement Guide—Solder Side 10 ______________________________________________________________________________________ MAX3831/MAX3832 Evaluation Kits Evaluate: MAX3831/MAX3832 ______________________________________________________________________________________ 11