19-2607; Rev 0; 10/02 MAX3953 Evaluation Kit Features ♦ Single +3.3V Supply ♦ 9.953Gbps/10.312Gbps Evaluation ♦ Fully Assembled and Tested ♦ Fully Matched with High-Bandwidth SMP Connectors at the Input Component List DESIGNATION QTY Ordering Information DESCRIPTION C1 1 2.2µF ±10% ceramic capacitor (0805) C2, C4, C16 3 0.1µF ±10% ceramic capacitors (0402) C3, C5, C7 3 0.01µF ±10% ceramic capacitors (0402) C6, C10 2 0.1µF ±10% ceramic capacitors (0201) C8 1 33µF ±10% tantalum capacitor, case B C9 1 0.047µF ±10% ceramic capacitor (0402) PART MAX3953EVKIT TEMP RANGE 0oC to +85oC IC PACKAGE 68 QFN Component Suppliers C13, C15 2 0.01µF ±10% ceramic capacitors (0201) PHONE FAX J1, J2, J7–J40 36 SMB connectors AVX 843-448-9411 843-448-1943 SUPPLIER J3, J4 2 SMP698 connectors, edge mount Coilcraft 408-224-8566 408-224-6304 J41, J42 2 Test points Murata 770-436-1300 770-436-3030 J43, J44 2 Do not install JU2 1 10 x 2 pin headers, 0.1in centers L1 1 56nH ±10% inductor (0805) 0805HS-560TKBC R1 1 100Ω ±1% resistor (0402) R5–R16, R18–R22 17 Open TP1, TP2 2 Test points MAX3953UGK 68-pin QFN U1* 1 None 4 Shunts None* 1 MAX3953 EV kit circuit board None* 1 MAX3953 EV kit data sheet None* 1 MAX3953 data sheet *Supplied by Maxim ________________________________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. 1 Evaluates: MAX3953 General Description The MAX3953 evaluation kit (EV kit) is an assembled surface-mount demonstration board that provides easy evaluation of the MAX3953 10Gbps 1:16 deserializer with clock data recovery (CDR). The EV kit includes all components necessary to interface with +3.3V CML inputs and LVDS outputs. Evaluates: MAX3953 MAX3953 Evaluation Kit Quick Start 1) Apply +3.3V to the VCC (J41) pin. Connect powersupply ground to GND (J42). Set the supply current limit to 500mA. 2) Install shunts from pins 1 to 2, 7 to 8, 9 to 10, and 17 to 18, of JU2. 3) Apply a differential input clock from 200mVP-P to 1600mVP-P at 622.08MHz to J1 and J2 (REFCLK+ and REFCLK-). 4) Apply a differential input signal from 100mVP-P to 1600mV P-P at 9.95328Gbps to J3 and J4 (SDI+ and SDI-). 5) Use a 50Ω terminated oscilloscope to monitor the output data on any of the parallel output lines (PDO0± to PDO15±). Monitor the output clock on PCLKO+ and PCLKO-. The oscilloscope should show a 622.08MHz clock output and a 622.08Mbps data output. LVDS outputs must be AC-coupled into the oscilloscope. Detailed Description The MAX3953 EV kit simplifies evaluation of the MAX3953 1:16 deserializer with CDR. The EV kit operates from a single +3.3V supply and includes all the external components necessary to interface with +3.3V CML inputs and LVDS outputs. Transmission-line test structures (J43 to J44) are included on the evaluation board to allow measurement of signal loss and dispersion of clock and data signals at 10GHz. Applications Information Connecting LVDS Outputs to 50Ω Oscilloscope Inputs To monitor LVDS signals with 50Ω oscilloscope inputs, set the inputs of the oscilloscope to “AC-coupling” or place a DC block in series with each output. If you are observing only one output with a 50Ω probe, balance the complementary output with a DC block and a 50Ω terminator to ground. Connecting LVDS Outputs to HighImpedance Oscilloscope Inputs To monitor LVDS signals with high-impedance oscilloscope inputs, install 100Ω (0402) resistors on locations 2 JU2 19 SYNC_ERR GND CLKSEL VCC GND REFSET VCC GND RATESET VCC 3 GND 1 VCC LOS_IN Figure 1. JU2 Header Configuration R5–R16 and R18–R22. Note that this does not provide as good a termination scheme as using the 50Ω inputs on an oscilloscope, which degrades the resulting output. Exposed-Pad Package The 68-pin QFN package with exposed pad incorporates features that provide a very low thermal-resistance path for heat removal from the IC, either to a PC board or to an external heatsink. The exposed pad on the MAX3953 must be soldered directly to a ground plane with good thermal conductance. Configuration for JU2 The 10 × 2 header (JU2) provides control for the input configuration of the MAX3953. Figure 1 shows the control structure for the JU2 header. _______________________________________________________________________________________ MAX3953 Evaluation Kit SYNC_ERR, LOS_IN, and CLKSEL pins. CLKSEL is an input signal used to select the VCO to lock on to incoming data (SDI) or the reference clock (REFCLK). Connecting SYNC_ERR to CLKSEL (pin 17 to 18 on JU2) activates the holdover mode. Adjustment and Control Description (see Quick Start first) COMPONENT NAME FUNCTION JU2 CLKSEL Output Clock Selector, TTL. CLKSEL is the control input for clock holdover. When CLKSEL = GND, PCLKO is derived from the input data. When CLKSEL = VCC, PCLKO is derived from the reference clock. JU2 REFSET Reference Clock Select Input, TTL. When the reference clock is 155MHz/161MHz, set REFSET to GND. When the reference clock is 622MHz/644MHz then set REFSET to VCC. JU2 RATESET Serial Data Rate Select Input, TTL. When the input serial data stream is 9.953Gbps, set RATESET to GND. When the input serial data stream is 10.312Gbps, set RATESET to VCC. JU2 LOS_IN Loss-of-Signal Input, TTL. The LOS_IN is an external input. Clock holdover is activated when LOS_IN is TTL low. (See the Clock Holdover section.) TP1 SYNC_ERR TP2 LOL Synchronization Error Output, TTL. SYNC_ERR is intended to drive CLKSEL for holdover mode. (See the Clock Holdover section.) Loss-of-Lock Indicator Output, TTL. LOL signals a TTL low when the VCO frequency is more than 1000ppm from the reference clock frequency. LOL signals a TTL high when the VCO frequency is within 500ppm of the reference clock frequency. (See the Clock Holdover section.) _______________________________________________________________________________________ 3 Evaluates: MAX3953 Clock Holdover The clock holdover mode of the MAX3953 is designed to provide an accurate parallel clock in the event of a loss-of-lock (LOL) or loss-of-signal (LOS) condition. The activation of the holdover mode is controlled by the Figure 2. MAX3953 EV Kit Schematic _______________________________________________________________________________________ GND VCC J42 J41 LOS_IN RATESET REFSET CLKSEL 3 1 2 7 8 4 9 10 5 11 12 6 13 14 17 19 15 C8 33µF JU2 16 18 20 J3 SMB J2 SMB J1 SMB C1 2.2µF L1 50nH VCC VCC VCC VCC SYNC_ERR J4 SMB C6 0.1µF REFSET C4 0.1µF C2 0.1µF C3 0.01µF VCC VCC VCC VCC VCC C10 0.1µF VCC R1 100Ω VCC C5 0.01µF 18 GND VCC VCC GND VCC VCC VCC SDI- SDI+ VCC REFSET GND GND GND REFCLK- REFCLK+ GND LOS_IN 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 FIL C7 0.01µF 19 LOS_IN 66 LOL TP2 20 65 64 63 62 22 R5 OPEN C13 0.01µF 24 R6 OPEN 61 R21 OPEN C16 0.1µF J9 J10 SMB SMB 23 C15 0.01µF J7 J8 SMB SMB 21 RATESET PCLKO+ 67 PDO0PCLKO- 68 VCC LOL R22 OPEN MAX3953 U1 26 R7 OPEN J11 J12 SMB SMB 25 60 59 VCC VCC 27 58 57 R20 OPEN 56 55 R19 OPEN 54 53 R18 OPEN 29 R8 OPEN J13 J14 SMB SMB 28 31 R9 OPEN J15 J16 SMB SMB 30 33 R10 OPEN J17 J18 SMB SMB 32 PD02PD013+ VCC PD00+ PD015+ J32 J31 SMB SMB PD02+ PD013- VCC PD01PD015- J34 J33 SMB SMB PD03PD012+ C9 0.047µF VCC J36 J35 SMB SMB PD03+ PD012- J38 J37 SMB SMB PD04PD011+ J40 J39 SMB SMB PD04+ PD011- RATESET PD01+ PD014+ GND GND GND PD014- 52 GND 34 GND PDO10+ PDO10- PDO9+ PDO9- PDO8+ PDO8- VCC PDO7+ PDO7- PDO6+ PDO6- PDO5+ PDO5- SYNC_ERR CLKSEL GND GND 4 VCC 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 R11 OPEN R12 OPEN R13 OPEN J20 SMB J22 SMB J24 SMB J26 SMB J28 SMB J19 SMB J21 SMB J23 SMB J25 SMB J27 SMB J29 SMB SYNC_ERR J30 SMB TP1 VCC R14 OPEN R15 OPEN R16 OPEN CLKSEL Evaluates: MAX3953 MAX3953 Evaluation Kit MAX3953 Evaluation Kit Evaluates: MAX3953 1.0" Figure 3. MAX3953 EV Kit Component Placement Guide—Component Side _______________________________________________________________________________________ 5 Evaluates: MAX3953 MAX3953 Evaluation Kit 1.0" 1.0" Figure 4. MAX3953 EV Kit PC Board Layout—Component Side 1.0" Figure 5. MAX3953 EV Kit PC Board Layout—Ground Plane 1.0" Figure 6. MAX3953 EV Kit PC Board Layout—Power Plane Figure 7. MAX3953 EV Kit PC Board Layout—Solder Side Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 6 _____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 2002 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.