W39F010 128K × 8 CMOS FLASH MEMORY Table of Contents1. GENERAL DESCRIPTION ......................................................................................................... 3 2. FEATURES ................................................................................................................................. 3 3. PIN CONFIGURATIONS ............................................................................................................ 4 4. BLOCK DIAGRAM ...................................................................................................................... 5 5. PIN DESCRIPTION..................................................................................................................... 6 6. FUNCTIONAL DESCRIPTION ................................................................................................... 7 6.1 6.1.1 Read Mode ...............................................................................................................7 6.1.2 Write Mode ...............................................................................................................7 6.1.3 Standby Mode ..........................................................................................................7 6.1.4 Output Disable Mode ................................................................................................7 6.2 Data Protection ............................................................................................................... 7 6.3 Boot Block Operation...................................................................................................... 8 6.4 6.5 7. Device Bus Operation..................................................................................................... 7 6.3.1 Low VDD Inhibit ........................................................................................................8 6.3.2 Write Pulse "Glitch" Protection .................................................................................8 6.3.3 Logical Inhibit............................................................................................................8 6.3.4 Power-up Write Inhibit ..............................................................................................8 Command Definitions ..................................................................................................... 8 6.4.1 Read Command .......................................................................................................9 6.4.2 Auto-select Command ..............................................................................................9 6.4.3 Byte Program Command ..........................................................................................9 6.4.4 Chip Erase Command ............................................................................................10 6.4.5 Page Erase Command ...........................................................................................10 Write Operation Status ................................................................................................. 10 6.5.1 DQ7: Data Polling...................................................................................................10 6.5.2 DQ6: Toggle Bit ......................................................................................................11 TABLE OF OPERATING MODES ............................................................................................ 12 7.1 Device Bus Operations ................................................................................................. 12 7.2 Command Definitions ................................................................................................... 12 7.3 Embedded Programming Algorithm ............................................................................. 14 7.4 Embedded Erase Algorithm.......................................................................................... 15 7.5 Embedded #Data Polling Algorithm.............................................................................. 16 7.6 Boot Block Lockout Enable Flow Chart ........................................................................ 17 7.7 Software Product Identification and Boot Block Lockout Detection Flow Chart........... 18 -1- Publication Release Date: December 26, 2005 Revision A4 W39F010 8. 9. 10. DC CHARACTERISTICS.......................................................................................................... 19 8.1 Absolute maximum Ratings .......................................................................................... 19 8.2 DC Operating Characteristics....................................................................................... 19 8.3 Pin Capacitance............................................................................................................ 19 AC CHARACTERISTICS .......................................................................................................... 20 9.1 AC Test Conditions....................................................................................................... 20 9.2 AC Test Load and Waveform ....................................................................................... 20 9.3 Read Cycle Timing Parameters.................................................................................... 21 9.4 Write Cycle Timing Parameters.................................................................................... 21 9.5 Power-up Timing........................................................................................................... 22 9.6 Data Polling and Toggle Bit Timing Parameters .......................................................... 22 TIMING WAVEFORMS ............................................................................................................. 23 10.1 Read Cycle Timing Diagram......................................................................................... 23 10.2 #WE Controlled Command Write Cycle Timing Diagram............................................. 23 10.3 #CE Controlled Command Write Cycle Timing Diagram.............................................. 24 10.4 Chip Erase Timing Diagram ......................................................................................... 24 10.5 Page Erase Timing Diagram ........................................................................................ 25 10.6 #DATA Polling Timing Diagram .................................................................................... 25 10.7 Toggle Bit Timing Diagram ........................................................................................... 26 11. ORDERING INFORMATION .................................................................................................... 27 12. HOW TO READ THE TOP MARKING...................................................................................... 28 13. PACKAGE DIMENSIONS ......................................................................................................... 29 14. 13.1 32-pin P-DIP ................................................................................................................. 29 13.2 32-pin TSOP (8 x 20 mm)............................................................................................. 30 13.3 32-pin PLCC ................................................................................................................. 31 13.4 32-pin STSOP (8 x 14 mm) .......................................................................................... 31 VERSION HISTORY ................................................................................................................. 32 -2- W39F010 1. GENERAL DESCRIPTION The W39F010 is a 1Mbit, 5-volt only CMOS flash memory organized as 128K × 8 bits. For flexible erase capability, the 1Mbits of data are divided into 32 small even pages with 4 Kbytes. The byte-wide (× 8) data appears on DQ7 − DQ0. The device can be programmed and erased in-system with a standard 5V power supply. A 12-volt VPP is not required. The unique cell architecture of the W39F010 results in fast program/erase operations with extremely low current consumption (compared to other comparable 5-volt flash memory products). The device can also be programmed and erased by using standard EPROM programmers. 2. y y FEATURES Single 5-volt operations − 5-volt Read − 5-volt Erase − 5-volt Program Fast Program operation: − y Byte-by-Byte programming: 50 μS (max.) Fast Erase operation: − Chip Erase cycle time: 100 mS (max.) − Page Erase cycle time: 25 mS (max.) y Read access time: 70/90 nS y 32 even pages with 4K bytes y Any individual page can be erased y Hardware protection: − Optional 16K byte Top/Bottom Boot Block with lockout protection y Flexible 4K-page size can be used as Parameter Blocks y Typical program/erase cycles: − 1K/10K y Twenty-year data retention y Low power consumption y − Active current: 15 mA (typ.) − Standby current: 15 μA (typ.) End of program detection − Software method: Toggle bit/Data polling y TTL compatible I/O y JEDEC standard byte-wide pinouts y Available packages: 32-pin 600 mil DIP, 32-pin PLCC, 32- pin STSOP (8 x 14 mm) and 32- pin TSOP -3- Publication Release Date: December 26, 2005 Revision A4 W39F010 3. PIN CONFIGURATIONS A11 A9 A8 A13 A14 NC #WE 1 2 V DD NC A16 A15 A12 A7 A6 A5 A4 8 NC 1 32 V DD A16 2 31 #WE A15 3 30 NC A12 4 29 A14 A7 5 28 A13 A6 6 27 A8 A5 7 26 A9 A4 8 A3 32-pin DIP 25 A11 9 24 #OE A2 10 23 A10 A1 11 22 #CE A0 12 21 DQ7 DQ0 13 20 DQ6 DQ1 14 19 DQ5 DQ2 15 18 DQ4 Vss 16 17 DQ3 A 1 2 A 1 5 A 1 6 N C V D D # W E N C 4 3 2 1 32 31 30 A7 5 29 A14 A6 6 28 A13 A5 7 27 A8 A4 8 A3 9 A2 A1 32-pin PLCC 26 A9 25 A11 10 24 #OE 11 23 A10 A0 12 22 #CE DQ0 13 21 DQ7 14 15 16 17 18 19 20 D Q 1 D Q 2 V S S D Q 3 D Q 4 D Q 5 D Q 6 32 31 3 30 4 5 29 28 6 27 7 26 25 9 10 32-pin TSOP 24 23 11 12 22 13 20 19 21 14 15 18 17 16 -4- #OE A10 #CE DQ7 DQ6 DQ5 DQ4 DQ3 Vss DQ2 DQ1 DQ0 A0 A1 A2 A3 Publication Release Date: December 26, 2005 Revision A4 W39F010 4. BLOCK DIAGRAM DQ0 - DQ7 VDD Vss Erase Voltage Input / output Generator #WE Buffers State Control Command Register Program Voltage Generator Chip Enable Output Enable Logic #CE #OE Data latch VDD Detect Timer A 0 - A16 A d d r e s s L a t c h Y-Decode Y-MUX / SENSING X-decode ARRAY -5- Publication Release Date: December 26, 2005 Revision A4 W39F010 5. PIN DESCRIPTION SYMBOL PIN NAME A0 − A16 Address Inputs DQ0 − DQ7 Data Inputs/Outputs #CE Chip Enable #OE Output Enable #WE Write Enable VDD Power Supply VSS Ground NC No Connections -6- W39F010 6. FUNCTIONAL DESCRIPTION 6.1 6.1.1 Device Bus Operation Read Mode The read operation of the W39F010 is controlled by #CE and #OE, both of which have to be low for the host to obtain data from the outputs. #CE is used for device selection. When #CE is high, the chip is de-selected and only standby power will be consumed. #OE is the output control and is used to gate data from the output pins. The data bus is in high impedance state when either #CE or #OE is high. Refer to the timing waveforms for further details. 6.1.2 Write Mode Device erasure and programming are accomplished via the command register. The contents of the register serve as inputs to the internal state machine. The state machine outputs dictate the function of the device. The command register itself does not occupy any addressable memory location. The register is a latch used to store the commands, along with the address and data information needed to execute the command. The command register is written to bring #WE to logic low state, while #CE is at logic low state and #OE is at logic high state. Addresses are latched on the falling edge of #WE or #CE, whichever happens later; while data is latched on the rising edge of #WE or #CE, whichever happens first. Standard microprocessor write timings are used. Refer to AC Write Characteristics and the Erase/Programming Waveforms for specific timing parameters. 6.1.3 Standby Mode There are two ways to implement the standby mode on the W39F010 device, both using the #CE pin. A CMOS standby mode is achieved with the #CE input held at VDD ±0.5V. Under this condition the current is typically reduced to less than 50 μA. A TTL standby mode is achieved with the #CE pin held at VIH. Under this condition the current is typically reduced to 2 mA. In the standby mode the outputs are in the high impedance state, independent of the #OE input. 6.1.4 Output Disable Mode With the #OE input at a logic high level (VIH), output from the device is disabled. This will cause the output pins to be in a high impedance state. 6.2 Data Protection The W39F010 is designed to offer protection against accidental erasure or programming caused by spurious system level signals that may exist during power transitions. During power up the device automatically resets the internal state machine in the Read mode. Also, with its control register architecture, alteration of the memory contents only occurs after successful completion of specific multi-bus cycle command sequences. The device also incorporates several features to prevent inadvertent write cycles resulting from VDD power-up and power-down transitions or system noise. -7- Publication Release Date: December 26, 2005 Revision A4 W39F010 6.3 Boot Block Operation There are two alternatives to set the boot block. The 16K-byte in the top/bottom location of this device can be locked as boot block, which can be used to store boot codes. It is located in the last 16K bytes or first 16K bytes of the memory with the address range from 1C000(hex) to 1FFFF(hex) for top location or 00000(hex) to 03FFF(hex) for bottom location. See Command Codes for Boot Block Lockout Enable for the specific code. Once this feature is set the data for the designated block cannot be erased or programmed (programming lockout), other memory locations can be changed by the regular programming method. In order to detect whether the boot block feature is set on the first/last 16K-byte block or not, users can perform software command sequence: enter the product identification mode (see Command Codes for Identification/Boot Block Lockout Detection for specific code), and then read from address 0002(hex) for first(bottom) location or 1FFF2(hex) for last(top) location. If the DQ0/DQ1 of output data is "1," the 16Kbytes boot block programming lockout feature will be activated; if the DQ0/DQ1 of output data is "0," the lockout feature will be inactivated and the block can be erased/programmed. To return to normal operation, perform a three-byte command sequence (or an alternate single-byte command) to exit the identification mode. For the specific code, see Command Codes for Identification/Boot Block Lockout Detection. 6.3.1 Low VDD Inhibit To avoid initiation of a write cycle during VDD power-up and power-down, the W39F010 locks out when VDD < 2.0V (see DC Characteristics section for voltages). The write and read operations are inhibited when VDD is less than 2.0V typical. The W39F010 ignores all write and read operations until VDD > 2,0V. The user must ensure that the control pins are in the correct logic state when VDD > 2.0V to prevent unintentional writes. 6.3.2 Write Pulse "Glitch" Protection Noise pulses of less than 10 nS (typical) on #OE, #CE, or #WE will not initiate a write cycle. 6.3.3 Logical Inhibit Writing is inhibited by holding any one of #OE = VIL, #CE = VIH, or #WE = VIH. To initiate a write cycle #CE and #WE must be a logical zero while #OE is a logical one. 6.3.4 Power-up Write Inhibit Power-up of the device with #WE = #CE = VIL and #OE = VIH will not accept commands on the rising edge of #WE except 5mS delay (see the power up timing in AC Characteristics). The internal state machine is automatically reset to the read mode on power-up. 6.4 Command Definitions Device operations are selected by writing specific address and data sequences into the command register. Writing incorrect address and data values or writing them in the improper sequence will reset the device to the read mode. "Command Definitions" defines the valid register command sequences. -8- W39F010 6.4.1 Read Command The device will automatically power-up in the read state. In this case, a command sequence is not required to read data. Standard microprocessor read cycles will retrieve array data. This default value ensures that no spurious alteration of the memory content occurs during the power transition. The device will automatically returns to read state after completing an Embedded Program or Embedded Erase algorithm. Refer to the AC Read Characteristics and Waveforms for the specific timing parameters. 6.4.2 Auto-select Command Flash memories are intended for use in applications where the local CPU can alter memory contents. As such, manufacture and device codes must be accessible while the device resides in the target system. The device contains an auto-select command operation to supplement traditional PROM programming methodology. The operation is initiated by writing the auto-select command sequence into the command register. Following the command write, a read cycle from address XX00H retrieves the manufacture code of DAH. A read cycle from address XX01H returns the device code (W39F010 = A1). To terminate the operation, it is necessary to write the auto-select exit command sequence into the register. 6.4.3 Byte Program Command The device is programmed on a byte-by-byte basis. Programming is a four-bus-cycle operation. The program command sequence is initiated by writing two "unlock" write cycles, followed by the program set-up command. The program address and data are written next, which in turn initiate the Embedded program algorithm. Addresses are latched on the falling edge of #CE or #WE, whichever happens later and the data is latched on the rising edge of #CE or #WE, whichever happens first. The rising edge of #CE or #WE (whichever happens first) begins programming using the Embedded Program Algorithm. Upon executing the algorithm, the system is not required to provide further controls or timings. The device will automatically provide adequate internally generated program pulses and verify the programmed cell margin. The automatic programming operation is completed when the data on DQ7 (also used as Data Polling) is equivalent to the data written to this bit at which time the device returns to the read mode and addresses are no longer latched (see "Hardware Sequence Flags"). Therefore, the device requires that a valid address to the device be supplied by the system at this particular instance of time for Data Polling operations. Data Polling must be performed at the memory location which is being programmed. Any commands written to the chip during the Embedded Program Algorithm will be ignored. If a hardware reset occurs during the programming operation, the data at that particular location will be corrupted. Programming is allowed in any sequence and across page boundaries. Beware that a data "0" cannot be programmed back to a "1". Attempting to program 0 back to 1, the toggle bit will stop toggling. Only erase operations can convert "0"s to "1"s. Refer to the Programming Command Flow Chart using typical command strings and bus operations. -9- Publication Release Date: December 26, 2005 Revision A4 W39F010 6.4.4 Chip Erase Command Chip erase is a six-bus-cycle operation. There are two "unlock" write cycles, followed by writing the "set-up" command. Two more "unlock" write cycles are asserted, followed by the chip erase command. Chip erase does not require the user to program the device prior to erase. Upon executing the Embedded Erase Algorithm command sequence the device will automatically erase and verify the entire memory for an all one data pattern. The erase is performed sequentially on each pages at the same time (see "Feature"). The system is not required to provide any controls or timings during these operations. The automatic erase begins on the rising edge of the last #WE pulse in the command sequence and terminates when the data on DQ7 is "1" at which time the device returns to read the mode. Refer to the Erase Command Flow Chart using typical command strings and bus operations. 6.4.5 Page Erase Command Page erase is a six-bus cycles operation. There are two "unlock" write cycles, followed by writing the "set-up" command. Two more "unlock" write cycles then follows by the page erase command. The page address (any address location within the desired page) is latched on the falling edge of #WE, while the command (50H) is latched on the rising edge of #WE. Page erase does not require the user to program the device prior to erase. When erasing a page, the remaining unselected pages are not affected. The system is not required to provide any controls or timings during these operations. The automatic page erase begins after the erase command is completed, right from the rising edge of the #WE pulse for the last page erase command pulse and terminates when the data on DQ7, Data Polling, is "1" at which time the device returns to the read mode. Data Polling must be performed at an address within any of the pages being erased. Refer to the Erase Command flow Chart using typical command strings and bus operations. 6.5 6.5.1 Write Operation Status DQ7: Data Polling The W39F010 device features Data Polling as a method to indicate to the host that the embedded algorithms are in progress or completed. During the Embedded Program Algorithm, an attempt to read the device will produce the complement of the data last written to DQ7. Upon completion of the Embedded Program Algorithm, an attempt to read the device will produce the true data last written to DQ7. During the Embedded Erase Algorithm, an attempt to read the device will produce a "0" at the DQ7 output. Upon completion of the Embedded Erase Algorithm, an attempt to read the device will produce a "1" at the DQ7 output. For chip erase, the Data Polling is valid after the rising edge of the sixth pulse in the six #WE write pulse sequences. For page erase, the Data Polling is valid after the last rising edge of the page erase #WE pulse. Data Polling must be performed at addresses within any of the pages being erased. Otherwise, the status may not be valid. - 10 - W39F010 Just prior to the completion of Embedded Algorithm operations DQ7 may change asynchronously while the output enable (#OE) is asserted low. This means that the device is driving status information on DQ7 at one instant of time and then that byte′s valid data at the next instant of time. Depending on when the system samples the DQ7 output, it may read the status or valid data. Even if the device has completed the Embedded Algorithm operations and DQ7 has a valid data, the data outputs on DQ0– DQ6 may be still invalid. The valid data on DQ0 − DQ7 will be read on the successive read attempts. The Data Polling feature is only active during the Embedded Programming Algorithm, Embedded Erase Algorithm, or page erase time-out (see "Command Definitions"). 6.5.2 DQ6: Toggle Bit The W39F010 also features the "Toggle Bit" as a method to indicate to the host system that the embedded algorithms are in progress or completed. During an Embedded Program or Erase Algorithm cycle, successive attempts to read (#OE toggling) data from the device at any address will result in DQ6 toggling between one and zero. Once the Embedded Program or Erase Algorithm cycle is completed, DQ6 will stop toggling and valid data will be read on the next successive attempt. During programming, the Toggle Bit is valid after the rising edge of the fourth #WE pulse in the four write pulse sequence. For chip erase, the Toggle Bit is valid after the rising edge of the sixth #WE pulse in the six write pulse sequence. For page erase, the Toggle Bit is valid after the last rising edge of the page erase #WE pulse. The Toggle Bit is active during the page erase time-out. Either #CE or #OE toggling will cause DQ6 to toggle. - 11 - Publication Release Date: December 26, 2005 Revision A4 W39F010 7. TABLE OF OPERATING MODES 7.1 Device Bus Operations PIN MODE #CE #OE #WE DQ0 − DQ7 Read VIL VIL VIH Dout Write VIL VIH VIL Din Standby VIH X X High Z X VIL X High Z/Dout X X VIH High Z/Dout VIL VIH VIH High Z Write Inhibit Output Disable 7.2 Command Definitions COMMAND NO. OF 1ST CYCLE 2ND CYCLE 3RD CYCLE 4TH CYCLE 5TH CYCLE 6TH CYCLE 7TH CYCLE Description Cycles Addr. Data Addr. Data (1) Read 1 AIN Chip Erase 6 5555 Addr. Data Addr. Data Addr. Data Addr. Data Addr. Data DOUT AA 2AAA 55 5555 80 5555 AA 2AAA 55 5555 10 2AAA 55 PA (3) 50 Page Erase 6 5555 AA 2AAA 55 5555 80 5555 AA Byte Program 4 5555 AA 2AAA 55 5555 A0 AIN DIN Top Boot Block Lockout –16KByte 6 5555 AA 2AAA 55 5555 80 5555 AA 2AAA 55 5555 70 1FFFF XX(4) Bottom Boot Block Lockout - 16KByte 6 5555 AA 2AAA 55 5555 80 5555 AA 2AAA 55 5555 70 00000 XX(4) Product ID Entry 3 5555 AA 2AAA 55 5555 90 2AAA 55 5555 F0 Product ID Exit (2) 3 5555 AA Product ID Exit (2) 1 XXXX F0 Notes: 1. Address Format: A14 − A0 (Hex); Data Format: DQ7 − DQ0 (Hex) 2. Either one of the two Product ID Exit commands can be used. 3. PA: Page Address - 12 - W39F010 PA = 1FXXXh for Page 31 PA = 0FXXXh for Page 15 PA = 1EXXXh for Page 30 PA = 0EXXXh for Page 14 PA = 1DXXXh for Page 29 PA = 0DXXXh for Page 13 PA = 1CXXXh for Page 28 PA = 0CXXXh for Page 12 PA = 1BXXXh for Page 27 PA = 0BXXXh for Page 11 PA = 1AXXXh for Page 26 PA = 0AXXXh for Page 10 PA = 19XXXh for Page 25 PA = 09XXXh for Page 9 PA = 18XXXh for Page 24 PA = 08XXXh for Page 8 PA = 17XXXh for Page 23 PA = 07XXXh for Page 7 PA = 16XXXh for Page 22 PA = 06XXXh for Page 6 PA = 15XXXh for Page 21 PA = 05XXXh for Page 5 PA = 14XXXh for Page 20 PA = 04XXXh for Page 4 PA = 13XXXh for Page 19 PA = 03XXXh for Page 3 PA = 12XXXh for Page 18 PA = 02XXXh for Page 2 PA = 11XXXh for Page 17 PA = 01XXXh for Page 1 PA = 10XXXh for Page 16 PA = 00XXXh for Page 0 4. XX: Don't care - 13 - Publication Release Date: December 26, 2005 Revision A4 W39F010 7.3 Embedded Programming Algorithm Start Write Program Command Sequence (see below) #Data Polling/ Toggle bit No Increment Address Last Address ? Yes Programming Completed Program Command Sequence (Address/Command): 5555H/AAH 2AAAH/55H 5555H/A0H Program Address/Program Data - 14 - Pause T BP W39F010 7.4 Embedded Erase Algorithm Start Write Erase Command Sequence (see below) #Data Polling or Toggle Bit Successfully Completed Pause T EC /T PEC Erasure Completed Chip Erase Command Sequence (Address/Command): Individual Page Erase Command Sequence (Address/Command): 5555H/AAH 5555H/AAH 2AAAH/55H 2AAAH/55H 5555H/80H 5555H/80H 5555H/AAH 5555H/AAH 2AAAH/55H 2AAAH/55H 5555H/10H Page Address/50H - 15 - Publication Release Date: December 26, 2005 Revision A4 W39F010 7.5 Embedded #Data Polling Algorithm Start Read Byte (DQ0 - DQ7) Address = VA No VA = Byte address for programming = Any of the page addresses within the page being erased during page erase operation =Any of the device addresses being erased during chip operation DQ7 = Data ? Yes Pass Embedded Toggle Bit Algorithm Start Read Byte (DQ0 - DQ7) Address = Don't Care Yes DQ6 = Toggle ? No Pass - 16 - W39F010 7.6 Boot Block Lockout Enable Flow Chart Boot Block Lockout Feature Set Flow Load data AA to address 5555 Load data 55 to address 2AAA Pause T BP Load data 80 to address 5555 Exit Load data AA to address 5555 Load data 55 to address 2AAA Load data 70 to address 5555 Load data XX to address 1FFFF/0 70 to lock 16K Boot Block 1FFFF(XX) to lock Top Boot Block 00000(XX) to lock Bottom Boot Block - 17 - Publication Release Date: December 26, 2005 Revision A4 W39F010 7.7 Software Product Identification and Boot Block Lockout Detection Flow Chart Product Identification Entry (1) Load data AA to address 5555 Product Identification and Boot Block Lockout Detection Mode (3) Load data 55 to address 2AAA Read address = 0000 data = DA Load data 90 to address 5555 Read address = 0001 data = A1 Pause 10 μS Read address=02/1FFF2 for Bottom/Top data: in DQ1="1" or "0" for 16K Boot Block Product Identification Exit(6) Load data AA to address 5555 (2) Load data 55 to address 2AAA (2) Load data F0 to address 5555 (4) Pause 10 μS (5) Normal Mode Notes for software product identification/boot block lockout detection: (1) Data Format: DQ7−DQ0 (Hex); Address Format: A14−A0 (Hex) (2) A1−A16 = VIL; manufacture code is read for A0 = VIL; device code is read for A0 = VIH. (3) The device does not remain in identification and boot block lockout detection mode if power down. (4) If the output data in DQ0 or DQ1= " 1 " the boot block programming lockout feature is activated; if the output data in DQ0 or DQ1= " 0 ," the lockout feature is inactivated and the matched boot block can be programmed. (5) The device returns to standard operation mode. (6) Optional 1-byte cycle (write F0 hex at XXXX address) can be used to exit the product identification/boot block lockout detection. - 18 - W39F010 8. DC CHARACTERISTICS 8.1 Absolute maximum Ratings PARAMETER RATING UNIT -2.0 to +7.0 V 0 to +70 °C Storage Temperature -65 to +125 °C Voltage on Any Pin to Ground Potential Except A9 -2.0 to +7.0 V Voltage on A9 Pin to Ground Potential -2.0 to +13.0 V Power Supply Voltage to VSS Potential Operating Temperature Note: Exposure to conditions beyond those listed under Absolute maximum Ratings may adversely affect the life and reliability of the device. 8.2 DC Operating Characteristics (VDD = 5V ±0.5V, VSS = 0V, TA = 0 to 70° C) PARAMETER SYM. LIMITS TEST CONDITIONS MIN. TYP. #CE = #OE = VIL, #WE = VIH, all DQs open Address inputs = VIL/VIH, at f = 5 MHz Power Supply Current IDD Standby VDD ISB1 #CE = VIH, all DQs open Current (TTL input) Standby VDD Current (CMOS input) Other inputs = VIL/VIH ISB2 #CE = VDD -0.3V, all DQs open Other inputs = VDD -0.3V/ VSS UNIT MAX. - 15 30 - 1 2 - 15 50 mA mA μA Input Leakage Current ILI VIN = VSS to VDD - - 1 μA Output Leakage Current ILO VOUT = VSS to VDD - - 1 μA Input Low Voltage VIL - -0.3 - 0.8 V Input High Voltage VIH - 2.0 - VDD +0.5 V Output Low Voltage VOL - - 0.45 V Output High Voltage VOH IOH = -0.4 mA 2.4 - - V 8.3 IOL = 2.1 mA Pin Capacitance (VDD = 5V, TA = 25° C, f = 1 MHz) PARAMETER SYMBOL Input Capacitance CIN Output Capacitance COUT CONDITIONS TYP. MAX. UNIT VIN = 0V 6 8 pF VOUT = 0V 10 12 pF - 19 - Publication Release Date: December 26, 2005 Revision A4 W39F010 9. AC CHARACTERISTICS 9.1 AC Test Conditions PARAMETER CONDITIONS Input Pulse Levels 0V to 3V Input Rise/Fall Time <5 nS Input/Output Timing Level 1.5V/1.5V Output Load 1 TTL Gate and CL = 30 pF 9.2 AC Test Load and Waveform +5V 1.8K Ω 1.3K Ω D OUT 30 pF (Including Jig and Scope) Input Output 3V 1.5V 1.5V 0V Test Point - 20 - Test Point W39F010 AC Characteristics, continued 9.3 Read Cycle Timing Parameters (VDD = 5V ±0.5V, VSS = 0V, TA = 0 to 70° C) PARAMETER SYMBOL W39F010-70 W39F010-90 MIN. MAX. MIN. MAX. UNIT Read Cycle Time TRC 70 - 90 - nS Chip Enable Access Time TCE - 70 - 90 nS Address Access Time TAA - 70 - 90 nS Output Enable Access Time TOE - 35 - 45 nS #CE Low to Active Output TCLZ 0 - 0 - nS #OE Low to Active Output TOLZ 0 - 0 - nS #CE High to High-Z Output TCHZ - 25 - 25 nS #OE High to High-Z Output TOHZ - 25 - 25 nS Output Hold from Address Change TOH 0 - 0 - nS 9.4 Write Cycle Timing Parameters PARAMETER SYMBOL MIN. TYP. MAX. UNIT Address Setup Time TAS 0 - - nS Address Hold Time TAH 40 - - nS #WE and #CE Setup Time TCS 0 - - nS #WE and #CE Hold Time TCH 0 - - nS #OE High Setup Time TOES 0 - - nS #OE High Hold Time TOEH 0 - - nS #CE Pulse Width TCP 100 - - nS #WE Pulse Width TWP 100 - - nS #WE High Width TWPH 100 - - nS Data Setup Time TDS 40 - - nS Data Hold Time TDH 10 - - nS Byte programming Time TBP - 35 50 μS Chip Erase Cycle Time TEC - 50 100 mS Page Erase Cycle Time TEP - 12.5 25 mS Note: All AC timing signals observe the following guidelines for determining setup and hold times: (a) High level signal's reference level is VIH and (b) low level signal's reference level is VIL. - 21 - Publication Release Date: December 26, 2005 Revision A4 W39F010 AC Characteristics, Continued 9.5 Power-up Timing PARAMETER SYMBOL TYPICAL UNIT Power-up to Read Operation TPU. READ 100 μS Power-up to Write Operation TPU. WRITE 5 mS 9.6 Data Polling and Toggle Bit Timing Parameters PARAMETER W39F010-70 SYM. W39F010-90 MIN. MAX. MIN. MAX. UNIT #OE to Data Polling Output Delay TOEP - 35 - 45 nS #CE to Data Polling Output Delay TCEP - 70 - 90 nS #OE to Toggle Bit Output Delay TOET - 35 - 45 nS #CE to Toggle Bit Output Delay TCET - 70 - 90 nS - 22 - W39F010 10. TIMING WAVEFORMS 10.1 Read Cycle Timing Diagram TRC Address A16-0 TCE #CE TOE #OE TOHZ TOLZ VIH #WE TCLZ TOH TCHZ High-Z High-Z DQ7-0 Data Valid Data Valid TAA 10.2 #WE Controlled Command Write Cycle Timing Diagram TAS TAH Address A16-0 #CE TCS TCH TOES TOEH #OE TWP #WE TWPH TDS DQ7-0 Data Valid TDH - 23 - Publication Release Date: December 26, 2005 Revision A4 W39F010 Timing Waveforms, Continued 10.3 #CE Controlled Command Write Cycle Timing Diagram T AS T AH Address A16-0 T CPH T CP #CE T OES T OEH #OE #WE T DS DQ7-0 High Z Data Valid T DH 10.4 Chip Erase Timing Diagram Six-byte code for 5V-only software chip erase Address A16-0 DQ7-0 5555 2AAA 55 AA 5555 5555 80 AA 2AAA 55 5555 10 #CE #OE TWP TEC #WE TWPH SB0 SB1 SB2 SB3 - 24 - SB4 SB5 Internal Erase starts W39F010 Timing Waveforms, Continued 10.5 Page Erase Timing Diagram Six-byte commands for 5V-only Page Erase Address A16-0 5555 DQ7-0 5555 2AAA 80 55 AA 5555 AA 2AAA PA 55 50 #CE #OE TWP TEP #WE TWPH SB0 SB2 SB1 SB3 SB5 SB4 Internal Erase starts PA = Page Address Please refer to page 9 for detail informatio 10.6 #DATA Polling Timing Diagram Address A16-0 An An An An #WE TCEP #CE TOEH TOES #OE TOEP DQ7 X X X X TBP or TEC - 25 - Publication Release Date: December 26, 2005 Revision A4 W39F010 Timing Waveforms, Continued 10.7 Toggle Bit Timing Diagram Address A16-0 #WE #CE TOES TOEH #OE DQ6 TBP orTEC - 26 - W39F010 11. ORDERING INFORMATION PART NO. ACCESS POWER SUPPLY CURRENT MAX. TIME STANDBY VDD CURRENT MAX. PACKAGE CYCLE (NS) (MA) (MA) W39F010-70B 70 30 2 32-pin DIP 10K W39F010-90B 90 30 2 32-pin DIP 10K W39F010T-70B 70 30 2 32-pin TSOP (8 mm x 20 mm) 10K W39F010T-90B 90 30 2 32-pin TSOP (8 mm x 20 mm) 10K W39F010Q-70B 70 30 2 32-pin STSOP (8 mm x 14 mm) 10K W39F010Q-90B 90 30 2 32-pin STSOP (8 mm x 14 mm) 10K W39F010P-70B 70 30 2 32-pin PLCC 10K W39F010P-90B 90 30 2 32-pin PLCC 10K W39F010P-70Z 70 30 2 32-pin PLCC (Lead free) 10K W39F010P-90Z 90 30 2 32-pin PLCC (Lead free) 10K Notes: 1. Winbond reserves the right to make changes to its products without prior notice. 2. Purchasers are responsible for performing appropriate quality assurance testing on products intended for use in applications where personal injury might occur as a consequence of product failure. - 27 - Publication Release Date: December 26, 2005 Revision A4 W39F010 12. HOW TO READ THE TOP MARKING Example: The top marking of 32-pin PLCC W39F010P-70 W39F010P-70 2138977A-A12 149OBSA 1st line: winbond logo 2nd line: the part number: W39F010P-70 3rd line: the lot number 4th line: the tracking code: 149 O B SA 149: Packages made in '01, week 49 O: Assembly house ID: A means ASE, O means OSE, ...etc. B: IC revision; A means version A, B means version B, ...etc. SA: Process code - 28 - W39F010 13. PACKAGE DIMENSIONS 13.1 32-pin P-DIP Dimension in inches Dimension in mm Symbol A A1 A2 B B1 c D E E1 e1 L D 17 32 E1 a eA S Notes: 16 1 E S c A A2 A1 L Base Plane Seating Plane B e1 eA a B1 - 29 - Min. Nom. Max. Min. Nom. Max. 5.33 0.210 0.010 0.25 0.150 0.155 0.160 3.81 3.94 4.06 0.016 0.018 0.022 0.41 0.46 0.56 0.048 0.050 0.054 1.22 1.27 1.37 0.008 0.010 0.014 0.20 0.25 0.36 1.650 1.660 41.91 42.16 0.590 0.600 0.610 14.99 15.24 15.49 0.545 0.550 0.555 13.84 13.97 14.10 0.090 0.100 0.110 2.29 2.54 2.79 0.120 0.130 0.140 3.05 3.30 3.56 0 15 0 15 0.630 0.650 0.670 16.00 16.51 17.02 0.085 2.16 1.Dimensions D Max. & S include mold fla tie bar burrs. 2.Dimension E1 does not include interlea 3.Dimensions D &. E1 include mold misma are determined at the mold parting lin 4.Dimension B1 does not include dam protrusion/intrusion. 5.Controlling dimension: Inches 6.General appearance spec. should be ba final visual inspection spec. Publication Release Date: December 26, 2005 Revision A4 W39F010 13.2 32-pin TSOP (8 x 20 mm) HD Dimension in Inches Dimension in mm Symbol D A c A1 M e E Min. Nom. __ __ 0.002 Max. Min. Nom. __ __ 0.047 __ 0.006 0.05 __ Max. 1.20 0.15 A2 0.037 0.039 0.041 0.95 1.00 b 0.007 0.008 0.009 0.17 0.20 0.23 c 0.005 0.006 0.007 0.12 0.15 0.17 D 0.720 0.724 0.728 18.30 18.40 18.50 E 0.311 0.315 0.319 HD 0.780 0.787 0.795 19.80 1.05 0.10(0.004) b e L L1 A θ L __ 0.016 __ A2 Y 0.000 A1 θ 1 L1 0.020 0.020 0.031 __ 3 7.90 __ __ 0.024 0.40 __ __ 0.004 0.00 5 1 Y Note: Controlling dimension: Millimeters - 30 - 8.00 8.10 20.00 20.20 0.50 0.50 0.80 __ 3 __ 0.60 __ 0.10 5 W39F010 Package Dimensions, Continued 13.3 32-pin PLCC HE E 4 1 32 30 Symbol 5 29 A A1 A2 b1 b c D E e GD GE HD HE L y θ GD D HD 21 13 14 c 20 Dimension in Inches Min. Nom. Max. Dimension in mm Min. Nom. Max. 3.56 0.140 0.50 0.020 0.105 0.110 0.115 2.67 2.80 2.93 0.026 0.028 0.032 0.66 0.71 0.81 0.016 0.018 0.022 0.41 0.46 0.56 0.008 0.010 0.014 0.20 0.25 0.35 0.547 0.550 0.553 13.89 13.97 14.05 0.447 0.450 0.453 11.35 11.43 11.51 0.044 0.050 0.056 1.12 1.27 1.42 0.490 0.510 0.530 12.45 12.95 13.46 0.390 0.410 0.430 9.91 10.41 10.92 0.590 0.595 14.86 14.99 15.11 0.485 0.490 0.495 12.32 12.45 12.57 0.075 0.090 0.095 1.91 2.29 2.41 0.585 0.10 0.004 0 10 0 10 Notes: L A2 θ e 1. Dimensions D & E do not include interlead flash. 2. Dimension b1 does not include dambar protrusion/intrusion. 3. Controlling dimension: Inches. 4. General appearance spec. should be based on final visual inspection sepc. A1 b b1 Seating Plane A y GE 13.4 32-pin STSOP (8 x 14 mm) HD D c Dimension in Inches Dimension in mm Symbol Min. Nom. Max. Min. Nom. Max. e E b θ A1 A2 A L Y A A1 A2 b c D E HD e L L1 Y θ 0.047 0.002 1.20 0.006 0.05 0.15 0.035 0.040 0.041 0.95 1.00 1.05 0.007 0.009 0.010 0.17 0.22 0.27 0.004 ----- 0.008 0.10 ----- 0.21 0.488 12.40 0.315 8.00 0.551 14.00 0.020 0.020 0.024 0.50 0.028 0.50 0.031 0.000 0 3 0.60 0.70 0.80 0.004 0.00 5 0 0.10 3 5 L1 - 31 - Publication Release Date: December 26, 2005 Revision A4 W39F010 14. VERSION HISTORY VERSION DATE PAGE A1 Dec. 2000 1, 23 1 4 10, 11, 12 A2 June 17, 2002 DESCRIPTION Initial Issued Add cycle of 1K Change active current from 10 to15mA (typ.) Change standby current from 20 to15 μA (typ.) Modify Low VDD Inhibit Delete old flow chart and add Embedded Algorithm 10 Remove Block Erase from the Embedded Erase Algorithm 11 Correct Embedded #Data Polling Algorithm 16 1, 23 Change IDD from 10/20 mA to15/30 mA (typ./max.) Change ISB2 from 20/50 μA to15/50 μA (typ./max.) Rename TSOP (8 x 14 mm) as STSOP (8 x 14 mm) 24 Add HOW TO READ THE TOP MARKING A3 April 15, 2005 27 Add Important Notice A4 December 26, 2005 27 Add 32-pin PLCC lead free part - 32 - W39F010 Important Notice Winbond products are not designed, intended, authorized or warranted for use as components in systems or equipment intended for surgical implantation, atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, or for other applications intended to support or sustain life. Further more, Winbond products are not intended for applications wherein failure of Winbond products could result or lead to a situation wherein personal injury, death or severe property or environmental damage could occur. Winbond customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Winbond for any damages resulting from such improper use or sales. - 33 - Publication Release Date: December 26, 2005 Revision A4