NCP5602 High Efficiency Ultra Small Thinnest White LED Driver The NCP5602 product is a dual output LED driver dedicated to the LCD display backlighting. The built−in DC−DC converter is based on a high efficient charge pump structure with operating mode 1x and 1.5x. It provides a peak 87% efficiency together with a 0.2% LED to LED matching. http://onsemi.com MARKING DIAGRAM Features 2.7 to 5.5 V Input Voltage Range 87% Peak Efficiency with 1x and 1.5x Mode ICON Function Implemented Built−in Short Circuit Protection Provides Two Independent LED Drives Support I2C Protocol Smallest Available Package on the Market Tight 0.2% LED to LED Matching This is a Pb−Free Device 1 ZA = Specific Device Code M = Date Code G = Pb−Free Package (Note: Microdot may be in either location) • Portable Back Light • Digital Cellular Phone Camera Photo Flash • LCD and Key Board Simultaneously Drive 220 nF/10 V 220 nF/10 V 1 mF/6.3 V 11 Vbat 8 C4 C2P 10 9 C2N C1N GND C1P 12 Vbat Vout 6 5 I2C−SDA R1 4 SCL U1 NCP5602 SDA LED1 2 LWY87SG IREF D2 GND LWY87SG GND LED/ICON 12 11 Vbat 2 LED2 3 10 C1P IREF 4 9 C2N SDA 5 8 C2P SCL 6 7 VOUT (Top View) GND ORDERING INFORMATION 10 k 1 1 LED1 1 mF/10 V 7 D1 I2C−SCL C1N PIN CONNECTIONS Typical Applications C3 ZA M G G LLGA12 (2x2 mm) MU SUFFIX CASE 513AA GND • • • • • • • • • 3 Device Package Shipping† NCP5602MUTBG LLGA12 (Pb−Free) 3000 Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. Figure 1. Typical Multiple White LED Driver © Semiconductor Components Industries, LLC, 2006 July, 2006 − Rev. 1 1 Publication Order Number: NCP5602/D NCP5602 C2 C1 220 nF 220 nF 12 10 9 8 C4 GND 1 mF/6.3 V Vbat Vout OVERVOLTAGE SDA 6 Vbat DIGITAL CONTROL 5 D1 SCL Q1 2 CURRENT CONTROL Vbat R1 GND 4 100 k GND ANALOG CONTROL 1 Q2 GND ICON OVERTEMPERATURE Figure 2. Simplified Block Diagram http://onsemi.com 2 3 D2 1 mF/6.3 V 7 LWT67C CHARGE PUMP DC−DC CONVERTER 11 LWT67C C3 GND NCP5602 PIN FUNCTION DESCRIPTION Pin No. Symbol Function Description 1 GND POWER 2 LED1 INPUT, POWER This pin sinks to ground and monitors the current flowing into the first LED, intended to be used in backlight application. The current is limited to 30 mA maximum (see Note 2). When the ICON bit of the LED−REG register is High, the LED2 fulfills the ICON function. In this case, LED1 is deactivated. 3 LED2 INPUT, POWER This pin sinks to ground and monitors the current flowing into the second LED, intended to be used in backlight application. The current is limited to 30 mA maximum (see Note 2). When the ICON bit of the LED−REG register is High, the LED2 fulfills the ICON function. In this case, LED1 is deactivated. The ICON current is 600 mA typical. 4 IREF INPUT, ANALOG This pin provides the reference current, based on the internal bandgap voltage reference, to control the output current flowing in the LED. A 1% tolerance, or better, resistor shall be used to get the highest accuracy of the LED biases. An external current source can be used to bias this pin to dim the light coming out of the LED. This pin is the GROUND signal for the analog and digital blocks and must be connected to the system ground. This pin is the GROUND reference for the DC−DC converter and the output current control. The pin must be connected to the system ground, a ground plane being strongly recommended. In no case shall the voltage at pin 4 be forced either higher or lower than the 600 mV provided by the internal reference. 5 SDA INPUT, DIGITAL This pin carries the data provided by the I2C protocol. The content of the SDA byte is used to program the mode of operation and to set up the output current (see Table 2). 6 SCL INPUT, DIGITAL This pin carries the I2C clock to control the DC−DC converter and to set up the output current. The SCL clock is associated with the SDA signal. 7 VOUT OUTPUT, POWER This pin provides the output voltage supplied by the DC−DC converter. The Vout pin must be bypassed by 1.0 mF ceramic capacitor located as close as possible to the pin to properly bypass the output voltage to ground. The circuit shall not operate without such bypass capacitor properly connected to the Vout pin. The output voltage is internally clamped to 5.5 V maximum in the event of no load situation. On the other hand, the output current is limited to 40 mA (typical) in the event of a short circuit to ground. 8 C2P POWER One side of the external charge pump capacitor (CFLY ) is connected to this pin, associated with C2N (see Note 1). 9 C2N POWER One side of the external charge pump capacitor (CFLY ) is connected to this pin, associated with C2P (see Note 1). 10 C1P POWER One side of the external charge pump capacitor (CFLY ) is connected to this pin, associated with C1N, pin 11 (see Note 1). 11 VBAT INPUT, POWER 12 C1N POWER Input Battery voltage to supply the analog and digital blocks. The pin must be decoupled to ground by a 1.0 mF ceramic capacitor. One side of the external charge pump capacitor (CFLY ) is connected to this pin, associated with C1P, pin 10 (see Note 1). 1. Using low ESR ceramic capacitor is mandatory to optimize the Charge Pump efficiency. 2. Total DC−DC output current is limited to 60 mA. http://onsemi.com 3 NCP5602 MAXIMUM RATINGS Symbol Value Unit Power Supply Rating VBAT −0.3 <V < 7.0 V Output Power Supply Vout 7.0 V Digital Input Voltage Digital Input Current SCL, SDA −0.3 < V < VBAT 1.0 V mA ESD 2.0 200 kV V PD RqJC RqJA 200 51 200 mW °C/W °C/W Operating Ambient Temperature Range TA −40 to +85 °C Operating Junction Temperature Range TJ −40 to +125 °C TJmax +150 °C Tstg −65 to +150 °C − "100 mA Human Body Model: R = 1500 W, C = 100 pF (Note 3) Machine Model LLGA12 Package Power Dissipation @ TA = +85°C (Note 4) Thermal Resistance, Junction−to−Case Thermal Resistance, Junction−to−Air Maximum Junction Temperature Storage Temperature Range Latchup Current Maximum Rating per JEDEC Standard: JESD78 Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 3. This device series contains ESD protection and exceeds the following tests: Human Body Model (HBM) "2.0 kV per JEDEC standard: JESD22−A114. Machine Model (MM) "200V per JEDEC standard: JESD22−A115. 4. The maximum package power dissipation limit must not be exceeded. 5. Moisture Sensitivity Level (MSL): 1 per IPC/JEDEC standard: J−STD−020A. http://onsemi.com 4 NCP5602 POWER SUPPLY SECTION (Typical values are referenced to TA = +25°C, Min & Max values are referenced −40°C to +85°C ambient temperature, operating conditions 2.85 V < Vbat < 5.5 V, unless otherwise noted.) Pin Symbol Min Typ Max Unit Power Supply 11 Vbat 2.7 − 5.5 V Continuous DC Current in the Load @ Vf = 3.0 V, ICON = L @ 3.2 V < Vbat < 5.5 V @ 3.0 V < Vbat < 5.5 V 7 Iout 60 45 − − − − Output ICON Current (ICON = H) @ Tj = + 25°C, Vf = 2.8 V, Vbat = 3.6 V 7 IICONTROL − 600 850 mA Continuous Output Short Circuit Current 7 Isch − 45 150 mA Output Voltage Compliance (OVP) 7 Vout 4.8 − 5.7 V DC−DC Start Time (Cout = 1.0 mF) 3.0 V < Vbat = Nominal < 5.5 V from Last ACK Bit to Full Load Operation 12 Tstart − 150 − ms Output Voltage Turn Off Time from Last ACK Bit to Vout = 5% 12 Toff − 300 − ms Standby Current, Vbat = 3.6 V, Iout = 0 mA, ICON = L @ SCL = SDA = L @ SCL = SDA = H (No Port Activity) 11 Istdb − − Operating Current, @ Iout = 0 mA, ICON = H, Vbat = 3.6 V 11 Iop − 750 − mA Output LED to LED Current Matching, @ 3.0 V < Vbat < 4.2 V, ILED = 10 mA, LED1 & LED2 are Identical −25°C < Ta < 85°C 2, 3 IMAT 1.0 "0.2 1.0 % Output Current Tolerance @ Vbat = 3.6 V, ILED = 10 mA −25°C < Ta < 85°C 2, 3 ITOL − "3.0 − % Charge Pump Operating Frequency −40°C < Ta < 85°C − Fpwr − 1.0 − MHz Thermal Shutdown Protection − TSD − 160 − °C Thermal Shutdown Protection Hysteresis − TSDH − 30 − °C Efficiency − LED1 = LED2 = 10 mA, Vf = 3.2 V, Vbat = 3.2 V (Total = 20 mA) − LED1 = LED2 = 30 mA, Vf = 3.4 V, Vbat = 3.75 V (Total = 60 mA) − − − − 87 84 − − Rating mA mA 6.0 12 EPWR % ANALOG SECTION (Typical values are referenced to TA = +25°C, Min & Max values are referenced −40°C to +85°C ambient temperature, operating conditions 2.85 V < Vbat < 5.5 V, unless otherwise noted.) Rating Pin Symbol Min Typ Max Unit Reference Current @ Vref = 600 mV (Note 7) 4 IREF 1.0 − 60 mA Reference Voltage (Note 7) 4 VREF −3% 600 +3% mV Reference Current (IREF) Current Ratio (see Table 2) − ILEDR − 16 − − 6. The overall output current tolerance depends upon the accuracy of the external resistor. Using 1% or better resistor is recommended. 7. The external circuit must not force the IREF pin voltage either higher or lower than the 600 mV specified. The limits represent the min/max values one can force to run the normal operation. DIGITAL PARAMETERS SECTION (Typical values are referenced to TA = +25°C, Min & Max values are referenced −40°C to +85°C ambient temperature, operating conditions 2.85 V < Vbat < 5.5 V, unless otherwise noted.) Note: Digital inputs undershoot < − 0.30 V to ground, Digital inputs overshoot < 0.30 V to VBAT. Rating Pin Symbol Min Typ Max Unit 6 FSCK − − 400 kHz Positive Going Input High Voltage Threshold, SCL, SDA Signals 5, 6 VIH 1.3 − VBAT V Negative Going Input High Voltage Threshold, SCL, SDA Signals 5, 6 VIL 0 − 0.4 V InputI2C Clock Frequency (Note 8) 8. Parameter not tested in production, guaranteed by design. http://onsemi.com 5 NCP5602 APPLICATION INFORMATION Rbias + 150ńIout DC−DC Operation The converter is based on a charge pump technique to generate a DC voltage capable to supply the White LED load. The system regulates the current flowing into each LED by means of internal current mirrors associated with the white diodes. Consequently, the output voltage will be equal to the Vf of the LED, plus the drop voltage (ranging from 200 mV to 400 mV, depending upon the output current) developed across the internal NMOS mirror. Typically, assuming a standard white LED forward biased at 10 mA, the output voltage will be 3.8 V. The built−in OVP circuit continuously monitor each output and stops the converter when the voltage is above 5.0 V. The converter resumes to normal operation when the voltage drops below 5.0 V (no latchup mechanism). Consequently, the chip can operate with no load during any test procedures. Consequently, the resistor value will range between Rbias = 150/30 mA = 5000 W and Rbias = 150/0.5 mA = 300 kW. Obviously, the tolerance of such a resistor must be 1% or better, with a 100 ppm thermal coefficient, to get the expected overall tolerance. VBandgap LED Return + − Load Current Calculation The load current is derived from the 600 mV reference voltage provided by the internal Bandgap associated to the external resistor connected across IREF pin and Ground (see Figure 3). In any case, no voltage shall be forced at IREF pin, either downward or upward. The reference current is multiplied by the constant k = 250 to yield the output load current. Since the reference voltage is based on a temperature compensated Bandgap, a tight tolerance resistor will provide a very accurate load current. The resistor is calculated from the Ohm’s law (Rbias = Vref/I REF) and a more practical equation can be arranged to define the resistor value for a given output current: Rbias + (Vref * k)ńIout Rbias + (0.6 * 250)ńIout Pin 4 GND R1 Note: The IREF pin must never be biased by an external voltage. GND Figure 3. Basic Reference Current Source Load Connection The NCP5602 chip is capable to drive the two LED simultaneously, as depicted in Figure 1, but the load can be arranged to accommodate one or two LED if necessary in the application (see Figure 4). In this case, the two current mirrors can be connected in parallel to drive a single power full LED, thus yielding 60 mA current capability in a single LED. (eq. 1) GND 2 3 3 Figure 4. Typical Single and Double LED Connections http://onsemi.com 6 1 mF/6.3 V C4 LWY8SG D2 LWY8SG D1 NCP5602 1 mF/6.3 V C4 LWY8SG 7 D1 NCP5602 Pin 2 & 3 600mV IREF 7 2 (eq. 2) GND NCP5602 Finally, an external network can be connected across Vout and ground , but the current through such network will not be regulated by the NCP5602 chip (see Figure 5). On 5 mA LWY8SG D4 220R 5 mA LWY8SG D3 220R R2 2 R1 20 mA LWY8SG D2 1 mF/6.3 V 20 mA LWY8SG NCP5602 7 C4 D1 GND top of that, the total current out of the Vout pin shall be limited to 60 mA. 3 GND Figure 5. Extra Load Connected to Vout I2C Protocol The standard I2C protocol is used to transfer the data from the MCU to the NCP5602. Leaving aside the Acknowledge bit, the NCP5602 does not return data back to the MCU. Figure 6. Basic I2C Timings MSB START A7 LSB A6 A5 A4 A3 A2 A1 R/W ACK 7 Bits Slave Address Start condition sent by Master Sent by Slave Figure 7. Peripheral Address Identification B7 B6 B5 B4 B3 B2 B1 B0 ACK STOP Sent by Slave Sent by Master Figure 8. Basic DATA Transfer from MCU to Peripheral http://onsemi.com 7 NCP5602 The physical address of the NCP5602 is 1001 111X, the X being the Read/Write identifier as defined by the I2C specification. Since the NCP5602 does not return data, the first byte of the I2C frame shall be 1001 1110 ($9E) as depicted in Table 2. To set up a new output current value, a full frame shall be sent by the MCU. The frame contains three consecutive bytes and shall fulfill the I2C specifications: First byte : I2C address ³$9E Second byte : internal register address ³$01 Third byte : output current value ³$00 to $1E (0 mA to 30 mA, Assuming Rext = 10 kW) The waveforms given in Figure 9 illustrate a typical output current update. Table 1. NCP5602 Physical I2C Address B7 B6 B5 B4 B3 B2 B1 B0 1 0 0 1 1 1 1 0 Figure 9. Typical NCP5602 I2C Startup Sequence Dimming The built−in I2C interface provides a simple way to accurately control the output current flowing in the two LED. Such dimming is active under the NORMAL mode only and the LED2 current cannot be adjusted when the ICON mode is active. The internal register LED−REG[0..7] is set up by the content of the SDA byte sent by the external MCU as depicted in Table 2. For typical application, the 60 mA reference current forced by the external resistor is multiply by 16 to get a 1.0 mA/step in the output LED. The waveforms given Figure 10 illustrate a normal programming sequence. Table 2. LED−REG[0..7] Internal Register Bits Assignment B7 B6 B5 B4 B3 B2 B1 B0 RFU RFU ICON IREF*16*16 IREF*16*8 IREF*16*4 IREF*16*2 IREF*16 = High ³ ICON mode takes place, LED#1 is deactivated, the current to LED#2 being setup to 450 mA. It is not possible to adjust this current. [B4..B0]= Output LED current. The content of these bits is latched to the current reference on the 8th SCK clock pulse. The DC−DC converter is switched OFF and the two LED are disconnected when LED−REG=$00. [B7,B6] = RFU:bits reserved for future use B5 = ICON:control the NORMAL/ICON mode of operation: ICON = Low ³ Normal MODE takes place, the two LED are activated and the current can be adjusted from 0 mA to 30 mA maximum per LED. ICON http://onsemi.com 8 NCP5602 When the ICON mode is activated, the DC−DC converter is switched OFF, LED#1 is deactivated from the VOUT and 450 mA are forced into LED#2. The waveforms, given Figure 11, illustrate the programming sequence to activate the ICON. Figure 11. ICON Programming Sequence Figure 10. Output Current I2C Programming Sequence VCC J2 2 1 220 nF/63 V C3 POWER GND SCL 10 k R2 10 k TP1 SCL 11 6 SDA 5 SDA TP2 4 1 IREFBK 8 C4 C2P C2N 10 Vbat Vout GND 7 Vout 2 LED1 4.7 mF/16 V SCL SDA D1 IREF LED1 GND LED/ICON LWY8S D2 3 LED2 LWY8S U1 NCP5602 10 k R3 CONTROL PORT GND R1 1 3 5 7 9 C1P 12 C1N VCC VCC C2 9 C1 4.7 mF/10 V GND J1 2 4 6 8 10 220 nF/63 V Z1 GND GND Figure 12. Demo Board Schematic Diagram http://onsemi.com 9 NCP5602 Figure 13. LED Current Matching Figure 14. Efficiency as a Function of VF, Vbat http://onsemi.com 10 NCP5602 Figure 15. NCP5602 Demo Board http://onsemi.com 11 NCP5602 PACKAGE DIMENSIONS LLGA12 MU SUFFIX CASE 513AA−01 ISSUE O D PIN ONE REFERENCE A B ÇÇÇÇ ÇÇÇÇ ÇÇÇÇ ÇÇÇÇ 2X 0.10 C 2X 0.10 C NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994 . 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.15 AND 0.20 MM FROM TERMINAL. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. E DIM A A1 b D D2 E E2 e K L L1 TOP VIEW 0.10 C MILLIMETERS MIN MAX 0.50 0.60 0.00 0.05 0.15 0.25 2.00 BSC 0.80 1.00 2.00 BSC 0.55 0.65 0.40 BSC 0.25 −−− 0.30 0.50 0.40 0.60 A 12X 0.08 C SIDE VIEW A1 SEATING PLANE C D2 SOLDERING FOOTPRINT* L1 6 2 11X e 9X 0.66 2.30 12X 0.23 1 L 0.40 PITCH K 1 E2 e/2 2.06 12 0.93 11 7 12X b 11X 0.10 C A B 0.05 C 0.91 0.56 NOTE 3 BOTTOM VIEW 0.63 DIMENSIONS: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. 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