NCP5612 D

NCP5612
High Efficiency Ultra Small
Thinnest White LED Driver
The NCP5612 product is a dual output LED driver dedicated to the
LCD display backlighting.
The built−in DC/DC converter is based on a high efficient charge
pump structure with operating mode 1x and 1.5x. It provides a peak
87% efficiency together with a 0.2% LED to LED matching.
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MARKING
DIAGRAM
Features
•
•
•
•
•
•
•
•
•
•
•
Support the Single Wire Serial Link Protocol
Peak Efficiency 90% with 1x and 1.5x Mode
Programmable Dimming ICON Function
Built−in Short Circuit Protection
Provides 16 steps Current Control
Controlled Start−up Inrush Current
Built−in Automatic Open Load Protection
Tight 0.2% Matching Tolerance
Accurate 1% Output Current Tolerance
Smallest Available Package on the Market
This is a Pb−Free Device
1
YD = Specific Device Code
M = Date Code
G
= Pb−Free Package
(Note: Microdot may be in either location)
PIN CONNECTIONS
Typical Applications
GND C1N
• Portable Back Light
• Digital Cellular Phone Camera Photo Flash
• LCD and Key Board Simultaneous Drive
VCC
Vbat
C5
C3
220 nF/10 V 220 nF/10 V
1 mF/6.3 V
1 mF/6.3 V
VCC−cpu
R1
MCU
11
Vbat
6
NC
5
CNTL
4
10k
1
GND
Vout
LED1
GND
LED/ICON
2
LED2
3
10 C1P
IREF
4
9
C2N
CNTL
5
8
C2P
NC
6
7
VOUT
GND
1
12
(Top View)
ORDERING INFORMATION
7
LWY87S
D1
IREF
GND
C4
11 Vbat
LED1
1 mF/10 V
C1
C2
12
10 9
8
C1N
C1P C2N
C2P
GND
I/O pin
YD M G
G
LLGA12 (2x2 mm)
MU SUFFIX
CASE 513AA
2
D2
3
Device
Package
Shipping†
NCP5612MUTBG
LLGA12
(Pb−Free)
3000/Tape & Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
LWY87S
U1
NCP5612
Figure 1. Typical Single Wire White LED Driver
© Semiconductor Components Industries, LLC, 2006
August, 2006 − Rev. 0
1
Publication Order Number:
NCP5612/D
NCP5612
C1
C2
220 nF
220 nF
12
10
9
8
C4
1 mF/10 V
Vbat
GND
C3
CHARGE PUMP
DC/DC CONVERTER
11
1 mF/6.3 V
7
Vout
GND
OVERVOLTAGE
CNTL
LWY87S
5
LWY87S
Vbat
DIGITAL CONTROL
150 k
Vbat
CURRENT MIRRORS
2
GND
R1
4
10 k
GND
D1
Q1
ANALOG CONTROL
1
GND
GND
NC 6
OVERTEMPERATURE
Figure 2. Simplified Block Diagram
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2
Q2
3
D2
NCP5612
PIN FUNCTION DESCRIPTION
Pin No.
Symbol
Function
Description
1
GND
POWER
This pin is the GROUND signal for the power analog blocks and must be
connected to the system ground. This pin is the GROUND reference for the
DC/DC converter and the output current control. The pin must be connected to
the system ground, a ground plane being strongly recommended.
2
LED1
INPUT, POWER
This pin sinks to ground and monitors the current flowing into the first LED,
intended to be used in backlight application. The current is limited to 30 mA
maximum (Note 2).
The LED1 is deactivated when the ICON bit of the LED−REG register is High.
The LED1 is automatically disconnected when an open load is sensed pin 2
during the operation.
3
LED2
INPUT, POWER
This pin sinks to ground and monitors the current flowing into the second LED,
intended to be used in backlight application. The current is limited to 30 mA
maximum (Note 2). The LED2 fulfills the ICON function, LED1 being
deactivated, when the ICON bit of the LED−REG register is High.
The LED2 is automatically disconnected when an open load is sensed pin 3
during the operation.
4
IREF
INPUT, ANALOG
This pin provides the reference current, based on the internal band−gap
voltage reference, to control the output current flowing in the LED. A 1%
tolerance, or better, resistor shall be used to get the highest accuracy of the
LED biases. An external current source can be used to bias this pin to dim the
light coming out of the LED.
In no case shall the voltage at pin 4 be forced either higher or lower than the
600 mV provided by the internal reference.
5
CNTL
INPUT, DIGITAL
This pin supports the flow of data between the external MCU and the
NCP5612 internal registers. The protocol makes profit of a Single Wire
structure associated to a Serial 8 bits format data flow.
6
NC
−
7
VOUT
OUTPUT, POWER
No internal connection
8
C2P
POWER
One side of the external charge pump capacitor (CFLY) is connected to this
pin, associated with C2N (Note 1)
9
C2N
POWER
One side of the external charge pump capacitor (CFLY) is connected to this
pin, associated with C2P (Note 1)
10
C1P
POWER
One side of the external charge pump capacitor (CFLY) is connected to this
pin, associated with C1N (Note 1)
11
VBAT
INPUT, POWER
12
C1N
POWER
This pin provides the output voltage supplied by the DC/DC converter. The
Vout pin must be decoupled to ground by a 1 mF ceramic capacitor located as
close as possible to the pin. Cares must be observed to minimize the parasitic
inductance at this pin. The circuit shall not operate without such bypass
capacitor connected across the Vout pin and ground.
The output voltage is internally clamped to 5.5 V maximum in the event of no
load situation. On the other hand, the output current is limited to 40 mA
(typical) in the event of a short circuit to ground.
Input Battery voltage to supply the analog and digital blocks. The pin must be
decoupled to ground by a 1.0 mF minimum ceramic capacitor.
One side of the external charge pump capacitor (CFLY) is connected to this
pin, associated with C1P (Note 1)
1. Using low ESR ceramic capacitor, 50 mW maximum, is mandatory to optimize the Charge Pump efficiency.
2. Total DC/DC output current is limited to 60 mA.
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3
NCP5612
MAXIMUM RATINGS
Symbol
Value
Unit
Power Supply
Rating
VBAT
7.0
V
Output Power Supply
Vout
7.0
V
Digital Input Voltage
Digital Input Current
CNTL
−0.3 < V < VBAT
1.0
V
mA
Human Body Model: R = 1500 W, C = 100 pF (Note 3)
Machine Model
ESD
2.0
200
kV
V
PD
RqJC
RqJA
200
51
200
mW
°C/W
°C/W
Operating Ambient Temperature Range
TA
−40 to +85
°C
Operating Junction Temperature Range
TJ
−40 to +125
°C
TJmax
+150
°C
Tstg
−65 to +150
°C
Latch−up Current Maximum Rating per JEDEC Standard: JESD78
−
"100
mA
Moisture Sensitivity (Note 5)
−
1
LLGA12 Package
Power Dissipation @ TA = +85°C (Note 4)
Thermal Resistance, Junction−to−Case
Thermal Resistance, Junction−to−Air
Maximum Junction Temperature
Storage Temperature Range
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
3. This device series contains ESD protection and exceeds the following tests:
Human Body Model (HBM) "2.0 kV per JEDEC standard: JESD22−A114.
Machine Model (MM) "200 V per JEDEC standard: JESD22−A115.
4. The maximum package power dissipation limit must not be exceeded.
5. Moisture Sensitivity Level (MSL): 1 per IPC/JEDEC standard: J−STD−020A.
POWER SUPPLY SECTION (Typical values are referenced to TA = +25°C, Min & Max values are referenced −40°C to +85°C ambient
temperature, operating conditions 2.85 V < Vbat < 5.5 V, unless otherwise noted.)
Rating
Pin
Symbol
Min
Typ
Max
Unit
Power Supply
11
Vbat
2.7
−
5.5
V
Continuous DC Current in the Load @ Vf = 3.8 V, 3.2 V < Vbat < 5.5 V, ICON = L
(30 mA per LED)
7
Iout
60
−
−
Output ICON Current (ICON bit = H) @ 3.2 V < Vbat < 4.2 V, TA = +25°C
7
IICONTOL
−
450
550
mA
Continuous Output Short Circuit Current
7
Isch
−
40
100
mA
Output Voltage Compliance (OVP)
7
Vout
4.8
−
5.7
V
DC/DC Start Time (Cout = 1.0 mF) from end of the CNTL Tdst delay to full load
operation, @ Vbat = 3.6 V
12
Tstart
−
150
−
ms
Output Voltage Turn−off (Cout = 1 mF) From Last Low Level at CNTL pin to
Vout = 5%
12
Toff
−
500
−
ms
Standby Current, 0°C < TA < +85°C
Vbat = 3.6 V, Iout = 0 mA, ICON = L
11
Istdb
−
−
1.0
mA
Operating Current, @ Iout = 0 mA, ICON = H, Vbat = 3.6 V
11
Iop
−
600
−
mA
Output LED to LED Current Matching, Vbat = 3.6 V,
ILED = 10 mA, LED1 & LED2 are Identical −25°C < TA < 85°C
2, 3
IMAT
−
"0.2
"1.0
%
Output Current Tolerance @ Vbat = 3.6 V, ILED = 10 mA −25°C < Ta < 85°C
2, 3
ITOL
−
"1.0
−
%
Charge Pump Operating Frequency
−
Fpwr
−
1.0
−
MHz
Thermal Shutdown Protection
−
TSD
−
160
−
°C
Thermal Shutdown Protection Hysteresis
−
TSDH
−
30
−
°C
Efficiency − LED1 = LED2 = 10 mA, Vf = 3.2 V, Vbat = 3.8 V (Total = 20 mA)
Efficiency − LED1 = LED2 = 30 mA, Vf = 3.75 V, Vbat = 3.8 V (Total = 60 mA)
−
−
EPWR
−
−
87
84
−
−
%
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4
mA
NCP5612
ANALOG SECTION (Typical values are referenced to TA = +25°C, Min & Max values are referenced −40°C to +85°C ambient
temperature, operating conditions 2.85 V < Vbat < 5.5 V, unless otherwise noted.)
Rating
Pin
Symbol
Min
Typ
Max
Unit
Reference Current @ Vref = 600 mV (Note 7)
4
IREF
1.0
−
60
mA
Reference Voltage (Note 7) 0°C < TA < +85°C
4
VREF
−3%
600
+3%
mV
Base Reference Current (IREF) Current Ratio
−
ILEDR
−
500
−
−
6. The overall output current tolerance depends upon the accuracy of the external resistor. Using 1% or better resistor is recommended.
7. The external circuit must not force the IREF pin voltage either higher or lower than the 600 mV specified.
DIGITAL PARAMETERS SECTION (Typical values are referenced to TA = +25°C, Min & Max values are referenced −40°C to +85°C
ambient temperature, operating conditions 2.85 V < Vbat < 5.5 V, unless otherwise noted.) Note: Digital inputs undershoot < − 0.30 V to
ground, Digital inputs overshoot < 0.30 V to VBAT.
Rating
Pin
Symbol
Min
Typ
Max
Unit
Positive going Input High Voltage Threshold, CNTL signals
5
VIH
1.4
−
VBAT
V
Negative going Input Low Voltage Threshold, CNTL signals
5
VIL
−
−
0.6
V
Pull Down Resistor
5
Rcntl
−
150
−
kW
Delay between two consecutive frame (Note 9)
5
tidle
10
−
−
ms
Wake up delay (Note 9)
5
twkp
−
−
1.0
ms
CNTL signal rise and fall time (Note 9)
5
tr, tf
−
−
200
ns
Clocked CNTL High (Note 9)
5
ton
−
−
75
ms
CNTL Low (Note 9)
5
ton, toff
1.0
−
−
ms
CNTL Store data delay (Note 9)
5
Tdst
−
200
300
ms
Input CNTL frequency (Note 9)
5
FCNTL
−
−
400
kHz
8. see Timings Reference
9. Parameter not tested in production, guaranteed by design.
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5
NCP5612
APPLICATION INFORMATION
ton
toff
twkp
tf
tr
90%
90%
VIH
10%
VIL
Bit = 1
Bit = 0
Bit = 0
Figure 3. Timings Reference
VOH @ Vccio = 3.0 V 2600 mV
VOH @ Vccio = 2.6 V 2400 mV
1400 mV
VOL @ MOTOROLA: 500 mV
VOL @ QUALCOMM: 450 mV
VOL @ INTEL: 400 mV
VIHsw
VIL
600 mV
100 mV/step
GROUND
Figure 4. Basic Cellular Phone Chip Set Digital Output Levels
DC/DC Operation
The converter is based on a charge pump technique to
generate a DC voltage capable to supply the White LED
load. The system regulates the current flowing into each
LED by means of internal current mirrors associated with
the white diodes. Consequently, the output voltage will be
equal to the Vf of the LED, plus the drop voltage (ranging
from 150 mV to 400 mV, depending upon the output
current and Vbat / Vf ratio) developed across the internal
NMOS mirror. Typically, assuming a standard white LED
forward biased at 10 mA, the output voltage will be 3.6 V.
The built−in OVP circuit continuously monitors the
output voltage and stops the converter when the voltage is
above 5.0 V typical. The converter resumes to normal
operation when the voltage drops below the typical 5.0 V
(no latch−up mechanism). Consequently, the chip can
operate with no load during any test procedures.
external resistor connected across IREF pin and Ground (see
Figure 5). In any case, no voltage shall be forced at IREF pin,
either downward or upward.
The reference current is multiplied by the internal
current mirror, associated to the number of pulses as
depicted Figure 9, to yield the output load current. Since the
reference voltage is based on a temperature compensated
Band Gap, a tight tolerance resistor will provide a very
accurate load current. The resistor is calculated from the
Ohm’s law (Rbias = Vref/IREF) and define the maximum
current flowing into the LED when 20 pulses have been
counted at the CNTL pin.
Since the reference current must be between the
minimum and maximum specified, the resistor value will
range between Rbias = 300/30 mA = 10 kW and Rbias =
300/0.5 mA = 600 kW. Obviously, the tolerance of such a
resistor must be 1% or better, with a 100 ppm thermal
coefficient, to get the expected overall tolerance.
Typical applications will run with Rbias = 10 kW to make
profit of the full dynamic range provided by the S−Wire
DATA byte.
Load Current Calculation
The load current is derived from the 600 mV reference
voltage provided by the internal Band Gap associated to the
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6
NCP5612
VBandGap
LED Return
Pin 2 & 3
600 mV
R1
IREF
GND
Pin 4
Note: the IREF pin must never be biased by an external voltage.
GND
Figure 5. Basic Reference Current Source
Load Connection
in the application (see Figure 6). In this case, the two
current mirrors can be connected in parallel to drive a
single powerful LED, thus yielding 60 mA current
capability in a single LED.
The NCP5612 is capable to drive the two LED
simultaneously, as depicted (see Figure 1), but the load can
be arranged to accommodate one or two LED if necessary
NCP5612
NCP5612
7
7
LWY87S
LWY87S
LWY87S
D1
D1
C4
D2
1 mF/6.3 V
2
C4
1 mF/6.3 V
2
GND
GND
3
3
Figure 6. Typical Single and Double LED Connections
Single Wire Serial Link Protocol
Finally, an external network can be connected across Vout
and ground, but the current through such network will not
be regulated by the NCP5612 chip (see Figure 7). On top
of that, the total current out of the Vout pin shall be limited
to 60 mA.
The proposed S−WIRE uses a pulse count technique
already existing in the data exchange systems. The protocol
supports broken transmission, assuming the hold time is
shorter than the maximum 200 ms typical specified in the
data sheet. The S−WIRE details are provided in the
AND8264 application note.
Based on the two examples provided in Figure 8, the
CNTL pin supports two digital level:
CNTL = Low ³ the system is shut−off and no current
flow in either LED1 or LED2.
CNTL = High ³ the system is active and the two LED
are powered according to the selected sequence.
There is no time delay associated with the Low state and
the LED are switched Off when the CNTL signal drops to
Low. To program a new LED configuration, one shall send
the number of pulses on the CNTL pin according to the true
table:
• The internal counter is reset to zero on the first
negative going transient present on the CNTL pin
C4
NCP5612
1uF/6.3V
GND
7
LWY87S
LWY87S
D3
D1
20 mA
2
LWY87S
5mA
LWY87S
D2
20 mA
D4
5mA
R1
220R
R2
220R
3
GND
Figure 7. Extra Load Connected to Vout
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7
NCP5612
• The first four positive going pulses are used to control
•
•
•
• The system returns to zero if a pulse, delayed by
the ICON (LED2):
1. Pulse #1 ³ ICON = 100 mA
2. Pulse #2 ³ ICON = 150 mA
3. Pulse #3 ³ ICON = 250 mA
4. Pulse #4 ³ ICON = 450 mA
The fifth positive pulse will clear the ICON and
activate the normal operation of LED1 and LED2
The pulses from the fifth to the twentieth will increase
the LED current according to a pseudo logarithmic
scale (see Figure 9).
Any pulses beyond the twentieth will not make change
to the LED current if the delay between the pulses is
shorter than 75 ms.
Start Bit
Negative going edge
Clear counter
Example #1: CNTL
LED1= 0 mA
LED2 = ICON
Pulse count
TEL
Tdst
1
2
3
ICON = 250 mA
Shut down mode
LED1=LED0= 0 mA
TEHmax 75 ms when clocked
Example #2: CNTL
LED1= 6 mA
LED2 = 6 mA
Pulse count
200Ăms – Tdst – , follows the twentieth one and the
cycle restart from the beginning.
Once the expected LED current value is reached, the
CNTL pin must stay High to store the new data and
maintain the LED active.
The contain of the counter is stored into the internal LED
registers at the end of the built−in 200 ms typical delay: no
action will take place during the end of the last positive
going pulse and the end of the Tdst delay. Such a protocol
prevent the system for broken transmission.
On the other hand, in order to avoid corrupted data
transmission, the High level shall be 75 ms maximum
during a given data frame. Consequently, the pulse
frequency is bounded by a 13 kHz minimum and a 400 kHz
maximum.
Tdst
TEH
1
2
3
4
5
6
7
8
9
10
LED1=LED2 = 6 mA
ICON = disabled
Tdst
Example #3: CNTL
LED1= 30 mA
LED2 = 30 mA
Pulse count 1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20
ICON = disabled
LED1=LED2 = 30 mA
LED1=LED2 = 0 mA
Note: timings are not scaled.
Figure 8. Basic NCP5612 Programming Sequence
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8
NCP5612
DIMMING
The built−in Single Wire Serial Link interface provides
a simple way to accurately control the output current
flowing in the two LED. Provision have been made, at
silicon level, to provide a full dimming of the backlight
(NORMAL mode of operation), the ICON current being
adjustable in four steps when it is activated.
Bit Clock
I−LED(mA)
1
2
Table 1. LED Dimming Configuration
LED activity
Pulse 1
LED#2 = 100 mA, LED#1 de−activated
Pulse 2
LED#2 = 150 mA, LED#1 de−activated
Pulse 3
LED#2 = 250 mA, LED#1 de−activated
Pulse 4
LED#2 = 450 mA, LED#1 de−activated
Pulse 5 to Pulse 20
ICON de−activated, NORMAL backlight takes place
I−LED(mA)
1
9
12
2
10
14
3
3
11
16
4
4
12
19
5
5
13
22
6
6
14
25
7
8
15
28
8
10
16
31
35
IOUT = F(Bit Clock)
(linear scale)
30
25
IOUT (mA)
Pulse Count
Bit Clock
The DC/DC converter is switched OFF and the two LED
are disconnected when LED−REG=$00.
When the ICON mode is activated, the DC/DC converter
is switched OFF, LED#1 is deactivated from the LED
current sense and the programmed bias current (powered
from the Vbat source) is forced into LED#2.
20
15
10
5.0
0
0
5.0
10
15
BIT CLOCK
Figure 9. Typical Output Current Slope
Figure 10. Typical Efficiency
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9
20
NCP5612
Figure 11. Typical LED to LED Current Matching
C1
4.7 mF/10 V
VBAT
J1
2
1
220 nF/6.3 V
220 nF/6.3 V
TP2
VOUT
GND
C2
POWER
12
GND
J2
2
4
6
8
10
1
3
5
7
9
11
TP1
DATA
6
5
DATA 4
S−WIRE PORT
GND
1
IREFBK
R1
10
C3
C4
9
8
C1N C1P C2N C2P
Vout
Vbat
NC
7 VOUT
GND
1.0 mF/10 V
U1
NCP5612
CNTL
IREF
GND
LED1
LED/ICON
2 LED1
D1
LWY87S
3 LED2
LWY87S
10 k
Z1
GND
GND
Figure 12. Demo Board Schematic Diagram
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10
D2
NCP5612
PACKAGE DIMENSIONS
LLGA12
MU SUFFIX
CASE 513AA−01
ISSUE O
D
A
B
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994 .
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.15 AND 0.20 MM FROM TERMINAL.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
PIN ONE
REFERENCE
ÇÇÇÇ
ÇÇÇÇ
ÇÇÇÇ
2X
0.10 C
2X
0.10 C
E
DIM
A
A1
b
D
D2
E
E2
e
K
L
L1
TOP VIEW
0.10 C
MILLIMETERS
MIN
MAX
0.50
0.60
0.00
0.05
0.15
0.25
2.00 BSC
0.80
1.00
2.00 BSC
0.55
0.65
0.40 BSC
0.25
−−−
0.30
0.50
0.40
0.60
A
12X
0.08 C
SIDE VIEW
A1
SEATING
PLANE
C
D2
SOLDERING FOOTPRINT*
L1
6
2
11X
e
9X
0.66
2.30
12X
0.23
1
L
0.40
PITCH
K
1
E2
e/2
2.06
12
0.93
11
7
12X
b
11X
0.10 C A B
0.05 C
0.91
0.56
NOTE 3
BOTTOM VIEW
0.63
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any
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damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over
time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under
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ON Semiconductor Website: www.onsemi.com
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NCP5612/D