MAXIM MAX11201

TION KIT
EVALUA BLE
AVAILA
19-5333; Rev 0; 6/10
24-Bit, Single-Channel, Ultra-Low-Power, Delta
Sigma ADC with 2-Wire Serial Interface
Features
The MAX11201 is an ultra-low-power (< 320FA max
active current), high-resolution, serial-output ADC. This
device provides the highest resolution per unit power in
the industry and is optimized for applications that require
very high dynamic range with low power such as sensors
on a 4mA to 20mA industrial control loop. The MAX11201
provides a high-accuracy internal oscillator that requires
no external components.
S 23.3-Bit ENOB
20.6-Bit Noise-Free Resolution at 13.75sps
19.1-Bit Noise-Free Resolution at 120sps
S 700nVRMS Noise ±3.6VFS Input (MAX11201B)
S INL: 3ppm (typ), 10ppm (max)
S No Missing Codes
S Ultra-Low Power Dissipation
Operating Mode Current Drain < 320µA (max)
Sleep Mode Current Drain < 0.4µA
When used with the specified data rates, the internal digital
filter provides more than 100dB rejection of 50Hz or 60Hz
line noise. The MAX11201 provides a simple 2-wire serial
interface in the space-saving, 10-pin FMAXM package.
S 2.7V to 3.6V Analog Supply Voltage Range
S 1.7V to 3.6V Digital and I/O Supply Voltage Range
The MAX11201 operates over the -40NC to +85NC temperature range.
S Fully Differential Signal and Reference Inputs
S High-Impedance Inputs
Buffers on Signal Inputs
Applications
Sensor Measurement
(Temperature and
Pressure)
S Programmable Internal System Clock or External
Clock
2.4576MHz (MAX11201A)
2.25275MHz (MAX11201B)
Portable Instrumentation
Battery Applications
Weigh Scales
S > 100dB (min) 50Hz/60Hz Rejection (MAX11201B)
Ordering Information
PART
PIN-PACKAGE
S Serial 2-Wire Interface (Clock Input and Data Output)
S On-Demand Offset and Gain Self-Calibration
OUTPUT RATE
(sps)
MAX11201AEUB+
10 FMAX
120
MAX11201BEUB+
10 FMAX
13.75
S -40°C to +85°C Operating Temperature Range
S ±2kV ESD Protection
S Lead(Pb)-Free and RoHS-Compliant µMAX Package
Note: All devices are specified over the -40°C to +85°C operating temperature range.
+Denotes a lead(Pb)-free/RoHS-compliant package.
Selector Guide
RESOLUTION
(BITS)
4-WIRE SPI, 16-PIN QSOP,
PROGRAMMABLE GAIN
4-WIRE SPI,
16-PIN QSOP
2-WIRE SERIAL,
10-PIN μMAX
24
MAX11210
MAX11200
MAX11201 (with buffers)
MAX11202 (without buffers)
20
MAX11206
MAX11207
MAX11208
18
MAX11209
MAX11211
MAX11212
16
MAX11213
MAX11203
MAX11205
µMAX is a registered trademark of Maxim Integrated Products, Inc.
________________________________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
MAX11201
General Description
MAX11201
24-Bit, Single-Channel, Ultra-Low-Power, Delta
Sigma ADC with 2-Wire Serial Interface
ABSOLUTE MAXIMUM RATINGS
Any Pin to GND.....................................................-0.3V to +3.9V
AVDD to GND........................................................-0.3V to +3.9V
DVDD to GND.......................................................-0.3V to +3.9V
Analog Inputs (AINP, AINN, REFP, REFN)
to GND............................................... -0.3V to (VAVDD + 0.3V)
Digital Inputs and Digital Outputs
to GND............................................... -0.3V to (VDVDD + 0.3V)
ESDHB (AVDD, AINP, AINN, REFP, REFN, DVDD, CLK, SCLK,
RDY/DOUT, GND)............................................. Q2kV (Note 1)
Continuous Power Dissipation (TA = +70NC)
10-Pin FMAX (derate 5.6mW/NC above +70NC)...........444mW
Operating Temperature Range........................... -40NC to +85NC
Junction Temperature......................................................+150NC
Storage Temperature Range............................. -55NC to +150NC
Lead Temperature (soldering, 10s).................................+300NC
Soldering Temperature (reflow).......................................+260NC
Note 1: Human Body Model to specification MIL-STD-883 Method 3015.7.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VAVDD = +3.6V, VDVDD = +1.7V, VREFP - VREFN = VAVDD; internal clock, TA = TMIN to TMAX, unless otherwise noted. Typical values
are at TA = +25NC under normal conditions, unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
ADC PERFORMANCE
Noise-Free Resolution
(Notes 2, 3)
Noise (Notes 2, 3)
Integral Nonlinearity
Zero Error
NFR
VN
INL
VOFF
MAX11201A
19.1
MAX11201B
20.6
MAX11201A
2.0
MAX11201B
0.70
Bits
FVRMS
(Note 4)
-10
+10
ppmFSR
After calibration, VREFP - VREFN = 2.5V
-10
+10
ppmFSR
Zero Drift
50
After calibration, VREFP - VREFN = 2.5V
(Note 5)
Full-Scale Error
-20
Full-Scale Error Drift
nV/NC
+20
ppmFSR/
NC
0.05
Power-Supply Rejection
AVDD DC rejection
70
80
DVDD DC rejection
90
100
DC rejection
90
123
50Hz/60Hz rejection, MAX11201A
90
ppmFSR
dB
ANALOG INPUTS/REFERENCE INPUTS
Common-Mode Rejection
CMR
dB
50Hz/60Hz rejection, MAX11201B
144
Normal-Mode 50Hz Rejection
NMR50
MAX11201B (Note 6)
100
144
Normal-Mode 60Hz Rejection
NMR60
MAX11201B (Note 6)
100
144
Common-Mode Voltage Range
GND
DC Input Leakage
VGND +
100mV
High input voltage
VAVDD 100mV
Sleep mode (Note 2)
dB
VAVDD
Low input voltage
Absolute Input Voltage
dB
Q1
2 _______________________________________________________________________________________
V
V
FA
24-Bit, Single-Channel, Ultra-Low-Power, Delta
Sigma ADC with 2-Wire Serial Interface
(VAVDD = +3.6V, VDVDD = +1.7V, VREFP - VREFN = VAVDD; internal clock, TA = TMIN to TMAX, unless otherwise noted. Typical values
are at TA = +25NC under normal conditions, unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
AIN_ Dynamic Input Current
±20
nA
REF_ Dynamic Input Current
±30
nA
5
pF
AIN_ Input Capacitance
REF_ Input Capacitance
7.5
AIN_ Voltage Range
AINP - AINN
REF_ Voltage Range
Input Sampling Rate
fS
REF Sampling Rate
pF
-VREF
+VREF
V
0
VAVDD
V
MAX11201A
246
MAX11201B
225
MAX11201A
246
MAX11201B
225
Input leakage current
Q1
kHz
kHz
LOGIC INPUTS (SCLK, CLK)
Input Current
Input Low Voltage
VIL
Input High Voltage
VIH
Input Hysteresis
0.3 x
VDVDD
0.7 x
VDVDD
VHYS
External Clock
FA
V
V
200
MAX11201A
2.4576
MAX11201B
2.25275
mV
MHz
LOGIC OUTPUT (RDY/DOUT)
Output Low Level
VOL
VOH
Output High Level
IOL = 1mA; also tested for VDVDD = 3.6V
IOH = 1mA; also tested for VDVDD = 3.6V
0.4
0.9 x
VDVDD
V
V
Leakage Current
High-impedance state
Q10
FA
Output Capacitance
High-impedance state
9
pF
POWER REQUIREMENTS
Analog Supply Voltage
AVDD
2.7
3.6
Digital Supply Voltage
DVDD
1.7
3.6
V
320
FA
Total Operating Current
AVDD + DVDD
245
V
DVDD Operating Current
50
60
FA
AVDD Operating Current
195
265
FA
AVDD Sleep Current
0.15
2
FA
DVDD Sleep Current
0.25
2
FA
5
MHz
2-WIRE SERIAL-INTERFACE TIMING CHARACTERISTICS
SCLK Frequency
fSCLK
SCLK Pulse Width Low
t1
60/40 duty cycle, 5MHz clock
80
ns
SCLK Pulse Width High
t2
40/60 duty cycle, 5MHz clock
80
ns
SCLK Rising Edge to Data Valid
Transition Time
t3
40
ns
_______________________________________________________________________________________ 3
MAX11201
ELECTRICAL CHARACTERISTICS (continued)
MAX11201
24-Bit, Single-Channel, Ultra-Low-Power, Delta
Sigma ADC with 2-Wire Serial Interface
ELECTRICAL CHARACTERISTICS (continued)
(VAVDD = +3.6V, VDVDD = +1.7V, VREFP - VREFN = VAVDD; internal clock, TA = TMIN to TMAX, unless otherwise noted. Typical values
are at TA = +25NC under normal conditions, unless otherwise noted.)
PARAMETER
SYMBOL
SCLK Rising Edge Data Hold
Time
t4
RDY/DOUT Fall to SCLK Rising
Edge
t5
Next Data Update Time;
No Read Allowed
t6
Data Conversion Time
t7
Data Ready Time After Calibration
Starts (CAL + CNV)
t8
SCLK High After RDY/DOUT
Goes Low to Activate Sleep Mode
t9
Time from RDY/DOUT Low to
SCLK High for Sleep-Mode
Activation
t10
Data Ready Time After Wake-Up
From Sleep Mode
t11
Data Ready Time After Calibration
From Sleep Mode Wake-Up (CAL
+ CNV)
t12
Note
Note
Note
Note
Note
CONDITIONS
Allows for positive edge data read
MIN
TYP
MAX
UNITS
3
ns
0
ns
MAX11201A
155
MAX11201B
169
MAX11201A
8.6
MAX11201B
73
MAX11201A
208.3
MAX11201B
256.1
Fs
ms
ms
MAX11201A
0
8.6
MAX11201B
0
73
MAX11201A
0
8.6
MAX11201B
0
73
MAX11201A
8.6
MAX11201B
73
MAX11201A
208.4
MAX11201B
256.2
2: These specifications are not fully tested and are guaranteed by design and/or characterization.
3: VAINP = VAINN.
4: ppmFSR is parts per million of full-scale range.
5: Positive full-scale error includes zero-scale errors.
6: The MAX11201A has no normal-mode rejection at 50Hz or 60Hz.
4 _______________________________________________________________________________________
ms
ms
ms
ms
24-Bit, Single-Channel, Ultra-Low-Power, Delta
Sigma ADC with 2-Wire Serial Interface
TA = +85°C
140
120
120
100
2.85
3.00
3.15
3.30
3.45
3.30
3.45
AVDD VOLTAGE (V)
100
TOTAL
200
VAVDD = 3.0V
150
100
VDVDD = 1.8V
VDVDD = 1.8V
50
0
0.8
-25
-5
15
35
55
75
95
-45
-25
-5
0.4
0.2
0
15
35
55
75
TOTAL
DVDD
AVDD
0
95
-45
-25
-5
15
35
55
75
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
DIGITAL ACTIVE CURRENT
vs. DVDD VOLTAGE
DIGITAL SLEEP CURRENT
vs. DVDD VOLTAGE
INTERNAL OSCILLATOR FREQUENCY
vs. TEMPERATURE
MAX11201A
90
80
MAX11201B
60
2.0
TA = -45°C
TA = +25°C
1.5
1.0
TA = +85°C
0.5
50
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6
DVDD VOLTAGE (V)
VAVDD = 3.0V
MAX11201A
2.5
95
2.4
2.3
MAX11201B
2.2
2.1
0
40
2.6
FREQUENCY (MHz)
110
2.5
CURRENT (µA)
TA = +85°C, +25°C, -45°C
MAX11201 toc08
3.0
MAX11201 toc07
-45
0.6
MAX11201 toc09
50
VAVDD = 3.0V
CURRENT (µA)
150
SLEEP CURRENT vs. TEMPERATURE
1.0
MAX11201 toc05
250
2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6
3.60
300
MAX11201 toc04
VAVDD = 3.0V
70
3.15
ACTIVE SUPPLY CURRENT
vs. TEMPERATURE (MAX11201B)
200
100
3.00
ACTIVE SUPPLY CURRENT
vs. TEMPERATURE (MAX11201A)
TOTAL
TA = -45°C
0
2.85
AVDD VOLTAGE (V)
250
TA = +85°C
TA = +25°C
2.70
CURRENT (µA)
CURRENT (µA)
3.60
0.4
0.2
AVDD VOLTAGE (V)
300
120
TA = -45°C
100
2.70
CURRENT (µA)
160
0.6
MAX11201 toc06
TA = -45°C
TA = +25°C
180
140
130
0.8
CURRENT (µA)
180
160
TA = +85°C
200
TA = +25°C
CURRENT (µA)
CURRENT (µA)
200
220
1.0
MAX11201 toc02
220
240
MAX11201 toc01
240
ANALOG SLEEP CURRENT
vs. AVDD VOLTAGE
ANALOG ACTIVE CURRENT
vs. AVDD VOLTAGE (MAX11201B)
MAX11201 toc03
ANALOG ACTIVE CURRENT
vs. AVDD VOLTAGE (MAX11201A)
2.0
1.7 1.9 2.1 2.3 2.5 2.7 2.9 3.1 3.3 3.5
DVDD VOLTAGE (V)
-45
-25
-5
15
35
55
75
95
TEMPERATURE (°C)
_______________________________________________________________________________________ 5
MAX11201
Typical Operating Characteristics
(VAVDD = 3.6V, VDVDD = 1.8V, VREFP - VREFN = AVDD; internal clock; TA = TMIN to TMAX, unless otherwise specified. Typical values
are at TA = +25NC.)
Typical Operating Characteristics (continued)
(VAVDD = 3.6V, VDVDD = 1.8V, VREFP - VREFN = AVDD; internal clock; TA = TMIN to TMAX, unless otherwise specified. Typical values
are at TA = +25NC.)
VREF = 2.5V
3.5
3.0
MAX11201B
2.0
1.5
MAX11201B
1.0
2.2
3.0
MAX11201A
2.5
2.85
3.00
3.15
3.30
3.45
3.60
MAX11201B
0
-45
-5
15
35
55
TEMPERATURE (°C)
NOISE HISTOGRAM
(MAX11201A, 120sps)
NOISE HISTOGRAM
(MAX11201B, 13.75sps)
LONG-TERM ADC READINGS
(MAX11201A)
6
4
0.5 1.0 1.5 2.0 2.5
30,000 CONSECUTIVE READINGS
18
16
TA = +25°C
VREF = 2.5V
RMS = 0.72µV
MEAN = 4.1µV
14
12
10
8
6
75
15
TA = +25°C
VIN = 0V
RMS = 2.1µV
10
4
2
-25
95
MAX11201 toc15
20
ADC READING (µV)
TA = +25°C
VREF = 2.5V
RMS = 2.1µV
MEAN = 5.0µV
-2.5 -2.0 -1.5 -1.0 -0.5 0
MAX11201 toc14
MAX11201 toc13
12
5
0
-5
-10
2
0
-0.3
2.0
4.3
6.7
9.0
-15
1.19
11.3
2.04
2.89
ADC OUTPUT (µV)
6.29
0.2
0
0.4
2
1
0
-1
-2
-3
TA = +25°C
TA = -45°C
TA = +85°C
0.8
1.0
OFFSET ERROR vs. TEMPERATURE
1.0
0.5
0.6
TIME (MINUTES)
VREF = VREFP - VREFN
1.5
OFFSET ERROR (ppmFSR)
3
5.44
OFFSET ERROR vs. VREF
2.0
MAX11201 toc16
TA = +25°C
VIN = 0V
RMS = 0.70µV
4
4.59
ADC OUTPUT (µV)
LONG-TERM ADC READINGS
(MAX11201B)
5
3.74
2.5
OFFSET ERROR (ppmFSR)
-2.7
0
MAX11201 toc18
0
MAX11201 toc17
NUMBER OF READINGS (%)
1.5
INPUT VOLTAGE (V)
30,000 CONSECUTIVE READINGS
8
2.0
AVDD VOLTAGE (V)
14
10
MAX11201A
0.5
0
NUMBER OF READINGS (%)
2.70
2.5
1.0
0.5
2.1
VREF = 3.0V
3.5
NOISE (µVRMS)
2.4
4.0
MAX11201 toc11
MAX11201 toc10
MAX11201A
2.3
4.0
NOISE (µVRMS)
FREQUENCY (MHz)
2.5
NOISE vs. TEMPERATURE
NOISE vs. INPUT VOLTAGE
2.6
MAX11201 toc12
INTERNAL OSCILLATOR FREQUENCY
vs. AVDD VOLTAGE
ADC READING (µV)
MAX11201
24-Bit, Single-Channel, Ultra-Low-Power, Delta
Sigma ADC with 2-Wire Serial Interface
CALIBRATED AT +25°C
2.0
1.5
1.0
0.5
-0.5
-4
-5
0
2
4
6
TIME (MINUTES)
8
10
0
-1.0
1.0
1.5
2.0
2.5
VREF (V)
3.0
3.5
4.0
-45
-25
-5
15
35
55
TEMPERATURE (°C)
6 _______________________________________________________________________________________
75
95
24-Bit, Single-Channel, Ultra-Low-Power, Delta
Sigma ADC with 2-Wire Serial Interface
TUE vs. INPUT VOLTAGE
4
INL (ppmFSR)
0
TA = +85°C
-2
0
TA = +85°C
-2
TA = +25°C
-4
TA = +25°C
2
-4
-6
-6
-8
-8
TA = -45°C
-10
-10
-2.5 -2.0 -1.5 -1.0 -0.5 0
-2.5 -2.0 -1.5 -1.0 -0.5 0
0.5 1.0 1.5 2.0 2.5
INPUT VOLTAGE (V)
PSRR vs. FREQUENCY
(MAX11201A)
PSRR vs. FREQUENCY
(MAX11201B)
AVDD
-100
-6
-FS ERROR
-8
-25
-5
15
35
-20
55
75
-40
CMRR (dB)
PSRR (dB)
-80
-4
0
-40
-60
0
-2
CMRR vs. FREQUENCY
-20
-40
2
-45
MAX11201 toc23
-20
4
TEMPERATURE (°C)
0
MAX11201 toc22
0
+FS ERROR
6
-10
0.5 1.0 1.5 2.0 2.5
INPUT VOLTAGE (V)
-60
-80
AVDD
-60
-80
MAX11201A
-100
-100
DVDD
-120
-120
-140
10
100
1000
10,000 100,000
-120
DVDD
1
10
100
1000
10,000 100,000
MAX11201 toc25
2000
GAIN (dB)
FREQUENCY (Hz)
1600
1400
1200
1000
800
600
400
0
10
100
1000
10,000 100,000
FREQUENCY (Hz)
NORMAL-MODE REJECTION
DATA RATE 13.750SPS
MAX11201A
200
1
FREQUENCY (Hz)
NORMAL-MODE REJECTION
DATA RATE 120.0SPS
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
-150
MAX11201B
-140
-140
FREQUENCY (Hz)
GAIN (dB)
1
1800
INL (ppmFSR)
2
VREF = 2.5V
8
MAX11201 toc21
6
4
PSRR (dB)
VIN(CM) = 1.8V
8
10
MAX11201 toc24
TA = -45°C
6
FULL-SCALE ERROR vs. TEMPERATURE
NORMALIZED FULL-SCALE ERROR (ppmFSR)
MAX11201 toc19
VIN(CM) = 1.8V
8
10
MAX11201 toc20
INL vs. INPUT VOLTAGE
10
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
-150
MAX11201 toc26
MAX11201B
0
10 20 30 40 50 60 70 80 90 100
FREQUENCY (Hz)
_______________________________________________________________________________________ 7
MAX11201
Typical Operating Characteristics (continued)
(VAVDD = 3.6V, VDVDD = 1.8V, VREFP - VREFN = AVDD; internal clock; TA = TMIN to TMAX, unless otherwise specified. Typical values
are at TA = +25NC.)
MAX11201
24-Bit, Single-Channel, Ultra-Low-Power, Delta
Sigma ADC with 2-Wire Serial Interface
Pin Configuration
TOP VIEW
+
GND 1
10 CLK
REFP
2
REFN
3
AINN
4
7
DVDD
AINP
5
6
AVDD
MAX11201
9
SCLK
8
RDY/DOUT
µMAX
Pin Description
PIN
NAME
1
GND
Ground. Ground reference for analog and digital circuitry.
FUNCTION
2
REFP
Differential Reference Positive Input. REFP must be more positive than REFN. Connect REFP to a voltage between AVDD and GND.
3
REFN
Differential Reference Negative Input. REFN must be more negative than REFP. Connect REFN to a
voltage between AVDD and GND.
4
AINN
Negative Fully Differential Analog Input
5
AINP
Positive Fully Differential Analog Input
6
AVDD
Analog Supply Voltage. Connect a supply voltage between +2.7V to +3.6V with respect to GND.
7
DVDD
Digital Supply Voltage. Connect a digital supply voltage between +1.7V to +3.6V with respect to GND.
8
RDY/DOUT
Data Ready Output/Serial Data Output. This output serves a dual function. In addition to the serial data
output function, the RDY/DOUT also indicates that the data is ready when the RDY is logic-low. RDY/
DOUT changes on the rising edge of SCLK.
9
SCLK
10
CLK
Serial Clock Input. Apply an external serial clock to SCLK.
External Clock Signal Input. The internal clock shuts down when CLK is driven by an external clock.
Use a 2.4576MHz oscillator (MAX11201A) or a 2.25275MHz oscillator (MAX11201B).
8 _______________________________________________________________________________________
24-Bit, Single-Channel, Ultra-Low-Power, Delta
Sigma ADC with 2-Wire Serial Interface
TIMING
AVDD
CLOCK GENERATOR
CLK
DIGITAL LOGIC
AND SERIALINTERFACE
CONTROLLER
SCLK
DVDD
GND
AINP
AINN
3RD-ORDER
DELTA-SIGMA
MODULATOR
DIGITAL FILTER
(SINC4)
RDY/DOUT
REFP
REFN
MAX11201
Detailed Description
The MAX11201 is an ultra-low-power (< 245FA active),
high-resolution, low-speed, serial-output ADC. This device
provides the highest resolution per unit power in the industry and is optimized for applications that require very high
dynamic range with low power such as sensors on a 4mA
to 20mA industrial control loop. The MAX11201 provides
a high-accuracy internal oscillator, which requires no
external components. When used with the specified data
rates, the internal digital filter provides more than 100dB
rejection of 50Hz or 60Hz line noise. The MAX11201 provides a simple, system-friendly, 2-wire serial interface in
the space-saving, 10-pin FMAX package.
Power-On Reset (POR)
The MAX11201 utilizes power-on reset (POR) supplymonitoring circuitry on both the digital supply (DVDD)
and the analog supply (AVDD). The POR circuitry
ensures proper device default conditions after either a
digital or analog power-sequencing event.
The MAX11201 performs a self-calibration operation as
part of the startup initialization sequence whenever a
digital POR is triggered. It is important to have a stable
reference voltage available at the REFP and REFN pins
to ensure an accurate calibration cycle. If the reference
voltage is not stable during a POR event, the part should
be calibrated once the reference has stabilized. The part
can be programmed for calibration by using 26 SCLKs
as shown in Figure 3.
The digital POR trigger threshold is approximately 1.2V
and has 100mV of hysteresis. The analog POR trigger
threshold is approximately 1.25V and has 100mV of hysteresis. Both POR circuits have lowpass filters that prevent high-frequency supply glitches from triggering the
POR. The analog supply (AVDD) and the digital supply
(DVDD) pins should be bypassed using 0.1µF capacitors placed as close as possible to the package pin.
Buffers
The MAX11201 includes signal input buffers capable of
reducing the average input current from 1.4FA/V on the
analog inputs to a constant 20nA. The MAX11201 analog
inputs provide > 100MI input impedance for connecting
directly to high-impedance sources.
Analog Inputs
The MAX11201 accepts two analog inputs (AINP and
AINN). The modulator input range is bipolar (-VREF to
+VREF).
Internal Oscillator
The MAX11201 incorporates a highly stable internal
oscillator that provides the system clock. The system
clock runs the internal state machine and is trimmed to
2.4576MHz (MAX11201A) or 2.25275MHz (MAX11201B).
The internal oscillator clock is divided down to run the
digital and analog timing.
_______________________________________________________________________________________ 9
MAX11201
Functional Diagram
MAX11201
24-Bit, Single-Channel, Ultra-Low-Power, Delta
Sigma ADC with 2-Wire Serial Interface
Reference
The MAX11201 provides differential inputs REFP and
REFN for an external reference voltage. Connect the
external reference directly across the REFP and REFN to
obtain the differential reference voltage. The commonmode voltage range for VREFP and VREFN is between 0
and VAVDD. The differential voltage range for REFP and
REFN is 1.25V to VAVDD.
Digital Filter
The MAX11201 contains an on-chip, digital lowpass filter
that processes the 1-bit data stream from the modulator
using a SINC4 (sinx/x)4 response. When the device is
operating in single-cycle conversion mode, the filter is
reset at the end of the conversion cycle. When operating in continuous conversion latent mode, the filter is not
reset. The SINC4 filter has a -3dB frequency equal to
24% of the data rate.
Data Output
The data output is clocked out on RDY/DOUT. D23 is
the MSB and D0 is the LSB. The data format is always
two’s complement. In two’s complement format, the most
negative value is 0x800000 (VAINP - VAINN = -VREF), the
midscale value is 0x000000 (AINP - AINN = 0), and the
most positive value is 0x7FFFFF (VAINP - VAINN = VREF).
Any input exceeding the available input range is limited
to the minimum or maximum data value.
Table 1. Output Data Format
INPUT VOLTAGE
VAINP - VAINN
DIGITAL OUTPUT CODE
≥ VREF
0x7FFFFF

1 
VREF x 1 −

 2 23 − 1
0x7FFFFE
VREF
2 23 − 1
0
− VREF
2 23 − 1
0x000001
0x000000
0xFFFFFF

1 
VREF x 1 −

23
 2 − 1
0x800001
≤ -VREF
0x800000
Serial-Digital Interface
The MAX11201 communicates through a 2-wire interface, with a clock input and data output. The output
rate is predetermined based on the package option
(MAX11201A at 120sps and MAX11201B at 13.75sps).
2-Wire Interface
The MAX11201 is compatible with the 2-wire interface
and uses SCLK and RDY/DOUT for serial communications. In this mode, all controls are implemented by timing the high or low phase of the SCLK. The 2-wire serial
interface only allows for data to be read out through the
RDY/DOUT output. Supply the serial clock to SCLK to
shift the conversion data out.
The RDY/DOUT is used to signal data ready, as well as
reading the data out when SCLK pulses are applied.
RDY/DOUT is high by default. The MAX11201 pulls
RDY/DOUT low when data is available at the end of conversion, and stays low until clock pulses are applied at
the SCLK input. On applying the clock pulses at SCLK,
the RDY/DOUT outputs the conversion data on every
SCLK positive edge. To monitor data availability, pull
RDY/DOUT high after reading the 24 bits of data by supplying a 25th SCLK pulse.
The different operational modes using this 2-wire interface are described in the following sections.
Data Read Following Every Conversion
The MAX11201 indicates conversion data availability, as
well as the retrieval of data through the RDY/DOUT output. The RDY/DOUT output idles at the value of the last
bit read unless a 25th SCLK pulse is provided, causing
RDY/DOUT to idle high.
The timing diagram for the data read is shown in
Figure 1. Once a low is detected on RDY/DOUT, clock
pulses at SCLK clock out the data. Data is shifted out
MSB first and is in binary two’s complement format.
Once all the data has been shifted out, a 25th SCLK is
required to pull the RDY/DOUT output back to the idle
high state. See Figure 2.
If the data is not read before the next conversion data is
updated, the old data is lost, as the new data overwrites
the old value.
10 �������������������������������������������������������������������������������������
24-Bit, Single-Channel, Ultra-Low-Power, Delta
Sigma ADC with 2-Wire Serial Interface
MAX11201
t1
t5
t2
SCLK
1
2
3
24
t3
t4
RDY/DOUT
D22
D23
D0
t6
CONVERSION IS DONE
DATA IS AVAILABLE
CONVERSION IS DONE
DATA IS AVAILABLE
t7
Figure 1. Timing Diagram for Data Read After Conversion
SCLK
1
2
3
24
25
25TH SLK RISING EDGE
PULLS RDY/DOUT
HIGH
RDY/DOUT
D23
D22
D0
CONVERSION IS DONE
DATA IS AVAILABLE
CONVERSION IS DONE
DATA IS AVAILABLE
Figure 2. Timing Diagram for Data Read Followed by RDY/DOUT Being Asserted High Using 25th SCLK
Data Read Followed by Self-Calibration
To initiate self-calibration at the end of a data read, provide a 26th SCLK clock pulse. After reading the 24 bits
of conversion data, a 25th positive edge on SCLK pulls
the RDY/DOUT output back high, indicating the end of
the data read. Provide a 26th SCLK clock pulse to initiate a self-calibration routine starting on the falling edge
of the SCLK. A subsequent falling edge of RDY/DOUT
indicates data availability at the end of calibration. The
timing is illustrated in Figure 3.
Data Read Followed by Sleep Mode
The MAX11201 can be put into sleep mode to save
power between conversions. To activate the sleep mode,
idle the SCLK high any time after the RDY/DOUT output
goes low (that is, after conversion data is available). It is
not required to read out all 24 bits before putting the part
in sleep mode. Sleep mode is activated after the SCLK is
held high (see Figure 4). The RDY/DOUT output is pulled
high once the device enters sleep mode. To come out
of the sleep mode, pull SCLK low. After the sleep mode
is deactivated (when the device wakes up), conversion
starts again and RDY/DOUT goes low, indicating the
next conversion data is available (see Figure 4).
Single-Conversion Mode
For operating the MAX11201 in single-conversion mode,
activate and deactivate sleep mode between conversions as described in the Data Read Followed by Sleep
Mode section). Single-conversion mode reduces power
consumption by shutting down the device when idle
between conversions. See Figure 4.
______________________________________________________________________________________ 11
MAX11201
24-Bit, Single-Channel, Ultra-Low-Power, Delta
Sigma ADC with 2-Wire Serial Interface
CALIBRATION STARTS ON 26TH SCLK
SCLK
2
1
3
24
25
26
1
2
25TH SCLK PULLS
RDY/DOUT HIGH
RDY/DOUT
D23
D22
D0
D23
CONVERSION IS DONE
DATA IS AVAILABLE
D22
CONVERSION IS DONE
DATA IS AVAILABLE AFTER CALIBRATION
t8
Figure 3. Timing Diagram for Data Read Followed by Two Extra Clock Cycles for Self-Calibration
DEVICE ENTERS
SLEEP MODE
SCLK
1
2
3
DEVICE EXITS OUT
SLEEP MODE
1
24
2
SLEEP
MODE
t9
t10
RDY/DOUT
D23
D22
D0
CONVERSION IS DONE
DATA IS AVAILABLE
D23
D22
CONVERSION IS DONE
DATA IS AVAILABLE
t11
Figure 4. Timing Diagram for Data Read Followed by Sleep Mode Activation; Single Conversion Timing
Single-Conversion Mode
with Self-Calibration at Wake-Up
The MAX11201 can be put in self-calibration mode immediately after wake-up from sleep mode. Self-calibration at
wake-up helps to compensate for temperature or supply
changes if the device is shut down for extensive periods.
To automatically start self-calibration at the end of sleep
mode, all the data bits must be shifted out followed by
the 25th SCLK edge to pull RDY/DOUT high. On the 26th
SCLK, keep it high for as long as shutdown is desired.
Once SCLK is pulled back low, the device automatically
performs a self-calibration and, when the data is ready,
the RDY/DOUT output goes low. See Figure 5. This also
achieves the purpose of single conversions with selfcalibration.
12 �������������������������������������������������������������������������������������
24-Bit, Single-Channel, Ultra-Low-Power, Delta
Sigma ADC with 2-Wire Serial Interface
1
SCLK
2
3
DEVICE ENTERS
SLEEP MODE
24
25
DEVICE EXITS OUT SLEEP MODE
AND STARTS CALIBRATION
1
26
2
SLEEP
MODE
t10
RDY/DOUT
D22
D23
D0
D23
CONVERSION IS DONE
DATA IS AVAILABLE
D22
CONVERSION IS DONE
DATA IS AVAILABLE AFTER CALIBRATION
t12
Figure 5. Timing Diagram for Sleep Mode Activation Followed by Self-Calibration at Wake-Up
Applications Information
IREF1 = K x IREF2
See Figure 6 for the RTD temperature measurement circuit
and Figure 7 for a resistive bridge measurement circuit.
IREF2
REFP
Chip Information
PROCESS: BiCMOS
RREF
MAX11201
IREF1
REFN
Package Information
AINP
For the latest package outline information and land patterns,
go to www.maxim-ic.com/packages. Note that a “+”, “#”, or
“-” in the package code indicates RoHS status only. Package
drawings may show a different suffix character, but the drawing
pertains to the package regardless of RoHS status.
RRTD
AINN
GND
Figure 6. RTD Temperature Measurement Circuit
PACKAGE
TYPE
PACKAGE
CODE
OUTLINE
NO.
LAND
PATTERN NO.
10 µMAX
U10+2
21-0061
90-0330
AVDD
REFP
REFN
AINP
MAX11201
AINN
Figure 7. Resistive Bridge Measurement Circuit
______________________________________________________________________________________ 13
MAX11201
25TH SCLK PULLS RDY/DOUT HIGH
MAX11201
24-Bit, Single-Channel, Ultra-Low-Power, Delta
Sigma ADC with 2-Wire Serial Interface
Revision History
REVISION
NUMBER
REVISION
DATE
0
6/10
DESCRIPTION
Initial release
PAGES
CHANGED
—
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied.
Maxim reserves the right to change the circuitry and specifications without notice at any time.
14
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