MAX11212 18-Bit, Single-Channel, Ultra-Low Power, DeltaSigma ADC with 2-Wire Serial Interface General Description Features The MAX11212 is an ultra-low power (< 300FA max active current), high-resolution, serial-output ADC. This device provides the highest resolution per unit power in the industry, and is optimized for applications that require very high dynamic range with low power such as sensors on a 4mA to 20mA industrial control loop. The MAX11212 provides a high-accuracy internal oscillator that requires no external components. S 18-Bit Full-Scale Resolution When used with the specified data rates, the internal digital filter provides more than 80dB rejection of 50Hz or 60Hz line noise. The MAX11212 provides a simple 2-wire serial interface in the space-saving, 10-pin FMAXM package. The MAX11212 operates over the -40NC to +85NC temperature range. S 2.7V to 3.6V Analog Supply Voltage Range Applications Sensor Measurement (Temperature and Pressure) Portable Instrumentation S 720nVRMS Noise (MAX11212B) S 3ppm INL S No Missing Codes S Ultra-Low-Power Dissipation Operating-Mode Current Drain < 300µA (max) Sleep-Mode Current Drain < 0.1µA S 1.7V to 3.6V Digital and I/O Supply Voltage Range S Fully Differential Signal Inputs S Fully Differential Reference Inputs S Internal System Clock 2.4576MHz (MAX11212A) 2.2528MHz (MAX11212B) S External Clock S Serial 2-Wire Interface (Clock Input and Data Output) S On-Demand Offset and Gain Self-Calibration Battery Applications S -40°C to +85°C Operating Temperature Range Weigh Scales S ±2kV ESD Protection S Lead(Pb)-Free and RoHS-Compliant µMAX Package Ordering Information PART PIN-PACKAGE OUTPUT RATE (sps) MAX11212AEUB+* 10 FMAX 120 MAX11212BEUB+ 10 FMAX 13.75 Note: All devices are specified over the -40°C to +85°C operating temperature range. +Denotes a lead(Pb)-free/RoHS-compliant package. *Future product—contact factory for availability. Selector Guide RESOLUTION (BITS) 4-WIRE SPI, 16-PIN QSOP, PROGRAMMABLE GAIN 4-WIRE SPI, 16-PIN QSOP 2-WIRE SERIAL, 10-PIN μMAX 24 MAX11210 MAX11200 MAX11201 (with buffers) MAX11202 (without buffers) 20 MAX11206 MAX11207 MAX11208 18 MAX11209 MAX11211 MAX11212 16 MAX11213 MAX11203 MAX11205 µMAX is a registered trademark of Maxim Integrated Products, Inc. For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim’s website at www.maximintegrated.com. 19-5247; Rev 0; 4/10 MAX11212 18-Bit, Single-Channel, Ultra-Low Power, DeltaSigma ADC with 2-Wire Serial Interface ABSOLUTE MAXIMUM RATINGS Any Pin to GND.....................................................-0.3V to +3.9V AVDD to GND........................................................-0.3V to +3.9V DVDD to GND.......................................................-0.3V to +3.9V Analog Inputs (AINP, AINN, REFP, REFN) to GND ............................................. -0.3V to (VAVDD + 0.3V) Digital Inputs and Digital Outputs to GND ............................................. -0.3V to (VDVDD + 0.3V) ESDHB (AVDD, AINP, AINN, REFP, REFN, DVDD, CLK, SCLK, RDY/DOUT, GND) ............................................ Q2kV (Note 1) Continuous Power Dissipation (TA = +70NC) 10-Pin FMAX (derate 5.6mW/NC above +70NC)...........444mW Operating Temperature Range........................... -40NC to +85NC Junction Temperature......................................................+150NC Storage Temperature Range............................. -55NC to +150NC Lead Temperature (soldering, 10s).................................+300NC Soldering Temperature (reflow).......................................+260NC Note 1: Human Body Model to specification MIL-STD-883 Method 3015.7. Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (VAVDD = +3.6V, VDVDD = +1.8V, VREFP - VREFN = VAVDD; internal clock, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25NC under normal conditions, unless otherwise noted.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS ADC PERFORMANCE Noise-Free Resolution Thermal Noise (Notes 2, 3) Integral Nonlinearity Zero Error NFR VN INL VOFF (Notes 2, 3) 18 MAX11212A 2.1 MAX11212B 0.72 (Note 4) -10 After calibration, VREFP - VREFN = 2.5V -20 Zero Drift 1 Bits FVRMS +10 ppmFSR +20 ppmFSR 50 Full-Scale Error After calibration, VREFP - VREFN = 2.5V (Note 5) -35 AVDD DC rejection 70 80 DVDD DC rejection 90 100 DC rejection 90 123 50Hz/60Hz rejection MAX11212A 90 50Hz/60Hz rejection MAX11212B 144 Full-Scale Error Drift 3 nV/NC +35 ppmFSR 0.05 Power-Supply Rejection ppmFSR/NC dB ANALOG INPUTS/REFERENCE INPUTS Common-Mode Rejection CMR dB Normal-Mode 50Hz Rejection NMR50 MAX11212B (Note 6) 65 80.5 Normal-Mode 60Hz Rejection NMR60 MAX11212B (Note 6) 73 87 Common-Mode Voltage Range GND DC Input Leakage GND 30mV High input voltage VAVDD + 30mV Sleep mode (Note 2) dB VAVDD Low input voltage Absolute Input Voltage dB V V ±1 FA AIN Dynamic Input Current 5 FA REF Dynamic Input Current 7.5 FA AIN Input Capacitance 10 pF 2 Maxim Integrated MAX11212 18-Bit, Single-Channel, Ultra-Low Power, DeltaSigma ADC with 2-Wire Serial Interface ELECTRICAL CHARACTERISTICS (continued) (VAVDD = +3.6V, VDVDD = +1.8V, VREFP - VREFN = VAVDD; internal clock, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25NC under normal conditions, unless otherwise noted.) PARAMETER SYMBOL CONDITIONS MIN REF Input Capacitance TYP AIN Voltage Range VAINP - VAINN -VREF REF Voltage Range Input Sampling Rate MAX 15 fS REF Sampling Rate MAX11212A 246 MAX11212B 225 MAX11212A 246 MAX11212B 225 Input leakage current ±1 UNITS pF +VREF V VAVDD V kHz kHz LOGIC INPUTS (SCLK, CLK) Input Current Input Low Voltage VIL Input High Voltage VIH Input Hysteresis 0.7 x VDVDD VHYS External Clock FA 0.3 x VDVDD V V 200 MAX11212A 2.4576 MAX11212B 2.2528 mV MHz LOGIC OUTPUTS (RDY/DOUT) Output Low Level VOL IOL = 1mA; also tested for VDVDD = 3.6V Output High Level VOH IOH = 1mA; also tested for VDVDD = 3.6V Floating State Leakage Current 0.4 0.9 x VDVDD Output leakage current Floating State Output Capacitance V V ±10 FA 9 pF POWER REQUIREMENTS Analog Supply Voltage AVDD 2.7 3.6 Digital Supply Voltage DVDD 1.7 3.6 V 300 FA Total Operating Current AVDD + DVDD 230 V DVDD Operating Current 45 60 FA AVDD Operating Current 185 245 FA AVDD Sleep Current 0.4 2 FA DVDD Sleep Current 0.35 2 FA 5 MHz 2-WIRE SERIAL-INTERFACE TIMING CHARACTERISITCS SCLK Frequency fSCLK SCLK Pulse Width Low t1 60/40 duty cycle 5MHz clock 80 ns SCLK Pulse Width High t2 40/60 duty cycle 5MHz clock 80 ns SCLK Rising Edge to Data Valid Transition Time t3 Maxim Integrated 40 ns 3 MAX11212 18-Bit, Single-Channel, Ultra-Low Power, DeltaSigma ADC with 2-Wire Serial Interface ELECTRICAL CHARACTERISTICS (continued) (VAVDD = +3.6V, VDVDD = +1.8V, VREFP - VREFN = VAVDD; internal clock, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25NC under normal conditions, unless otherwise noted.) PARAMETER SYMBOL SCLK Rising Edge Data Hold Time t4 RDY/DOUT Fall to SCLK Rising Edge t5 Next Data Update Time; No Read Allowed t6 Data Conversion Time t7 Data Ready Time After Calibration Starts (CAL + CNV) t8 SCLK High After RDY/DOUT Goes Low to Activate Sleep Mode t9 Time From RDY/DOUT Low to SCLK High for Sleep Mode Activation t10 Data Ready Time After Wake-Up from Sleep Mode t11 Data Ready Time After Calibration from Sleep Mode Wake-Up (CAL + CNV) t12 Note Note Note Note 4 CONDITIONS Allows for positive edge data read MIN TYP MAX UNITS 3 ns 0 ns MAX11212A 155 MAX11212B 169 MAX11212A 8.6 MAX11212B 73 MAX11212A 208.3 MAX11212B 256.1 Fs ms ms MAX11212A 0 8.6 MAX11212B 0 73 MAX11212A 0 8.6 MAX11212B 0 73 MAX11212A 8.6 MAX11212B 73 MAX11212A 208.4 MAX11212B 256.2 ms ms ms ms 2: These specifications are not fully tested and are guaranteed by design and/or characterization. 3: VAINP = VAINN. 4: ppmFSR is parts per million of full-scale range. 5: Positive full-scale error includes zero-scale errors. Maxim Integrated MAX11212 18-Bit, Single-Channel, Ultra-Low Power, DeltaSigma ADC with 2-Wire Serial Interface Typical Operating Characteristics (VAVDD = 3.6V, VDVDD = 1.8V, VREFP - VREFN = VAVDD; internal clock; TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25NC.) TA = +85°C TA = +25°C 160 TA = -45°C 220 180 TA = +25°C 160 TA = -45°C 140 140 120 120 100 2.85 3.00 3.15 3.30 3.45 0.4 0.2 TA = +25°C TA = -45°C TA = +85°C 0 2.70 2.85 3.00 3.15 3.30 3.45 3.60 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6 AVDD VOLTAGE (V) ACTIVE SUPPLY CURRENT vs. TEMPERATURE (MAX11212A) ACTIVE SUPPLY CURRENT vs. TEMPERATURE (MAX11212B) SLEEP CURRENT vs. TEMPERATURE (MAX11212A/MAX11212B) 250 0.8 VAVDD = 3.6V 150 200 CURRENT (µA) CURRENT (µA) TOTAL VAVDD = 3.6V 150 MAX11212 toc06 1.0 MAX11212 toc05 300 100 VAVDD = 3.6V VDVDD = 1.8V 0.6 0.4 100 VDVDD = 1.8V 50 VDVDD = 1.8V 50 0 0.2 0 -25 -5 15 35 55 75 95 VDVDD VAVDD TOTAL 0 -45 -25 -5 15 35 55 75 95 -45 -25 -5 15 35 55 75 TEMPERATURE (°C) TEMPERATURE (°C) TEMPERATURE (°C) DIGITAL ACTIVE CURRENT vs. DVDD VOLTAGE DIGITAL SLEEP CURRENT vs. DVDD VOLTAGE (MAX11212A/MAX11212B) INTERNAL OSCILLATOR FREQUENCY vs. TEMPERATURE 90 80 70 MAX11212B 2.0 TA = +25°C 1.5 1.0 95 MAX11212 toc09 TA = -45°C VDVDD = 1.8V VAVDD = 3.0V 2.5 FREQUENCY (MHz) MAX11212A 2.5 2.6 MAX11212 toc08 110 VAVDD = 3.6V CURRENT (µA) VAVDD = 3.6V TA = +85°C, +25°C, -45°C 100 3.0 MAX11212 toc07 -45 CURRENT (µA) 0.6 AVDD VOLTAGE (V) TOTAL 200 3.60 MAX11212 toc04 250 120 0.8 AVDD VOLTAGE (V) 300 130 VDVDD = 1.8V 100 2.70 CURRENT (µA) TA = +85°C 200 CURRENT (µA) CURRENT (µA) 180 VDVDD = 1.8V CURRENT (µA) 220 1.0 MAX11212 toc02 VDVDD = 1.8V 200 240 MAX11212 toc01 240 ANALOG SLEEP CURRENT vs. AVDD VOLTAGE (MAX11212A/MAX11212B) ANALOG ACTIVE CURRENT vs. AVDD VOLTAGE (MAX11212B) MAX11212 toc03 ANALOG ACTIVE CURRENT vs. AVDD VOLTAGE (MAX11212A) MAX11212A 2.4 2.3 MAX11212B 2.2 TA = +85°C 60 0.5 50 2.1 0 40 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 DVDD VOLTAGE (V) Maxim Integrated 2.0 1.7 1.9 2.1 2.3 2.5 2.7 2.9 3.1 3.3 3.5 DVDD VOLTAGE (V) -45 -25 -5 15 35 55 75 95 TEMPERATURE (°C) 5 MAX11212 18-Bit, Single-Channel, Ultra-Low Power, DeltaSigma ADC with 2-Wire Serial Interface Typical Operating Characteristics (continued) (VAVDD = 3.6V, VDVDD = 1.8V, VREFP - VREFN = VAVDD; internal clock; TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25NC.) OFFSET ERROR vs. VREF (MAX11212A/MAX11212B) 2.4 2.3 MAX11212B 2.2 2.85 3.00 3.15 3.30 3.45 TA = +85°C TA = -45°C 1.5 2.0 2.5 3.0 3.5 -45 15 35 55 75 FULL-SCALE ERROR vs. TEMPERATURE (MAX11212A/MAX11212B) PSRR vs. FREQUENCY (MAX11212A) TA = +25°C 0 -2 -4 TA = -45°C -6 -8 +FS ERROR 6 0 -2.5 -2.0 -1.5 -1.0 -0.5 0 -20 -40 4 2 0 -2 -4 -60 -80 VAVDD -100 -6 -FS ERROR VDVDD -120 -8 -140 -45 0.5 1.0 1.5 2.0 2.5 95 MAX11212 toc15 VREF = 2.5V 8 MAX11212 toc14 10 -10 -10 -25 -5 15 35 55 75 1 10 100 1k 10k 100k INPUT VOLTAGE (V) TEMPERATURE (°C) FREQUENCY (Hz) PSRR vs. FREQUENCY (MAX11212B) CMRR vs. FREQUENCY (MAX11212A/MAX11212B) NORMAL-MODE FREQUENCY RESPONSE (MAX11212A) -20 -20 -60 VAVDD -100 -40 GAIN (dB) -40 CMRR (dB) -40 -60 -80 MAX11212A -100 VDVDD -120 -140 100 1k FREQUENCY (Hz) 10k 100k -60 -80 -100 -120 MAX11212B -140 10 MAX11212 toc18 -20 0 MAX11212 toc17 0 MAX11212 toc16 0 1 -5 INTEGRAL NONLINEARITY vs. INPUT VOLTAGE (MAX11212A/MAX11212B) 2 -120 -25 TEMPERATURE (°C) TA = +85°C -80 1.0 0 4.0 PSRR (dB) 4 1.5 VREF VOLTAGE (V) NORMALIZED FULL-SCALE ERROR (ppmFSR) 6 2.0 AVDD VOLTAGE (V) VAVDD = 3.0V VDVDD = 1.8V VREF = 2.5V VIN(CM) = 1.5V 8 CALIBRATED AT +25°C 0.5 1.0 3.60 MAX11212 toc13 10 INL (ppmFSR) 0.5 -1.0 2.70 PSRR (dB) 1.0 -0.5 2.1 6 TA = +25°C 0 2.5 MAX11212 toc12 1.5 OFFSET ERROR (ppmFSR) FREQUENCY (MHz) MAX11212A VREF = VREFP - VREFN OFFSET ERROR (ppmFSR) VDVDD = 1.8V 2.5 2.0 MAX11212 toc10 2.6 OFFSET ERROR vs. TEMPERATURE (MAX11212A/MAX11212B) MAX11212 toc11 INTERNAL OSCILLATOR FREQUENCY vs. AVDD VOLTAGE -140 1 10 100 1k FREQUENCY (Hz) 10k 100k 1 10 100 1k FREQUENCY (Hz) Maxim Integrated MAX11212 18-Bit, Single-Channel, Ultra-Low Power, DeltaSigma ADC with 2-Wire Serial Interface Typical Operating Characteristics (continued) (VAVDD = 3.6V, VDVDD = 1.8V, VREFP - VREFN = VAVDD; internal clock; TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25NC.) NORMAL-MODE REJECTION OF 50Hz TO 60Hz (MAX11212B) NORMAL-MODE FREQUENCY RESPONSE (MAX11212B) -20 -20 -40 GAIN (dB) -40 GAIN (dB) MAX11212 toc20 0 MAX11212 toc19 0 -60 -80 -60 -80 -100 -100 -120 -120 -140 -140 1 10 100 40 1k 45 FREQUENCY (Hz) 50 55 60 65 70 FREQUENCY (Hz) Functional Diagram TIMING AVDD CLOCK GENERATOR CLK DIGITAL LOGIC AND SERIALINTERFACE CONTROLLER SCLK DVDD GND AINP AINN REFP REFN Maxim Integrated 3RD-ORDER DELTA-SIGMA MODULATOR DIGITAL FILTER (SINC4) RDY/DOUT MAX11212 7 MAX11212 18-Bit, Single-Channel, Ultra-Low Power, DeltaSigma ADC with 2-Wire Serial Interface Pin Configuration TOP VIEW + GND 1 10 CLK REFP 2 REFN 3 AINN 4 7 DVDD AINP 5 6 AVDD MAX11212 9 SCLK 8 RDY/DOUT µMAX Pin Description PIN NAME 1 GND Ground. Ground reference for analog and digital circuitry. 2 REFP Differential Reference Positive Input. REFP must be more positive than REFN. Connect REFP to a voltage between AVDD and GND. 3 REFN Differential Reference Negative Input. REFN must be more negative than REFP. Connect REFN to a voltage between AVDD and GND. 4 AINN Negative Fully Differential Analog Input 5 AINP Positive Fully Differential Analog Input 6 AVDD Analog Supply Voltage. Connect a supply voltage between +2.7V to +3.6V with respect to GND. 7 DVDD Digital Supply Voltage. Connect a digital supply voltage between +1.7V to +3.6V with respect to GND. 8 Data-Ready Output/Serial-Data Output. This output serves a dual function. In addition to the serial-data output RDY/DOUT function, the RDY/DOUT also indicates that the data is ready when the RDY is logic-low. RDY/DOUT changes on the falling edge of SCLK. 9 SCLK 10 CLK 8 FUNCTION Serial-Clock Input. Apply an external serial clock to SCLK. External Clock Signal Input. The internal clock shuts down when CLK is driven by an external clock. Use a 2.4576MHz oscillator (MAX11212A) or a 2.2528MHz oscillator (MAX11212B). Maxim Integrated MAX11212 18-Bit, Single-Channel, Ultra-Low Power, DeltaSigma ADC with 2-Wire Serial Interface Detailed Description The MAX11212 is an ultra-low-power (< 240FA active), high-resolution, low-speed, serial-output ADC. This device provides the highest resolution per unit power in the industry, and is optimized for applications that require very high dynamic range with low power such as sensors on a 4mA to 20mA industrial control loop. The MAX11212 provides a high-accuracy internal oscillator, which requires no external components. When used with the specified data rates, the internal digital filter provides more than 80dB rejection of 50Hz or 60Hz line noise. The MAX11212 provides a simple, system-friendly, 2-wire serial interface in the space-saving, 10-pin FMAX package. Power-On Reset (POR) The MAX11212 utilizes power-on reset (POR) supplymonitoring circuitry on both the digital supply (DVDD) and the analog supply (AVDD). The POR circuitry ensures proper device default conditions after either a digital or analog power-sequencing event. The MAX11212 performs a self-calibration operation as part of the startup initialization sequence whenever a digital POR is triggered. It is important to have a stable reference voltage available at the REFP and REFN pins to ensure an accurate calibration cycle. If the reference voltage is not stable during a POR event, the part should be calibrated once the reference has stabilized. The part can be programmed for calibration by using 26 SCLKs as shown in Figure 3. The digital POR trigger threshold is approximately 1.2V and has 100mV of hysteresis. The analog POR trigger threshold is approximately 1.25V and has 100mV of hysteresis. Both POR circuits have lowpass filters that prevent high-frequency supply glitches from triggering the POR. The analog supply (AVDD) and the digital supply (DVDD) pins should be bypassed using 0.1FF capacitors placed as close as possible to the package pin. Analog Inputs The MAX11212 accepts two analog inputs (AINP and AINN). The modulator input range is bipolar (-VREF to +VREF). Internal Oscillator The MAX11212 incorporates a highly stable internal oscillator that provides the system clock. The system clock runs the internal state machine and is trimmed to Maxim Integrated 2.4576MHz (MAX11212A) or 2.2528MHz (MAX11212B). The internal oscillator clock is divided down to run the digital and analog timing. Reference The MAX11212 provides differential inputs REFP and REFN for an external reference voltage. Connect the external reference directly across REFP and REFN to obtain the differential reference voltage. The commonmode voltage range for VREFP and VREFN is between 0 and VAVDD. The differential voltage range for REFP and REFN is 1V to VAVDD. Digital Filter The MAX11212 contains an on-chip, digital lowpass filter that processes the 1-bit data stream from the modulator using a SINC4 (sinx/x)4 response. When the device is operating in single-cycle conversion mode, the filter is reset at the end of the conversion cycle. When operating in continuous conversion latent mode, the filter is not reset. The SINC4 filter has a -3dB frequency equal to 24% of the data rate. Serial-Digital Interface The MAX11212 communicates through a 2-wire serial interface with a clock input and data output. The output rate is predetermined based on the package option (MAX11212A at 120sps and MAX11212B at 13.75sps). 2-Wire Interface The MAX11212 is compatible with the 2-wire interface and uses SCLK and RDY/DOUT for serial communications. In this mode, all controls are implemented by timing the high or low phase of the SCLK. The 2-wire serial interface only allows for data to be read out through the RDY/DOUT output. Supply the serial clock to SCLK to shift the conversion data out. The RDY/DOUT is used to signal data ready, as well as reading the data out when SCLK pulses are applied. RDY/DOUT is high by default. The MAX11212 pulls RDY/DOUT low when data is available at the end of conversion, and stays low until clock pulses are applied at SCLK input; on applying the clock pulses at SCLK, the RDY/DOUT outputs the conversion data on every SCLK positive edge. To monitor data availability, pull RDY/DOUT high after reading the 18 bits of data by supplying a 25th SCLK pulse. The different operational modes using this 2-wire interface are described in the following sections. 9 MAX11212 18-Bit, Single-Channel, Ultra-Low Power, DeltaSigma ADC with 2-Wire Serial Interface Data Read Following Every Conversion The MAX11212 indicates conversion data availability as well as allows the retrieval of data through the RDY/DOUT output. The RDY/DOUT output idles at the value of the last bit read unless a 25th SCLK pulse is provided, causing RDY/DOUT to idle high. RDY/DOUT is pulled low when the conversion data is available. If the data is not read before the next conversion data is updated, the old data is lost, as the new data overwrites the old value. Data Read Followed by Self-Calibration To initiate self-calibration at the end of a data read, provide a 26th SCLK pulse. After reading the 16 bits of conversion data, a 25th positive edge on SCLK pulls the RDY/DOUT output back high, indicating end of data read. Provide a 26th SCLK pulse to initiate a self-calibration routine starting on the falling edge of the 26th SCLK. A subsequent falling edge of RDY/DOUT indicates data availability at the end of calibration. The timing is illustrated in Figure 3. Figure 1 shows the timing diagram for the data read. Once a low is detected on RDY/DOUT, clock pulses at SCLK clock out the data. Data is shifted out MSB first and is in binary two’s complement format. Once all the data has been shifted out, a 25th SCLK is required to pull the RDY/DOUT output back to the idle high state. See Figure 2. t1 t5 t2 SCLK 1 2 3 24 t3 t4 RDY/DOUT D17 D16 0 t6 CONVERSION IS DONE DATA IS AVAILABLE CONVERSION IS DONE DATA IS AVAILABLE t7 Figure 1. Timing Diagram for Data Read After Conversion SCLK 1 2 3 24 25 25TH SLK RISING EDGE PULLS RDY/DOUT HIGH RDY/DOUT D17 D16 0 CONVERSION IS DONE DATA IS AVAILABLE CONVERSION IS DONE DATA IS AVAILABLE Figure 2. Timing Diagram for Data Read Followed by RDY/DOUT Being Asserted High Using 25th SCLK 10 Maxim Integrated MAX11212 18-Bit, Single-Channel, Ultra-Low Power, DeltaSigma ADC with 2-Wire Serial Interface CALIBRATION STARTS ON 26TH SCLK SCLK 1 2 3 25 24 26 1 2 25TH SCLK PULLS RDY/DOUT HIGH RDY/DOUT D17 D16 0 D17 CONVERSION IS DONE DATA IS AVAILABLE D16 CONVERSION IS DONE DATA IS AVAILABLE AFTER CALIBRATION t8 Figure 3. Timing Diagram for Data Read Followed by Two Extra Clock Cycles for Self-Calibration DEVICE ENTERS SLEEP MODE SCLK 1 2 3 DEVICE EXITS OUT SLEEP MODE 1 24 2 SLEEP MODE t9 t10 RDY/DOUT D17 D16 0 D17 CONVERSION IS DONE DATA IS AVAILABLE D16 CONVERSION IS DONE DATA IS AVAILABLE t11 Figure 4. Timing Diagram for Data Read Followed by Sleep Mode Activation; Single-Conversion Timing Data Read Followed by Sleep Mode The MAX11212 can be put into sleep mode to save power between conversions. To activate the sleep mode, idle the SCLK high any time after the RDY/DOUT output goes low (that is, after conversion data is available). It is not required to read out all 18 bits before putting the part in sleep mode. Sleep mode is activated after the SCLK is held high (see Figure 4). The RDY/DOUT output is pulled high once the device enters sleep mode. To come out of sleep mode, pull SCLK low. After the sleep mode is deactivated (when the device wakes up), conversion Maxim Integrated starts again and RDY/DOUT goes low, indicating the next conversion data is available. See Figure 4. Single-Conversion Mode For operating the MAX11212 in single-conversion mode, activate and deactivate sleep mode between conversions as described in the Data Read Followed by Sleep Mode section). Single-conversion mode reduces power consumption by shutting down the device when idle between conversions. See Figure 4. Single-Conversion Mode with 11 MAX11212 18-Bit, Single-Channel, Ultra-Low Power, DeltaSigma ADC with 2-Wire Serial Interface ed out followed by 25th SCLK edge to pull RDY/DOUT high, and then on the 26th SCLK keep it high for as long as shutdown is desired. Once SCLK is pulled back low, the device automatically performs a self-calibration and, when the data is ready, the RDY/DOUT output goes low. See Figure 5. This also achieves the purpose of single conversions with self-calibration. Self-Calibration at Wake-Up The MAX11212 can be put in self-calibration mode immediately after wake-up from sleep mode. Selfcalibration at wake-up helps to compensate for temperature or supply changes if the device is shut down for extensive periods. To automatically start self-calibration at the end of sleep mode, all the data bits must be shift- 25TH SCLK PULLS RDY/DOUT HIGH SCLK 1 2 3 DEVICE ENTERS SLEEP MODE 24 25 DEVICE EXITS OUT SLEEP MODE AND STARTS CALIBRATION 1 26 2 SLEEP MODE t10 RDY/DOUT D17 D16 0 CONVERSION IS DONE DATA IS AVAILABLE D17 D16 CONVERSION IS DONE DATA IS AVAILABLE AFTER CALIBRATION t12 Figure 5. Timing Diagram for Sleep Mode Activation Followed by Self-Calibration at Wake-Up 12 Maxim Integrated MAX11212 18-Bit, Single-Channel, Ultra-Low Power, DeltaSigma ADC with 2-Wire Serial Interface Applications Information See Figure 6 for the RTD temperature measurement circuit and Figure 7 for a resistive bridge measurement circuit. Chip Information PROCESS: BiCMOS IREF2 REFP IREF1 Package Information MAX11212 RREF REFN IREF1 = K x IREF2 AINP RRTD For the latest package outline information and land patterns, go to www.maximintegrated.com/packages. Note that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. PACKAGE TYPE PACKAGE CODE DOCUMENT NO. 10 µMAX U10+2 21-0061 AINN GND Figure 6. RTD Temperature Measurement Circuit AVDD REFP REFN MAX11212 AINP AINN Figure 7. Resistive Bridge Measurement Circuit Maxim Integrated 13 MAX11212 18-Bit, Single-Channel, Ultra-Low Power, DeltaSigma ADC with 2-Wire Serial Interface Revision History REVISION NUMBER REVISION DATE 0 4/10 DESCRIPTION Initial release PAGES CHANGED — Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits) shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance. 14 © 2010 Maxim Integrated 160 Rio Robles, San Jose, CA 95134 USA 1-408-601-1000 Maxim Integrated Products, Inc. Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc.