19-5962; Rev 1; 9/11 KIT ATION EVALU E L B A AVAIL 12-Bit, 300ksps ADCs with Differential Track/Hold, and Internal Reference Features o Analog Multiplexer with True Differential Track/Hold 8-/4-Channel Single-Ended 4-/2-Channel True Differential Unipolar or Bipolar Inputs Applications System Supervision o 10MHz 3-Wire SPI-/QSPI-/MICROWIRE-Compatible Interface Data-Acquisition Systems o Small 16-Pin QSOP Package o Single Supply 2.7V to 3.6V (MAX11635/MAX11637) 4.75V to 5.25V (MAX11634/MAX11636) o External Reference: 1V to VDD o 16-Entry First-In/First-Out (FIFO) o Scan Mode, Internal Averaging, and Internal Clock o Accuracy: ±1 LSB INL, ±1 LSB DNL, No Missing Codes Over Temperature Industrial Control Systems Patient Monitoring Data Logging Instrumentation Ordering Information/Selector Guide PART NUMBER OF INPUTS SUPPLY VOLTAGE (V) TEMP RANGE PIN-PACKAGE MAX11634EEE+T 4 Single-Ended/ 2 Differential 4.75 to 5.25 -40°C to +85°C 16 QSOP MAX11635EEE+T 4 Single-Ended/ 2 Differential 2.7 to 3.6 -40°C to +85°C 16 QSOP MAX11636EEE+T 8 Single-Ended/ 4 Differential 4.75 to 5.25 -40°C to +85°C 16 QSOP MAX11637EEE+T 8 Single-Ended/ 4 Differential 2.7 to 3.6 -40°C to +85°C 16 QSOP +Denotes a lead(Pb)-free/RoHS-compliant package. T = Tape and reel. AutoShutdown is a trademark of Maxim Integrated Products, Inc. SPI/QSPI are trademarks of Motorola, Inc. MICROWIRE is a trademark of National Semiconductor Corp. ________________________________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. 1 MAX11634–MAX11637 General Description The MAX11634–MAX11637 are serial 12-bit analog-todigital converters (ADCs) with an internal reference and true differential track/hold. These devices feature on-chip FIFO, scan mode, internal clock mode, internal averaging, and AutoShutdown™. The maximum sampling rate is 300ksps using an external clock. The MAX11636/ MAX11637 have 8 input channels and the MAX11634/ MAX11635 have 4 input channels. These four devices operate from either a +3V supply or a +5V supply, and contain a 10MHz SPI™-/QSPI™-/MICROWIRE™-compatible serial port. The MAX11634–MAX11637 are available in a 16-pin QSOP package. All four devices are specified over the extended -40°C to +85°C temperature range. MAX11634–MAX11637 12-Bit, 300ksps ADCs with Differential Track/Hold, and Internal Reference ABSOLUTE MAXIMUM RATINGS VDD to GND ..............................................................-0.3V to +6V CS, SCLK, DIN, EOC, DOUT to GND.........-0.3V to (VDD + 0.3V) AIN0–AIN5, REF-/AIN6, CNVST/AIN7, REF+ to GND.........................................-0.3V to (VDD + 0.3V) Maximum Current into any Pin ............................................50mA Continuous Power Dissipation (TA = +70°C) QSOP (single-layer board) (derate 8.3mW/°C above +70°C) .................................667mW Operating Temperature Range ...........................-40°C to +85°C Storage Temperature Range .............................-60°C to +150°C Junction Temperature ......................................................+150°C Lead Temperature (soldering, 10s) .................................+300°C Soldering Temperature (reflow) .......................................+260°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. PACKAGE THERMAL CHARACTERISTICS (Note 1) QSOP Junction-to-Ambient Thermal Resistance (θJA)...............105°C/W Junction-to-Case Thermal Resistance (θJC)......................37°C/W Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a fourlayer board. For detailed information on package thermal considerations, refer to www.maxim-ic.com/thermal-tutorial. ELECTRICAL CHARACTERISTICS (VDD = 2.7V to 3.6V (MAX11635/MAX11637), VDD = 4.75V to 5.25V (MAX11634/MAX11636), fSAMPLE = 300kHz, fSCLK = 4.8MHz (external clock, 50% duty cycle), VREF = 2.5V (MAX11635/MAX11637), VREF = 4.096V (MAX11634/MAX11636) TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) (Note 2) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS DC ACCURACY (Note 3) Resolution RES Integral Nonlinearity INL Differential Nonlinearity DNL 12 ±1.0 LSB ±1.0 LSB ±0.5 ±4.0 LSB ±0.5 ±4.0 No missing codes over temperature Offset Error Gain Error Bits (Note 4) Offset Error Temperature Coefficient LSB ±2 ppm/°C FSR Gain Temperature Coefficient ±0.8 ppm/°C Channel-to-Channel Offset Matching ±0.1 LSB DYNAMIC SPECIFICATIONS (30kHz sine-wave input, 300ksps, fSCLK = 4.8MHz) Signal-to-Noise Plus Distortion SINAD Total Harmonic Distortion THD Spurious-Free Dynamic Range SFDR Intermodulation Distortion 71 73 Up to the 5th harmonic MAX11635/MAX11637 -80 MAX11634/MAX11636 -88 MAX11635/MAX11637 81 MAX11634/MAX11636 89 dB dBc dBc f IN1 = 29.9kHz, f IN2 = 30.2kHz 76 dBc Full-Power Bandwidth -3dB point 1 MHz Full-Linear Bandwidth S/(N + D) > 68dB 100 kHz 2 IMD MAX11635/MAX11637 MAX11634/MAX11636 _______________________________________________________________________________________ 12-Bit, 300ksps ADCs with Differential Track/Hold, and Internal Reference (VDD = 2.7V to 3.6V (MAX11635/MAX11637), VDD = 4.75V to 5.25V (MAX11634/MAX11636), fSAMPLE = 300kHz, fSCLK = 4.8MHz (external clock, 50% duty cycle), VREF = 2.5V (MAX11635/MAX11637), VREF = 4.096V (MAX11634/MAX11636) TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) (Note 2) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS CONVERSION RATE Power-Up Time t PU Acquisition Time tACQ Conversion Time tCONV External Clock Frequency f SCLK External reference 0.8 Internal reference (Note 5) 65 µs 0.6 Internally clocked µs 3.5 Externally clocked (Note 6) 2.7 Externally clocked conversion 0.1 µs 4.8 Data I/O 10 MHz Aperture Delay 30 ns Aperture Jitter < 50 ps ANALOG INPUT Unipolar Input Voltage Range Bipolar (Note 7) Input Leakage Current VIN = VDD Input Capacitance During acquisition time (Note 8) 0 VREF -VREF/2 +VREF/2 ±0.01 ±1 24 V µA pF INTERNAL REFERENCE REF Output Voltage REF Temperature Coefficient TCREF MAX11634/MAX11636 4.024 4.096 4.168 MAX11635/MAX11637 2.48 2.50 2.52 MAX11634/MAX11636 ±20 MAX11635/MAX11637 ±30 V ppm/°C Output Resistance 6.5 k REF Output Noise 200 µVRMS -70 dB REF Power-Supply Rejection PSRR EXTERNAL REFERENCE INPUT REF- Input Voltage Range VREF- REF+ Input Voltage Range VREF+ REF+ Input Current IREF+ 0 500 1.0 VDD + 50mV VREF+ = 2.5V (MAX11635/MAX11637), VREF+ = 4.096V (MAX11634/MAX11636), f SAMPLE = 300ksps 40 VREF+ = 2.5V (MAX11635/MAX11637), VREF+ = 4.096V (MAX11634/MAX11636), f SAMPLE = 0 ±0.1 mV V 100 µA ±5 DIGITAL INPUTS (SCLK, DIN, CS, CNVST (Note 9) Input Voltage Low VIL Input Voltage High VIH Input Hysteresis VHYST MAX11634/MAX11636 0.8 MAX11635/MAX11637 VDD x 0.3 MAX11634/MAX11636 2.0 MAX11635/MAX11637 VDD x 0.7 V V 200 mV _______________________________________________________________________________________ 3 MAX11634–MAX11637 ELECTRICAL CHARACTERISTICS (continued) MAX11634–MAX11637 12-Bit, 300ksps ADCs with Differential Track/Hold, and Internal Reference ELECTRICAL CHARACTERISTICS (continued) (VDD = 2.7V to 3.6V (MAX11635/MAX11637), VDD = 4.75V to 5.25V (MAX11634/MAX11636), fSAMPLE = 300kHz, fSCLK = 4.8MHz (external clock, 50% duty cycle), VREF = 2.5V (MAX11635/MAX11637), VREF = 4.096V (MAX11634/MAX11636) TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) (Note 2) PARAMETER SYMBOL Input Leakage Current I IN Input Capacitance CIN CONDITIONS MIN VIN = 0V or VDD TYP MAX UNITS ±0.01 ±1.0 µA 15 pF DIGITAL OUTPUTS (DOUT, EOC) Output Voltage Low VOL Output Voltage High VOH Three-State Leakage Current Three-State Output Capacitance I SINK = 2mA 0.4 I SINK = 4mA 0.8 I SOURCE = 1.5mA VDD - 0.5 V V IL CS = VDD ±0.05 C OUT CS = VDD 15 ±1 µA pF POWER REQUIREMENTS Supply Voltage MAX11635/MAX11637 Supply Current (Note 10) VDD MAX11634/MAX11636 4.75 5.25 MAX11635/MAX11637 2.7 3.6 Internal reference IDD Internal reference PSR 2000 1000 1200 0.2 5 1050 1200 f SAMPLE = 300ksps Shutdown 0.2 5 f SAMPLE = 300ksps 2300 2550 f SAMPLE = 0, REF on 1050 1350 Shutdown IDD External reference Power-Supply Rejection 1750 f SAMPLE = 0, REF on Shutdown External reference MAX11634/MAX11636 Supply Current (Note 10) f SAMPLE = 300ksps f SAMPLE = 300ksps Shutdown 0.2 5 1500 1700 0.2 5 VDD = 2.7V to 3.6V, full-scale input ±0.2 ±1 VDD = 4.75V to 5.25V, full-scale input ±0.2 ±1.4 V µA µA mV Limits at TA = -40°C are guaranteed by design and not production tested. Tested at VDD = 3V (MAX11635/MAX11637); VDD = 5V (MAX11634/MAX11636), unipolar input mode. Offset nulled. Time for reference to power up and settle to within 1 LSB. Conversion time is defined as the number of clock cycles multiplied by the clock period; clock has 50% duty cycle. The operational input voltage range for each individual input of a differentially configured pair is from GND to VDD. The operational input voltage difference is from -VREF/2 to +VREF/2. Note 8: See Figure 3 (Equivalent Input Circuit) and the Sampling Error vs. Source Impedance curve in the Typical Operating Characteristics section. Note 9: When CNVST is configured as a digital input, do not apply a voltage between VIL and VIH. Note 10: Supply current is specified depending on whether an internal or external reference is used for voltage conversions. Temperature measurements always use the internal reference. Note 2: Note 3: Note 4: Note 5: Note 6: Note 7: 4 _______________________________________________________________________________________ 12-Bit, 300ksps ADCs with Differential Track/Hold, and Internal Reference MAX11634–MAX11637 TIMING CHARACTERISTICS (Figure 1) PARAMETER SYMBOL SCLK Clock Period tCP SCLK Pulse-Width High tCH SCLK Pulse-Width Low CONDITIONS MIN Externally clocked conversion 208 Data I/O 100 TYP MAX UNITS ns 40 tCL ns 40 ns SCLK Fall to DOUT Transition tDOT CLOAD = 30pF 40 ns CS Rise to DOUT Disable tDOD CLOAD = 30pF 40 ns CS Fall to DOUT Enable tDOE CLOAD = 30pF 40 ns DIN to SCLK Rise Setup tDS 40 ns SCLK Rise to DIN Hold tDH 0 ns CS Low to SCLK Setup tCSS0 40 ns CS High to SCLK Setup tCSS1 40 ns CS High After SCLK Hold tCSH1 0 ns CS Low After SCLK Hold tCSH0 0 tCSPW CNVST Pulse-Width Low CS or CNVST Rise to EOC Low (Note 11) 4 µs CKSEL = 00 40 ns CKSEL = 01 1.4 µs Voltage conversion 7 Reference power-up 65 µs Note 11: This time is defined as the number of clock cycles needed for conversion multiplied by the clock period. If the internal reference needs to be powered up, the total time is additive. The internal reference is always used for temperature measurements. Typical Operating Characteristics (VDD = 3V, VREF = 2.5V, fSCLK = 4.8MHz, CLOAD = 30pF, TA = +25°C for MAX11635/MAX11637, unless otherwise noted. VDD = 5V, VREF = 4.096V, fSCLK = 4.8MHz, CLOAD = 30pF, TA = +25°C for MAX11634/MAX11636, unless otherwise noted.) INTEGRAL NONLINEARITY vs. OUTPUT CODE 0.6 1.0 MAX11634 toc02 0.8 0.8 0.6 0.8 0.6 0.4 0.4 0.2 0.2 0.2 0 -0.2 0 -0.2 -0.4 -0.4 -0.6 -0.6 MAX11634/MAX11636 fSAMPLE = 300ksps -0.8 -1.0 DNL (LSB) 0.4 INL (LSB) INL (LSB) 1.0 MAX11634 toc01 1.0 DIFFERENTIAL NONLINEARITY vs. OUTPUT CODE 1024 2048 3072 OUTPUT CODE (DECIMAL) 4096 0 -0.2 -0.4 -0.6 MAX11635/MAX11637 fSAMPLE = 300ksps -0.8 -1.0 0 MAX11634 toc03 INTEGRAL NONLINEARITY vs. OUTPUT CODE 0 1024 2048 3072 OUTPUT CODE (DECIMAL) 4096 MAX11634/MAX11636 fSAMPLE = 300ksps -0.8 -1.0 0 1024 2048 3072 4096 OUTPUT CODE (DECIMAL) _______________________________________________________________________________________ 5 Typical Operating Characteristics (continued) (VDD = 3V, VREF = 2.5V, fSCLK = 4.8MHz, CLOAD = 30pF, TA = +25°C for MAX11635/MAX11637, unless otherwise noted. VDD = 5V, VREF = 4.096V, fSCLK = 4.8MHz, CLOAD = 30pF, TA = +25°C for MAX11634/MAX11636, unless otherwise noted.) SFDR vs. FREQUENCY SINAD vs. FREQUENCY 0.6 MAX11634/MAX11636 75 SINAD (dB) 0.4 0.2 0 -0.2 MAX11634/MAX11636 90 70 SFDR (dB) 0.8 100 MAX11634 toc05 80 MAX11634 toc04 1.0 MAX11635/MAX11637 65 80 70 60 -0.4 -0.6 0 1024 2048 50 50 4096 3072 1 OUTPUT CODE (DECIMAL) 10 1 1000 100 10 1000 100 FREQUENCY (kHz) FREQUENCY (kHz) THD vs. FREQUENCY SUPPLY CURRENT vs. SAMPLING RATE 3000 MAX11634 toc07 -50 -60 MAX11634/MAX11636 VDD = 5V 2500 MAX11635/MAX11637 2000 IDD (µA) -70 THD (dB) MAX11635/MAX11637 MAX11634 toc08 -1.0 60 55 MAX11635/MAX11637 fSAMPLE = 300ksps -0.8 INTERNAL REFERENCE 1500 -80 1000 EXTERNAL REFERENCE -90 500 MAX11634/MAX11636 -100 0 10 100 1000 1 10 FREQUENCY (kHz) SUPPLY CURRENT vs. SAMPLING RATE MAX11635/MAX11637 VDD = 3V 1600 1400 INTERNAL REFERENCE 2400 2200 INTERNAL REFERENCE IDD (µA) 1200 IDD (µA) SUPPLY CURRENT vs. SUPPLY VOLTAGE 2600 MAX11634 toc09 1800 1000 100 SAMPLING RATE (ksps) MAX11634 toc10 1 1000 800 600 2000 1800 EXTERNAL REFERENCE 1600 EXTERNAL REFERENCE 400 1400 200 1200 0 MAX11634/MAX11636 fSAMPLE = 300ksps 1000 1 10 100 SAMPLING RATE (ksps) 6 MAX11634 toc06 DIFFERENTIAL NONLINEARITY vs. OUTPUT CODE DNL (LSB) MAX11634–MAX11637 12-Bit, 300ksps ADCs with Differential Track/Hold, and Internal Reference 1000 4.75 4.85 4.95 5.05 VDD (V) _______________________________________________________________________________________ 5.15 5.25 12-Bit 300ksps ADCs with FIFO, Temp Sensor, Internal Reference SHUTDOWN SUPPLY CURRENT vs. SUPPLY VOLTAGE INTERNAL REFERENCE 0.8 1600 0.7 EXTERNAL REFERENCE 800 0.5 IDD (µA) IDD (µA) 1200 0.4 0.2 0.3 600 0.3 0.2 400 0.1 MAX11634/MAX11636 VDD = 5V 0.1 0 0 4.75 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6 4.85 4.95 5.05 MAX11635/MAX11637 VDD = 3V 2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6 VDD (V) VDD (V) VDD (V) SUPPLY CURRENT vs. TEMPERATURE SUPPLY CURRENT vs. TEMPERATURE 1800 MAX11634 toc14 2500 INTERNAL REFERENCE 2200 0 5.25 5.15 MAX11634 toc15 MAX11635/MAX11637 fSAMPLE = 300ksps 200 INTERNAL REFERENCE 1600 IDD (µA) IDD (µA) 1400 1900 MAX11635/MAX11637 VDD = 3V fSAMPLE = 300ksps 1200 1600 1000 EXTERNAL REFERENCE 1300 MAX11634/MAX11636 VDD = 5V fSAMPLE = 300ksps 1000 2.5 -15 10 35 60 -40 -15 10 35 60 TEMPERATURE (°C) TEMPERATURE (°C) SHUTDOWN SUPPLY CURRENT vs. TEMPERATURE SHUTDOWN SUPPLY CURRENT vs. TEMPERATURE MAX11634/MAX11636 VDD = 5V 2.0 1.0 1.5 MAX11635/MAX11637 VDD = 3V 0.8 IDD (µA) IDD (µA) EXTERNAL REFERENCE 600 85 MAX11634 toc16 -40 800 85 MAX11634 toc17 IDD (µA) 0.4 0.6 1400 1000 0.5 MAX11634 toc12 1800 MAX11634 toc11 2000 SHUTDOWN SUPPLY CURRENT vs. SUPPLY VOLTAGE MAX11634 toc13 SUPPLY CURRENT vs. SUPPLY VOLTAGE 0.6 1.0 0.4 0.5 0.2 0 0 -40 -15 10 35 TEMPERATURE (°C) 60 85 -40 -15 10 35 60 85 TEMPERATURE (°C) _______________________________________________________________________________________ 7 MAX11634–MAX11637 Typical Operating Characteristics (continued) (VDD = 3V, VREF = 2.5V, fSCLK = 4.8MHz, CLOAD = 30pF, TA = +25°C for MAX11635/MAX11637, unless otherwise noted. VDD = 5V, VREF = 4.096V, fSCLK = 4.8MHz, CLOAD = 30pF, TA = +25°C for MAX11634/MAX11636, unless otherwise noted.) Typical Operating Characteristics (continued) (VDD = 3V, VREF = 2.5V, fSCLK = 4.8MHz, CLOAD = 30pF, TA = +25°C for MAX11635/MAX11637, unless otherwise noted. VDD = 5V, VREF = 4.096V, fSCLK = 4.8MHz, CLOAD = 30pF, TA = +25°C for MAX11634/MAX11636, unless otherwise noted.) INTERNAL REFERENCE VOLTAGE vs. SUPPLY VOLTAGE INTERNAL REFERENCE VOLTAGE vs. TEMPERATURE INTERNAL REFERENCE VOLTAGE vs. SUPPLY VOLTAGE VREF (V) 4.097 4.096 4.11 2.500 2.499 4.095 4.85 4.95 5.05 5.25 5.15 4.08 MAX11635/MAX11637 VDD = 3V 4.094 4.75 MAX11634/MAX11636 VDD = 5V 2.497 4.07 2.7 VDD (V) 3.0 3.6 3.3 35 MAX11634 toc22 0 -0.2 MAX11634/MAX11636 fSAMPLE = 300ksps -0.6 4.75 85 60 0.2 -0.4 MAX11635/MAX11637 VDD = 3V 10 4.85 OFFSET ERROR vs. SUPPLY VOLTAGE 5.25 MAX11634 toc24 MAX11634 toc23 0.95 0.6 0.2 -0.2 -0.6 MAX11635/MAX11637 fSAMPLE = 300ksps 0.90 VDD (V) 5.15 1.0 OFFSET ERROR (LSB) OFFSET ERROR (LSB) 1.00 3.3 5.05 OFFSET ERROR vs. TEMPERATURE 1.05 3.0 4.95 VDD (V) TEMPERATURE (°C) 1.10 60 0.4 2.48 2.47 35 0.6 MAX11634 toc21 2.50 2.49 8 10 TEMPERATURE (°C) OFFSET ERROR (LSB) VREF (V) 2.51 2.7 -15 OFFSET ERROR vs. SUPPLY VOLTAGE 2.52 -15 -40 VDD (V) INTERNAL REFERENCE VOLTAGE vs. TEMPERATURE -40 4.10 4.09 2.498 MAX11634/MAX11636 VDD = 5V MAX11634 toc20 2.501 VREF (V) 4.098 4.12 MAX11634 toc19 2.502 MAX11634 toc18 4.099 VREF (V) MAX11634–MAX11637 12-Bit, 300ksps ADCs with Differential Track/Hold, and Internal Reference 3.6 MAX11634/MAX11636 fSAMPLE = 300ksps -1.0 -40 -15 10 35 TEMPERATURE (°C) _______________________________________________________________________________________ 60 85 85 12-Bit, 300ksps ADCs with Differential Track/Hold, and Internal Reference 0.9 0.5 -0.1 GAIN ERROR (LSB) 1.1 0 MAX11634 toc26 MAX11634 toc25 0.6 GAIN ERROR (LSB) 0.4 0.3 -0.2 -0.3 0.2 0.7 -0.4 MAX11634/MAX11636 fSAMPLE = 300ksps 0.1 MAX11635/MAX11637 fSAMPLE = 300ksps -15 10 35 60 4.75 85 4.85 4.95 5.05 5.15 3.0 3.6 3.3 TEMPERATURE (°C) VDD (V) VDD (V) GAIN ERROR vs. TEMPERATURE GAIN ERROR vs. TEMPERATURE SAMPLING ERROR vs. SOURCE IMPEDANCE 0.3 GAIN ERROR (LSB) 0.6 MAX11635/MAX11637 fSAMPLE = 300ksps 0.2 -0.2 -0.6 0.1 -0.1 -0.3 10 35 TEMPERATURE (°C) 60 85 -2 -4 -6 -10 -0.5 -15 0 -8 MAX11634/MAX11636 fSAMPLE = 300ksps -1.0 2 MAX11634 toc30 0.5 MAX11634 toc28 1.0 -40 2.7 5.25 SAMPLING ERROR (LSB) -40 MAX11635/MAX11637 fSAMPLE = 300ksps -0.5 0 0.5 MAX11634 toc29 OFFSET ERROR (LSB) 1.3 GAIN ERROR (LSB) GAIN ERROR vs. SUPPLY VOLTAGE GAIN ERROR vs. SUPPLY VOLTAGE 0.7 MAX11634 toc27 OFFSET ERROR vs. TEMPERATURE 1.5 -40 -15 10 35 TEMPERATURE (°C) 60 85 0 2 4 6 8 10 SOURCE IMPEDANCE (kΩ) _______________________________________________________________________________________ 9 MAX11634–MAX11637 Typical Operating Characteristics (continued) (VDD = 3V, VREF = 2.5V, fSCLK = 4.8MHz, CLOAD = 30pF, TA = +25°C for MAX11635/MAX11637, unless otherwise noted. VDD = 5V, VREF = 4.096V, fSCLK = 4.8MHz, CLOAD = 30pF, TA = +25°C for MAX11634/MAX11636, unless otherwise noted.) 12-Bit, 300ksps ADCs with Differential Track/Hold, and Internal Reference MAX11634–MAX11637 Pin Configuration TOP VIEW AIN0 1 + 16 EOC AIN1 2 15 DOUT AIN2 3 14 DIN AIN3 4 AIN4 (N.C.) 5 MAX11634– MAX11637 13 SCLK 12 CS AIN5 (N.C.) 6 11 VDD REF-/AIN6 (REF-) 7 10 GND CNVST/AIN7 (CNVST) 8 9 REF+ QSOP ( ) PINOUT FOR THE MAX11634/MAX11635. Pin Description PIN MAX11636 MAX11637 NAME 1–4 — AIN0–AIN3 5, 6 — N.C. No Connection. Not internally connected. 7 — REF- External Differential Reference Negative Input 8 — CNVST MAX11634 MAX11635 10 FUNCTION Analog Inputs Active-Low Conversion Start Input. See Table 3 for details on programming the setup register. 9 9 REF+ Positive Reference Input. Bypass to GND with a 0.1µF capacitor. 10 10 GND Ground 11 11 VDD Power Input. Bypass to GND with a 0.1µF capacitor. 12 12 CS Active-Low Chip-Select Input. When CS is high, DOUT is high impedance. 13 13 SCLK Serial-Clock Input. Clocks data in and out of the serial interface (duty cycle must be 40% to 60%). See Table 3 for details on programming the clock mode. 14 14 DIN Serial-Data Input. DIN data is latched into the serial interface on the rising edge of SCLK. 15 15 DOUT Serial-Data Output. Data is clocked out on the falling edge of SCLK. High impedance when CS is connected to VDD. Active-Low End-of-Conversion Output. Data is valid after EOC pulls low. 16 16 EOC — 1–6 AIN0–AIN5 Analog Inputs External Differential Reference Negative Input/Analog Input 6. See Table 3 for details on programming the setup register. — 7 REF-/AIN6 — 8 CNVST/AIN7 Active-Low Conversion Start Input/Analog Input 7. See Table 3 for details on programming the setup register. ______________________________________________________________________________________ 12-Bit, 300ksps ADCs with Differential Track/Hold, and Internal Reference MAX11634–MAX11637 CS tCP tCH tCSS0 tCSH1 tCL tCSH0 tCSS1 SCLK tDH tDS DIN tDOT tDOD tDOE DOUT Figure 1. Detailed Serial-Interface Timing Diagram CS DIN SCLK SERIAL INTERFACE OSCILLATOR CONTROL DOUT EOC CNVST AIN0 AIN1 T/H 12-BIT SAR ADC FIFO AND ACCUMULATOR AIN7 REFREF+ INTERNAL REFERENCE MAX11634–MAX11637 Figure 2. Functional Diagram Detailed Description The MAX11634–MAX11637 are low-power, serial-output, multichannel ADCs for temperature-control, process-control, and monitoring applications. These 12-bit ADCs have internal track and hold (T/H) circuitry that supports single-ended and fully differential inputs. Data is converted from analog voltage sources in a variety of channel and data-acquisition configurations. Microprocessor (µP) control is made easy through a 3wire SPI/QSPI/MICROWIRE-compatible serial interface. Figure 2 shows a simplified functional diagram of the MAX11634–MAX11637 internal architecture. The MAX11636/MAX11637 have eight single-ended analog input channels or four differential channels. The MAX11634/MAX11635 have four single-ended analog input channels or two differential channels. ______________________________________________________________________________________ 11 MAX11634–MAX11637 12-Bit, 300ksps ADCs with Differential Track/Hold, and Internal Reference Converter Operation The MAX11634–MAX11637 ADCs use a fully differential, successive-approximation register (SAR) conversion technique and an on-chip T/H block to convert temperature and voltage signals into a 12-bit digital result. Both single-ended and differential configurations are supported, with a unipolar signal range for singleended mode and bipolar or unipolar ranges for differential mode. Input Bandwidth The ADC’s input-tracking circuitry has a 1MHz smallsignal bandwidth, so it is possible to digitize highspeed transient events and measure periodic signals with bandwidths exceeding the ADC’s sampling rate by using undersampling techniques. Anti-alias prefiltering of the input signals is necessary to avoid high-frequency signals aliasing into the frequency band of interest. Analog Input Protection Internal ESD protection diodes clamp all pins to VDD and GND, allowing the inputs to swing from (GND 0.3V) to (VDD + 0.3V) without damage. However, for accurate conversions near full scale, the inputs must not exceed VDD by more than 50mV or be lower than GND by 50mV. If an off-channel analog input voltage exceeds the supplies, limit the input current to 2mA. 3-Wire Serial Interface The MAX11634–MAX11637 feature a serial interface compatible with SPI/QSPI and MICROWIRE devices. For SPI/QSPI, ensure the CPU serial interface runs in master mode so it generates the serial clock signal. Select the SCLK frequency of 10MHz or less, and set clock polarity (CPOL) and phase (CPHA) in the µP control registers to the same value. The MAX11634– MAX11637 operate with SCLK idling high or low, and thus operate with CPOL = CPHA = 0 or CPOL = CPHA = 1. Set CS low to latch input data at DIN on the rising edge of SCLK. Output data at DOUT is updated on the falling edge of SCLK. Bipolar true differential results are available in two’s complement format, while all others are in binary. Serial communication always begins with an 8-bit input data byte (MSB first) loaded from DIN. Use a second byte, immediately following the setup byte, to write to the unipolar mode or bipolar mode registers (see Tables 1, 3, 4, and 5). A high-to-low transition on CS initiates the data input operation. The input data byte and 12 the subsequent data bytes are clocked from DIN into the serial interface on the rising edge of SCLK. Tables 1–7 detail the register descriptions. Bits 5 and 4, CKSEL1 and CKSEL0, respectively, control the clock modes in the setup register (see Table 3). Choose between four different clock modes for various ways to start a conversion and determine whether the acquisitions are internally or externally timed. Select clock mode 00 to configure CNVST/AIN7 to act as a conversion start and use it to request the programmed, internally timed conversions without tying up the serial bus. In clock mode 01, use CNVST to request conversions one channel at a time, controlling the sampling speed without tying up the serial bus. Request and start internally timed conversions through the serial interface by writing to the conversion register in the default clock mode 10. Use clock mode 11 with SCLK up to 4.8MHz for externally timed acquisitions to achieve sampling rates up to 300ksps. Clock mode 11 disables scanning and averaging. See Figures 4–7 for timing specifications and how to begin a conversion. These devices feature an active-low, end-of-conversion output. EOC goes low when the ADC completes the lastrequested operation and is waiting for the next input data byte (for clock modes 00 and 10). In clock mode 01, EOC goes low after the ADC completes each requested operation. EOC goes high when CS or CNVST goes low. EOC is always high in clock mode 11. Single-Ended/Differential Input The MAX11634–MAX11637 use a fully differential ADC for all conversions. The analog inputs can be configured for either differential or single-ended conversions by writing to the setup register (see Table 3). Singleended conversions are internally referenced to GND (see Figure 3). In differential mode, the T/H samples the difference between two analog inputs, eliminating common-mode DC offsets and noise. IN+ and IN- are selected from the following pairs: AIN0/AIN1, AIN2/AIN3, AIN4/AIN5, and AIN6/AIN7. AIN0–AIN7 are available on the MAX11636/ MAX11637. AIN0–AIN3 are available on the MAX11634/ MAX11635. See Tables 2–5 for more details on configuring the inputs. For the inputs that can be configured as CNVST or an analog input, only one can be used at a time. For the inputs that can be configured as REF- or an analog input, the REF- configuration excludes the analog input. ______________________________________________________________________________________ 12-Bit, 300ksps ADCs with Differential Track/Hold, and Internal Reference CIN+ DAC COMPARATOR + HOLD GND (SINGLE-ENDED); AIN1, AIN3, AIN5, AIN7 (DIFFERENTIAL) CIN- HOLD HOLD VDD/2 Figure 3. Equivalent Input Circuit Unipolar/Bipolar Address the unipolar and bipolar registers through the setup register (bits 1 and 0). Program a pair of analog channels for differential operation by writing a 1 to the appropriate bit of the bipolar or unipolar register. Unipolar mode sets the differential input range from 0 to VREF. A negative differential analog input in unipolar mode causes the digital output code to be zero. Selecting bipolar mode sets the differential input range to ±VREF/2. The digital output code is binary in unipolar mode and two’s complement in bipolar mode (Figures 8 and 9). In single-ended mode, the MAX11634–MAX11637 always operate in unipolar mode. The analog inputs are internally referenced to GND with a full-scale input range from 0 to VREF. True Differential Analog Input T/H The equivalent circuit of Figure 3 shows the MAX11634–MAX11637s’ input architecture. In track mode, a positive input capacitor is connected to AIN0–AIN7 in single-ended mode (and AIN0, AIN2, AIN4, AIN5, AIN6 in differential mode). A negative input capacitor is connected to GND in single-ended mode (or AIN1, AIN3, AIN5, AIN6, AIN7 in differential mode). For external T/H timing, use clock mode 01. After the where RIN = 1.5kΩ, RS is the source impedance of the input signal, and tPWR = 1µs, the power-up time of the device. The varying power-up times are detailed in the explanation of the clock mode conversions. When the conversion is internally timed, tACQ is never less than 1.4µs, and any source impedance below 300Ω does not significantly affect the ADC’s AC performance. A high-impedance source can be accommodated either by lengthening tACQ or by placing a 1µF capacitor between the positive and negative analog inputs. Internal FIFO The MAX11634–MAX11637 contain a FIFO buffer that can hold up to 16 ADC results. This allows the ADC to handle multiple internally clocked conversions without tying up the serial bus. If the FIFO is filled and further conversions are requested without reading from the FIFO, the oldest ADC results are overwritten by the new ADC results. Each result contains 2 bytes, with the MSB preceded by four leading zeros. After each falling edge of CS, the oldest available byte of data is available at DOUT, MSB first. When the FIFO is empty, DOUT is zero. Internal Clock The MAX11634–MAX11637 operate from an internal oscillator, which is accurate within 10% of the 4.4MHz nominal clock rate. The internal oscillator is active in clock modes 00, 01, and 10. Read out the data at clock speeds up to 10MHz. See Figures 4–7 for details on timing specifications and starting a conversion. ______________________________________________________________________________________ 13 MAX11634–MAX11637 REF GND AIN0–AIN7 (SINGLE-ENDED); AIN0, AIN2, AIN4, AIN6 (DIFFERENTIAL) T/H enters hold mode, the difference between the sampled positive and negative input voltages is converted. The time required for the T/H to acquire an input signal is determined by how quickly its input capacitance is charged. If the input signal’s source impedance is high, the required acquisition time lengthens. The acquisition time, tACQ, is the maximum time needed for a signal to be acquired, plus the power-up time. It is calculated by the following equation: tACQ = 9 x (RS + RIN) x 24pF + tPWR MAX11634–MAX11637 12-Bit, 300ksps ADCs with Differential Track/Hold, and Internal Reference Applications Information Register Descriptions The MAX11634–MAX11637 communicate between the internal registers and the external circuitry through the SPI/QSPI-compatible serial interface. Table 1 details the registers and the bit names. Tables 2–7 show the various functions within the conversion register, setup register, averaging register, reset register, unipolar register, and bipolar register. Conversion Time Calculations The conversion time for each scan is based on a number of different factors: conversion time per sample, samples per result, results per scan, and if the external reference is in use. Use the following formula to calculate the total conversion time for an internally timed conversion in clock modes 00 and 10 (see the Electrical Characteristics table as applicable): Total Conversion Time = tCNV x nAVG x nRESULT + tRP where: tCNV = tACQ(MAX) + tCONV(MAX) nAVG = samples per result (amount of averaging) nRESULT = number of FIFO results requested; determined by number of channels being scanned or by NSCAN1, NSCAN0 tRP = internal reference wake up; set to zero if internal reference is already powered up or external reference is being used In clock mode 01, the total conversion time depends on how long CNVST is held low or high, including any time required to turn on the internal reference. Conversion time in externally clocked mode (CKSEL1, CKSEL0 = 11) depends on the SCLK period and how long CS is held high between each set of eight SCLK cycles. In clock mode 01, the total conversion time does not include the time required to turn on the internal reference. Conversion Register Select active analog input channels and scan modes by writing to the conversion register. Table 2 details channel selection, the four scan modes, and how to request a temperature measurement. Request a scan by writing to the conversion register when in clock mode 10 or 11, or by applying a low pulse to the CNVST pin when in clock mode 00 or 01. A conversion is not performed if it is requested on a channel that has been configured as CNVST or REF-. Do not request conversions on channels 4–7 on the MAX11634/MAX11635. Set CHSEL[2:0] to the lower channel’s binary values. If the last two channels are configured as a differential pair and one of them has been reconfigured as CNVST or REF-, the pair is ignored. Select scan mode 00 or 01 to return one result per single-ended channel and one result per differential pair within the requested range. Select scan mode 10 to scan a single input channel numerous times, depending on NSCAN1 and NSCAN0 in the averaging register (Table 6). Select scan mode 11 to return only one result from a single channel. Table 1. Input Data Byte (MSB First) REGISTER NAME BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 Conversion 1 X CHSEL2 CHSEL1 CHSEL0 SCAN1 SCAN0 X Setup 0 1 CKSEL1 CKSEL0 REFSEL1 REFSEL0 DIFFSEL1 DIFFSEL0 NSCAN0 Averaging 0 0 1 AVGON NAVG1 NAVG0 NSCAN1 Reset 0 0 0 1 RESET X X X Unipolar Mode (Setup) UCH0/1 UCH2/3 UCH4/5 UCH6/7 X X X X Bipolar Mode (Setup) BCH0/1 BCH1/2 BCH4/5 BCH6/7 X X X X X = Don’t care. 14 ______________________________________________________________________________________ 12-Bit, 300ksps ADCs with Differential Track/Hold, and Internal Reference BIT NAME — BIT FUNCTION 7 (MSB) Set to 1 to select conversion register X 6 Don’t care CHSEL2 5 Analog input channel select CHSEL1 4 Analog input channel select CHSEL0 3 Analog input channel select SCAN1 2 Scan mode select 1 Scan mode select SCAN0 X 0 (LSB) Don’t care *See below for bit details. CHSEL2 CHSEL1 CHSEL0 SELECTED CHANNEL (N) 0 0 0 AIN0 0 0 1 AIN1 0 1 0 AIN2 0 1 1 AIN3 1 0 0 AIN4 1 0 1 AIN5 1 1 0 AIN6 1 1 1 AIN7 SCAN1 SCAN0 SCAN MODE (CHANNEL N IS SELECTED BY BITS CHSEL[2:0]) 0 0 Scans channels 0 through N 0 1 Scans channels N through the highest numbered channel 1 0 Scans channel N repeatedly. The averaging register sets the number of results. 1 1 No scan. Converts channel N once only. Setup Register Write a byte to the setup register to configure the clock, reference, and power-down modes. Table 3 details the bits in the setup register. Bits 5 and 4 (CKSEL1 and CKSEL0) control the clock mode, acquisition and sampling, and the conversion start. Bits 3 and 2 (REFSEL1 and REFSEL0) control internal or external reference use. Unipolar/Bipolar Mode Registers The final 2 bits (LSBs) of the setup register control the unipolar/bipolar mode address registers. Set bits 1 and 0 (DIFFSEL1 and DIFFSEL0) to 10 to write to the unipolar mode register. Set bits 1 and 0 to 11 to write to the bipolar mode register. In both cases, the setup byte must be followed immediately by 1 byte of data written to the unipolar register or bipolar register. Hold CS low and run 16 SCLK cycles before pulling CS high. If the last 2 bits of the setup register are 00 or 01, neither the unipolar mode register nor the bipolar mode register is written. Any subsequent byte is recognized as a new input data byte. See Tables 4 and 5 to program the unipolar and bipolar mode registers. If a channel is configured as both unipolar and bipolar, the unipolar setting takes precedence. In unipolar mode, AIN+ can exceed AIN- by up to VREF. The output format in unipolar mode is binary. In bipolar mode, either input can exceed the other by up to VREF/2. The output format in bipolar mode is two's complement. Averaging Register Write to the averaging register to configure the ADC to average up to 32 samples for each requested result, and to independently control the number of results requested for single-channel scans. Table 2 details the four scan modes available in the conversion register. All four scan modes allow averaging as long as the AVGON bit, bit 4 in the averaging register, is set to 1. Select scan mode 10 to scan the same channel multiple times. Clock mode 11 disables averaging. Reset Register Write to the reset register (as shown in Table 7) to clear the FIFO or to reset all registers to their default states. Set the RESET bit to 1 to reset the FIFO. Set the RESET bit to zero to return the MAX11634–MAX11637 to the default power-up state. Power-Up Default State The MAX11634–MAX11637 power up with all blocks in shutdown, including the reference. All registers power up in state 00000000, except for the setup register, which powers up in clock mode 10 (CKSEL1 = 1). ______________________________________________________________________________________ 15 MAX11634–MAX11637 Bits 1 and 0 (DIFFSEL1 and DIFFSEL0) address the unipolar mode and bipolar mode registers and configure the analog input channels for differential operation. Table 2. Conversion Register* MAX11634–MAX11637 12-Bit, 300ksps ADCs with Differential Track/Hold, and Internal Reference Table 3. Setup Register* BIT NAME BIT — 7 (MSB) Set to 0 to select setup register FUNCTION — 6 Set to 1 to select setup register CKSEL1 5 Clock mode and CNVST configuration. Resets to 1 at power-up. CKSEL0 4 Clock mode and CNVST configuration REFSEL1 3 Reference mode configuration REFSEL0 2 Reference mode configuration DIFFSEL1 1 Unipolar/bipolar mode register configuration for differential mode DIFFSEL0 0 (LSB) Unipolar/bipolar mode register configuration for differential mode *See below for bit details. ACQUISITION/SAMPLING CNVST CONFIGURATION CKSEL1 CKSEL0 CONVERSION CLOCK 0 0 Internal Internally timed CNVST 0 1 Internal Externally timed through CNVST CNVST 1 0 Internal Internally timed AIN7* 1 1 External (4.8MHz max) Externally timed through SCLK AIN7* *The MAX11634/MAX11635 have a dedicated CNVST pin. REFSEL1 REFSEL0 VOLTAGE REFERENCE 0 0 Internal 0 1 1 1 AutoShutdown REF- CONFIGURATION Reference off after scan; need wake-up delay AIN6 External single-ended Reference off; no wake-up delay AIN6 0 Internal Reference always on; no wakeup delay AIN6 1 External differential Reference off; no wake-up delay REF-* *The MAX11634/MAX11635 have a dedicated REF- pin. DIFFSEL1 DIFFSEL0 0 0 No data follows the setup byte. Unipolar mode and bipolar mode registers remain unchanged. 0 1 No data follows the setup byte. Unipolar mode and bipolar mode registers remain unchanged. 1 0 1 byte of data follows the setup byte and is written to the unipolar mode register. 1 1 1 byte of data follows the setup byte and is written to the bipolar mode register. 16 FUNCTION ______________________________________________________________________________________ 12-Bit, 300ksps ADCs with Differential Track/Hold, and Internal Reference edge of SCLK. Conversions in clock modes 00 and 01 are initiated by CNVST. Conversions in clock modes 10 and 11 are initiated by writing an input data byte to the conversion register. Data is binary for unipolar mode and two’s complement for bipolar mode. Table 4. Unipolar Mode Register (Addressed Through Setup Register) BIT NAME BIT FUNCTION UCH0/1 7 (MSB) Set to 1 to configure AIN0 and AIN1 for unipolar differential conversion UCH2/3 6 Set to 1 to configure AIN2 and AIN3 for unipolar differential conversion UCH4/5 5 Set to 1 to configure AIN4 and AIN5 for unipolar differential conversion UCH6/7 4 Set to 1 to configure AIN6 and AIN7 for unipolar differential conversion X 3 Don’t care X 2 Don’t care X 1 Don’t care X 0 (LSB) Don’t care Table 5. Bipolar Mode Register (Addressed Through Setup Register) BIT NAME BIT FUNCTION BCH0/1 7 (MSB) Set to 1 to configure AIN0 and AIN1 for bipolar differential conversion BCH2/3 6 Set to 1 to configure AIN2 and AIN3 for bipolar differential conversion BCH4/5 5 Set to 1 to configure AIN4 and AIN5 for bipolar differential conversion BCH6/7 4 Set to 1 to configure AIN6 and AIN7 for bipolar differential conversion X 3 Don’t care X 2 Don’t care X 1 Don’t care X 0 (LSB) Don’t care ______________________________________________________________________________________ 17 MAX11634–MAX11637 Output Data Format Figures 4–7 illustrate the conversion timing for the MAX11634–MAX11637. The 12-bit conversion result is output in MSB-first format with four leading zeros. DIN data is latched into the serial interface on the rising edge of SCLK. Data on DOUT transitions on the falling MAX11634–MAX11637 12-Bit, 300ksps ADCs with Differential Track/Hold, and Internal Reference Table 6. Averaging Register* BIT NAME BIT — 7 (MSB) Set to 0 to select averaging register FUNCTION — 6 Set to 0 to select averaging register Set to 1 to select averaging register — 5 AVGON 4 Set to 1 to turn averaging on. Set to 0 to turn averaging off. NAVG1 3 Configures the number of conversions for single-channel scans NAVG0 2 Configures the number of conversions for single-channel scans NSCAN1 1 Single-channel scan count (scan mode 10 only) NSCAN0 0 (LSB) Single-channel scan count (scan mode 10 only) *See below for bit details. AVGON NAVG1 NAVG0 FUNCTION 0 X X Performs 1 conversion for each requested result 1 0 0 Performs 4 conversions and returns the average for each requested result 1 0 1 Performs 8 conversions and returns the average for each requested result 1 1 0 Performs 16 conversions and returns the average for each requested result 1 1 1 Performs 32 conversions and returns the average for each requested result NSCAN1 NSCAN0 0 0 Scans channel N and returns 4 results 0 1 Scans channel N and returns 8 results 1 0 Scans channel N and returns 12 results 1 1 Scans channel N and returns 16 results FUNCTION (APPLIES ONLY IF SCAN MODE 10 IS SELECTED) Table 7. Reset Register BIT NAME BIT — 7 (MSB) Set to 0 to select reset register — 6 Set to 0 to select reset register — 5 Set to 0 to select reset register — 4 Set to 1 to select reset register RESET 3 Set to 0 to reset all registers; set to 1 to clear the FIFO only X 2 Don’t care X 1 Don’t care X 0 (LSB) Don’t care 18 FUNCTION ______________________________________________________________________________________ 12-Bit, 300ksps ADCs with Differential Track/Hold, and Internal Reference Performing Conversions in Clock Mode 00 In clock mode 00, the wake-up, acquisition, conversion, and shutdown sequences are initiated through CNVST and performed automatically using the internal oscillator. Results are added to the internal FIFO to be read out later. See Figure 4 for clock mode 00 timing. Initiate a scan by setting CNVST low for at least 40ns before pulling it high again. The MAX11634–MAX11637 then wake up, scan all requested channels, store the results in the FIFO, and shut down. After the scan is complete, EOC is pulled low and the results are available in the FIFO. Wait until EOC goes low before pulling CS low to communicate with the serial interface. EOC stays low until CS or CNVST is pulled low again. Do not initiate a second CNVST before EOC goes low; otherwise, the FIFO can become corrupted. Externally Timed Acquisitions and Internally Timed Conversions with CNVST Performing Conversions in Clock Mode 01 In clock mode 01, conversions are requested one at a time using CNVST and performed automatically using the internal oscillator. See Figure 5 for clock mode 01 timing. Setting CNVST low begins an acquisition, wakes up the ADC, and places it in track mode. Hold CNVST low for at least 1.4µs to complete the acquisition. If the internal reference needs to wake up, an additional 65µs is required for the internal reference to power up. If a temperature measurement is being requested, reference power-up and temperature measurement are internally timed. In this case, hold CNVST low for at least 40ns. Set CNVST high to begin a conversion. After the conversion is complete, the ADC shuts down and pulls EOC low. EOC stays low until CS or CNVST is pulled low again. Wait until EOC goes low before pulling CS or CNVST low. If averaging is turned on, multiple CNVST pulses need to be performed before a result is written to the FIFO. Once the proper number of conversions has been performed to generate an averaged FIFO result, as specified by the averaging register, the scan logic automatically switches the analog input multiplexer to the next requested channel. The result is available on DOUT once EOC has been pulled low. CNVST (UP TO 514 INTERNALLY CLOCKED ACQUISITIONS AND CONVERSIONS) CS SCLK DOUT MSB1 LSB1 MSB2 EOC SET CNVST LOW FOR AT LEAST 40ns TO BEGIN A CONVERSION. Figure 4. Clock Mode 00 ______________________________________________________________________________________ 19 MAX11634–MAX11637 Internally Timed Acquisitions and Conversions Using CNVST MAX11634–MAX11637 12-Bit, 300ksps ADCs with Differential Track/Hold, and Internal Reference CNVST (CONVERSION2) (ACQUISITION1) (ACQUISITION2) CS (CONVERSION1) SCLK DOUT LSB1 MSB1 MSB2 EOC REQUEST MULTIPLE CONVERSIONS BY SETTING CNVST LOW FOR EACH CONVERSION. Figure 5. Clock Mode 01 (CONVERSION BYTE) DIN (UP TO 514 INTERNALLY CLOCKED ACQUISITIONS AND CONVERSIONS) CS SCLK DOUT MSB1 LSB1 MSB2 EOC THE CONVERSION BYTE BEGINS THE ACQUISITION. CNVST IS NOT REQUIRED. Figure 6. Clock Mode 10 Internally Timed Acquisitions and Conversions Using the Serial Interface Externally Clocked Acquisitions and Conversions Using the Serial Interface Performing Conversions in Clock Mode 10 In clock mode 10, the wake-up, acquisition, conversion, and shutdown sequences are initiated by writing an input data byte to the conversion register, and are performed automatically using the internal oscillator. This is the default clock mode upon power-up. See Figure 6 for clock mode 10 timing. Performing Conversions in Clock Mode 11 In clock mode 11, acquisitions and conversions are initiated by writing to the conversion register and are performed one at a time using the SCLK as the conversion clock. Scanning and averaging are disabled, and the conversion result is available at DOUT during the conversion. See Figure 7 for clock mode 11 timing. Initiate a scan by writing a byte to the conversion register. The MAX11634–MAX11637 then power up, scan all requested channels, store the results in the FIFO, and shut down. After the scan is complete, EOC is pulled low and the results are available in the FIFO. EOC stays low until CS is pulled low again. Initiate a conversion by writing a byte to the conversion register followed by 16 SCLK cycles. If CS is pulsed high between the eighth and ninth cycles, the pulse width must be less than 100µs. To continuously convert at 16 cycles per conversion, alternate 1 byte of zeros between each conversion byte. 20 ______________________________________________________________________________________ 12-Bit, 300ksps ADCs with Differential Track/Hold, and Internal Reference (ACQUISITION1) (CONVERSION1) (ACQUISITION2) CS SCLK DOUT MSB1 LSB1 MSB2 EOC EXTERNALLY TIMED ACQUISITION, SAMPLING AND CONVERSION WITHOUT CNVST. Figure 7. Clock Mode 11 Partial Reads and Partial Writes If the first byte of an entry in the FIFO is partially read (CS is pulled high after fewer than eight SCLK cycles), the second byte of data that is read out contains the next 8 bits (not b[7:0]). The remaining bits are lost for that entry. If the first byte of an entry in the FIFO is read out fully, but the second byte is read out partially, the rest of the entry is lost. The remaining data in the FIFO is uncorrupted and can be read out normally after taking CS low again, as long as the four leading bits (normally zeros) are ignored. Internal registers that are written partially through the SPI contain new values, starting at the MSB up to the point that the partial write is stopped. The part of the register that is not written contains previously written values. If CS is pulled low before EOC goes low, a conversion cannot be completed and the FIFO is corrupted. Transfer Function Figure 8 shows the unipolar transfer function for singleended or differential inputs. Figure 9 shows the bipolar transfer function for differential inputs. Code transitions occur halfway between successive-integer LSB values. Output coding is binary, with 1 LSB = VREF/4096 for unipolar and bipolar operation, and 1 LSB = 0.125°C for temperature measurements. Layout, Grounding, and Bypassing For best performance, use PC boards. Do not use wirewrap boards. Board layout should ensure that digital and analog signal lines are separated from each other. Do not run analog and digital (especially clock) signals parallel to one another or run digital lines underneath the MAX11634–MAX11637 package. High-frequency noise in the V DD power supply can affect performance. Bypass the VDD supply with a 0.1µF capacitor to GND, close to the VDD pin. Minimize capacitor lead lengths for best supply-noise rejection. If the power supply is very noisy, connect a 10Ω resistor in series with the supply to improve power-supply filtering. Definitions Integral Nonlinearity Integral nonlinearity (INL) is the deviation of the values on an actual transfer function from a straight line. This straight line can be either a best-straight-line fit or a line drawn between the end points of the transfer function, once offset and gain errors have been nullified. INL for the MAX11634–MAX11637 is measured using the endpoint method. Differential Nonlinearity Differential nonlinearity (DNL) is the difference between an actual step width and the ideal value of 1 LSB. A DNL error specification of less than 1 LSB guarantees no missing codes and a monotonic transfer function. Aperture Jitter Aperture jitter (tAJ) is the sample-to-sample variation in the time between the samples. Aperture Delay Aperture delay (t AD ) is the time between the rising edge of the sampling clock and the instant when an actual sample is taken. ______________________________________________________________________________________ 21 MAX11634–MAX11637 (CONVERSION BYTE) DIN MAX11634–MAX11637 12-Bit, 300ksps ADCs with Differential Track/Hold, and Internal Reference OUTPUT CODE OUTPUT CODE FULL-SCALE TRANSITION 11. . .111 11. . .110 11. . .101 011. . . 111 V FS = REF + VCOM 2 011. . .110 ZS = COM 000. . . 010 000. . .001 FS = VREF + VCOM ZS = VCOM V 1 LSB = REF 4096 00. . .011 00. . .010 -VREF + VCOM 2 VREF 1 LSB = 4096 -FS = 000. . .000 111 . . .111 111 . . . 110 111 . . . 101 100 . . . 001 00. . . 001 100. . . 000 00. . . 000 0 1 (COM) 2 3 FS INPUT VOLTAGE (LSB) - FS FS - 3/2 LSB Figure 8. Unipolar Transfer Function, Full Scale (FS) = VREF Signal-to-Noise Ratio For a waveform perfectly reconstructed from digital samples, signal-to-noise ratio (SNR) is the ratio of the full-scale analog input (RMS value) to the RMS quantization error (residual error). The ideal, theoretical minimum analog-to-digital noise is caused by quantization error only and results directly from the ADC’s resolution (N bits): SNR = (6.02 x N + 1.76)dB In reality, there are other noise sources besides quantization noise, including thermal noise, reference noise, clock jitter, etc. Therefore, SNR is calculated by taking the ratio of the RMS signal to the RMS noise, which includes all spectral components minus the fundamental, the first five harmonics, and the DC offset. Signal-to-Noise Plus Distortion Signal-to-noise plus distortion (SINAD) is the ratio of the fundamental input frequency’s RMS amplitude to the RMS equivalent of all other ADC output signals: SINAD (dB) = 20 x log (SignalRMS/NoiseRMS) Effective Number of Bits COM* INPUT VOLTAGE (LSB) *VCOM ≥ VREF / 2 Figure 9. Bipolar Transfer Function, Full Scale (±FS) = ±VREF /2 sampling rate. An ideal ADC error consists of quantization noise only. With an input range equal to the fullscale range of the ADC, calculate the effective number of bits as follows: ENOB = (SINAD - 1.76)/6.02 Total Harmonic Distortion Total harmonic distortion (THD) is the ratio of the RMS sum of the first five harmonics of the input signal to the fundamental itself. This is expressed as: ⎡ THD = 20 x log ⎢ ⎣ (V22 + V32 + V42 + V52 ) ⎤ V1 ⎥ ⎦ where V1 is the fundamental amplitude, and V2–V5 are the amplitudes of the 2nd-order to 5th-order harmonics. Spurious-Free Dynamic Range Spurious-free dynamic range (SFDR) is the ratio of the RMS amplitude of the fundamental (maximum signal component) to the RMS value of the next largest distortion component. Effective number of bits (ENOB) indicates the global accuracy of an ADC at a specific input frequency and 22 +FS - 1 LSB ______________________________________________________________________________________ 12-Bit, 300ksps ADCs with Differential Track/Hold, and Internal Reference PROCESS: BiCMOS For the latest package outline information and land patterns (footprints), go to www.maxim-ic.com/packages. Note that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. PACKAGE TYPE PACKAGE CODE OUTLINE NO. LAND PATTERN NO. 16 QSOP E16+5 21-0055 90-0167 ______________________________________________________________________________________ 23 MAX11634–MAX11637 Package Information Chip Information MAX11634–MAX11637 12-Bit, 300ksps ADCs with Differential Track/Hold, and Internal Reference Revision History REVISION NUMBER REVISION DATE 0 6/11 Initial release 1 9/11 Released the MAX11636/MAX11637 and revised the Transfer Function section. DESCRIPTION PAGES CHANGED — 1, 21 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 24 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 2011 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.