MAXIM MAX1258BETM

19-3295; Rev 7; 2/12
KIT
ATION
EVALU
LE
B
A
IL
A
AV
12-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
Features
The MAX1220/MAX1257/MAX1258 integrate a 12-bit,
multichannel, analog-to-digital converter (ADC), and a 12bit, octal, digital-to-analog converter (DAC) in a single IC.
These devices also include a temperature sensor and
configurable general-purpose I/O ports (GPIOs) with a
25MHz SPI-/QSPI™-/MICROWIRE®-compatible serial
interface. The ADC is available in 8 and 16 input-channel
versions. The octal DAC outputs settle within 2.0µs and
the ADC has a 225ksps conversion rate.
All devices include an internal reference (2.5V or
4.096V) for both the ADC and DAC. Programmable reference modes allow the use of an internal reference, an
external reference, or a combination of both. Features
such as an internal ±1°C accurate temperature sensor,
FIFO, scan modes, programmable internal or external
clock modes, data averaging, and AutoShutdown™
allow users to minimize power consumption and processor requirements. The low glitch energy (4nV•s) and low
digital feedthrough (0.5nV•s) of the integrated octal
DACs make these devices ideal for digital control of
fast-response closed-loop systems.
The devices are guaranteed to operate with a supply voltage from +2.7V to +3.6V (MAX1257) and from +4.75V to
+5.25V (MAX1220/MAX1258). These devices consume
2.5mA at 225ksps throughput, only 22µA at 1ksps
throughput, and under 0.2µA in the shutdown mode. The
MAX1257/MAX1258 feature 12 GPIOs, while the
MAX1220 offers four GPIOs that can be configured as
inputs or outputs.
The MAX1220 is available in a 36-pin TQFN package.
The MAX1257/MAX1258 are available in 48-pin TQFN
package. All devices are specified over the
-40°C to +85°C temperature range.
o 12-Bit, 225ksps ADC
Analog Multiplexer with True-Differential
Track/Hold (T/H)
16 Single-Ended Channels or 8 Differential
Channels (Unipolar or Bipolar)
(MAX1257/MAX1258)
Eight Single-Ended Channels or Four Differential
Channels (Unipolar or Bipolar) (MAX1220)
Excellent Accuracy: ±0.5 LSB INL, ±0.5 LSB DNL
o 12-Bit, Octal, 2µs Settling DAC
Ultra-Low Glitch Energy (4nV•s)
Power-Up Options from Zero Scale or Full Scale
Excellent Accuracy: ±0.5 LSB INL
o Internal Reference or External Single-Ended/
Differential Reference
Internal Reference Voltage 2.5V or 4.096V
o Internal ±1°C Accurate Temperature Sensor
o On-Chip FIFO Capable of Storing 16 ADC
Conversion Results and One Temperature Result
o On-Chip Channel-Scan Mode and Internal
Data-Averaging Features
o Analog Single-Supply Operation
+2.7V to +3.6V or +4.75V to +5.25V
o Digital Supply: +2.7V to AVDD
o 25MHz, SPI/QSPI/MICROWIRE Serial Interface
o AutoShutdown Between Conversions
o Low-Power ADC
2.5mA at 225ksps
22µA at 1ksps
0.2µA at Shutdown
o Low-Power DAC: 1.5mA
o Evaluation Kit Available (Order MAX1258EVKIT)
Applications
Controls for Optical Components
Base-Station Control Loops
QSPI is a trademark of Motorola, Inc.
MICROWIRE is a registered trademark of National
Semiconductor Corp.
AutoShutdown is a trademark of Maxim Integrated Products, Inc.
System Supervision and Control
Data-Acquisition Systems
Pin Configurations appear at end of data sheet.
Ordering Information/Selector Guide
PIN-PACKAGE
REF
VOLTAGE
(V)
ANALOG
SUPPLY
VOLTAGE (V)
RESOLUTION
BITS**
ADC
CHANNELS
DAC
CHANNELS
GPIOs
MAX1220BETX+
36 Thin QFN-EP*
4.096
4.75 to 5.25
12
8
8
4
MAX1257BETM+
48 Thin QFN-EP*
2.5
2.7 to 3.6
12
16
8
12
MAX1258BETM+
48 Thin QFN-EP*
4.096
4.75 to 5.25
12
16
8
12
PART
Note: All devices are specified over the -40°C to +85°C operating range.
+Denotes a lead(Pb)-free/RoHS-compliant package.
*EP = Exposed pad.
**Number of resolution bits refers to both DAC and ADC.
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
MAX1220/MAX1257/MAX1258
General Description
MAX1220/MAX1257/MAX1258
12-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
ABSOLUTE MAXIMUM RATINGS
AVDD to AGND ........................................................-0.3V to +6V
DGND to AGND.....................................................-0.3V to +0.3V
DVDD to AVDD......................................................-3.0V to +0.3V
Digital Inputs to DGND.............................................-0.3V to +6V
Digital Outputs to DGND ........................-0.3V to (VDVDD + 0.3V)
Analog Inputs, Analog Outputs and REF_
to AGND .............................................-0.3V to (VAVDD + 0.3V)
Maximum Current into Any Pin (except AGND, DGND, AVDD,
DVDD, and OUT_)...........................................................50mA
Maximum Current into OUT_.............................................100mA
Continuous Power Dissipation (multilayer board, TA = +70°C)
36-Pin TQFN (6mm x 6mm)
(derate 35.7mW/°C above +70°C) ......................2857.1mW
48-Pin TQFN (7mm x 7mm)
(derate 40mW/°C above +70°C) ............................3200mW
Operating Temperature Range ...........................-40°C to +85°C
Storage Temperature Range .............................-60°C to +150°C
Junction Temperature ......................................................+150°C
Lead Temperature (soldering, 10s) .................................+300°C
Soldering Temperature ...................................................+260°C
Note: If the package power dissipation is not exceeded, one output at a time may be shorted to AVDD, DVDD, AGND, or DGND
indefinitely.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VAVDD = VDVDD = 2.7V to 3.6V (MAX1257), external reference VREF = 2.5V (MAX1257), VAVDD = 4.75V to 5.25V, VDVDD = 2.7V to VAVDD
(MAX1220/MAX1258), external reference VREF = 4.096V (MAX1220/MAX1258), fCLK = 3.6MHz (50% duty cycle), TA = -40°C to +85°C,
unless otherwise noted. Typical values are at VAVDD = VDVDD = 3V (MAX1257), VAVDD = VDVDD = 5V (MAX1220/MAX1258), TA = +25°C.
Outputs are unloaded, unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
ADC
DC ACCURACY (Note 1)
Resolution
12
Bits
Integral Nonlinearity
INL
±0.5
±1.0
LSB
Differential Nonlinearity
DNL
±0.5
±1.0
LSB
Offset Error
Gain Error
(Note 2)
±1
±4.0
LSB
±0.1
±4.0
LSB
Gain Temperature Coefficient
±0.8
ppm/°C
Channel-to-Channel Offset
±0.1
LSB
DYNAMIC SPECIFICATIONS (10kHz sine-wave input, VIN = 2.5VP-P (MAX1257), VIN = 4.096VP-P (MAX1220/MAX1258),
225ksps, fCLK = 3.6MHz)
Signal-to-Noise Plus Distortion
SINAD
70
dB
Total Harmonic Distortion
(Up to the Fifth Harmonic)
THD
-76
dBc
Spurious-Free Dynamic Range
SFDR
72
dBc
fIN1 = 9.9kHz, fIN2 = 10.2kHz
76
dBc
Full-Linear Bandwidth
SINAD > 70dB
100
kHz
Full-Power Bandwidth
-3dB point
1
MHz
External reference
0.8
µs
Internal reference (Note 4)
218
Conversion
clock
cycles
Intermodulation Distortion
IMD
CONVERSION RATE (Note 3)
Power-Up Time
2
tPU
_______________________________________________________________________________________
12-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
(VAVDD = VDVDD = 2.7V to 3.6V (MAX1257), external reference VREF = 2.5V (MAX1257), VAVDD = 4.75V to 5.25V, VDVDD = 2.7V to VAVDD
(MAX1220/MAX1258), external reference VREF = 4.096V (MAX1220/MAX1258), fCLK = 3.6MHz (50% duty cycle), TA = -40°C to +85°C,
unless otherwise noted. Typical values are at VAVDD = VDVDD = 3V (MAX1257), VAVDD = VDVDD = 5V (MAX1220/MAX1258), TA = +25°C.
Outputs are unloaded, unless otherwise noted.)
PARAMETER
Acquisition Time
SYMBOL
tACQ
Conversion Time
tCONV
External Clock Frequency
fCLK
CONDITIONS
(Note 5)
MIN
TYP
MAX
0.6
Internally clocked
UNITS
µs
5.5
µs
Externally clocked
3.6
Externally clocked conversion (Note 5)
0.1
3.6
MHz
40
60
%
Duty Cycle
Aperture Delay
30
ns
Aperture Jitter
< 50
ps
ANALOG INPUTS
Input Voltage Range (Note 6)
Unipolar
0
VREF
Bipolar
-VREF/2
+VREF/2
Input Leakage Current
±0.01
Input Capacitance
±1
24
V
µA
pF
INTERNAL TEMPERATURE SENSOR
Measurement Error (Notes 5, 7)
TA = +25°C
±0.7
TA = TMIN to TMAX
±1.0
Temperature Resolution
±3.0
1/8
°C
°C/LSB
INTERNAL REFERENCE
REF1 Output Voltage (Note 8)
REF1 Voltage Temperature
Coefficient
MAX1257
2.482
2.50
2.518
MAX1220/MAX1258
4.066
4.096
4.126
TCREF
REF1 Output Impedance
REF1 Short-Circuit Current
V
±30
ppm/°C
6.5
k
VREF = 2.5V
0.39
VREF = 4.096V
0.63
mA
EXTERNAL REFERENCE
REF1 Input Voltage Range
VREF1
REF2 Input Voltage Range
(Note 4)
VREF2
REF mode 11 (Note 4)
1
VAVDD
+ 0.05
REF mode 01
1
VAVDD
+ 0.05
REF mode 11
0
1
V
V
_______________________________________________________________________________________
3
MAX1220/MAX1257/MAX1258
ELECTRICAL CHARACTERISTICS (continued)
MAX1220/MAX1257/MAX1258
12-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
ELECTRICAL CHARACTERISTICS (continued)
(VAVDD = VDVDD = 2.7V to 3.6V (MAX1257), external reference VREF = 2.5V (MAX1257), VAVDD = 4.75V to 5.25V, VDVDD = 2.7V to VAVDD
(MAX1220/MAX1258), external reference VREF = 4.096V (MAX1220/MAX1258), fCLK = 3.6MHz (50% duty cycle), TA = -40°C to +85°C,
unless otherwise noted. Typical values are at VAVDD = VDVDD = 3V (MAX1257), VAVDD = VDVDD = 5V (MAX1220/MAX1258), TA = +25°C.
Outputs are unloaded, unless otherwise noted.)
PARAMETER
REF1 Input Current (Note 9)
REF2 Input Current
SYMBOL
IREF1
IREF2
CONDITIONS
MIN
TYP
MAX
VREF = 2.5V (MAX1257), fSAMPLE =
25
80
VREF = 4.096V (MAX1220/MAX1258),
f SAMPLE = 225ksps
40
80
Acquisition between conversions
±0.01
±1
VREF = 2.5V (MAX1257), fSAMPLE =
25
80
VREF = 4.096V (MAX1220/MAX1258),
f SAMPLE = 225ksps
40
80
±0.01
±1
Acquisition between conversions
UNITS
µA
µA
DAC
DC ACCURACY (Note 10)
Resolution
12
Integral Nonlinearity
INL
Differential Nonlinearity
DNL
Guaranteed monotonic
Offset Error
VOS
(Note 8)
±0.5
±3
Offset-Error Drift
Gain Error
Bits
±4
LSB
±1.0
LSB
±10
mV
ppm of
FS/°C
±10
GE
(Note 8)
±5
Gain Temperature Coefficient
±10
LSB
ppm of
FS/°C
±8
DAC OUTPUT
No load
0.02
VAVDD 0.02
10k load to either rail
0.1
VAVDD 0.1
Output-Voltage Range
DC Output Impedance
0.5
Capacitive Load
Resistive Load to AGND
V
(Note 11)
RL
1
VAVDD = 2.7V, VREF = 2.5V (MAX1257),
gain error < 1%
2000
VAVDD = 4.75V, VREF = 4.096V
(MAX1220/MAX1258), gain error < 2%
500
nF
From power-down mode, VAVDD = 5V
25
From power-down mode, VAVDD = 2.7V
21
1k Output Termination
Programmed in from power-down mode
1
k
100k Output Termination
At wake-up or programmed in
power-down mode
100
k
Wake-Up Time (Note 12)
4
_______________________________________________________________________________________
µs
12-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
(VAVDD = VDVDD = 2.7V to 3.6V (MAX1257), external reference VREF = 2.5V (MAX1257), VAVDD = 4.75V to 5.25V, VDVDD = 2.7V to VAVDD
(MAX1220/MAX1258), external reference VREF = 4.096V (MAX1220/MAX1258), fCLK = 3.6MHz (50% duty cycle), TA = -40°C to +85°C,
unless otherwise noted. Typical values are at VAVDD = VDVDD = 3V (MAX1257), VAVDD = VDVDD = 5V (MAX1220/MAX1258), TA = +25°C.
Outputs are unloaded, unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
5
UNITS
DYNAMIC PERFORMANCE (Notes 5, 13)
Output-Voltage Slew Rate
SR
Positive and negative
Output-Voltage Settling Time
tS
To 1 LSB, 400 - C00 hex (Note 7)
2
Digital Feedthrough
Code 0, all digital inputs from 0 to
VDVDD
0.5
nV • s
Major Code Transition Glitch
Impulse
Between codes 2047 and 2048
4
nV • s
Output Noise (0.1Hz to 50MHz)
Output Noise (0.1Hz to
500kHz)
3
V/µs
From VREF
660
Using internal reference
720
From VREF
260
Using internal reference
320
DAC-to-DAC Transition
Crosstalk
µs
µVP-P
µVP-P
0.5
nV • s
INTERNAL REFERENCE
REF1 Output Voltage (Note 8)
REF1 Temperature Coefficient
MAX1257
2.482
2.5
2.518
MAX1220/MAX1258
4.066
4.096
4.126
TCREF
REF1 Short-Circuit Current
ppm/°C
±30
VREF = 2.5V
0.39
VREF = 4.096V
0.63
V
mA
EXTERNAL-REFERENCE INPUT
REF1 Input Voltage Range
VREF1
REF1 Input Impedance
RREF1
REF modes 01, 10, and 11 (Note 4)
0.7
70
100
VAVDD
V
130
k
DIGITAL INTERFACE
DIGITAL INPUTS (SCLK, DIN, CS, CNVST, LDAC)
Input-Voltage High
VIH
Input-Voltage Low
VIL
Input Leakage Current
Input Capacitance
VDVDD = 2.7V to 5.25V
2.4
V
VDVDD = 3.6V to 5.25V
0.8
VDVDD = 2.7V to 3.6V
0.6
IL
±0.01
CIN
15
±10
V
µA
pF
DIGITAL OUTPUT (DOUT) (Note 14)
Output-Voltage Low
VOL
I SINK = 2mA
Output-Voltage High
VOH
I SOURCE = 2mA
0.4
VDVDD 0.5
V
Three-State Leakage Current
Three-State Output
Capacitance
±10
C OUT
V
15
µA
pF
_______________________________________________________________________________________
5
MAX1220/MAX1257/MAX1258
ELECTRICAL CHARACTERISTICS (continued)
MAX1220/MAX1257/MAX1258
12-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
ELECTRICAL CHARACTERISTICS (continued)
(VAVDD = VDVDD = 2.7V to 3.6V (MAX1257), external reference VREF = 2.5V (MAX1257), VAVDD = 4.75V to 5.25V, VDVDD = 2.7V to VAVDD
(MAX1220/MAX1258), external reference VREF = 4.096V (MAX1220/MAX1258), fCLK = 3.6MHz (50% duty cycle), TA = -40°C to +85°C,
unless otherwise noted. Typical values are at VAVDD = VDVDD = 3V (MAX1257), VAVDD = VDVDD = 5V (MAX1220/MAX1258), TA = +25°C.
Outputs are unloaded, unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
0.4
V
DIGITAL OUTPUT (EOC) (Note 14)
Output-Voltage Low
VOL
I SINK = 2mA
Output-Voltage High
VOH
I SOURCE = 2mA
VDVDD 0.5
V
Three-State Leakage Current
Three-State Output
Capacitance
±10
C OUT
15
µA
pF
DIGITAL OUTPUTS (GPIO_) (Note 14)
GPIOB_, GPIOC_ OutputVoltage Low
I SINK = 2mA
0.4
I SINK = 4mA
0.8
GPIOB_, GPIOC_ OutputVoltage High
I SOURCE = 2mA
GPIOA_ Output-Voltage Low
I SINK = 15mA
GPIOA_ Output-Voltage High
I SOURCE = 15mA
VDVDD 0.5
V
0.8
VDVDD 0.8
±10
C OUT
V
V
Three-State Leakage Current
Three-State Output
Capacitance
V
15
µA
pF
POWER REQUIREMENTS (Note 15)
Digital Positive-Supply Voltage
Digital Positive-Supply Current
Analog Positive-Supply Voltage
Analog Positive-Supply Current
REF1 Positive-Supply
Rejection
DAC Positive-Supply Rejection
ADC Positive-Supply Rejection
6
DVDD
DIDD
AVDD
2.7
Idle, all blocks shut down
0.2
Only ADC on, external reference
VAVDD
V
4
µA
1
mA
MAX1257
2.7
3.6
MAX1220/MAX1258
4.75
5.25
Idle, all blocks shut down
0.2
2
f SAMPLE = 225ksps
Only ADC on,
external reference f SAMPLE = 100ksps
All DACs on, no load, internal reference
2.8
4.2
1.5
MAX1257, VAVDD = 2.7V
-77
MAX1220/MAX1258, VAVDD = 4.75V
-80
±0.1
±0.5
PSRD
Output MAX1257, VAVDD = 2.7V to
code = MAX1220/MAX1258,
FFFhex VAVDD = 4.75V to 5.25V
±0.1
±0.5
MAX1257, VAVDD = 2.7V to
±0.06
±0.5
PSRA
Fullscale
input
MAX1220/MAX1258,
VAVDD = 4.75V to 5.25V
±0.06
±0.5
AIDD
PSRR
µA
mA
2.6
_______________________________________________________________________________________
V
4
dB
mV
mV
12-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
(VAVDD = VDVDD = 2.7V to 3.6V (MAX1257), external reference VREF = 2.5V (MAX1257), VAVDD = 4.75V to 5.25V, VDVDD = 2.7V to VAVDD
(MAX1220/MAX1258), external reference VREF = 4.096V (MAX1220/MAX1258), fCLK = 3.6MHz (50% duty cycle), TA = -40°C to +85°C,
unless otherwise noted. Typical values are at VAVDD = VDVDD = 3V (MAX1257), VAVDD = VDVDD = 5V (MAX1220/MAX1258), TA = +25°C.
Outputs are unloaded, unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
TIMING CHARACTERISTICS (Figures 6–13)
SCLK Clock Period
tCP
40
ns
SCLK Pulse-Width High
tCH
40/60 duty cycle
16
ns
SCLK Pulse-Width Low
tCL
60/40 duty cycle
16
ns
GPIO Output Rise/Fall After
CS Rise
t GOD
GPIO Input Setup Before CS
Fall
t GSU
0
ns
tLDACPWL
20
ns
LDAC Pulse Width
SCLK Fall to DOUT Transition
(Note 16)
tDOT
SCLK Rise to DOUT Transition
(Notes 16, 17)
tDOT
CLOAD = 20pF
100
CLOAD = 20pF, SLOW = 0
1.8
12.0
CLOAD = 20pF, SLOW = 1
10
40
CLOAD = 20pF, SLOW = 0
1.8
12.0
CLOAD = 20pF, SLOW = 1
10
40
ns
ns
ns
CS Fall to SCLK Fall Setup Time
tCSS
10
SCLK Fall to CS Rise Hold Time
tCSH
0
DIN to SCLK Fall Setup Time
tDS
10
ns
DIN to SCLK Fall Hold Time
tDH
0
ns
tCSPWH
50
ns
CS Pulse-Width High
CS Rise to DOUT Disable
tDOD
CLOAD = 20pF
CS Fall to DOUT Enable
tDOE
CLOAD = 20pF
EOC Fall to CS Fall
tRDS
CS or CNVST Rise to EOC
Fall—Internally Clocked
Conversion Time
CNVST Pulse Width
tDOV
tCSW
1.5
ns
2000
ns
25
ns
25.0
ns
30
ns
CKSEL = 01 (temp sense) or CKSEL =
10 (temp sense), internal reference on
(Note 18)
65
CKSEL = 01 (temp sense) or CKSEL =
10 (temp sense), internal reference
initially off
140
µs
CKSEL = 01 (voltage conversion)
9
CKSEL = 10 (voltage conversion),
internal reference on (Note 18)
9
CKSEL = 10 (voltage conversion),
internal reference initially off
80
CKSEL = 00, CKSEL = 01 (temp sense)
40
ns
CKSEL = 01 (voltage conversion)
1.4
µs
_______________________________________________________________________________________
7
MAX1220/MAX1257/MAX1258
ELECTRICAL CHARACTERISTICS (continued)
MAX1220/MAX1257/MAX1258
12-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
ELECTRICAL CHARACTERISTICS (continued)
(VAVDD = VDVDD = 2.7V to 3.6V (MAX1257), external reference VREF = 2.5V (MAX1257), VAVDD = 4.75V to 5.25V, VDVDD = 2.7V to VAVDD
(MAX1220/MAX1258), external reference VREF = 4.096V (MAX1220/MAX1258), fCLK = 3.6MHz (50% duty cycle), TA = -40°C to +85°C,
unless otherwise noted. Typical values are at VAVDD = VDVDD = 3V (MAX1257), VAVDD = VDVDD = 5V (MAX1220/MAX1258), TA = +25°C.
Outputs are unloaded, unless otherwise noted.)
Note 1: Tested at VDVDD = VAVDD = +2.7V (MAX1257), VDVDD = +2.7V, VAVDD = +5.25V (MAX1220/MAX1258).
Note 2: Offset nulled.
Note 3: No bus activity during conversion. Conversion time is defined as the number of conversion clock cycles multiplied by the
clock period.
Note 4: See Table 5 for reference-mode details.
Note 5: Not production tested. Guaranteed by design.
Note 6: See the ADC/DAC References section.
Note 7: Fast automated test, excludes self-heating effects.
Note 8: Specified over the -40°C to +85°C temperature range.
Note 9: REFSEL[1:0] = 00 and when DACs are not powered up.
Note 10: DAC linearity, gain, and offset measurements are made between codes 115 and 3981.
Note 11: The DAC buffers are guaranteed by design to be stable with a 1nF load.
Note 12: Time required by the DAC output to power up and settle within 1 LSB in the external reference mode.
Note 13: All DAC dynamic specifications are valid for a load of 100pF and 10kΩ.
Note 14: Only one digital output (either DOUT, EOC, or the GPIOs) can be indefinitely shorted to either supply at one time.
Note 15: All digital inputs at either VDVDD or DGND. VDVDD should not exceed VAVDD.
Note 16: See the Reset Register section and Table 9 for details on programming the SLOW bit.
Note 17: Clock mode 11 only.
Note 18: First conversion after reference power-up is always timed as if the internal reference was initially off to ensure the internal
reference has settled. Subsequent conversions are timed as shown.
8
_______________________________________________________________________________________
12-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
ANALOG SHUTDOWN CURRENT
vs. ANALOG SUPPLY VOLTAGE
0.3
0.2
0.1
0.4
0.3
0.2
0.1
MAX1220/MAX1258
0
4.875
5.000
5.125
0.1
MAX1257
0
2.7
3.0
3.3
3.6
-40
-15
10
35
60
TEMPERATURE (°C)
ADC INTEGRAL NONLINEARITY
vs. OUTPUT CODE
ADC INTEGRAL NONLINEARITY
vs. OUTPUT CODE
ADC DIFFERENTIAL NONLINEARITY
vs. OUTPUT CODE
0
-0.25
-0.50
0.25
0
-0.25
-0.50
0.75
0.50
0.25
0
-0.25
-0.50
-0.75
-0.75
MAX1220/MAX1258
MAX1257
MAX1220/MAX1258
-1.00
-1.00
-1.00
1024
MAX1220 toc06
MAX1220 toc05
0.50
2048
3072
4096
1024
0
2048
3072
0
4096
1024
2048
3072
OUTPUT CODE
OUTPUT CODE
OUTPUT CODE
ADC DIFFERENTIAL NONLINEARITY
vs. OUTPUT CODE
ADC OFFSET ERROR
vs. ANALOG SUPPLY VOLTAGE
ADC OFFSET ERROR
vs. ANALOG SUPPLY VOLATGE
0.25
0
-0.25
0.6
0.4
MAX1220 toc09
0.8
OFFSET ERROR (LSB)
0.50
4096
1.0
0.8
OFFSET ERROR (LSB)
0.75
MAX1220 toc08
1.0
MAX1220 toc07
1.00
85
1.00
DIFFERENTIAL NONLINEARITY (LSB)
0.25
0.75
INTEGRAL NONLINEARITY (LSB)
MAX1220 toc04
0.50
1.00
-0.75
DIFFERENTIAL NONLINEARITY (LSB)
0.2
SUPPLY VOLTAGE (V)
0.75
0
MAX1220/MAX1258
SUPPLY VOLTAGE (V)
1.00
INTEGRAL NONLINEARITY (LSB)
5.250
0.3
MAX1257
0
4.750
0.4
MAX1220 toc03
MAX1220 toc02
0.4
0.5
ANALOG SHUTDOWN CURRENT (µA)
MAX1220 toc01
ANALOG SHUTDOWN CURRENT (µA)
0.5
ANALOG SHUTDOWN CURRENT
vs. TEMPERATURE
ANALOG SHUTDOWN CURRENT (µA)
ANALOG SHUTDOWN CURRENT
vs. ANALOG SUPPLY VOLTAGE
0.6
0.4
-0.50
0.2
0.2
-0.75
MAX1220/MAX1258
MAX1257
-1.00
MAX1257
0
0
1024
2048
OUTPUT CODE
3072
4096
0
4.750
4.875
5.000
5.125
SUPPLY VOLTAGE (V)
5.250
2.7
3.0
3.3
3.6
SUPPLY VOLTAGE (V)
_______________________________________________________________________________________
9
MAX1220/MAX1257/MAX1258
Typical Operating Characteristics
(VAVDD = VDVDD = 3V (MAX1257), external VREF = 2.5V (MAX1257), VAVDD = VDVDD = 5V (MAX1220/MAX1258), external VREF =
4.096V (MAX1220/MAX1258), fCLK = 3.6MHz (50% duty cycle), fSAMPLE = 225ksps, CLOAD = 50pF, 0.1µF capacitor at REF,
TA = +25°C, unless otherwise noted.)
Typical Operating Characteristics (continued)
(VAVDD = VDVDD = 3V (MAX1257), external VREF = 2.5V (MAX1257), VAVDD = VDVDD = 5V (MAX1220/MAX1258), external VREF =
4.096V (MAX1220/MAX1258), fCLK = 3.6MHz (50% duty cycle), fSAMPLE = 225ksps, CLOAD = 50pF, 0.1µF capacitor at REF,
TA = +25°C, unless otherwise noted.)
ADC GAIN ERROR
ADC GAIN ERROR
ADC OFFSET ERROR
vs. ANALOG SUPPLY VOLTAGE
vs. ANALOG SUPPLY VOLTAGE
vs. TEMPERATURE
MAX1257
0
-0.5
-0.5
-2
MAX1220/MAX1258
-1.0
4.750
4.875
5.000
-1.0
10
35
60
85
3.0
3.3
3.6
SUPPLY VOLTAGE (V)
ADC GAIN ERROR
vs. TEMPERATURE
ADC EXTERNAL REFERENCE
INPUT CURRENT vs. SAMPLING RATE
ANALOG SUPPLY CURRENT
vs. SAMPLING RATE
MAX1257
-2
10
35
60
50
40
MAX1220/MAX1258
30
20
10
3.0
MAX1220/MAX1258
2.5
2.0
1.5
1.0
0.5
MAX1257
MAX1257
0
0
0
85
MAX1220 toc15
60
ANALOG SUPPLY CURRENT (mA)
MAX1220 toc13
0
-15
2.7
5.250
SUPPLY VOLTAGE (V)
MAX1220/MAX1258
50
100
150
200
250
0
300
50
100
150
200
250
TEMPERATURE (°C)
SAMPLING RATE (ksps)
SAMPLING RATE (ksps)
ANALOG SUPPLY CURRENT
vs. ANALOG SUPPLY VOLTAGE
ANALOG SUPPLY CURRENT
vs. ANALOG SUPPLY VOLTAGE
ANALOG SUPPLY CURRENT
vs. TEMPERATURE
1.98
1.96
1.94
1.92
MAX1220/MAX1258
1.90
4.750
4.875
5.000
5.125
SUPPLY VOLTAGE (V)
2.00
1.98
1.96
1.94
MAX1220/MAX1258
2.00
300
MAX1220 toc18
2.02
2.02
ANALOG SUPPLY CURRENT (mA)
2.00
MAX1220 toc17
2.02
2.04
SUPPLY CURRENT (mA)
2.04
MAX1220 toc16
-40
5.125
TEMPERATURE (°C)
1
-1
MAX1257
MAX1220 toc14
-15
MAX1220 toc12
MAX1220 toc11
0
-1
2
GAIN ERROR (LSB)
0.5
GAIN ERROR (LSB)
GAIN ERROR (LSB)
0
-40
10
1.0
0.5
1
ADC EXTERNAL REFERENCE INPUT CURRENT (µA)
OFFSET ERROR (LSB)
MAX1220/MAX1258
1.0
MAX1220 toc10
2
SUPPLY CURRENT (mA)
MAX1220/MAX1257/MAX1258
12-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
1.98
1.96
1.94
1.92
MAX1257
1.90
1.92
MAX1257
1.88
1.90
5.250
2.7
3.0
3.3
SUPPLY VOLTAGE (V)
3.6
-40
-15
10
35
TEMPERATURE (°C)
______________________________________________________________________________________
60
85
12-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
0
-0.5
-1.0
0.5
0
-0.5
-1.0
MAX1220/MAX1258
2048
3072
1024
0
2048
3072
2047
4096
2053
2056
2059
DAC DIFFERENTIAL NONLINEARITY
vs. OUTPUT CODE
DAC FULL-SCALE ERROR
vs. ANALOG SUPPLY VOLTAGE
DAC FULL-SCALE ERROR
vs. ANALOG SUPPLY VOLTAGE
0.8
0.6
0.4
0.8
0.6
0.4
MAX1257
EXTERNAL REFERENCE = 2.5V
0.2
0.2
2050
1.0
MAX1220/MAX1258
EXTERNAL REFERENCE = 4.096V
-0.4
2053
2056
2059
4.750
2062
4.875
5.000
5.125
2.7
5.250
3.0
3.3
3.6
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
DAC FULL-SCALE ERROR
vs. TEMPERATURE
DAC FULL-SCALE ERROR
vs. TEMPERATURE
DAC FULL-SCALE ERROR
vs. REFERENCE VOLTAGE
4
2
0
EXTERNAL
REFERENCE = 4.096V
-4
8
6
4
2
0
EXTERNAL
REFERENCE = 2.5V
-2
-4
0.50
0.25
0
-0.25
-0.50
MAX1220/MAX1258
MAX1257
-6
-6
10
0.75
-0.75
MAX1220/MAX1258
-15
1.00
MAX1220 toc27
INTERNAL
REFERENCE
DAC FULL-SCALE ERROR (LSB)
6
MAX1220 toc26
INTERNAL
REFERENCE
10
DAC FULL-SCALE ERROR (LSB)
8
MAX1220 toc25
OUTPUT CODE
10
35
TEMPERATURE (°C)
60
85
2062
MAX1220 toc24
MAX1220 toc23
1.0
1.2
DAC FULL-SCALE ERROR (LSB)
-0.2
1.2
DAC FULL-SCALE ERROR (LSB)
0
-40
2050
OUTPUT CODE
MAX1257
DAC FULL-SCALE ERROR (LSB)
MAX1220/MAX1258
OUTPUT CODE
MAX1220 toc22
DIFFERENTIAL NONLINEARITY (LSB)
4096
0.2
-2
-0.2
OUTPUT CODE
0.4
2047
0
-0.4
-1.5
1024
0.2
MAX1257
-1.5
0
MAX1220 toc21
1.0
0.4
DIFFERENTIAL NONLINEARITY (LSB)
0.5
MAX1220 toc20
1.0
1.5
INTEGRAL NONLINEARITY (LSB)
MAX1220 toc19
INTEGRAL NONLINEARITY (LSB)
1.5
-1.00
-40
-15
10
35
TEMPERATURE (°C)
60
85
0
1
2
3
4
5
REFERENCE VOLTAGE (V)
______________________________________________________________________________________
11
MAX1220/MAX1257/MAX1258
Typical Operating Characteristics (continued)
(VAVDD = VDVDD = 3V (MAX1257), external VREF = 2.5V (MAX1257), VAVDD = VDVDD = 5V (MAX1220/MAX1258), external VREF =
4.096V (MAX1220/MAX1258), fCLK = 3.6MHz (50% duty cycle), fSAMPLE = 225ksps, CLOAD = 50pF, 0.1µF capacitor at REF,
TA = +25°C, unless otherwise noted.)
DAC INTEGRAL NONLINEARITY
DAC DIFFERENTIAL NONLINEARITY
DAC INTEGRAL NONLINEARITY
vs. OUTPUT CODE
vs. OUTPUT CODE
vs. OUTPUT CODE
Typical Operating Characteristics (continued)
(VAVDD = VDVDD = 3V (MAX1257), external VREF = 2.5V (MAX1257), VAVDD = VDVDD = 5V (MAX1220/MAX1258), external VREF =
4.096V (MAX1220/MAX1258), fCLK = 3.6MHz (50% duty cycle), fSAMPLE = 225ksps, CLOAD = 50pF, 0.1µF capacitor at REF,
TA = +25°C, unless otherwise noted.)
DAC FULL-SCALE ERROR
vs. REFERENCE VOLTAGE
-3
-4
-5
-5
-10
MAX1220 toc30
MAX1220 toc29
0
5
DAC FULL-SCALE ERROR (LSB)
-2
5
DAC FULL-SCALE ERROR (LSB)
-1
DAC FULL-SCALE ERROR
vs. LOAD CURRENT
DAC FULL-SCALE ERROR
vs. LOAD CURRENT
MAX1220 toc28
DAC FULL-SCALE ERROR (LSB)
0
0
-5
-10
-6
0.5
1.0
1.5
2.0
2.5
5
0
3.0
10
15
20
25
0
30
1.5
2.0
2.5
3.0
LOAD CURRENT (mA)
INTERNAL REFERENCE VOLTAGE
vs. TEMPERATURE
INTERNAL REFERENCE VOLTAGE
vs. TEMPERATURE
ADC REFERENCE SUPPLY CURRENT
vs. ANALOG SUPPLY VOLTAGE
2.50
2.49
MAX1220/MAX1258
MAX1257
4.08
10
35
60
85
-40
-15
10
35
60
24.94
24.92
24.90
24.88
24.86
MAX1220/MAX1258
24.84
4.750
4.875
5.000
2.48
-15
MAX1220 toc33
MAX1220 toc32
2.51
24.96
ADC REFERENCE SUPPLY CURRENT (µA)
4.09
2.52
INTERNAL REFERENCE VOLTAGE (V)
MAX1220 toc31
4.10
85
5.125
5.250
TEMPERATURE (°C)
TEMPERATURE (°C)
SUPPLY VOLTAGE (V)
ADC REFERENCE SUPPLY CURRENT
vs. ANALOG SUPPLY VOLATAGE
ADC REFERENCE SUPPLY CURRENT
vs. TEMPERATURE
ADC REFERENCE SUPPLY CURRENT
vs. TEMPERATURE
24.9
24.8
40.8
40.7
40.6
MAX1220/MAX1258
EXTERNAL REFERENCE = 4.096V
MAX1257
3.0
3.3
SUPPLY VOLTAGE (V)
3.6
25.0
24.9
24.8
MAX1257, EXTERNAL REFERENCE = 2.5V
40.5
24.7
MAX1220 toc36
MAX1220 toc35
40.9
25.1
ADC REFERENCE SUPPLY CURRENT (µA)
25.0
41.0
ADC REFERENCE SUPPLY CURRENT (µA)
MAX1220 toc34
25.1
2.7
1.0
LOAD CURRENT (mA)
4.11
-40
0.5
REFERENCE VOLTAGE (V)
4.12
INETRNAL REFERENCE VOLTAGE (V)
-15
-15
0
12
MAX1257
MAX1220/MAX1258
MAX1257
-7
ADC REFERENCE SUPPLY CURRENT (µA)
MAX1220/MAX1257/MAX1258
12-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
24.7
-40
-15
10
35
TEMPERATURE (°C)
60
85
-40
-15
10
35
TEMPERATURE (°C)
______________________________________________________________________________________
60
85
12-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
-40
-100
-80
-100
-120
-120
-140
-140
-140
-160
50
100
150
200
150
200
50
0
100
150
ANALOG INPUT FREQUENCY (kHz)
DAC OUTPUT LOAD REGULATION
vs. OUTPUT CURRENT
DAC OUTPUT LOAD REGULATION
vs. OUTPUT CURRENT
GPIO OUTPUT VOLTAGE
vs. SOURCE CURRENT
DAC OUTPUT VOLTAGE (V)
2.05
2.04
SINKING
SOURCING
2.02
1.28
1.27
1.26
1.25
1.24
SINKING
1.23
SOURCING
1.22
DAC OUTPUT = MIDSCALE
MAX1220/MAX1258
2.00
5
GPIO OUTPUT VOLTAGE (V)
1.29
MAX1220 toc40
2.06
DAC OUTPUT = MIDSCALE
MAX1257
OUTPUT CURRENT (mA)
GPIO OUTPUT VOLTAGE
vs. SOURCE CURRENT
GPIO OUTPUT VOLTAGE
vs. SINK CURRENT
MAX1257
GPIOA0–A3 OUTPUTS
2.5
2.0
1.5
GPIOB0–B3, C0–C3
OUTPUTS
1.0
0.5
-20
20
GPIOA0–A3 OUTPUTS
3
2
GPIOB0–B3,
C0–C3 OUTPUTS
0
30
20
40
60
80
1500
GPIOB0–B3, C0–C3
OUTPUTS
1200
GPIO OUTPUT VOLTAGE
vs. SINK CURRENT
900
600
GPIOA0–A3 OUTPUTS
300
1500
GPIOB0–B3, C0–C3
OUTPUTS
1200
900
600
GPIOA0–A3 OUTPUTS
300
MAX1220/MAX1258
MAX1257
0
0
20
40
60
SOURCE CURRENT (mA)
80
100
100
SOURCE CURRENT (mA)
GPIO OUTPUT VOLTAGE (mV)
3.0
-30
4
0
0
10
-10
OUTPUT CURRENT (mA)
90
MAX1220 toc44
60
GPIO OUTPUT VOLTAGE (mV)
30
MAX1220 toc43
0
-30
MAX1220/MAX1258
1
1.21
0
200
ANALOG INPUT FREQUENCY (kHz)
2.07
2.01
100
ANALOG INPUT FREQUENCY (kHz)
2.08
2.03
-160
50
0
MAX1220 toc41
0
DAC OUTPUT VOLTAGE (V)
-80
-60
-120
-160
GPIO OUTPUT VOLTAGE (V)
-60
MAX1220 toc42
-100
-40
MAX1220 toc45
-80
fCLK = 5.24288MHz
fIN1 = 10.080kHz
fIN2 = 8.0801kHz
SNR = 72.00dBc
THD = 85.24dBc
ENOB = 11.65 BITS
-20
AMPLITUDE (dB)
-60
fCLK = 5.24288MHz
fIN1 = 9.0kHz
fIN2 = 11.0kHz
AIN = -6dBFS
IMD = 82.99dBc
-20
AMPLITUDE (dB)
-40
ADC CROSSTALK PLOT
0
MAX1220 toc38
MAX1220 toc37
fSAMPLE = 32.768kHz
fANALOG_N = 10.080kHz
fCLK = 5.24288MHz
SINAD = 71.27dBc
SNR = 71.45dBc
THD = 85.32dBc
SFDR = 87.25dBc
-20
AMPLITUDE (dB)
ADC IMD PLOT
0
MAX1220 toc39
ADC FFT PLOT
0
0
0
20
40
60
SINK CURRENT (mA)
80
100
0
10
20
30
40
50
60
SINK CURRENT (mA)
______________________________________________________________________________________
13
MAX1220/MAX1257/MAX1258
Typical Operating Characteristics (continued)
(VAVDD = VDVDD = 3V (MAX1257), external VREF = 2.5V (MAX1257), VAVDD = VDVDD = 5V (MAX1220/MAX1258), external VREF =
4.096V (MAX1220/MAX1258), fCLK = 3.6MHz (50% duty cycle), fSAMPLE = 225ksps, CLOAD = 50pF, 0.1µF capacitor at REF,
TA = +25°C, unless otherwise noted.)
Typical Operating Characteristics (continued)
(VAVDD = VDVDD = 3V (MAX1257), external VREF = 2.5V (MAX1257), VAVDD = VDVDD = 5V (MAX1220/MAX1258), external VREF =
4.096V (MAX1220/MAX1258), fCLK = 3.6MHz (50% duty cycle), fSAMPLE = 225ksps, CLOAD = 50pF, 0.1µF capacitor at REF,
TA = +25°C, unless otherwise noted.)
DAC-TO-DAC CROSSTALK
DAC-TO-DAC CROSSTALK
TEMPERATURE SENSOR ERROR
RLOAD = 10kΩ, CLOAD = 100pF
RLOAD = 10kΩ, CLOAD = 100pF
vs. TEMPERATURE
MAX1220 toc48
MAX1220 toc47
MAX1220 toc46
1.00
TEMPERATURE SENSOR ERROR (°C)
MAX1220/MAX1257/MAX1258
12-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
0.75
VOUTA
1V/div
0.50
VOUTA
2V/div
0.25
0
-0.25
VOUTB
10mV/div
AC-COUPLED
VOUTB
10mV/div
AC-COUPLED
-0.50
-0.75
MAX1220/MAX1258
MAX1257
-1.00
-40
-15
10
35
60
100µs/div
100µs/div
85
TEMPERATURE (°C)
DYNAMIC RESPONSE RISE TIME
RLOAD = 10kΩ, CLOAD = 100pF
DYNAMIC RESPONSE FALL TIME
RLOAD = 10kΩ, CLOAD = 100pF
DYNAMIC RESPONSE RISE TIME
RLOAD = 10kΩ, CLOAD = 100pF
MAX1220 toc49
MAX1220 toc51
MAX1220 toc50
MAX1257
MAX1257
CS
2V/div
VOUT_
1V/div
VOUT_
1V/div
VOUT_
2V/div
CS
1V/div
CS
1V/div
MAX1220/MAX1258
1µs/div
1µs/div
1µs/div
DYNAMIC RESPONSE FALL TIME
RLOAD = 10kΩ, CLOAD = 100pF
MAJOR CARRY TRANSITION
RLOAD = 10kΩ, CLOAD = 100pF
MAJOR CARRY TRANSITION
RLOAD = 10kΩ, CLOAD = 100pF
MAX1220 toc52
CS
2V/div
1µs/div
14
CS
2V/div
CS
1V/div
VOUT_
20mV/div
AC-COUPLED
VOUT_
10mV/div
AC-COUPLED
VOUT_
2V/div
MAX1220/MAX1258
MAX1220 toc54
MAX1220 toc53
MAX1257
MAX1220/MAX1258
1µs/div
1µs/div
______________________________________________________________________________________
12-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
DAC DIGITAL FEEDTHROUGH RLOAD = 10kΩ,
CLOAD = 100pF, CS = HIGH, DIN = LOW
DAC DIGITAL FEEDTHROUGH RLOAD = 10kΩ,
CLOAD = 100pF, CS = HIGH, DIN = LOW
MAX1220 toc56
MAX1220 toc55
NEGATIVE FULL-SCALE SETTLING TIME
RLOAD = 10kΩ, CLOAD = 100pF
MAX1220 toc57
MAX1257
SCLK
2V/div
SCLK
1V/div
VOUT_
1V/div
VOUT_
100mV/div
AC-COUPLED
VOUT_
100mV/div
AC-COUPLED
VLDAC
1V/div
MAX1220/MAX1258
MAX1257
200ns/div
200ns/div
1µs/div
NEGATIVE FULL-SCALE SETTLING TIME
RLOAD = 10kΩ, CLOAD = 100pF
POSITIVE FULL-SCALE SETTLING TIME
RLOAD = 10kΩ, CLOAD = 100pF
POSITIVE FULL-SCALE SETTLING TIME
RLOAD = 10kΩ, CLOAD = 100pF
MAX1220 toc59
MAX1220 toc60
MAX1220 toc58
MAX1257
VLDAC
2V/div
VLDAC
2V/div
VOUT_
1V/div
VOUT_
2V/div
VOUT_
2V/div
VLDAC
1V/div
MAX1220/MAX1258
2µs/div
MAX1220/MAX1258
1µs/div
ADC REFERENCE FEEDTHROUGH
RLOAD = 10kΩ, CLOAD = 100pF
1µs/div
ADC REFERENCE FEEDTHROUGH
RLOAD = 10kΩ, CLOAD = 100pF
MAX1220 toc61
MAX1220 toc62
VREF2
1V/div
VREF2
2V/div
VDAC-OUT
10mV/div
AC-COUPLED
MAX1257
ADC REFERENCE SWITCHING
200µs/div
MAX1220/MAX1258
ADC REFERENCE SWITCHING
VDAC-OUT
2mV/div
AC-COUPLED
200µs/div
______________________________________________________________________________________
15
MAX1220/MAX1257/MAX1258
Typical Operating Characteristics (continued)
(VAVDD = VDVDD = 3V (MAX1257), external VREF = 2.5V (MAX1257), VAVDD = VDVDD = 5V (MAX1220/MAX1258), external VREF =
4.096V (MAX1220/MAX1258), fCLK = 3.6MHz (50% duty cycle), fSAMPLE = 225ksps, CLOAD = 50pF, 0.1µF capacitor at REF,
TA = +25°C, unless otherwise noted.)
MAX1220/MAX1257/MAX1258
12-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
Pin Description
PIN
NAME
FUNCTION
MAX1220
MAX1257
MAX1258
1, 2
—
3
4
EOC
4
7
DVDD
Digital Positive-Power Input. Bypass DVDD to DGND with a 0.1µF
capacitor.
5
8
DGND
Digital Ground. Connect DGND to AGND.
6
9
DOUT
Serial-Data Output. Data is clocked out on the falling edge of the SCLK
clock in modes 00, 01, and 10. Data is clocked out on the rising edge of
the SCLK clock in mode 11. It is high impedance when CS is high.
7
10
SCLK
Serial-Clock Input. Clocks data in and out of the serial interface. (Duty
cycle must be 40% to 60%.) See Table 5 for details on programming the
clock mode.
8
11
DIN
9–12, 16–19
12–15,
22–25
OUT0–OUT7
13
18
AVDD
Positive Analog Power Input. Bypass AVDD to AGND with a 0.1µF
capacitor.
14
19
AGND
Analog Ground
15, 23, 32, 33
—
N.C.
20
26
LDAC
21
27
CS
16
22
28
24, 25
—
GPIOA0, GPIOA1 General-Purpose I/O A0, A1. GPIOA0, A1 can sink and source 15mA.
RES_SEL
Active-Low End-of-Conversion Output. Data is valid after the falling edge
of EOC.
Serial-Data Input. DIN data is latched into the serial interface on the
falling edge of SCLK.
DAC Outputs
No Connection. Not internally connected.
Active-Low Load DAC. LDAC is an asynchronous active-low input that
updates the DAC outputs. Drive LDAC low to make the DAC registers
transparent.
Active-Low Chip-Select Input. When CS is low, the serial interface is
enabled. When CS is high, DOUT is high impedance.
Reset Select. Select DAC wake-up mode. Set RES_SEL low to wake up
the DAC outputs with a 100k resistor to AGND or set RES_SEL high to
wake up the DAC outputs with a 100k resistor to VREF. Set RES_SEL
high to power up the DAC input register to FFFh. Set RES_SEL low to
power up the DAC input register to 000h.
GPIOC0, GPIOC1 General-Purpose I/O C0, C1. GPIOC0, C1 can sink 4mA and source 2mA.
______________________________________________________________________________________
12-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
PIN
MAX1220
MAX1257
MAX1258
NAME
FUNCTION
Reference 1 Input. Reference voltage; leave unconnected to use the
internal reference (2.5V for the MAX1257 or 4.096V for the
MAX1220/MAX1258). REF1 is the positive reference in ADC external
differential reference mode. Bypass REF1 to AGND with a 0.1µF
capacitor in external reference mode only. See the ADC/DAC
References section.
26
35
REF1
27–31, 34
—
AIN0–AIN5
Analog Inputs
Reference 2 Input/Analog Input 6. See Table 5 for details on
programming the setup register. REF2 is the negative reference in the
ADC external differential reference mode.
35
—
REF2/AIN6
36
—
CNVST/AIN7
Active-Low Conversion-Start Input/Analog Input 7. See Table 5 for details
on programming the setup register.
—
1
CNVST/AIN15
Active-Low Conversion-Start Input/Analog Input 15. See Table 5 for
details on programming the setup register.
—
2, 3, 5, 6
—
16, 17,
20, 21
GPIOB0–GPIOB3
General-Purpose I/O B0–B3. GPIOB0–GPIOB3 can sink 4mA and
source 2mA.
—
29–32
GPIOC0–GPIOC3
General-Purpose I/O C0–C3. GPIOC0–GPIOC3 can sink 4mA and
source 2mA.
—
33, 34, 36–47
AIN0–AIN13
Analog Inputs
—
48
REF2/AIN14
Reference 2 Input/Analog Input 14. See Table 5 for details on
programming the setup register. REF2 is the negative reference in the
ADC external differential reference mode.
—
—
EP
Exposed Pad. Must be externally connected to AGND. Do not use as a
ground connect.
GPIOA0–GPIOA3 General-Purpose I/O A0–A3. GPIOA0–GPIOA3 can sink and source 15mA.
______________________________________________________________________________________
17
MAX1220/MAX1257/MAX1258
Pin Description (continued)
MAX1220/MAX1257/MAX1258
12-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
Detailed Description
The MAX1220/MAX1257/MAX1258 integrate a 12-bit,
multichannel, analog-to-digital converter (ADC), and a
12-bit, octal, digital-to-analog converter (DAC) in a single IC. These devices also include a temperature sensor and configurable GPIOs with a 25MHz
SPI-/QSPI-/MICROWIRE-compatible serial interface.
The ADC is available in 8 and 16 input-channel
versions. The octal DAC outputs settle within 2.0µs, and
the ADC has a 225ksps conversion rate.
All devices include an internal reference (2.5V or
4.096V) providing a well-regulated, low-noise reference
for both the ADC and DAC. Programmable reference
modes for the ADC and DAC allow the use of an internal reference, an external reference, or a combination
of both. Features such as an internal ±1°C accurate
temperature sensor, FIFO, scan modes, programmable
internal or external clock modes, data averaging, and
AutoShutdown allow users to minimize both power consumption and processor requirements. The low glitch
energy (4nV•s) and low digital feedthrough (0.5nV•s) of
the integrated octal DACs make these devices ideal for
digital control of fast-response closed-loop systems.
These devices are guaranteed to operate with a supply
voltage from +2.7V to +3.6V (MAX1257) and from
+4.75V to +5.25V (MAX1220/MAX1258). These devices
consume 2.5mA at 225ksps throughput, only 22µA at
1ksps throughput, and under 0.2µA in the shutdown
mode. The MAX1257/MAX1258 feature 12 GPIOs while
the MAX1220 offers four GPIOs that can be configured
as inputs or outputs.
Figure 1 shows the MAX1257/MAX1258 functional diagram. The MAX1220 only includes the GPIOA0,
GPIOA1 and GPIOC0, GPIOC1 block. The output-conditioning circuitry takes the internal parallel data bus
and converts it to a serial data format at DOUT, with the
appropriate wake-up timing. The arithmetic logic unit
(ALU) performs the averaging function.
SPI-Compatible Serial Interface
The MAX1220/MAX1257/MAX1258 feature a serial interface that is compatible with SPI and MICROWIRE
devices. For SPI, ensure the SPI bus master (typically a
microcontroller (µC)) runs in master mode so that it
generates the serial clock signal. Select the SCLK frequency of 25MHz or less, and set the clock polarity
18
(CPOL) and phase (CPHA) in the µC control registers to
the same value. The MAX1220/MAX1257/MAX1258
operate with SCLK idling high or low, and thus operate
with CPOL = CPHA = 0 or CPOL = CPHA = 1. Set CS
low to latch any input data at DIN on the falling edge of
SCLK. Output data at DOUT is updated on the falling
edge of SCLK in clock modes 00, 01, and 10. Output
data at DOUT is updated on the rising edge of SCLK in
clock mode 11. See Figures 6–11. Bipolar true-differential results and temperature-sensor results are available
in two’s complement format, while all other results are in
binary.
A high-to-low transition on CS initiates the data-input
operation. Serial communications to the ADC always
begin with an 8-bit command byte (MSB first) loaded
from DIN. The command byte and the subsequent data
bytes are clocked from DIN into the serial interface on
the falling edge of SCLK. The serial-interface and fastinterface circuitry is common to the ADC, DAC, and
GPIO sections. The content of the command byte
determines whether the SPI port should expect 8, 16, or
24 bits and whether the data is intended for the ADC,
DAC, or GPIOs (if applicable). See Table 1. Driving CS
high resets the serial interface.
The conversion register controls ADC channel selection, ADC scan mode, and temperature-measurement
requests. See Table 4 for information on writing to the
conversion register. The setup register controls the
clock mode, reference, and unipolar/bipolar ADC configuration. Use a second byte, following the first, to
write to the unipolar-mode or bipolar-mode registers.
See Table 5 for details of the setup register and see
Tables 6, 7, and 8 for setting the unipolar- and bipolarmode registers. Hold CS low between the command
byte and the second and third byte. The ADC averaging register is specific to the ADC. See Table 9 to
address that register. Table 11 shows the details of the
reset register.
Begin a write to the DAC by writing 0001XXXX as a
command byte. The last 4 bits of this command byte
are don’t-care bits. Write another 2 bytes (holding CS
low) to the DAC interface register following the command byte to select the appropriate DAC and the data
to be written to it. See the DAC Serial Interface section
and Tables 10, 20, and 21.
______________________________________________________________________________________
12-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
USER-PROGRAMMABLE
I/O
MAX1220/MAX1257/MAX1258
AVDD
GPIOA0– GPIOB0– GPIOC0–
GPIOA3 GPIOB3 GPIOC3
DVDD
MAX1257
MAX1258
GPIO
CONTROL
OSCILLATOR
INPUT
REGISTER
DAC
REGISTER
12-BIT
DAC
BUFFER
OUTPUT
CONDITIONING
OUT0
INPUT
REGISTER
DAC
REGISTER
12-BIT
DAC
BUFFER
OUTPUT
CONDITIONING
OUT1
INPUT
REGISTER
DAC
REGISTER
12-BIT
DAC
BUFFER
OUTPUT
CONDITIONING
OUT2
INPUT
REGISTER
DAC
REGISTER
12-BIT
DAC
BUFFER
OUTPUT
CONDITIONING
OUT3
INPUT
REGISTER
DAC
REGISTER
12-BIT
DAC
BUFFER
OUTPUT
CONDITIONING
OUT4
INPUT
REGISTER
DAC
REGISTER
12-BIT
DAC
BUFFER
OUTPUT
CONDITIONING
OUT5
INPUT
REGISTER
DAC
REGISTER
12-BIT
DAC
BUFFER
OUTPUT
CONDITIONING
OUT6
INPUT
REGISTER
DAC
REGISTER
12-BIT
DAC
BUFFER
OUTPUT
CONDITIONING
OUT7
SCLK
CS
DIN
SPI
PORT
DOUT
TEMPERATURE
SENSOR
ADDRESS
EOC
LOGIC
CONTROL
CNVST
AIN0
AIN13
REF2/
AIN14
CNVST/
AIN15
REF1
T/H
12-BIT
SAR
ADC
FIFO AND
ALU
REF2
INTERNAL
REFERENCE
LDAC
AGND
DGND
RES_SEL
Figure 1. MAX1257/MAX1258 Functional Diagram
______________________________________________________________________________________
19
MAX1220/MAX1257/MAX1258
12-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
Table 1. Command Byte (MSB First)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
ADDITIONAL
NO. OF
BYTES
Conversion
1
CHSEL3
CHSEL2
CHSEL1
CHSEL0
SCAN1
SCAN0
TEMP
0
Setup
ADC
0
1
CKSEL1
CKSEL0
REFSEL1
REFSEL0
DIFFSEL1
DIFFSEL0
1
0
0
1
AVGON
NAVG1
NAVG0
NSCAN1
NSCAN0
0
DAC Select
0
0
0
1
X
X
X
X
2
Reset
0
0
0
0
1
RESET
SLOW
FBGON
0
GPIO Configure
0
0
0
0
0
0
1
1
1 or 2
GPIO Write
0
0
0
0
0
0
1
0
1 or 2
GPIO Read
0
0
0
0
0
0
0
1
1 or 2
No Operation
0
0
0
0
0
0
0
0
0
REGISTER
NAME
X = Don’t care.
Write to the GPIOs by issuing a command byte to the
appropriate register. Writing to the MAX1220 GPIOs
requires 1 additional byte following the command byte.
Writing to the MAX1257/MAX1258 requires 2 additional
bytes following the command byte. See Tables 12–19
for details on GPIO configuration, writes, and reads.
See the GPIO Command section. Command bytes written to the GPIOs on devices without GPIOs are ignored.
Power-Up Default State
The MAX1220/MAX1257/MAX1258 power up with all
blocks in shutdown (including the reference). All registers power up in state 00000000, except for the setup
register and the DAC input register. The setup register
powers up at 0010 1000 with CKSEL1 = 1 and
REFSEL1 = 1. The DAC input register powers up to
FFFh when RES_SEL is high and powers up to 000h
when RES_SEL is low.
12-Bit ADC
The MAX1220/MAX1257/MAX1258 ADCs use a fully
differential successive-approximation register (SAR)
conversion technique and on-chip track-and-hold (T/H)
circuitry to convert temperature and voltage signals into
12-bit digital results. The analog inputs accept both single-ended and differential input signals. Single-ended
signals are converted using a unipolar transfer function,
and differential signals are converted using a selectable bipolar or unipolar transfer function. See the ADC
Transfer Functions section for more data.
ADC Clock Modes
When addressing the setup, register bits 5 and 4 of the
command byte (CKSEL1 and CKSEL0, respectively)
control the ADC clock modes. See Table 5. Choose
between four different clock modes for various ways to
20
start a conversion and determine whether the acquisitions are internally or externally timed. Select clock
mode 00 to configure CNVST/AIN_ to act as a conversion start and use it to request internally timed conversions, without tying up the serial bus. In clock mode 01,
use CNVST to request conversions one channel at a
time, thereby controlling the sampling speed without
tying up the serial bus. Request and start internally
timed conversions through the serial interface by writing to the conversion register in the default clock mode,
10. Use clock mode 11 with SCLK up to 3.6MHz for
externally timed acquisitions to achieve sampling rates
up to 225ksps. Clock mode 11 disables scanning and
averaging. See Figures 6–9 for timing specifications on
how to begin a conversion.
These devices feature an active-low, end-of-conversion
output. EOC goes low when the ADC completes the last
requested operation and is waiting for the next command byte. EOC goes high when CS or CNVST go low.
EOC is always high in clock mode 11.
Single-Ended or Differential Conversions
The MAX1220/MAX1257/MAX1258 use a fully differential ADC for all conversions. When a pair of inputs are
connected as a differential pair, each input is connected to the ADC. When configured in single-ended mode,
the positive input is the single-ended channel and the
negative input is referred to AGND. See Figure 2.
In differential mode, the T/H samples the difference
between two analog inputs, eliminating common-mode
DC offsets and noise. IN+ and IN- are selected from the
following pairs: AIN0/AIN1, AIN2/AIN3, AIN4/AIN5,
AIN6/AIN7, AIN8/AIN9, AIN10/AIN11, AIN12/AIN13,
AIN14/AIN15. AIN0–AIN7 are available on all devices.
AIN0–AIN15 are available on the MAX1257/MAX1258.
______________________________________________________________________________________
12-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
Unipolar or Bipolar Conversions
Address the unipolar- and bipolar-mode registers
through the setup register (bits 1 and 0). See Table 5 for
the setup register. See Figures 3 and 4 for the transferfunction graphs. Program a pair of analog inputs for differential operation by writing a one to the appropriate bit
of the bipolar- or unipolar-mode register. Unipolar mode
sets the differential input range from 0 to VREF1. A negative differential analog input in unipolar mode causes the
digital output code to be zero. Selecting bipolar mode
sets the differential input range to ±VREF1 / 2. The digital
output code is binary in unipolar mode and two’s complement in bipolar mode.
In single-ended mode, the MAX1220/MAX1257/
MAX1258 always operate in unipolar mode. The analog
inputs are internally referenced to AGND with a full-scale
input range from 0 to the selected reference voltage.
Analog Input (T/H)
The equivalent circuit of Figure 2 shows the ADC input
architecture of the MAX1220/MAX1257/MAX1258. In
track mode, a positive input capacitor is connected to
AIN0–AIN15 in single-ended mode and AIN0, AIN2,
and AIN4–AIN14 (only positive inputs) in differential
mode. A negative input capacitor is connected to
AGND in single-ended mode or AIN1, AIN3, and
AIN0–AIN15
(SINGLE-ENDED),
AIN0, AIN2,
AIN4–AIN14
(DIFFERENTIAL)
REF1
ACQ
DAC
AGND
CIN+
COMPARATOR
HOLD
CINAGND
(SINGLE-ENDED),
AIN1, AIN3,
AIN5–AIN15
(DIFFERENTIAL)
ACQ
HOLD
AVDD / 2
ACQ
HOLD
AIN5–AIN15 (only negative inputs) in differential mode.
For external T/H timing, use clock mode 01. After the
T/H enters hold mode, the difference between the sampled positive and negative input voltages is converted.
The input capacitance charging rate determines the
time required for the T/H to acquire an input signal. If
the input signal’s source impedance is high, the
required acquisition time lengthens.
Any source impedance below 300Ω does not significantly affect the ADC’s AC performance. A high-impedance source can be accommodated either by
lengthening tACQ (only in clock mode 01) or by placing
a 1µF capacitor between the positive and negative analog inputs. The combination of the analog-input source
impedance and the capacitance at the analog input creates an RC filter that limits the analog input bandwidth.
Input Bandwidth
The ADC’s input-tracking circuitry has a 1MHz smallsignal bandwidth, making it possible to digitize highspeed transient events and measure periodic signals
with bandwidths exceeding the ADC’s sampling rate by
using undersampling techniques. Anti-alias prefiltering
of the input signals is necessary to avoid high-frequency signals aliasing into the frequency band
of interest.
Analog Input Protection
Internal electrostatic-discharge (ESD) protection diodes
clamp all analog inputs to AVDD and AGND, allowing
the inputs to swing from (AGND - 0.3V) to (AVDD +
0.3V) without damage. However, for accurate conversions near full scale, the inputs must not exceed AVDD
by more than 50mV or be lower than AGND by 50mV. If
an analog input voltage exceeds the supplies, limit the
input current to 2mA.
Internal FIFO
The MAX1220/MAX1257/MAX1258 contain a firstin/first-out (FIFO) buffer that holds up to 16 ADC results
plus one temperature result. The internal FIFO allows
the ADC to process and store multiple internally
clocked conversions and a temperature measurement
without being serviced by the serial bus.
If the FIFO is filled and further conversions are requested without reading from the FIFO, the oldest ADC
results are overwritten by the new ADC results. Each
result contains 2 bytes, with the MSB preceded by four
leading zeros. After each falling edge of CS, the oldest
available pair of bytes of data is available at DOUT,
MSB first. When the FIFO is empty, DOUT is zero.
Figure 2. Equivalent Input Circuit
______________________________________________________________________________________
21
MAX1220/MAX1257/MAX1258
See Tables 5–8 for more details on configuring the
inputs. For the inputs that are configurable as CNVST,
REF2, and an analog input, only one function can be
used at a time.
MAX1220/MAX1257/MAX1258
12-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
The first 2 bytes of data read out after a temperature
measurement always contain the 12-bit temperature
result, preceded by four leading zeros, MSB first. If
another temperature measurement is performed before
the first temperature result is read out, the old measurement is overwritten by the new result. Temperature
results are in degrees Celsius (two’s complement), at a
resolution of 8 LSB per degree. See the Temperature
Measurements section for details on converting the digital code to a temperature.
12-Bit DAC
In addition to the 12-bit ADC, the MAX1220/
MAX1257/MAX1258 also include eight voltage-output,
12-bit, monotonic DACs with less than 4 LSB integral
nonlinearity error and less than 1 LSB differential nonlinearity error. Each DAC has a 2µs settling time and ultralow glitch energy (4nV • s). The 12-bit DAC code is
unipolar binary with 1 LSB = VREF/4096.
DAC Digital Interface
Figure 1 shows the functional diagram of the MAX1257/
MAX1258. The shift register converts a serial 16-bit word
to parallel data for each input register operating with a
clock rate up to 25MHz. The SPI-compatible digital interface to the shift register consists of CS, SCLK, DIN, and
DOUT. Serial data at DIN is loaded on the falling edge
of SCLK. Pull CS low to begin a write sequence. Begin a
write to the DAC by writing 0001XXXX as a command
byte. The last 4 bits of the DAC select register are don’tcare bits. See Table 10. Write another 2 bytes to the
DAC interface register following the command byte to
select the appropriate DAC and the data to be written to
it. See Tables 20 and 21.
The eight double-buffered DACs include an input and a
DAC register. The input registers are directly connected to the shift register and hold the result of the most
recent write operation. The eight 12-bit DAC registers
hold the current output code for the respective DAC.
Data can be transferred from the input registers to the
DAC registers by pulling LDAC low or by writing the
appropriate DAC command sequence at DIN. See
Table 20. The outputs of the DACs are buffered through
eight rail-to-rail op amps.
The MAX1220/MAX1257/MAX1258 DAC output voltage
range is based on the internal reference or an external
reference. Write to the setup register (see Table 5) to
program the reference. If using an external voltage reference, bypass REF1 with a 0.1µF capacitor to AGND.
22
The MAX1257 internal reference is 2.5V. The
MAX1220/MAX1258 internal reference is 4.096V. When
using an external reference on any of these devices,
the voltage range is 0.7V to VAVDD.
DAC Transfer Function
See Table 2 for various analog outputs from the DAC.
DAC Power-On Wake-Up Modes
The state of the RES_SEL input determines the wake-up
state of the DAC outputs. Connect RES_SEL to AVDD
or AGND upon power-up to be sure the DAC outputs
wake up to a known state. Connect RES_SEL to AGND
to wake up all DAC outputs at 000h. While RES_SEL is
low, the 100kΩ internal resistor pulls the DAC outputs to
AGND and the output buffers are powered down.
Connect RES_SEL to AVDD to wake up all DAC outputs
at FFFh. While RES_SEL is high, the 100kΩ pullup
resistor pulls the DAC outputs to VREF1 and the output
buffers are powered down.
DAC Power-Up Modes
See Table 21 for a description of the DAC power-up
and power-down modes.
GPIOs
In addition to the internal ADC and DAC, the
MAX1257/MAX1258 also provide 12 general-purpose
input/output channels, GPIOA0–GPIOA3, GPIOB0–
Table 2. DAC Output Code Table
DAC CONTENTS
MSB
LSB
ANALOG OUTPUT
1111
1111
1111
⎛ 4095 ⎞
+ VREF ⎜
⎝ 4096 ⎟⎠
1000
0000
0001
⎛ 2049 ⎞
+ VREF ⎜
⎝ 4096 ⎟⎠
1000
0000
0000
⎛ + VREF ⎞
⎛ 2048 ⎞
= ⎜
+ VREF ⎜
⎝ 2 ⎟⎠
⎝ 4096 ⎟⎠
0111
0111
0111
⎛ 2047 ⎞
+ VREF ⎜
⎝ 4096 ⎟⎠
0000
0000
0001
⎛ 1 ⎞
+ VREF ⎜
⎝ 4096 ⎟⎠
0000
0000
0000
______________________________________________________________________________________
0
12-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
The GPIOs can sink and source current. The
MAX1257/MAX1258 GPIOA0–GPIOA3 can sink and
source up to 15mA. GPIOB0–GPIOB3 and GPIOC0–
GPIOC3 can sink 4mA and source 2mA. The MAX1220
GPIOA0 and GPIOA1 can sink and source up to 15mA.
The MAX1220 GPIOC0 and GPIOC1 can sink 4mA and
source 2mA. See Table 3.
Clock Modes
Internal Clock
The MAX1220/MAX1257/MAX1258 can operate from an
internal oscillator. The internal oscillator is active in
clock modes 00, 01, and 10. Figures 6, 7, and 8 show
how to start an ADC conversion in the three internally
timed conversion modes.
Read out the data at clock speeds up to 25MHz
through the SPI interface.
External Clock
Set CKSEL1 and CKSEL0 in the setup register to 11 to
set up the interface for external clock mode 11. See
Table 5. Pulse SCLK at speeds from 0.1MHz to
3.6MHz. Write to SCLK with a 40% to 60% duty cycle.
The SCLK frequency controls the conversion timing.
See Figures 9a and 9b for clock mode 11 timing. See
the ADC Conversions in Clock Mode 11 section.
ADC/DAC References
Address the reference through the setup register, bits 3
and 2. See Table 5. Following a wake-up delay, set
REFSEL[1:0] = 00 to program both the ADC and DAC
for internal reference use. Set REFSEL[1:0] = 10 to program the ADC for internal reference. Set REFSEL[1:0] =
10 to program the DAC for external reference, REF1.
When using REF1 or REF2/AIN_ in external-reference
mode, connect a 0.1µF capacitor to AGND. Set
REFSEL[1:0] = 01 to program the ADC and DAC for
external-reference mode. The DAC uses REF1 as its
external reference, while the ADC uses REF2 as its
external reference. Set REFSEL[1:0] = 11 to program
the ADC for external differential reference mode. REF1
is the positive reference and REF2 is the negative reference in the ADC external differential mode.
When REFSEL[1:0] = 00 or 10, REF2/AIN_ functions as
an analog input channel. When REFSEL[1:0] = 01 or 11,
REF2/AIN_ functions as the device’s negative reference.
Temperature Measurements
Issue a command byte setting bit 0 of the conversion
register to one to take a temperature measurement.
See Table 4. The MAX1220/MAX1257/MAX1258 perform
temperature measurements with an internal diode-connected transistor. The diode bias current changes from
68µA to 4µA to produce a temperature-dependent bias
voltage difference. The second conversion result at 4µA
is subtracted from the first at 68µA to calculate a digital
value that is proportional to absolute temperature. The
output data appearing at DOUT is the digital code
above, minus an offset to adjust from Kelvin to Celsius.
The reference voltage used for the temperature measurements is always derived from the internal reference
source to ensure that 1 LSB corresponds to 1/8 of a
degree Celsius. On every scan where a temperature
measurement is requested, the temperature conversion
is carried out first. The first 2 bytes of data read from
the FIFO contain the result of the temperature measurement. If another temperature measurement is performed before the first temperature result is read out,
the old measurement is overwritten by the new result.
Temperature results are in degrees Celsius (two’s complement). See the Applications Information section for
information on how to perform temperature measurements in each clock mode.
Register Descriptions
The MAX1220/MAX1257/MAX1258 communicate
between the internal registers and the external circuitry
through the SPI-compatible serial interface. Table 1
details the command byte, the registers, and the bit
Table 3. GPIO Maximum Sink/Source Current
CURRENT
MAX1257/MAX1258 (mA)
MAX1220 (mA)
GPIOA0–GPIOA3
GPIOB0–GPIOB3
GPIOC0–GPIOC3
GPIOA0, GPIOA1
GPIOC0, GPIOC1
Sink
15
4
4
15
4
Source
15
2
2
15
2
______________________________________________________________________________________
23
MAX1220/MAX1257/MAX1258
GPIOB3, and GPIOC0–GPIOC3. The MAX1220 includes
four GPIO channels (GPIOA0, GPIOA1, GPIOC0,
GPIOC1). Read and write to the GPIOs as detailed in
Table 1 and Tables 12–19. Also, see the GPIO Command
section. See Figures 11 and 12 for GPIO timing.
Write to the GPIOs by writing a command byte to the
GPIO command register. Write a single data byte to the
MAX1220 following the command byte. Write 2 bytes to
the MAX1257/MAX1258 following the command byte.
MAX1220/MAX1257/MAX1258
12-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
names. Tables 4–12 show the various functions within
the conversion register, setup register, unipolar-mode
register, bipolar-mode register, ADC averaging register, DAC select register, reset register, and GPIO command register, respectively.
Conversion Register
Select active analog input channels, scan modes, and
a single temperature measurement per scan by issuing
a command byte to the conversion register. Table 4
details channel selection, the four scan modes, and
how to request a temperature measurement. Start a
scan by writing to the conversion register when in clock
mode 10 or 11, or by applying a low pulse to the
CNVST pin when in clock mode 00 or 01. See Figures 6
and 7 for timing specifications for starting a scan with
CNVST.
A conversion is not performed if it is requested on a
channel or one of the channel pairs that has been configured as CNVST or REF2. For channels configured as
differential pairs, the CHSEL0 bit is ignored and the two
pins are treated as a single differential channel.
Select scan mode 00 or 01 to return one result per single-ended channel and one result per differential pair
within the selected scanning range (set by bits 2 and 1,
SCAN1 and SCAN0), plus one temperature result, if
selected. Select scan mode 10 to scan a single input
channel numerous times, depending on NSCAN1 and
NSCAN0 in the ADC averaging register (Table 9).
Select scan mode 11 to return only one result from a
single channel.
Setup Register
Issue a command byte to the setup register to configure the clock, reference, power-down modes, and ADC
single-ended/differential modes. Table 5 details the bits
in the setup-register command byte. Bits 5 and 4
(CKSEL1 and CKSEL0) control the clock mode, acquisition and sampling, and the conversion start. Bits 3
and 2 (REFSEL1 and REFSEL0) set the device for either
internal or external reference. Bits 1 and 0 (DIFFSEL1
and DIFFSEL0) address the ADC unipolar-mode and
bipolar-mode registers and configure the analog input
channels for differential operation.
24
Table 4. Conversion Register*
BIT
NAME
—
BIT
FUNCTION
7 (MSB)
Set to one to select conversion register.
CHSEL3
6
Analog-input channel select.
CHSEL2
5
Analog-input channel select.
CHSEL1
4
Analog-input channel select.
CHSEL0
3
Analog-input channel select.
SCAN1
2
Scan-mode select.
SCAN0
1
Scan-mode select.
TEMP
0 (LSB)
Set to one to take a single temperature measurement. The first
conversion result of a scan contains
temperature information.
*See below for bit details.
CHSEL3
CHSEL2
CHSEL1
CHSEL0
SELECTED
CHANNEL
(N)
0
0
0
0
AIN0
0
0
0
1
AIN1
0
0
1
0
AIN2
0
0
1
1
AIN3
0
1
0
0
AIN4
0
1
0
1
AIN5
0
1
1
0
AIN6
0
1
1
1
AIN7
1
0
0
0
AIN8
1
0
0
1
AIN9
1
0
1
0
AIN10
1
0
1
1
AIN11
1
1
0
0
AIN12
1
1
0
1
AIN13
1
1
1
0
AIN14
1
1
1
1
AIN15
SCAN MODE
(CHANNEL N IS SELECTED BY
BITS CHSEL3–CHSEL0)
SCAN1
SCAN0
0
0
Scans channels 0 through N.
0
1
Scans channels N through the highest
numbered channel.
1
0
Scans channel N repeatedly. The ADC
averaging register sets the number of
results.
1
1
No scan. Converts channel N once only.
______________________________________________________________________________________
12-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
BIT NAME
BIT
—
7 (MSB)
Set to zero to select setup register.
FUNCTION
—
6
Set to one to select setup register.
CKSEL1
5
Clock mode and CNVST configuration; resets to one at power-up.
CKSEL0
4
Clock mode and CNVST configuration.
REFSEL1
3
Reference-mode configuration.
REFSEL0
2
Reference-mode configuration.
DIFFSEL1
1
Unipolar-/bipolar-mode register configuration for differential mode.
DIFFSEL0
0 (LSB)
Unipolar-/bipolar-mode register configuration for differential mode.
*See below for bit details.
Table 5a. Clock Modes*
CKSEL1
CKSEL0
CONVERSION CLOCK
ACQUISITION/SAMPLING
CNVST CONFIGURATION
0
0
Internal
Internally timed.
CNVST
0
1
Internal
Externally timed by CNVST.
CNVST
1
0
Internal
Internally timed.
AIN15/AIN7
External (3.6MHz max)
Externally timed by SCLK.
AIN15/AIN7
1
1
*See the Clock Modes section.
Table 5b. Clock Modes 00, 01, and 10
REFSEL1 REFSEL0
VOLTAGE
REFERENCE
OVERRIDE
CONDITIONS
AIN
0
0
Internal (DAC
and ADC)
0
1
1
0
AIN
1
Internal reference required. There is a programmed
delay of 244 internal-conversion clock cycles for the
internal reference to settle after wake-up.
Internal reference not used.
Temperature
AIN
Default reference mode. Internal reference turns off
after scan is complete. If internal reference is turned
off, there is a programmed delay of 218 internalconversion clock cycles.
Temperature
1
Internal reference turns off after scan is complete. If
internal reference is turned off, there is a programmed
delay of 218 internal-conversion clock cycles.
Internal reference required. There is a programmed
delay of 244 internal-conversion clock cycles for the
internal reference to settle after wake-up.
Internal (ADC)
and external
REF1 (DAC)
External
differential
(ADC), external
REF1 (DAC)
REF2
CONFIGURATION
AIN14/AIN6
Temperature
External singleended (REF1
for DAC and
REF2 for ADC)
AUTOSHUTDOWN
AIN
Temperature
REF2
AIN14/AIN6
Internal reference required. There is a programmed
delay of 244 internal-conversion clock cycles for the
internal reference to settle after wake-up.
Internal reference not used.
Internal reference required. There is a programmed
delay of 244 internal-conversion clock cycles for the
internal reference to settle after wake-up.
REF2
______________________________________________________________________________________
25
MAX1220/MAX1257/MAX1258
Table 5. Setup Register*
MAX1220/MAX1257/MAX1258
12-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
The ADC reference is always on if any of the following
conditions are true:
3) At least one DAC is powered down through the
100kΩ to VREF and REFSEL[1:0] = 00.
1) The FBGON bit is set to one in the reset register.
2) At least one DAC output is powered up and
REFSEL[1:0] (in the setup register) = 00.
If any of the above conditions exist, the ADC reference
is always on, but there is a 188 clock-cycle delay
before temperature-sensor measurements begin, if
requested.
Table 5c. Clock Mode 11
REFSEL1 REFSEL0
0
0
VOLTAGE
REFERENCE
OVERRIDE
CONDITIONS
AIN
Internal reference turns off after scan is complete. If
internal reference is turned off, there is a programmed
delay of 218 external conversion clock cycles.
Temperature
Internal reference required. There is a programmed
delay of 244 external conversion clock cycles for the
internal reference. Temperature-sensor output appears
at DOUT after 188 further external clock cycles.
Internal (DAC
and ADC)
AIN
0
1
1
0
External singleended (REF1
for DAC and
REF2 for ADC)
Temperature
AIN
Default reference mode. Internal reference turns off
after scan is complete. If internal reference is turned
off, there is a programmed delay of 218 external
conversion clock cycles.
Temperature
Internal reference required. There is a programmed
delay of 244 external conversion clock cycles for the
internal reference. Temperature-sensor output appears
at DOUT after 188 further external clock cycles.
1
AIN14/AIN6
REF2
AIN14/AIN6
AIN
1
REF2
CONFIGURATION
Internal reference not used.
Internal reference required. There is a programmed
delay of 244 external conversion clock cycles for the
internal reference. Temperature-sensor output appears
at DOUT after 188 further external clock cycles.
Internal (ADC)
and external
REF1 (DAC)
External
differential
(ADC), external
REF1 (DAC)
AUTOSHUTDOWN
Temperature
Internal reference not used.
Internal reference required. There is a programmed
delay of 244 external conversion clock cycles for the
internal reference. Temperature-sensor output appears
at DOUT after 188 further external clock cycles.
REF2
Table 5d. Differential Select Modes
DIFFSEL1 DIFFSEL0
26
FUNCTION
0
0
No data follows the command setup byte. Unipolar-mode and bipolar-mode registers remain unchanged.
0
1
No data follows the command setup byte. Unipolar-mode and bipolar-mode registers remain unchanged.
1
0
1 byte of data follows the command setup byte and is written to the unipolar-mode register.
1
1
1 byte of data follows the command setup byte and is written to the bipolar-mode register.
______________________________________________________________________________________
12-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
BIT NAME
BIT
UCH0/1
7 (MSB)
Configure AIN0 and AIN1 for unipolar differential conversion.
FUNCTION
UCH2/3
6
Configure AIN2 and AIN3 for unipolar differential conversion.
UCH4/5
5
Configure AIN4 and AIN5 for unipolar differential conversion.
UCH6/7
4
Configure AIN6 and AIN7 for unipolar differential conversion.
UCH8/9
3
Configure AIN8 and AIN9 for unipolar differential conversion.
UCH10/11
2
Configure AIN10 and AIN11 for unipolar differential conversion.
UCH12/13
1
Configure AIN12 and AIN13 for unipolar differential conversion.
UCH14/15
0 (LSB)
Configure AIN14 and AIN15 for unipolar differential conversion.
Table 7. Bipolar-Mode Register (Addressed Through the Setup Register)
BIT NAME
BIT
FUNCTION
BCH0/1
7 (MSB)
Set to one to configure AIN0 and AIN1 for bipolar differential conversion. Set the corresponding bits
in the unipolar-mode and bipolar-mode registers to zero to configure AIN0 and AIN1 for unipolar
single-ended conversion.
BCH2/3
6
Set to one to configure AIN2 and AIN3 for bipolar differential conversion. Set the corresponding bits
in the unipolar-mode and bipolar-mode registers to zero to configure AIN2 and AIN3 for unipolar
single-ended conversion.
BCH4/5
5
Set to one to configure AIN4 and AIN5 for bipolar differential conversion. Set the corresponding bits
in the unipolar-mode and bipolar-mode registers to zero to configure AIN4 and AIN5 for unipolar
single-ended conversion.
BCH6/7
4
Set to one to configure AIN6 and AIN7 for bipolar differential conversion. Set the corresponding bits
in the unipolar-mode and bipolar-mode registers to zero to configure AIN6 and AIN7 for unipolar
single-ended conversion.
BCH8/9
3
Set to one to configure AIN8 and AIN9 for bipolar differential conversion. Set the corresponding bits
in the unipolar-mode and bipolar-mode registers to zero to configure AIN8 and AIN9 for unipolar
single-ended conversion.
BCH10/11
2
Set to one to configure AIN10 and AIN11 for bipolar differential conversion. Set the corresponding
bits in the unipolar-mode and bipolar-mode registers to zero to configure AIN10 and AIN11 for
unipolar single-ended conversion.
BCH12/13
1
Set to one to configure AIN12 and AIN13 for bipolar differential conversion. Set the corresponding
bits in the unipolar-mode and bipolar-mode registers to zero to configure AIN12 and AIN13 for
unipolar single-ended conversion.
BCH14/15
0 (LSB)
Set to one to configure AIN14 and AIN15 for bipolar differential conversion. Set the corresponding
bits in the unipolar-mode and bipolar-mode registers to zero to configure AIN14 and AIN15 for
unipolar single-ended conversion.
______________________________________________________________________________________
27
MAX1220/MAX1257/MAX1258
Table 6. Unipolar-Mode Register (Addressed Through the Setup Register)
MAX1220/MAX1257/MAX1258
12-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
Unipolar/Bipolar Registers
The final 2 bits (LSBs) of the setup register control the
unipolar-/bipolar-mode address registers. Set
DIFFSEL[1:0] = 10 to write to the unipolar-mode register. Set bits DIFFSEL[1:0] = 11 to write to the bipolarmode register. In both cases, the setup command byte
must be followed by 1 byte of data that is written to the
unipolar-mode register or bipolar-mode register. Hold
CS low and run 16 SCLK cycles before pulling CS high.
Table 8. Unipolar/Bipolar Channel Function
UNIPOLARMODE
REGISTER BIT
BIPOLAR-MODE
REGISTER BIT
CHANNEL PAIR
FUNCTION
0
0
Unipolar single-ended
0
1
Bipolar differential
1
0
Unipolar differential
1
1
Unipolar differential
If the last 2 bits of the setup register are 00 or 01, neither the unipolar-mode register nor the bipolar-mode
register is written. Any subsequent byte is recognized
as a new command byte. See Tables 6, 7, and 8 to program the unipolar- and bipolar-mode registers.
Both registers power up at all zeros to set the inputs as
16 unipolar single-ended channels. To configure a
channel pair as single-ended unipolar, bipolar differential, or unipolar differential, see Table 8.
In unipolar mode, AIN+ can exceed AIN- by up to
VREF. The output format in unipolar mode is binary. In
bipolar mode, either input can exceed the other by up
to VREF / 2. The output format in bipolar mode is two’s
complement (see the ADC Transfer Functions section).
ADC Averaging Register
Write a command byte to the ADC averaging register to
configure the ADC to average up to 32 samples for
each requested result, and to independently control the
number of results requested for single-channel scans.
Table 9. ADC Averaging Register*
BIT NAME
BIT
—
7 (MSB)
Set to zero to select ADC averaging register.
FUNCTION
—
6
Set to zero to select ADC averaging register.
—
5
Set to one to select ADC averaging register.
AVGON
4
Set to one to turn averaging on. Set to zero to turn averaging off.
NAVG1
3
Configures the number of conversions for single-channel scans.
NAVG0
2
Configures the number of conversions for single-channel scans.
NSCAN1
1
Single-channel scan count. (Scan mode 10 only.)
NSCAN0
0 (LSB)
Single-channel scan count. (Scan mode 10 only.)
*See below for bit details.
FUNCTION
AVGON
NAVG1
NAVG0
0
X
X
Performs one conversion for each requested result.
1
0
0
Performs four conversions and returns the average for each requested result.
1
0
1
Performs eight conversions and returns the average for each requested result.
1
1
0
Performs 16 conversions and returns the average for each requested result.
1
1
1
Performs 32 conversions and returns the average for each requested result.
28
NSCAN1
NSCAN0
0
0
Scans channel N and returns four results.
FUNCTION (APPLIES ONLY IF SCAN MODE 10 IS SELECTED)
0
1
Scans channel N and returns eight results.
1
0
Scans channel N and returns 12 results.
1
1
Scans channel N and returns 16 results.
______________________________________________________________________________________
12-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
DAC Select Register
Write a command byte 0001XXXX to the DAC select
register (as shown in Table 10) to set up the DAC interface and indicate that another word will follow. The last
4 bits of the DAC select register are don’t-care bits. The
word that follows the DAC select-register command
Table 10. DAC Select Register
BIT
NAME
—
BIT
FUNCTION
byte controls the DAC serial interface. See Table 20
and the DAC Serial Interface section.
Reset Register
Write to the reset register (as shown in Table 11) to
clear the FIFO or reset all registers (excluding the DAC
and GPIO registers) to their default states. When the
RESET bit in the reset register is set to 0, the FIFO is
cleared. Set the RESET bit to one to return all the
device registers to their default power-up state. All registers power up in state 00000000, except for the setup
register that powers up in clock mode 10 (CKSEL1 = 1
and REFSEL1 = 1). The DAC and GPIO registers are
not reset by writing to the reset register. Set the SLOW
bit to one to add a 15ns delay in the DOUT signal path
to provide a longer hold time. Writing a one to the
SLOW bit also clears the contents of the FIFO. Set the
FBGON bit to one to force the bias block and bandgap
reference to power up regardless of the state of the
DAC and activity of the ADC block. Setting the FBGON
bit high also removes the programmed wake-up delay
between conversions in clock modes 01 and 11.
Setting the FBGON bit high also clears the FIFO.
7 (MSB) Set to zero to select DAC select register.
—
6
Set to zero to select DAC select register.
—
5
Set to zero to select DAC select register.
—
4
Set to one to select DAC select register.
X
3
Don’t care.
X
2
Don’t care.
X
1
Don’t care.
BIT NAME
BIT
FUNCTION
Don’t care.
—
7 (MSB)
Set to zero to select GPIO register.
—
6
Set to zero to select GPIO register.
—
5
Set to zero to select GPIO register.
—
4
Set to zero to select GPIO register.
—
3
Set to zero to select GPIO register.
—
2
Set to zero to select GPIO register.
GPIOSEL1
1
GPIO configuration bit.
GPIOSEL2
0 (LSB)
GPIOSEL1
GPIOSEL2
1
1
GPIO configuration; written data is
entered in the GPIO configuration
register.
1
0
GPIO write; written data is entered
in the GPIO write register.
0
1
GPIO read; the next 8/16 SCLK
cycles transfer the state of all GPIO
drivers into DOUT.
X
0
Table 12. GPIO Command Register
Table 11. Reset Register
BIT
NAME
—
BIT
FUNCTION
7 (MSB) Set to zero to select ADC reset register.
—
6
Set to zero to select ADC reset register.
—
5
Set to zero to select ADC reset register.
—
4
Set to zero to select ADC reset register.
—
3
Set to one to select ADC reset register.
RESET
SLOW
FBGON
2
1
0 (LSB)
Set to zero to clear the FIFO only. Set to
one to set the device in its power-on
condition.
Set to one to turn on slow mode.
Set to one to force internal bias block and
bandgap reference to be always powered
up.
GPIO write bit.
FUNCTION
______________________________________________________________________________________
29
MAX1220/MAX1257/MAX1258
Table 9 details the four scan modes available in the
ADC conversion register. All four scan modes allow
averaging as long as the AVGON bit, bit 4 in the
averaging register, is set to 1. Select scan mode 10 to
scan the same channel multiple times. Clock mode 11
disables averaging. For example, if AVGON = 1,
NAVG[1:0] = 00, NSCAN[1:0] = 11, and SCAN[1:0] =
10, 16 results are written to the FIFO, with each result
being the average of four conversions of channel N.
GPIO Command
Write a command byte to the GPIO command register
to configure, write, or read the GPIOs, as detailed in
Table 12.
Write the command byte 00000011 to configure the
GPIOs. The eight SCLK cycles following the command
byte load data from DIN to the GPIO configuration register in the MAX1220. The 16 SCLK cycles following the
command byte load data from DIN to the GPIO configu-
ration register in the MAX1257/MAX1258. See Tables
13 and 14. The register bits are updated after the last
CS rising edge. All GPIOs default to inputs upon powerup.
The data in the register controls the function of each
GPIO, as shown in Tables 13–19.
Table 13. MAX1220 GPIO Configuration
DATA PIN
GPIO COMMAND BYTE
DATA BYTE
DIN
0
0
0
0
0
0
1
1
GPIOC1
GPIOC0
GPIOA1
GPIOA0
X
X
X
X
DOUT
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Table 14. MAX1257/MAX1258 GPIO Configuration
0
0
0
0
0
0
1
1
GPIOB3
GPIOB2
GPIOB1
GPIOB0
GPIOA3
GPIOA2
GPIOA1
DOUT
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
GPIOA0
DIN
GPIOC0
DATA BYTE 2
GPIOC1
DATA BYTE 1
GPIOC2
GPIO COMMAND BYTE
GPIOC3
DATA PIN
X
X
X
X
0
0
0
0
0
Table 15. MAX1220 GPIO Write
DATA PIN
GPIO COMMAND BYTE
DATA BYTE
DIN
0
0
0
0
0
0
1
0
GPIOC1
GPIOC0
GPIOA1
GPIOA0
X
X
X
X
DOUT
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Table 16. MAX1257/MAX1258 GPIO Write
0
0
0
0
0
0
1
0
GPIOB2
GPIOB1
GPIOB0
GPIOA3
GPIOA2
GPIOA1
DOUT
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
30
GPIOA0
DIN
GPIOB3
DATA BYTE 2
GPIOC0
DATA BYTE 1
GPIOC1
GPIO COMMAND BYTE
GPIOC2
DATA PIN
GPIOC3
MAX1220/MAX1257/MAX1258
12-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
X
X
X
X
0
0
0
0
0
______________________________________________________________________________________
12-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
GPIO Read
Write the command byte 00000001 to indicate a GPIO
read operation. The eight SCLK cycles following the
command byte transfer the state of the GPIOs to DOUT
in the MAX1220. The 16 SCLK cycles following the command byte transfer the state of the GPIOs to DOUT in the
MAX1257/MAX1258. See Tables 18 and 19.
DAC Serial Interface
Write a command byte 0001XXXX to the DAC select
register to indicate the word to follow is written to the
DAC serial interface, as detailed in Tables 1, 10, 20, and
21. Write the next 16 bits to the DAC interface register,
as shown in Tables 20 and 21. Following the high-to-low
transition of CS, the data is shifted synchronously and
latched into the input register on each falling edge of
SCLK. Each word is 16 bits. The first 4 bits are the control bits followed by 12 data bits (MSB first) and 2 don’tcare sub-bits. See Figures 10–12 for DAC timing
specifications.
Table 17. GPIO-Mode Control
CONFIGURATION
BIT
WRITE
BIT
OUTPUT
STATE
GPIO
FUNCTION
1
1
1
Output
1
0
0
Output
0
1
Three-state
Input
0
0
0
Pulldown
(open drain)
Table 18. MAX1220 GPIO Read
DATA PIN
GPIO COMMAND BYTE
DATA BYTE
DIN
0
0
0
0
0
0
0
1
X
X
X
X
X
X
X
X
DOUT
0
0
0
0
0
0
0
0
0
0
0
0
GPIOC1
GPIOC0
GPIOA1
GPIOA0
Table 19. MAX1257/MAX1258 GPIO Read
DIN
0
0
0
0
0
0
0
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
DOUT
0
0
0
0
0
0
0
0
0
0
0
0
GPIOC0
GPIOB3
GPIOB2
GPIOB1
GPIOB0
GPIOA3
GPIOA2
GPIOA1
GPIOA0
DATA BYTE 2
GPIOC1
DATA BYTE 1
GPIOC2
GPIO COMMAND BYTE
GPIOC3
DATA PIN
______________________________________________________________________________________
31
MAX1220/MAX1257/MAX1258
GPIO Write
Write the command byte 00000010 to indicate a GPIO
write operation. The eight SCLK cycles following the
command byte load data from DIN into the GPIO write
register in the MAX1220. The 16 SCLK cycles following
the command byte load data from DIN into the GPIO
write register in the MAX1257/MAX1258. See Tables 15
and 16. The register bits are updated after the last CS
rising edge.
Table 20. DAC Serial-Interface Configuration
16-BIT SERIAL WORD
MSB
LSB
CONTROL
BITS
DESCRIPTION
DATA BITS
FUNCTION
C3 C2 C1 C0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
0
0
0
0
X
X
X
X
X
X
X
X
X
X
X
X
NOP
No operation.
X
X
X
X
X
X
X
X
X
RESET
0
0
0
1
1
X
1
X
X
X
X
X
X
X
X
X
Pull-High
Preset all internal registers to FFFh and
leave output buffers in their present state.
0
0
1
0
—
—
—
—
—
—
—
—
—
—
—
—
DAC0
D11–D0 to input register 0,
DAC output unchanged.
0
0
1
1
—
—
—
—
—
—
—
—
—
—
—
—
DAC1
D11–D0 to input register 1,
DAC output unchanged.
0
1
0
0
—
—
—
—
—
—
—
—
—
—
—
—
DAC2
D11–D0 to input register 2,
DAC output unchanged.
0
1
0
1
—
—
—
—
—
—
—
—
—
—
—
—
DAC3
D11–D0 to input register 3,
DAC output unchanged.
0
1
1
0
—
—
—
—
—
—
—
—
—
—
—
—
DAC4
D11–D0 to input register 4,
DAC output unchanged.
0
1
1
1
—
—
—
—
—
—
—
—
—
—
—
—
DAC5
D11–D0 to input register 5,
DAC output unchanged.
1
0
0
0
—
—
—
—
—
—
—
—
—
—
—
—
DAC6
D11–D0 to input register 6,
DAC output unchanged.
1
0
0
1
—
—
—
—
—
—
—
—
—
—
—
—
DAC7
D11–D0 to input register 7,
DAC output unchanged.
1
0
1
0
—
—
—
—
—
—
—
—
—
—
—
—
DAC0–DAC3
D11–D0 to input registers 0–3 and DAC
registers 0–3. DAC outputs updated
(write-through).
1
0
1
1
—
—
—
—
—
—
—
—
—
—
—
—
DAC4–DAC7
D11–D0 to input registers 4–7 and DAC
registers 4–7. DAC outputs updated
(write-through).
1
1
0
0
—
—
—
—
—
—
—
—
—
—
—
—
DAC0–DAC7
D11–D0 to input registers 0–7 and DAC
registers 0–7. DAC outputs updated
(write-through).
1
1
0
1
—
—
—
—
—
—
—
—
—
—
—
—
DAC0–DAC7
D11–D0 to input registers 0–7.
DAC outputs unchanged.
DAC0–DAC7
Input registers to DAC registers indicated
by ones, DAC outputs updated,
equivalent to software LDAC.
(No effect on DACs indicated by zeros.)
1
32
1
1
0
DAC0
0
DAC1
X
DAC2
0
DAC3
1
DAC4
0
DAC5
0
DAC6
0
Reset all internal registers to 000h and
leave output buffers in their present state.
DAC7
MAX1220/MAX1257/MAX1258
12-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
X
X
X
X
______________________________________________________________________________________
12-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
CONTROL
BITS
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
DAC0
DAC1
DAC2
DAC3
DAC4
DAC5
DAC6
DAC7
C3 C2 C1 C0
DATA BITS
DESCRIPTION
FUNCTION
D3 D2 D1 D0
— — — — — — — — 0
— — — — — — — — 0
— — — — — — — — 1
— — — — — — — — 0
— — — — — — — — 1
0
1
0
0
1
1
0
0
0
1
X
Power-Up
Power up individual DAC buffers indicated by data
in DAC0 through DAC7. A one indicates the DAC
output is connected and active. A zero does not
affect the DAC’s present state.
X
Power down individual DAC buffers indicated by
data in DAC0 through DAC7. A one indicates the
Power-Down 1
DAC output is disconnected and high impedance.
A zero does not affect the DAC’s present state.
X
Power down individual DAC buffers indicated by
data in DAC0 through DAC7. A one indicates the
Power-Down 2 DAC output is disconnected and pulled to AGND
with a 1kΩ resistor. A zero does not affect the DAC’s
present state.
X
Power down individual DAC buffers indicated by
data in DAC0 through DAC7. A one indicates the
Power-Down 3 DAC output is disconnected and pulled to AGND
with a 100kΩ resistor. A zero does not affect the
DAC’s present state.
X
Power down individual DAC buffers indicated by
data in DAC0 through DAC7. A one indicates the
Power-Down 4 DAC output is disconnected and pulled to REF1 with
a 100kΩ resistor. A zero does not affect the DAC’s
present state.
If CS goes high prior to completing 16 SCLK cycles, the
command is discarded. To initiate a new transfer, drive
CS low again.
For example, writing the DAC serial interface word 1111
0000 and 1111 0100 disconnects DAC outputs 4
through 7 and forces them to a high-impedance state.
DAC outputs 0 through 3 remain in their previous state.
Output-Data Format
Figures 6–9 illustrate the conversion timing for the
MAX1220/MAX1257/MAX1258. All 12-bit conversion
results are output in 2-byte format, MSB first, with four
leading zeros. Data appears on DOUT on the falling
edges of SCLK. Data is binary for unipolar mode and
two’s complement for bipolar mode and temperature
results. See Figures 3, 4, and 5 for input/output and
temperature-transfer functions.
ADC Transfer Functions
Figure 3 shows the unipolar transfer function for singleended or differential inputs. Figure 4 shows the bipolar
transfer function for differential inputs. Code transitions
occur halfway between successive-integer LSB values.
Output coding is binary, with 1 LSB = V REF1 /4096
(MAX1257) and 1 LSB = V REF1 /4096 (MAX1220/
MAX1258) for unipolar and bipolar operation, and 1
LSB = +0.125°C for temperature measurements.
Bipolar true-differential results and temperature-sensor
______________________________________________________________________________________
33
MAX1220/MAX1257/MAX1258
Table 21. DAC Power-Up and Power-Down Commands
Partial Reads and Partial Writes
If the 1st byte of an entry in the FIFO is partially read
(CS is pulled high after fewer than eight SCLK cycles),
the remaining bits are lost for that byte. The next byte of
data that is read out contains the next 8 bits. If the first
byte of an entry in the FIFO is read out fully, but the
second byte is read out partially, the rest of that byte is
lost. The remaining data in the FIFO is unaffected and
can be read out normally after taking CS low again, as
long as the 4 leading bits (normally zeros) are ignored.
If CS is pulled low before EOC goes low, a conversion
may not be completed and the FIFO data may not be
correct. Incorrect writes (pulling CS high before completing eight SCLK cycles) are ignored and the register
remains unchanged.
Applications Information
Internally Timed Acquisitions and
Conversions Using CNVST
ADC Conversions in Clock Mode 00
In clock mode 00, the wake-up, acquisition, conversion,
and shutdown sequence is initiated through CNVST
and performed automatically using the internal oscillator. Results are added to the internal FIFO to be read
out later. See Figure 6 for clock mode 00 timing after a
command byte is issued. See Table 5 for details on
programming the clock mode in the setup register.
Initiate a scan by setting CNVST low for at least 40ns
before pulling it high again. The MAX1220/MAX1257/
MAX1258 then wake up, scan all requested channels,
store the results in the FIFO, and shut down. After the
VREF = VREF+ - VREFVREF
VREF
011....111
OFFSET BINARY OUTPUT CODE (LSB)
results are available in two’s complement format, while
all others are in binary. See Tables 6, 7, and 8 for
details on which setting (unipolar or bipolar) takes
precedence.
In unipolar mode, AIN+ can exceed AIN- by up to
VREF1. In bipolar mode, either input can exceed the
other by up to VREF1/2.
011....110
011....101
FS = VREF/2 + VCOM
ZS = COM
-FS = -VREF/2
VREF
1 LSB = VREF/4096
000....001
000....000
(COM)
111....111
VREF
100....011
100....010
100....001
100....000
-FS
-1 0 +1
(COM)
INPUT VOLTAGE (LSB)
+FS - 1 LSB
Figure 4. Bipolar Transfer Function—Full Scale (±FS) = ±VREF/2
OUTPUT CODE
FULL-SCALE
TRANSITION
111....111
OFFSET BINARY OUTPUT CODE (LSB)
MAX1220/MAX1257/MAX1258
12-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
111....110
FS = VREF
111....101
1 LSB = VREF/4096
011....111
011....110
000....010
000....001
000....000
111....111
000....011
111....110
111....101
000....010
000....001
000....000
0 1 2 3
FS
100....001
100....000
INPUT VOLTAGE (LSB)
FS - 3/2 LSB
Figure 3. Unipolar Transfer Function—Full Scale (FS) = VREF
34
-256
0
TEMPERATURE (°C)
Figure 5. Temperature Transfer Function
______________________________________________________________________________________
+255.5
12-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
MAX1220/MAX1257/MAX1258
CNVST
(UP TO 514 INTERNALLY CLOCKED ACQUISITIONS AND CONVERSIONS)
CS
SCLK
DOUT
MSB1
LSB1
MSB2
tRDS
EOC
Figure 6. Clock Mode 00—After writing a command byte, set CNVST low for at least 40ns to begin a conversion.
tCSW
CNVST
(CONVERSION 2)
(ACQUISITION 1)
(ACQUISITION 2)
CS
tDOV
SCLK
(CONVERSION 1)
DOUT
MSB1
LSB1
MSB2
EOC
Figure 7. Clock Mode 01—After writing a command byte, request multiple conversions by setting CNVST low for each conversion.
scan is complete, EOC is pulled low and the results are
available in the FIFO. Wait until EOC goes low before
pulling CS low to communicate with the serial interface.
EOC stays low until CS or CNVST is pulled low again. A
temperature-conversion result, if requested, precedes
all other FIFO results.
Do not issue a second CNVST signal before EOC goes
low; otherwise, the FIFO can be corrupted. Wait until all
conversions are complete before reading the FIFO. SPI
communications to the DAC and GPIO registers are permitted during conversion. However, coupled noise may
result in degraded ADC signal-to-noise ratio (SNR).
Externally Timed Acquisitions and
Internally Timed Conversions with CNVST
ADC Conversions in Clock Mode 01
In clock mode 01, conversions are requested one at a
time using CNVST and performed automatically using
the internal oscillator. See Figure 7 for clock mode 01
timing after a command byte is issued.
Setting CNVST low begins an acquisition, wakes up the
ADC, and places it in track mode. Hold CNVST low for
at least 1.4µs to complete the acquisition. If reference
mode 00 or 10 is selected, an additional 45µs is
required for the internal reference to power up. If a temperature measurement is being requested, reference
power-up and temperature measurement is internally
timed. In this case, hold CNVST low for at least 40ns.
______________________________________________________________________________________
35
MAX1220/MAX1257/MAX1258
12-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
CONVERSION BYTE
DIN
(UP TO 514 INTERNALLY CLOCKED ACQUISITIONS AND CONVERSIONS)
CS
SCLK
DOUT
tDOV
MSB1
LSB1
MSB2
EOC
Figure 8. Clock Mode 10—The command byte to the conversion register begins the acquisition (CNVST is not required).
Set CNVST high to begin a conversion. Sampling is
completed approximately 500ns after CNVST goes
high. After the conversion is complete, the ADC shuts
down and pulls EOC low. EOC stays low until CS or
CNVST is pulled low again. Wait until EOC goes low
before pulling CS or CNVST low. The number of CNVST
signals must equal the number of conversions requested by the scan and averaging registers to correctly
update the FIFO. Wait until all conversions are complete before reading the FIFO. SPI communications to
the DAC and GPIO registers are permitted during
conversion. However, coupled noise may result in
degraded ADC SNR.
If averaging is turned on, multiple CNVST pulses need to
be performed before a result is written to the FIFO. Once
the proper number of conversions has been performed
to generate an averaged FIFO result (as specified to the
averaging register), the scan logic automatically switches the analog input multiplexer to the next requested
channel. If a temperature measurement is programmed,
it is performed after the first rising edge of CNVST following the command byte written to the conversion register.
The temperature-conversion result is available on DOUT
once EOC has been pulled low.
Internally Timed Acquisitions and
Conversions Using the Serial Interface
ADC Conversions in Clock Mode 10
In clock mode 10, the wake-up, acquisition, conversion,
and shutdown sequence is initiated by writing a command byte to the conversion register, and is performed
automatically using the internal oscillator. This is the
default clock mode upon power-up. See Figure 8 for
clock mode 10 timing.
36
Initiate a scan by writing a command byte to the conversion register. The MAX1220/MAX1257/MAX1258 then
power up, scan all requested channels, store the results
in the FIFO, and shut down. After the scan is complete,
EOC is pulled low and the results are available in the
FIFO. If a temperature measurement is requested, the
temperature result precedes all other FIFO results. EOC
stays low until CS is pulled low again. Wait until all conversions are complete before reading the FIFO. SPI
communications to the DAC and GPIO registers are permitted during conversion. However, coupled noise may
result in degraded ADC SNR.
Externally Clocked Acquisitions and
Conversions Using the Serial Interface
ADC Conversions in Clock Mode 11
In clock mode 11, acquisitions and conversions are initiated by writing a command byte to the conversion
register and are performed one at a time using SCLK
as the conversion clock. Scanning, averaging and the
FIFO are disabled, and the conversion result is available at DOUT during the conversion. Output data is
updated on the rising edge of SCLK in clock mode 11.
See Figures 9a and 9b for clock mode 11 timing.
Initiate a conversion by writing a command byte to the
conversion register followed by 16 SCLK cycles. If CS
is pulsed high between the eighth and ninth cycles, the
pulse width must be less than 100µs. To continuously
convert at 16 cycles per conversion, alternate 1 byte of
zeros (NOP byte) between each conversion byte. If 2
NOP bytes follow a conversion byte, the analog cells
power down at the end of the second NOP. Set the
FBGON bit to one in the reset register to keep the internal bias block powered.
______________________________________________________________________________________
12-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
NOP
CONVERSION BYTE #2
NOP
CONVERSION
ACQUISITION #1
CONVERSION #1
ACQUISITION #2
CONVERSION #2
CS
SCLK
DOUT
MSB1
LSB1
MSB2
EOC
Figure 9a. Clock Mode 11—Externally Timed Acquisition, Sampling and Conversion without CNVST for Maximum ADC Throughput
CONVERSION BYTE
NOP
NOP
DIN
ACQUISITION
CONVERSION
CS
SCLK
DOUT
MSB1
LSB1
EOC
Figure 9b. Clock Mode 11—Externally Timed Acquisition, Sampling and Conversion without CNVST to Reduce Analog Power
Dissipation
If reference mode 00 is requested, or if an external reference is selected but a temperature measurement is
being requested, wait 45µs with CS high after writing
the conversion byte to extend the acquisition and allow
the internal reference to power up. To perform a temperature measurement, write 24 bytes (192 cycles) of
zeros after the conversion byte using 8-bit NOP commands each framed by CS (to match production test
method; other length NOP sequences are not production tested). The temperature result appears on DOUT
during the last 2 bytes of the 192 cycles. For temperature conversion in clock mode 11 with the TEMP bit set
in the conversion register, no scanning of AIN0 to
AIN15 is performed. Therefore, the CHSEL[3:0] bits are
don’t cares. These bits can be set to 0000b. When the
conversion is complete, only the temperature data is
available.
Conversion-Time Calculations
The conversion time for each scan is based on a number of different factors: conversion time per sample,
samples per result, results per scan, if a temperature
measurement is requested, and if the external reference is in use. Use the following formula to calculate
the total conversion time for an internally timed conver-
sion in clock mode 00 and 10 (see the Electrical
Characteristics, as applicable):
Total conversion time =
tCONV x nAVG x nSCAN + tTS + tINT-REF,SU
where:
tCONV = tDOV, where tDOV is dependent on the clock
mode and the reference mode selected
nAVG = samples per result (amount of averaging)
nSCAN = number of times each channel is scanned; set
to one unless [SCAN1, SCAN0] = 10
t TS = time required for temperature measurement
(53.1µs); set to zero if temperature measurement is not
requested
tINT-REF,SU = tWU (external-reference wake-up); if a
conversion using the external reference is requested
In clock mode 01, the total conversion time depends on
how long CNVST is held low or high. Conversion time in
externally clocked mode (CKSEL1, CKSEL0 = 11)
depends on the SCLK period and how long CS is held
high between each set of eight SCLK cycles. In clock
mode 01, the total conversion time does not include the
time required to turn on the internal reference.
______________________________________________________________________________________
37
MAX1220/MAX1257/MAX1258
CONVERSION BYTE #1
DIN
MAX1220/MAX1257/MAX1258
12-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
tCL
SCLK
1
tDS
2
3
Dn-3
Dn-2
Dn-4
Dn-5
D1
D0
tDOT
tDOE
D15
D7
DOUT
32
16
8
5
4
tDH
Dn-1
DIN
tCH
D14
D6
D13
D5
tDOD
D12
D4
D1
D0
tCSS
tCSPWH
tCSH
CS
NOTE: FOR THE MAX1220 GPIO WRITES, n = 16; FOR ALL DAC WRITES AND GPIO WRITES ON THE MAX1257/MAX1258, n = 24.
Figure 10. DAC/GPIO Serial-Interface Timing (Clock Modes 00, 01, and 10)
DAC/GPIO Timing
Figures 10–13 detail the timing diagrams for writing to
the DAC and GPIOs. Figure 10 shows the timing specifications for clock modes 00, 01, and 10. Figure 11
shows the timing specifications for clock mode 11.
Figure 12 details the timing specifications for the DAC
input select register and 2 bytes to follow. Output data
38
is updated on the rising edge of SCLK in clock mode
11. Figure 13 shows the GPIO timing. Figure 14 shows
the timing details of a hardware LDAC command DACregister update. For a software-command DAC-register
update, tS is valid from the rising edge of CS, which follows the last data bit in the software command word.
______________________________________________________________________________________
12-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
MAX1220/MAX1257/MAX1258
tCH
tCL
SCLK
1
2
3
32
16
8
5
4
tDH
tDS
Dn-1
DIN
Dn-2
Dn-3
Dn-4
D1
Dn-5
D0
tDOT
tDOE
D15
D7
DOUT
D14
D6
tDOD
D13
D5
D12
D4
D1
D0
tCSS
tCSPWH
tCSH
CS
NOTE: FOR THE MAX1220 GPIO WRITES, n = 16; FOR ALL DAC WRITES AND GPIO WRITES ON THE MAX1257/MAX1258, n = 24.
Figure 11. DAC/GPIO Serial-Interface Timing (Clock Mode 11)
SCLK
DIN
1
2
BIT 7 (MSB)
8
BIT 6
BIT 0 (LSB)
10
9
BIT 15
BIT 14
24
BIT 1
BIT 0
DOUT
THE COMMAND BYTE
INITIALIZES THE DAC SELECT
REGISTER
THE NEXT 16 BITS SELECT THE DAC
AND THE DATA WRITTEN TO IT
CS
Figure 12. DAC-Select Register Byte and DAC Serial-Interface Word
______________________________________________________________________________________
39
MAX1220/MAX1257/MAX1258
12-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
CS
tGOD
tGSU
GPIO INPUT/OUTPUT
Figure 13. GPIO Timing
tLDACPWL
LDAC
tS
±1 LSB
OUT_
Figure 14. LDAC Functionality
LDAC Functionality
Drive LDAC low to transfer the content of the input registers to the DAC registers. Drive LDAC permanently
low to make the DAC register transparent. The DAC
output typically settles from zero to full scale within ±1
LSB after 2µs. See Figure 14.
Layout, Grounding, and Bypassing
For best performance, use PC boards. Ensure that digital and analog signal lines are separated from each
other. Do not run analog and digital signals parallel to
one another (especially clock signals) or do not run digital lines underneath the MAX1220/MAX1257/
MAX1258 package. High-frequency noise in the AVDD
power supply may affect performance. Bypass the
AVDD supply with a 0.1µF capacitor to AGND, close to
the AVDD pin. Bypass the DVDD supply with a 0.1µF
capacitor to DGND, close to the DVDD pin. Minimize
capacitor lead lengths for best supply-noise rejection. If
the power supply is very noisy, connect a 10Ω resistor in
series with the supply to improve power-supply filtering.
40
The MAX1220/MAX1257/MAX1258 thin QFN packages
contain an exposed pad on the underside of the device.
Connect this exposed pad to AGND. Refer to the
MAX1258EVKIT for an example of proper layout.
Definitions
Integral Nonlinearity
Integral nonlinearity (INL) is the deviation of the values
on an actual transfer function from a straight line. This
straight line can be either a best-straight-line fit or a line
drawn between the end points of the transfer function,
once offset and gain errors have been nullified. INL for
the MAX1220/MAX1257/MAX1258 is measured using
the end-point method.
Differential Nonlinearity
Differential nonlinearity (DNL) is the difference between
an actual step width and the ideal value of 1 LSB. A
DNL error specification of less than 1 LSB guarantees
no missing codes and a monotonic transfer function.
______________________________________________________________________________________
12-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
Signal-to-Noise Plus Distortion
Signal-to-noise plus distortion (SINAD) is the ratio of the
fundamental input frequency’s RMS amplitude to the
RMS equivalent of all other ADC output signals:
SINAD(dB) = 20 x log (SignalRMS / NoiseRMS)
Bipolar ADC Offset Error
While in bipolar mode, the ADC’s ideal midscale transition occurs at AGND -0.5 LSB. Bipolar offset error is the
measured deviation from this ideal value.
ADC Gain Error
Gain error is defined as the amount of deviation
between the ideal transfer function and the measured
transfer function, with the offset error removed and with
a full-scale analog input voltage applied to the ADC,
resulting in all ones at DOUT.
DAC Offset Error
DAC offset error is determined by loading a code of all
zeros into the DAC and measuring the analog output
voltage.
DAC Gain Error
DAC gain error is defined as the amount of deviation
between the ideal transfer function and the measured
transfer function, with the offset error removed, when
loading a code of all ones into the DAC.
Aperture Jitter
Aperture jitter (tAJ) is the sample-to-sample variation in
the time between the samples.
Aperture Delay
Aperture delay (t AD ) is the time between the rising
edge of the sampling clock and the instant when an
actual sample is taken.
Signal-to-Noise Ratio
For a waveform perfectly reconstructed from digital samples, signal-to-noise ratio (SNR) is the ratio of full-scale
analog input (RMS value) to the RMS quantization error
(residual error). The ideal, theoretical minimum analogto-digital noise is caused by quantization error only and
results directly from the ADC’s resolution (N bits):
SNR = (6.02 x N + 1.76)dB
In reality, there are other noise sources besides quantization noise, including thermal noise, reference noise,
clock jitter, etc. Therefore, SNR is calculated by taking
the ratio of the RMS signal to the RMS noise. RMS noise
includes all spectral components to the Nyquist frequency excluding the fundamental, the first five harmonics, and the DC offset.
Effective Number of Bits
Effective number of bits (ENOB) indicates the global
accuracy of an ADC at a specific input frequency and
sampling rate. An ideal ADC’s error consists of quantization noise only. With an input range equal to the fullscale range of the ADC, calculate the ENOB as follows:
ENOB = (SINAD - 1.76) / 6.02
Total Harmonic Distortion
Total harmonic distortion (THD) is the ratio of the RMS
sum of the first five harmonics of the input signal to the
fundamental itself. This is expressed as:
THD = 20 x log ⎡⎢
⎣
( V22
+ V 3 2 + V 4 2 + V 5 2 + V 6 2 ) / V1⎤⎥
⎦
where V1 is the fundamental amplitude, and V2 through
V6 are the amplitudes of the first five harmonics.
Spurious-Free Dynamic Range
Spurious-free dynamic range (SFDR) is the ratio of RMS
amplitude of the fundamental (maximum signal component) to the RMS value of the next largest distortion
component.
ADC Channel-to-Channel Crosstalk
Bias the ON channel to midscale. Apply a full-scale sine
wave test tone to all OFF channels. Perform an FFT on
the ON channel. ADC channel-to-channel crosstalk is
expressed in dB as the amplitude of the FFT spur at the
frequency associated with the OFF channel test tone.
Intermodulation Distortion (IMD)
IMD is the total power of the intermodulation products
relative to the total input power when two tones, f1 and
f2, are present at the inputs. The intermodulation products are (f1 ± f2), (2 x f1), (2 x f2), (2 x f1 ± f2), (2 x f2 ±
f1). The individual input tone levels are at -7dBFS.
Small-Signal Bandwidth
A small -20dBFS analog input signal is applied to an
ADC so the signal’s slew rate does not limit the ADC’s
performance. The input frequency is then swept up to
the point where the amplitude of the digitized conversion result has decreased by -3dB. Note that the T/H
performance is usually the limiting factor for the smallsignal input bandwidth.
______________________________________________________________________________________
41
MAX1220/MAX1257/MAX1258
Unipolar ADC Offset Error
For an ideal converter, the first transition occurs at 0.5
LSB, above zero. Offset error is the amount of deviation
between the measured first transition point and the
ideal first transition point.
12-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
OUT7
16
17
18
OUT5
OUT6
15
N.C.
OUT4
TQFN
OUT0
AIN5
AIN4
AIN3
37
38
39
40
41
42
43
AIN11
AIN10
AIN9
AIN8
AIN7
AIN6
44
45
46
REF2/AIN14
AIN13
AIN12
47
28
10
27
11
26
12
25
AIN0
GPIOC3
GPIOC2
GPIOC1
GPIOC0
RES_SEL
CS
LDAC
OUT7
24
19
29
9
23
9
30
8
22
20
31
MAX1257
MAX1258
AIN2
REF1
AIN1
OUT4
OUT5
OUT6
8
14
7
6
21
21
13
DVDD
DGND
DOUT
SCLK
DIN
20
7
12
32
GPIOB2
GPIOB3
SCLK
DIN
OUT0
11
5
19
24
5
10
33
GPIOA2
GPIOA3
18
4
DGND
DOUT
GPIOC1
GPIOC0
N.C.
RES_SEL
CS
LDAC
17
25
16
3
OUT2
OUT3
AVDD
AGND
34
4
15
EOC
DVDD
OUT1
3
14
26
22
35
13
27
2
6
36
2
OUT2
OUT3
GPIOB0
GPIOB1
AVDD
AGND
1
23
1
GPIOA0
GPIOA1
EOC
AIN0
REF1
GPIOA0
GPIOA1
MAX1220
CNVST/AIN15
OUT1
+
48
+
28
29
30
31
N.C.
N.C.
AIN4
AIN3
AIN2
AIN1
33
32
REF2/AIN6
AIN5
34
CNVST/AIN7
35
TOP VIEW
36
MAX1220/MAX1257/MAX1258
Pin Configurations
TQFN
Full-Power Bandwidth
A large -0.5dBFS analog input signal is applied to an
ADC, and the input frequency is swept up to the point
where the amplitude of the digitized conversion result
has decreased by -3dB. This point is defined as fullpower input bandwidth frequency.
Chip Information
PROCESS: BiCMOS
Package Information
DAC Digital Feedthrough
DAC digital feedthrough is the amount of noise that
appears on the DAC output when the DAC digital control lines are toggled.
ADC Power-Supply Rejection
ADC power-supply rejection (PSR) is defined as the
shift in offset error when the power supply is moved
from the minimum operating voltage to the maximum
operating voltage.
DAC Power-Supply Rejection
For the latest package outline information and land patterns
(footprints), go to www.maxim-ic.com/packages. Note that a
“+”, “#”, or “-” in the package code indicates RoHS status only.
Package drawings may show a different suffix character, but
the drawing pertains to the package regardless of RoHS status.
PACKAGE
TYPE
PACKAGE
CODE
OUTLINE NO.
LAND
PATTERN NO.
36 TQFN-EP
T3666+3
21-0141
90-0050
48 TQFN-EP
T4877+6
21-0144
90-0132
DAC PSR is the amount of change in the converter’s
value at full-scale as the power-supply voltage changes
from its nominal value. PSR assumes the converter’s linearity is unaffected by changes in the power-supply
voltage.
42
______________________________________________________________________________________
12-Bit, Multichannel ADCs/DACs with FIFO,
Temperature Sensing, and GPIO Ports
REVISION REVISION
NUMBER
DATE
5
12/07
DESCRIPTION
Changed timing characteristic specification.
7
Changed the Ordering Information table to show lead(Pb)-free packages.
1
Added Note 18 to the Electrical Characteristics table (tDOV spec).
6
1/10
Added the ADDITIONAL NO. OF BYTES column to Table 1.
Corrected Figure 8, replaced Figure 9 with Figures 9a and 9b, and modified Figures
10 and 11.
7
2/12
PAGES
CHANGED
7, 8
20
36–39
Updated the ADC Conversions in Clock Mode 11 section.
36
Clarified Note 9.
8
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits) shown in
the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
43 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2012 Maxim Integrated Products
Maxim is a registered trademark of Maxim Integrated Products, Inc.
MAX1220/MAX1257/MAX1258
Revision History