VISHAY SUM110P04-05

SPICE Device Model SUM110P04-05
Vishay Siliconix
P-Channel 40-V (D-S) MOSFET
CHARACTERISTICS
• P-Channel Vertical DMOS
• Macro Model (Subcircuit Model)
• Level 3 MOS
• Apply for both Linear and Switching Application
• Accurate over the −55 to 125°C Temperature Range
• Model the Gate Charge, Transient, and Diode Reverse Recovery
Characteristics
DESCRIPTION
The attached spice model describes the typical electrical
characteristics of the p-channel vertical DMOS. The subcircuit
model is extracted and optimized over the −55 to 125°C
temperature ranges under the pulsed 0-V to 10-V gate drive. The
saturated output impedance is best fit at the gate bias near the
threshold voltage.
A novel gate-to-drain feedback capacitance network is used to model
the gate charge characteristics while avoiding convergence difficulties
of the switched Cgd model. All model parameter values are optimized
to provide a best fit to the measured electrical data and are not
intended as an exact physical interpretation of the device.
SUBCIRCUIT MODEL SCHEMATIC
This document is intended as a SPICE modeling guideline and does not constitute a commercial product data sheet. Designers should refer to the appropriate
data sheet of the same number for guaranteed specification limits.
Document Number: 74144
S-52522Rev. A, 12-Dec-05
www.vishay.com
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SPICE Device Model SUM110P04-05
Vishay Siliconix
SPECIFICATIONS (TJ = 25°C UNLESS OTHERWISE NOTED)
Parameter
Symbol
Test Condition
Simulated
Data
VGS(th)
VDS = VGS, ID = − 250 µA
2.8
Measured
Data
Unit
Static
Gate Threshold Voltage
a
V
ID(on)
VDS ≥ −5 V, VGS = −10 V
982
rDS(on)
VGS = −10 V, ID = −20 A
0.0040
Forward Transconductancea
gfs
VDS = −15 V, ID = −20 A
126
75
S
Diode Forward Voltagea
VSD
IS = −20 A
−0.88
−80
V
9687
11300
1524
1510
844
1000
195
185
48
48
42
42
On-State Drain Current
Drain-Source On-State Resistancea
A
0.0041
Ω
Dynamicb
Input Capacitance
Ciss
Output Capacitance
Coss
Reverse Transfer Capacitance
Crss
c
Qg
Total Gate Charge
c
Gate-Source Charge
c
Gate-Drain Charge
VGS = 0 V, VDS = −25 V, f = 1 MHz
Qgs
Qgd
VDS = −20 V, VGS = −10 V, ID = −20 A
pF
nC
Notes
a. Pulse test; pulse width ≤ 300 µs, duty cycle ≤ 2%.
b. Guaranteed by design, not subject to production testing.
c. Independent of operating temperature.
www.vishay.com
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Document Number: 74144
S-52522Rev. A, 12-Dec-05
SPICE Device Model SUM110P04-05
Vishay Siliconix
COMPARISON OF MODEL WITH MEASURED DATA (TJ=25°C UNLESS OTHERWISE NOTED)
Document Number: 74144
S-52522Rev. A, 12-Dec-05
www.vishay.com
3