VISHAY SI4911DY

SPICE Device Model Si4911DY
Vishay Siliconix
Dual P-Channel 20-V (D-S) MOSFET
CHARACTERISTICS
• P-Channel Vertical DMOS
• Macro Model (Subcircuit Model)
• Level 3 MOS
• Apply for both Linear and Switching Application
• Accurate over the −55 to 125°C Temperature Range
• Model the Gate Charge, Transient, and Diode Reverse Recovery
Characteristics
DESCRIPTION
The attached spice model describes the typical electrical
characteristics of the p-channel vertical DMOS. The subcircuit
model is extracted and optimized over the −55 to 125°C
temperature ranges under the pulsed 0-V to 5-V gate drive. The
saturated output impedance is best fit at the gate bias near the
threshold voltage.
A novel gate-to-drain feedback capacitance network is used to model
the gate charge characteristics while avoiding convergence difficulties
of the switched Cgd model. All model parameter values are optimized
to provide a best fit to the measured electrical data and are not
intended as an exact physical interpretation of the device.
SUBCIRCUIT MODEL SCHEMATIC
This document is intended as a SPICE modeling guideline and does not constitute a commercial product data sheet. Designers should refer to the appropriate
data sheet of the same number for guaranteed specification limits.
Document Number: 72191
S-52285Rev. B, 31-Oct-05
www.vishay.com
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SPICE Device Model Si4911DY
Vishay Siliconix
SPECIFICATIONS (TJ = 25°C UNLESS OTHERWISE NOTED)
Parameter
Symbol
Test Condition
Simulated
Data
VGS(th)
VDS = VGS, ID = −250 µA
0.62
Measured
Data
Unit
Static
Gate Threshold Voltage
On-State Drain Current
a
Drain-Source On-State Resistancea
Forward Transconductancea
Diode Forward Voltage
a
ID(on)
rDS(on)
V
VDS = −5 V, VGS = −4.5 V
201
VGS = −4.5 V, ID = −8.4 A
0.015
0.015
VGS = −2.5 V, ID = −7.6 A
0.019
0.018
A
Ω
VGS = −1.8 V, ID = −3 A
0.023
0.023
gfs
VDS = −10 V, ID = − 8.4 A
33
35
S
VSD
IS = −1.7 A, VGS = 0 V
−0.80
−0.70
V
33
33
4
4
b
Dynamic
Total Gate Charge
Qg
Gate-Source Charge
Qgs
VDS = −10 V, VGS = −4.5 V, ID = −8.4 A
Gate-Drain Charge
Qgd
7.8
7.8
Turn-On Delay Time
td(on)
32
30
Rise Time
Turn-Off Delay Time
Fall Time
tr
td(off)
tf
VDD = −10 V, RL = 10 Ω
ID ≅ −1 A, VGEN = −4.5 V, RG = 6 Ω
32
35
272
280
43
140
nC
ns
Notes
a. Pulse test; pulse width ≤ 300 µs, duty cycle ≤ 2%.
b. Guaranteed by design, not subject to production testing.
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Document Number: 72191
S-52285Rev. B, 31-Oct-05
SPICE Device Model Si4911DY
Vishay Siliconix
COMPARISON OF MODEL WITH MEASURED DATA (TJ=25°C UNLESS OTHERWISE NOTED)
Document Number: 72191
S-52285Rev. B, 31-Oct-05
www.vishay.com
3