MAXIM MAX1772

Low-Cost, Multichemistry BatteryCharger Building Block
19-1772; Rev 4; 2/09
Applications
Features
o Input Current Limiting
o ±0.5% Output Voltage Accuracy Using Internal
Reference (0°C to +85°C)
o Programmable Battery Charge Current >4A
o Analog Inputs Control Charge Current and
Charge Voltage
o Monitor Outputs for:
Current Drawn from AC Input Source
Charging Current
AC Adapter Present
o Up to 18.2V (max) Battery Voltage
o 8V to 28V Input Voltage
o > 95% Efficiency
o 99.99% (max) Duty Cycle for Low-Dropout
Operation
o Charges Any Battery Chemistry: Li+, NiCd, NiMH,
Lead Acid, etc.
Notebook and Subnotebook Computers
Personal Digital Assistants
Handheld Terminals
Ordering Information
Pin Configuration
PART
TOP VIEW
DCIN 1
28 IINP
LDO 2
27 CSSP
CLS 3
26 CSSN
REF 4
25 BST
CCS 5
MAX1772
TEMP RANGE
PIN-PACKAGE
MAX1772EEI
-40°C to +85°C
28 QSOP
MAX1772EEI+
-40°C to +85°C
28 QSOP
+Denotes lead(Pb)-free/RoHS-compliant package.
24 DHI
CCI 6
23 LX
CCV 7
22 DLOV
GND 8
21 DLO
GND 9
20 PGND
ICHG 10
19 CSIP
ACIN 11
18 CSIN
ACOK 12
17 BATT
REFIN 13
16 CELLS
ICTL 14
15 VCTL
QSOP
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
MAX1772
General Description
The MAX1772 is a highly-integrated, multichemistry
battery-charger control IC that simplifies the construction of accurate and efficient chargers. The MAX1772
uses analog inputs to control charge current and voltage and can be programmed by the host or hardwired.
High efficiency is achieved by a buck topology with
synchronous rectification.
Maximum current drawn from the AC adapter is programmable to avoid overloading the AC adapter when
supplying the load and the battery charger simultaneously. This enables the user to reduce the cost of the
AC adapter. The MAX1772 provides outputs that can
be used to monitor the current drawn from the AC
adapter, battery-charging current, and the presence of
an AC adapter.
The MAX1772 can charge two to four lithium-ion (Li+)
series cells, easily providing 4A. When charging, the
MAX1772 automatically transitions from regulating current to regulating voltage. It is available in a space-saving 28-pin QSOP package.
MAX1772
Low-Cost, Multichemistry BatteryCharger Building Block
ABSOLUTE MAXIMUM RATINGS
DCIN, CSSP, CSSN to GND ...................................-0.3V to +30V
BST to GND ............................................................-0.3V to +36V
BST to LX..................................................................-0.3V to +6V
DHI to LX ...................................................-0.3V to (VBST + 0.3V)
LX to GND .................................................................-6V to +30V
BATT, CSIP, CSIN to GND........................................-0.3V to 20V
CSIP to CSIN or CSSP to CSSN or
PGND to GND ...........……….……………..…….-0.3V to +0.3V
CCI, CCS, CCV, DLO, ICHG, IINP,
ACIN, REF to GND ...............................-0.3V to (VLDO + 0.3V)
DLOV, VCTL, ICTL, REFIN, CELLS,
CLS, LDO, ACOK to GND ....................................-0.3V to +6V
DLOV to LDO.........................................................-0.3V to +0.3V
DLO to PGND .........................................-0.3V to (VDLOV + 0.3V)
LDO Short-Circuit Current ..................................................50mA
Continuous Power Dissipation (TA = +70°C)
28-Pin QSOP (derate 12.6mW/°C above +70°C).......1008mW
Junction-to-Ambient Thermal Resistance (θJA)
(Note 1) .....................................................................79.3°C/W
Junction-to-Case Thermal Resistance ( θJC)
(Note 1) ........................................................................27°C/W
Operating Temperature Range ...........................-40°C to +85°C
Junction Temperature ........................................................150°C
Storage Temperature Range .............................-60°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer
board. For detailed information on package thermal considerations, refer to www.maxim-ic.com/thermal-tutorial.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VDCIN = VCSSP = VCSSN = 18V, VBATT = VCSIP = VCSIN = 12V, VREFIN = 3.0V, VVCTL = VICTL = 0.75 VREFIN, VCELLS = 2.0V,
VACIN = 0V, CLS = REF, VBST - VLX = 4.5V, VGND = VPGND = 0V, CLDO = 1µF, LDO = DLOV, CREF = 1µF; pins CCI, CCS, and CCV
are compensated per Figure 1a; TA = 0°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
SUPPLY AND LDO REGULATOR
VDCIN
DCIN Input Voltage Range
DCIN Quiescent Current
7.0
VDCIN rising
IDCIN
TYP
8
VDCIN falling
DCIN Undervoltage Lockout
Trip Point
MIN
8.0V < VDCIN < 28V, no load
LDO Load Regulation
0 < ILDO < 10mA
LDO Undervoltage Lockout
Trip Point
VDCIN = 8.0V
REF Output Voltage
0 < IREF < 500µA
REF Undervoltage Lockout
Trip Point
VREF falling
UNITS
28
V
7.4
7.5
8.0V < VDCIN < 28V
LDO Output Voltage
MAX
7.85
V
2.7
6.0
mA
5.40
5.55
V
34
100
mV
3.20
4.00
5.15
V
4.072
4.096
4.120
V
3.1
3.9
V
50
100
150
mV
100
200
300
mV
2.007
2.048
2.089
V
20
5.25
TRIP POINTS
BATT POWER_FAIL Threshold
VCSSP falling
BATT POWER_FAIL Threshold
Hysteresis
ACIN Threshold
VACIN rising
ACIN Threshold Hysteresis
0.5% of VREF
10
30
mV
ACIN Input Bias Current
VACIN = 2.048V
-1
+1
µA
1.6
REF
V
-1
+1
µA
1.50
µs
CLS Input Range
CLS Input Bias Current
VCLS = 2.0V
SWITCHING REGULATOR
Minimum Off-Time
2
VBATT =16.8V
1.00
1.25
_______________________________________________________________________________________
Low-Cost, Multichemistry BatteryCharger Building Block
(VDCIN = VCSSP = VCSSN = 18V, VBATT = VCSIP = VCSIN = 12V, VREFIN = 3.0V, VVCTL = VICTL = 0.75 VREFIN, VCELLS = 2.0V,
VACIN = 0V, CLS = REF, VBST - VLX = 4.5V, VGND = VPGND = 0V, CLDO = 1µF, LDO = DLOV, CREF = 1µF; pins CCI, CCS, and CCV
are compensated per Figure 1a; TA = 0°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
Maximum On-Time
MIN
TYP
MAX
5
10
15
UNITS
ms
400
kHz
Oscillator Frequency
fOSC
(Note 2)
DLOV Supply Current
IDLOV
DLO low
5
10
µA
IBST
DHI high
6
15
µA
150
500
µA
0.3
1.0
µA
BST Supply Current
LX Input Bias Current
VDCIN = 28V, VBATT = VLX = 20V
LX Input Quiescent Current
VDCIN = 0V, VBATT = VLX = 20V
DHI Maximum Duty Cycle
99.0
99.9
%
DHI On-Resistance High
VBST - VLX = 4.5V, IDHI = +100mA
4
7
Ω
DHI On-Resistance Low
VBST - VLX = 4.5V, IDHI = -100mA
1
2
Ω
DLO On-Resistance High
VDLOV = 4.5V, IDLO = +100mA
4
7
Ω
DLO On-Resistance Low
VDLOV = 4.5V, IDLO = -100mA
1
2
Ω
200
500
IBATT
BATT Input Current
CSIP/CSIN Input Current
CSSP/CSSN Input Current
VBATT = 19V, VDCIN = 0V
VDCIN = 0V
1
VCSIP = VCSIN = 12V
0.1
VCSSP = VCSSN = VDCIN > 8.0V
CSSP to CSSN Full-Scale
Current-Sense Voltage
0.3
800
0
VBATT = 12V
5
800
VDCIN = 0V
BATT/CSIP/CSIN Input Voltage
Range
CSIP to CSIN Full-Scale
Current-Sense Voltage
5
VBATT = 2V to 19V, VDCIN > VBATT + 0.3V
µA
µA
µA
19
V
189
204
219
mV
189
204
219
mV
0.0625
0.1250
0.250
µS
ERROR AMPLIFIERS
GMV Amplifier
Transconductance
VCTL = REFIN, VBATT = 16.8V, CELLS = LDO
GMI Amplifier
Transconductance
ICTL = REFIN, VCSIP - VCSIN = 150.4mV
0.5
1
2
µS
GMS Amplifier
Transconductance
VCLS = 2.048V, VCSSP - VCSSN = 102.4mV
0.5
1
2
µS
CCI/CCS/CCV Clamp Voltage
0.25V < VCCI, VCCS, VCCV < 2.0V
150
300
600
mV
CURRENT AND VOLTAGE SETTING
Charging-Current Accuracy
ICTL, VCTL, REFIN Input Bias
Current
ICTL Power-Down Mode
Threshold Voltage
ICTL = REFIN (see Equation 2)
-8
+8
ICTL = REFIN/32 (see Equation 2)
-55
+55
VVCTL = VICTL = VREFIN = 3V
-1
+1
VDCIN = 0, VVCTL = VICTL = VREFIN = 5V
-1
+1
REFIN
/100
REFIN
/55
REFIN
/33
%
µA
V
_______________________________________________________________________________________
3
MAX1772
ELECTRICAL CHARACTERISTICS (continued)
MAX1772
Low-Cost, Multichemistry BatteryCharger Building Block
ELECTRICAL CHARACTERISTICS (continued)
(VDCIN = VCSSP = VCSSN = 18V, VBATT = VCSIP = VCSIN = 12V, VREFIN = 3.0V, VVCTL = VICTL = 0.75 VREFIN, VCELLS = 2.0V,
VACIN = 0V, CLS = REF, VBST - VLX = 4.5V, VGND = VPGND = 0V, CLDO = 1µF, LDO = DLOV, CREF = 1µF; pins CCI, CCS, and CCV
are compensated per Figure 1a; TA = 0°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.)
PARAMETER
Battery-Regulation Voltage
Accuracy
SYMBOL
CONDITIONS
MIN
IINP Transconductance
IINP Current Accuracy
CSSP - CSSN Accuracy
UNITS
-0.5
+0.5
VVCTL = VREFIN/20 (2, 3, or 4 cells)
(see Equation 1)
-0.5
+0.5
2.0
3.6
V
1.20
1.92
V
1.00
1.05
µS
%
REFIN Undervoltage Lockout
ICHG Accuracy
MAX
VVCTL = VREFIN (2, 3, or 4 cells)
(see Equation 1)
REFIN Range
ICHG Transconductance
TYP
VICHG to (VCSIP - VCSIN); VCSIP VCSIN = 0.185V; VICHG = 0V, 3.0V
0.95
VCSIP - VCSIN = 0.185V
-5
+5
VCSIP - VCSIN = 0.05V
-10
+10
VIINP to (VCSSP - VCSSN); VCSSP VCSSN = 0.185V; VIINP = 0V, 3.0V (Note 3)
0.85
VCSSP - VCSSN = 0.185V
-15
+15
-20
+20
VCSSP - VCSSN = 0.08V, VCLS = 1.6V
-10
+10
VCSSP - VCSSN = 0.2V, CLS = REF
-10
+10
8.0
28
V
0.2
V
0.4
VLDO
- 0.5
V
VLDO
- 0.25
VLDO
V
-10
+10
µA
VCSSP - VCSSN = 0.05V
CSSP + CSSN Input Voltage
Range
(Note 3)
1.00
1.15
%
µS
%
%
LOGIC LEVELS
CELLS Input Low Voltage
CELLS Input Middle Voltage
CELLS Input High Voltage
CELLS Input Bias Current
VCELLS = 0V or VLDO
ACOK Sink Current
VACOK = 0.4V
1
ACOK Leakage Current
VACOK = 5.5V
-1
4
_______________________________________________________________________________________
mA
+1
µA
Low-Cost, Multichemistry BatteryCharger Building Block
(VDCIN = VCSSP = VCSSN = 18V, VBATT = VCSIP = VCSIN = 12V, VREFIN = 3.0V, VVCTL = VICTL = 0.75 VREFIN, VCELLS = 2.0V,
VACIN = 0V, CLS = REF, VBST - VLX = 4.5V, VGND = VPGND = 0V, CLDO = 1µF, LDO = DLOV, CREF = 1µF; pins CCI, CCS, and CCV
are compensated per Figure 1a; TA = -40°C to +85°C, unless otherwise noted.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
28.0
V
SUPPLY AND LDO REGULATOR
DCIN Input Voltage Range
VDCIN
VDCIN falling
DCIN Undervoltage Lockout
Trip Point
DCIN Quiescent Current
8.0
7
VDCIN rising
IDCIN
8.0V < VDCIN < 28V
8.0V < VDCIN < 28V, no load
LDO Output Voltage
7.85
V
6
mA
5.25
5.65
V
50
150
mV
100
300
mV
2.089
V
TRIP POINTS
VCSSP falling
BATT POWER_FAIL Threshold
BATT POWER_FAIL Threshold
Hysteresis
ACIN Threshold
VACIN rising
2.007
ACIN Threshold Hysteresis
0.5% of REF
10
30
mV
ACIN Input Bias Current
VACIN = 2.048V
-1
+1
µA
1.6
REF
V
VCLS = 2.0V
-1
+1
µA
VBATT = 16.8V
1
1.5
µs
CLS Input Range
CLS Input Bias Current
SWITCHING REGULATOR
Minimum Off-Time
Maximum On-Time
5
Oscillator Frequency
fOSC
(Note 1)
DHI Maximum Duty Cycle
ms
kHz
99
IBATT
BATT Input Current
15
400
CSIP/CSIN Input Current
CSSP/CSSN Input Current
VBATT = 19V, VDCIN = 0V
5
VBATT = 2V to 19V, VDCIN > VBATT + 0.3V
500
VDCIN = 0V
5
VCSIP = VCSIN = 12V
800
VDCIN = 0V
0.3
VCSSP = VCSSN = VDCIN > 8.0V
800
BATT/CSIP/CSIN Input Voltage
Range
CSIP to CSIN Full-Scale
Current-Sense Voltage
%
µA
µA
µA
0
19
V
189
219
mV
189
219
mV
ICTL = REFIN (see Equation 2)
-8
+8
ICTL = REFIN/32 (see Equation 2)
-55
+55
VVCTL = VICTL = VREFIN = 3V
-1
+1
VDCIN = 0V, VVCTL = VICTL = VREFIN = 5V
-1
+1
VBATT = 12V
CSSP to CSSN Full-Scale
Current-Sense Voltage
CURRENT AND VOLTAGE SETTING
Charging Current Accuracy
ICTL, VCTL, REFIN Input Bias
Current
%
µA
_______________________________________________________________________________________
5
MAX1772
ELECTRICAL CHARACTERISTICS
MAX1772
Low-Cost, Multichemistry BatteryCharger Building Block
ELECTRICAL CHARACTERISTICS (continued)
(VDCIN = VCSSP = VCSSN = 18V, VBATT = VCSIP = VCSIN = 12V, VREFIN = 3.0V, VVCTL = VICTL = 0.75 VREFIN, VCELLS = 2.0V,
VACIN = 0V, CLS = REF, VBST - VLX = 4.5V, VGND = VPGND = 0V, CLDO = 1µF, LDO = DLOV, CREF = 1µF; pins CCI, CCS, and CCV
are compensated per Figure 1a; TA = -40°C to +85°C, unless otherwise noted.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MAX
UNITS
REFIN
/100
REFIN
/33
V
VVCTL = VREFIN (2, 3, or 4 cells)
(see Equation 1)
-1
+1
VVCTL = VREFIN/20 (2, 3, or 4 cells)
(see Equation 1)
-1
+1
ICTL Power-Down Mode
Threshold Voltage
Battery Regulation Voltage
Accuracy
MIN
TYP
%
REFIN Range
2.0
REFIN Undervoltage Lockout
ICHG Accuracy
IINP Current Accuracy
CSSP - CSSN Accuracy
3.6
V
1.92
V
VCSIP - VCSIN = 0.185V
-5
+5
VCSIP - VCSIN = 0.05V
-10
+10
-15
+15
-20
+20
VCSSP - VCSSN = 0.08V, VCLS = 1.6V
-10
+10
VCSSP - VCSSN = 0.2V, CLS = REF
-10
+10
8
28
V
0.2
V
0.4
VLDO
- 0.5
V
VLDO
- 0.25
VLDO
V
-10
+10
VCSSP - VCSSN = 0.185V
VCSSP - VCSSN = 0.05V
CSSP + CSSN Input Voltage
Range
(Note 3)
%
%
%
LOGIC LEVELS
CELLS Input Low Voltage
CELLS Input Middle Voltage
CELLS Input High Voltage
CELLS Input Bias Current
VCELLS = 0V or VLDO
ACOK Sink Current
VACOK = 0.4V
1
ACOK Leakage Current
VACOK = 5.5V
-1
Note 2: Guaranteed by design. Not production tested.
Note 3: Tested under DC conditions. See text for more detail.
6
_______________________________________________________________________________________
µA
mA
+1
µA
Low-Cost, Multichemistry BatteryCharger Building Block
LOAD-TRANSIENT RESPONSE
(BATTERY REMOVAL AND REINSERTION)
LOAD-TRANSIENT RESPONSE
(STEP-IN LOAD CURRENT)
MAX1772 toc01
MAX1772 toc02
VBATT
20V/div
VCCS
500mV/div
VCCI
500mV/div
CCI
CCS
IBATT
2A/div
CCV
VBATT
20V/div
CCI
VCCI
500mV/div
VCCV
500mV/div
ILOAD
2A/div
1ms/div
1ms/div
BATTERY PRESENT
VICTL = 3.30V
CHARGING CURRENT = 2.0A
VBATT = 16V
LOAD STEP = 0 TO 3A
ISOURCE LIMIT = 5A
VICTL = 0.957V
VCTL = 3.3V
LDO LOAD REGULATION
VVCTL = 0V
VICTL = 3.3V
VDCIN = 20.0V
VLDO = 5.40V
MAX1772 toc03
0.3
VDCIN
10V/div
0.2
LDO ERROR (%)
VBATT
(AC-COUPLED)
100mV/div
MAX1772 toc04
0.4
LINE-TRANSIENT RESPONSE
0.1
0
-0.1
-0.2
-0.3
-0.4
0
2ms/div
1
2
3
4
5
6
7
8
9
10
LDO CURRENT (mA)
VBATT = 16V
VDCIN = 18.5V TO 27.5V
ILOAD = 150mA
_______________________________________________________________________________________
7
MAX1772
Typical Operating Characteristics
(Circuit of Figure 1a, VDCIN = 20V, TA = +25°C, unless otherwise noted.)
Typical Operating Characteristics (continued)
(Circuit of Figure 1a, VDCIN = 20V, TA = +25°C, unless otherwise noted.)
REF VOLTAGE LOAD REGULATION
0.10
REF ERROR (%)
0.4
0.2
0
-0.2
0.05
0
-0.05
-0.4
-0.10
-0.6
0.3
0.2
0.1
0
-0.1
-0.2
-0.3
-0.8
-0.15
-1.0
-0.20
12
16
20
24
-0.4
-0.5
0
28
50 100 150 200 250 300 350 400 450 500
70
100
CELL = 4
CELL = 3
60
50
90
80
EFFICIENCY (%)
EFFICIENCY (%)
VVCTL = 0V
VICTL = 3.3V
VREFIN = 3.3V
10
35
60
EFFICIENCY vs. BATTERY CURRENT
(CURRENT CONTROL LOOP)
MAX1772 toc08
100
80
-15
TEMPERATURE (°C)
EFFICIENCY vs. BATTERY CURRENT
(VOLTAGE CONTROL LOOP)
90
-40
REF CURRENT (μA)
DCIN (V)
CELL = 2
40
MAX1772 toc09
8
CELL = 4
70
CELL = 3
CELL = 2
60
50
40
30
30
20
20
10
10
VVCTL = 0V
VICTL = 3.3V
VREFIN = 3.3V
0
0
0.1
1
10
100
BATT CURRENT (mA)
8
VICTL = 0V
VVCTL = 0V
NO LOAD
VREF = 4.096V
0.4
REF VOLTAGE ERROR (%)
0.6
VVCTL = 0V
VICTL = 3.3V
CELL = 4
VREF = 4.096V
0.15
REF VOLTAGE ERROR vs. TEMPERATURE
0.5
MAX1772 toc06
MAX1772 toc05
VLDO = 5.40V
0.8
0.20
MAX1772 toc07
LDO LINE REGULATION
1.0
LDO ERROR (%)
MAX1772
Low-Cost, Multichemistry BatteryCharger Building Block
1000
10,000
100
1000
BATT CURRENT (mA)
_______________________________________________________________________________________
10,000
85
Low-Cost, Multichemistry BatteryCharger Building Block
OUTPUT V/I CHARACTERISTICS
0.035
CELL = 3
0.030
0.025
CELL = 2
0.020
0.015
CELL = 4
VREFIN = 3.3V
NO LOAD
0.18
0.16
0.14
0.12
0.10
0.08
0.06
0.010
0.04
0.005
0.02
0
MAX1772 toc11
0.040
0
500 1000 1500 2000 2500 3000 3500 4000
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
BATT CURRENT (mA)
VCTL/REFIN (%)
CURRENT SETTING ERROR vs. ICTL
ICHG ERROR vs. BATT LOAD CURRENT
4.0
MAX1772 toc12
5
VREFIN = 3.3V
4
VVCTL = 0V
VICTL = 3.3V
CELL = 4
3.5
MAX1772 toc13
0
3.0
ICHG ERROR (%)
CURRENT SETTING ERROR (%)
BATT VOLTAGE ERROR (%)
CELL = 4
BATT VOLTAGE ERROR (%)
VVCTL = 0V
VICTL = 3.3V
0.045
BATT VOLTAGE ERROR vs. VCTL
0.20
MAX1772 toc10
0.050
3
2
2.5
2.0
1.5
1.0
1
VBATT > 2V
0
0.5
0
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
ICTL/REFIN (%)
0
500 1000 1500 2000 2500 3000 3500 4000
BATT LOAD CURRENT (mA)
_______________________________________________________________________________________
9
MAX1772
Typical Operating Characteristics (continued)
(Circuit of Figure 1a, VDCIN = 20V, TA = +25°C, unless otherwise noted.)
Low-Cost, Multichemistry BatteryCharger Building Block
MAX1772
Pin Description
10
PIN
NAME
FUNCTION
1
DCIN
Charging Voltage Input
2
LDO
Device Power Supply. Output of the 5.4V linear regulator supplied from DCIN. Bypass LDO with a 1µF
capacitor to GND.
3
CLS
Source Current-Limit Input. Voltage input for setting the current limit of the input source.
4
REF
4.096V Voltage Reference. Bypass REF with a 1µF capacitor to GND.
5
CCS
Input Current Regulation Loop Compensation Point. Connect a 0.01µF capacitor from CCS to GND.
6
CCI
Output Current Regulation Loop Compensation Point. Connect a 0.01µF capacitor from CCI to GND.
7
CCV
Voltage Regulation Loop Compensation Point. Connect 1kΩ resistor in series with a 0.1µF capacitor
to GND.
8, 9
GND
Analog Ground
10
ICHG
ICHG is a scaled-down replica of the battery output current being sensed. It is used to monitor the
charging current and indicates when the chip changes from voltage mode to current mode. The
transconductance of (CSIP - CSIN) to ICHG is 1µS. Connect ICHG pin to GND if it is unused.
11
ACIN
AC Detect Input. Detects when the AC adapter voltage is available for charging.
12
ACOK
AC Detect Output. Open-drain output is high when ACIN is less than REF/2.
13
REFIN
Reference Input. Allows the ICTL and VCTL pins to have ratiometric ranges for increased DAC
accuracy.
14
ICTL
Input for Setting Maximum Output Current. Range is REFIN/32 to REFIN. The device shuts down if
this pin is forced below REFIN/55 (typ).
15
VCTL
Input for Setting Maximum Output Voltage. Range is 0 to REFIN.
16
CELLS
17
BATT
Battery Voltage Input
18
CSIN
Output Current-Sense Negative Input
19
CSIP
Output Current-Sense Positive Input. Connect a current-sense resistor from CSIP to CSIN.
20
PGND
21
DLO
Low-Side Power MOSFET Driver Output. Connect DLO to a low-side nMOS gate.
22
DLOV
Low-Side Driver Supply
23
LX
Power Connection for the High-Side Power MOSFET Driver. Connect LX to a source of high-side nMOS.
24
DHI
High-Side Power MOSFET Driver Output. Connect DHI to a high-side nMOS gate.
25
BST
Power Connection for the High-Side Power MOSFET Driver. Connect a 0.1µF capacitor from LX to
BST.
26
CSSN
Input Current-Sense for Charger (negative input)
27
CSSP
Input Current-Sense for Charger (positive input). Connect a current-sense resistor from CSSP to
CSSN.
28
IINP
Trilevel Input for Setting Number of Cells. GND = 2 cells, LDO/2 = 3 cells, LDO = 4 cells.
Power Ground
IINP is a scaled-down replica of the input current being sensed. It is used to monitor the total system
current. The transconductance of (CSSP - CSSN) to IINP is 1mS. Connect IINP pin to GND if it is unused.
______________________________________________________________________________________
Low-Cost, Multichemistry BatteryCharger Building Block
The MAX1772 includes all of the functions necessary to
charge Li+, NiMH, and NiCd batteries. A high-efficiency
synchronous-rectified step-down DC-DC converter controls charging voltage and current. It also includes input
source-current limiting and analog inputs for setting the
charge current and charge voltage. The DC-DC converter uses external N-channel MOSFETs as the buck
switch and synchronous rectifier to convert the input
voltage to the required charging current and voltage.
The typical application circuit shown in Figure 1a uses
a microcontroller (µC) to allow control of charging current or voltage, while Figure 1b shows a typical application with charging voltage and current fixed to
specific values for the application. The voltage at ICTL
and the value of RS2 set the charging current. The DCDC converter generates the control signals for the
external MOSFETs to regulate the voltage and the current set by the VCTL, ICTL, and CELLS inputs.
The MAX1772 features a voltage-regulation loop (CCV)
and two current-regulation loops (CCI and CCS). The
CCV voltage-regulation loop monitors BATT to ensure
that its voltage never exceeds the voltage set by VCTL.
The CCI battery current-regulation loop monitors current delivered to BATT to ensure that it never exceeds
the current limit set by ICTL. A third loop (CCS) takes
control and reduces the battery-charging current when
the sum of the system load and the battery-charging
current exceeds the charging source current limit set
by CLS.
Setting the Battery Regulation Voltage
The MAX1772 uses a high-accuracy voltage regulator
for charging voltage. The VCTL input adjusts the battery output voltage. VCTL is allowed to vary from 0 to
REFIN (≈ 3.3V). The per-cell battery termination voltage
is a function of the battery chemistry and construction;
thus, consult the battery manufacturer to determine this
voltage. The battery voltage is calculated by the equation:
⎛
⎛V
⎞⎞
V
VBATT = CELLS × ⎜ VREF + ⎜ REF × VCTL ⎟ ⎟
VREFIN ⎠ ⎠
⎝ 10
⎝
(1)
CELLS is the programming input for selecting cell
count. Table 1 shows how CELLS is connected to
charge 2, 3, or 4 cells. Use a voltage-divider from LDO
to set the desired voltage at CELLS.
The internal error amplifier (GMV) maintains voltage
regulation (Figure 2). The voltage error amplifier is compensated at CCV. The component values shown in
Figure 1 provide suitable performance for most appli-
cations. Individual compensation of the voltage regulation and current-regulation loops allow for optimal compensation.
Setting the Charging-Current Limit
The ICTL input sets the maximum charging current. The
current is set by current-sense resistor RS2, connected
between CSIP and CSIN. The nominal differential voltage between CSIP and CSIN is 204mV; thus, for a
0.05Ω sense resistor, the maximum charging current is
4A. Battery-charging current is programmed with ICTL
using the equation:
ICHG =
VREF
V
1
× ICTL ×
RS2
VREFIN
20
(2)
The input range for ICTL is REFIN/32 to REFIN (≈ 3.3V).
The device shuts down if ICTL is forced below
REFIN/55 (typical). The current at ICHG is a scaleddown replica of the battery output current being sensed
across CSIP and CSIN.
When choosing the current-sense resistor, note that the
voltage drop across this resistor causes further power
loss, reducing efficiency. However, adjusting ICTL to
reduce the voltage across the current-sense resistor
may degrade accuracy due to the input offset of the
current-sense amplifier. The charging current-error
amplifier (GMI) is compensated at CCI. A 0.01µF
capacitor at CCI provides suitable performance for
most applications.
Setting the Input Current Limit
The total input current (from a wall cube or other DC
source) is a function of the system supply current and
the battery-charging current. The input current regulator limits the source current by reducing the charging
current when the input current exceeds the set input
current limit. System current will normally fluctuate as
portions of the system are powered up or put to sleep.
Without input current regulation, the input source must
be able to supply the maximum system current and the
maximum charger input current. By using the input current limiter, the current capability of the AC wall adapter
may be lowered, reducing system cost.
The MAX1772 limits the current drawn by the charger
when the load current becomes high. The device limits
the charging current, so the AC adapter voltage is not
loaded down. An internal amplifier compares the voltage between CSSP and CSSN to the voltage at CLS.
VCLS can be set by a resistor-divider between REF and
GND. Connect CLS to REF for maximum input current
limiting.
______________________________________________________________________________________
11
MAX1772
Detailed Description
MAX1772
Low-Cost, Multichemistry BatteryCharger Building Block
VIN
8VDC TO 28VDC
RS1
0.04Ω
D1
TO EXTERNAL
LOAD
R14
4.7Ω
C6
O.47μF
R6
59.0kΩ
C1
22μF
R15
4.7Ω
C7
O.47μF
D4
CSSP
R7
19.6kΩ
CSSN
CELLS
DCIN
C5
1μF
LDO
C13
1μF
R13
33Ω
D3
D/A OUTPUT
VCTL
BST
D/A OUTPUT
ICTL
DLOV
VCC
C15
0.1μF
REFIN
R8
1MΩ
ACIN
DIGITAL
INPUT
ACOK
A/D INPUT
ICHG
C16
1.0μF
N1
DHI
LX
N2
DLO
D2
MAX1772
L1
22μH
PGND
R11
1Ω
IINP
A/D INPUT
C14
0.1μF
C2
22μF
R9
15.4kΩ
C20
0.1μF
CSIP
R10
12.4kΩ
CCV
C18
0.1μF
R5
1kΩ
HOST
RS2
0.05Ω
C11
0.1μF
R12
1Ω
C19
0.1μF
CSIN
CCI
C9
0.01μF
C10
0.01μF
GND
REF
AVDD/REF
R20, R21, R22
10kΩ
BATT+
BATT
CCS
C3
22μF
CLS
C4
22μF
C12
1μF
SMART
BATTERY
SCL
SCL
SDA
SDA
A/D INPUT
TEMP
GND
BATT-
PGND
GND
Figure 1a. µC-Controlled Typical Application Circuit
12
______________________________________________________________________________________
Low-Cost, Multichemistry BatteryCharger Building Block
RS1
0.04Ω
D1
TO EXTERNAL
LOAD
R14
4.7Ω
C1
22μF
R15
4.7Ω
C6
O.47μF
MAX1772
VIN
8VDC TO 28VDC
C2
22μF
C7
O.47μF
3.30V
D4
3.30V
R21
10kΩ
910Ω
R6
59.0kΩ
CSSP
R7
19.6kΩ
R19
29.4kΩ
CSSN
CELLS
DCIN
C5
1μF
1.5kΩ
LDO
C13
1μF
R13
33Ω
D3
R22
10kΩ
R20
10kΩ
REFIN
BST
VCTL
DLOV
C15
0.1μF
ICTL
R8
1M
ACIN
C16
1.0μF
N1
DHI
ACOK
LX
ICHG
N2
DLO
D2
MAX1772
L1
22μH
PGND
R11
1Ω
IINP
C14
0.1μF
R9
15.4kΩ
C20
0.1μF
CSIP
R10
12.4kΩ
CCV
C18
0.1μF
R5
1kΩ
RS2
0.05Ω
C11
0.1μF
R12
1Ω
C19
0.1μF
CSIN
CCI
C9
0.01μF
BATT+
BATT
CCS
C10
0.01μF
GND
REF
CLS
C3
22μF
C4
22μF
BATTERY
BATT-
C12
1μF
Figure 1b. Stand-Alone Typical Application Circuit
______________________________________________________________________________________
13
MAX1772
Low-Cost, Multichemistry BatteryCharger Building Block
DCIN
LDO
5.4V LINEAR
REGULATOR
4.096V
REFERENCE
REF
MAX1772
LOGIC
BLOCK
GND
1/55
REFIN
GND
ICTL
ACIN
SRDY
ACOK
REF/2
IINP
CCS
CLS
GMS
CSSP
CSSN
LEVEL
SHIFTER
CSIP
CSIN
LEVEL
SHIFTER
ICHG
BST
LEVEL
SHIFTER
DRIVER
GMI
DHI
LX
204mV
X ——REFIN
ICTL
CCI
BATT
LVC
DC-DC
CONVERTER
R1
CELLS
CELL SELECT
LOGIC
DLOV
GMV
DRIVER
DLO
CCV
PGND
VCTL
409mV
X ——REFIN
VOS
Figure 2. Functional Diagram
14
______________________________________________________________________________________
Low-Cost, Multichemistry BatteryCharger Building Block
CELL
CELL COUNT
VCELLS < 0.20V
2
0.40V < VCELLS < VLDO-0.5V
3
VLDO - 0.25V < VCELLS < VLDO
4
VIINP = ISOURCE × RS1 × GIINP × R10
The input source current is the sum of the device current, the charger input current, and the load current.
The device current is minimal (6mA) in comparison to
the charge and load currents. The actual source current required is determined as follows:
[
]
ISOURCE = ILOAD + (ICHARGE × VBATT ) / (VIN × η)
(3)
where η is the efficiency of the DC-DC converter (85%
to 95% typ).
V CLS determines the reference voltage of the GMS
error amplifier. Sense resistor RS1 sets the maximum
allowable source current. Calculate the maximum current as follows:
ISOURCE_MAX = VCLS / (20 × RS1)
(4)
Once the input current limit is reached, the charging
current is tapered back until the input current is below
the desired threshold.
When choosing the current-sense resistor, note that the
voltage drop across this resistor causes further power
loss, reducing efficiency.
AC Adapter Detection
Connect the AC adapter voltage through a resistive
divider to ACIN to detect when AC power is available,
as shown in Figure 1. ACOK is an open-drain output
and is high when ACIN is less than REF/2.
Current Measurement
Use ICHG to monitor the battery-charging current
being sensed across CSIP and CSIN. The output voltage range is 0 to 3V. The voltage of ICHG is proportional to the output current by the equation:
VICHG = IICHG × RS2 × GICHG × R9
Use IINP to monitor the system input current being
sensed across CSSP and CSSN. The output voltage
range is 0 to 3V. The voltage of IINP is proportional to
the output current by the equation:
( 5)
where IICHG is the battery-charging current, GICHG is
the transconductance of ICHG (1mS typ), and R9 is the
resistor connected between ICHG and ground.
(6)
where ISOURCE is the DC current being supplied by the
AC adapter power, GIINP is the transconductance of
IINP (1µS typ), and R10 is the resistor connected
between IINP and ground.
In the typical application circuit, duty cycle affects the
accuracy of V IINP (Figure 3). AC load current also
affects accuracy (Figure 4).
Connect IINP pin to ground if it is not used.
LDO Regulator
LDO provides a 5.4V supply derived from DCIN and
can deliver up to 15mA of current. The MOSFET drivers
are powered by DLOV and BST, which must be connected to LDO as shown in Figure 1. LDO also supplies
the 4.096V reference (REF) and most of the control circuitry. Bypass LDO with a 1µF capacitor.
DC-to-DC Converter
The MAX1772 employs a buck regulator with a bootstrapped NMOS high-side switch and a low-side NMOS
synchronous rectifier.
DC-DC Controller
The control scheme is a constant off-time variable frequency, cycle-by-cycle current mode. The off-time is
constant for a given BATT voltage. It varies with VBATT
operation; a maximum on-time of 10ms allows the controller to achieve >99% duty cycle with continuous conduction. Figure 5 shows the controller functional
diagram.
MOSFET Drivers
The low-side driver output DLO swings from 0 to DLOV.
DLOV is usually connected through a filter to LDO. The
high-side driver output DHI is bootstrapped off LX and
swings from V LX to V BST. When the low-side driver
turns on, BST rises to one diode voltage below DLOV.
Filter DLOV with a resistor-capacitor (RC) circuit whose
cutoff frequency is about 50kHz. The configuration in
Figure 1 introduces a cutoff frequency of around
48kHz:
f = 1/2πRC = 1 / (2π 33Ω 0.1µF) = 48kHz
(7)
Connect ICHG pin to ground if it is not used.
______________________________________________________________________________________
15
MAX1772
Table 1. Cell-Count Programming Table
MAX1772
Low-Cost, Multichemistry BatteryCharger Building Block
30
0
IINP ACCURACY (%)
20
AC ADAPTER
RS1
AC LOAD
2A
1A
-1
FREQUENCY
MAX1772
IINP ACCURACY (%)
VDCIN = 16V
VBATT = 8.2V
VDCIN = 16V
VBATT = 12.3V
10
VDCIN = 18V
VBATT = 16.4V
-2
FREQ = 50kHz
-3
FREQ = 125kHz
-4
0
FREQ = 250kHz
-5
-6
-10
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
0
10
20
30
40
50
60
70
80
DUTY CYCLE (%)
IRS1 (A)
Figure 4. IINP Accuracy vs. AC Load Duty Cycle
Figure 3. IINP Accuracy vs. VDCIN/VBATT
Dropout Operation
MOSFETs and Schottky Diodes
The MAX1772 has 99.99% duty-cycle capability with a
10ms maximum on-time and 1µs off-time. This allows
the charger to achieve dropout performance limited
only by resistive losses in the DC-DC converter components (D1, N1, RS1, RS2) (Figure 1). The actual dropout
voltage is limited to 100mV between CSSP and CSIN by
the power-fail comparator.
Schottky diode D1 provides power to the load when the
AC adapter is inserted. This diode must be able to
deliver the maximum current as set by RS1.
The n-channel MOSFETs (N1, N2) are the switching
devices for the buck controller. High-side switch N1
should have a current rating of at least 8A and have an
on-resistance (RDS(ON)) of 50mΩ or less. The driver for
N1 is powered by BST; its current should be less than
10mA. Select a MOSFET with a low total gate charge
(QGATE) and determine the required drive current by
IGATE = QGATE f (where f is the DC-DC converter’s
400kHz maximum switching frequency).
The low-side switch (N2) should also have a current rating of at least 8A, have an RDS(ON) of 100mΩ or less,
and a total gate charge less than 10nC. N2 is used to
provide the starting charge to the BST capacitor (C15).
During normal operation, the current is carried by
Schottky diode D2. Choose a Schottky diode capable
of carrying the maximum charging current.
D3 is a signal-level diode, such as the 1N4148. This
diode provides the supply current to the high-side
MOSFET driver.
Compensation
Each of the three regulation loops—the input current
limit, the charging current limit, and charging voltage
limit—can be compensated separately using the CCS,
CCI, and CCV pins, respectively.
The charge-current-loop error-amp output is brought
out at CCI. Likewise, the source current error-amp output is brought out at CCS; 0.01µF capacitors to ground
at CCI and CCS compensate the current loops in most
charger designs. Raising the value of these capacitors
reduces the bandwidth of these loops.
The voltage-regulating-loop error-amp output is brought
out at CCV. Compensate this loop by connecting a
series RC network from CCV to GND. Recommended
values are 1kΩ and 0.1µF. The zero set by the series
RC increases midfrequency gain to provide phase
compensation. The pole at CCV is set by the capacitor
and the voltage error-amp output impedance at low frequencies to integrate the DC error.
Component Selection
Table 2 lists the recommended components and refers
to the circuit of Figure 1. The following sections describe
how to select these components.
16
Inductor Selection
Inductor L1 provides power to the battery while it is
being charged. It must have a saturation current of at
least 4A plus 1/2 of the current ripple (ΔIL):
ISAT = 4A + (1/2) ΔIL
______________________________________________________________________________________
(8)
Low-Cost, Multichemistry BatteryCharger Building Block
MAX1772
10ms
S
RESET
CSSP
BST
IMAX
R
4.0V
RS1
CSS
MAX1772
Q
DCIN
LDO
CSSN
BST
R
Q
DHI
CCMP
DHI
CBST
LX
CHG
Q
S
IMIN
0.25V
DLO
L1
DLO
1μs
CSIP
ZCMP
0.1V
CSI
RS2
CSIN
GMS
LVC
BATT
COUT
BATTERY
GMI
GMV
SETV
CONTROL SETI
CLS
CELL
SELECT
LOGIC
CELLS
CCS
CCI
CCV
Figure 5. DC-to-DC Converter Functional Diagram
______________________________________________________________________________________
17
MAX1772
Low-Cost, Multichemistry BatteryCharger Building Block
The controller determines the constant off-time period,
which is dependent on BATT voltage. This makes the
ripple current independent of input and battery voltage,
and it should be kept to less than 1A. Calculate ΔIL with
the following equation:
ΔIL =
21Vμs
L(μH)
Use the following step-by-step guide:
1) Place the high power connections first, with their
grounds adjacent:
• Minimize the current-sense resistor trace
lengths, and ensure accurate current sensing
with Kelvin connections.
(9)
• Minimize ground trace lengths in the high
current paths.
Higher inductor values decrease the ripple current.
Smaller inductor values require high saturation current
capabilities and degrade efficiency. Typically, a 22µH
inductor is ideal for all operating conditions.
• Minimize other trace lengths in the high current
paths.
Current-Sense Input Filtering
In normal circuit operation with typical components, the
current-sense signals can have high-frequency transients that exceed 0.5V due to large current changes
and parasitic component inductance. To achieve proper battery and input current compliance, the currentsense input signals should be filtered to remove large
common-mode transients. The input current-limit sensing circuitry is the most sensitive case due to large current steps in the input filter capacitors (C6, C7) in
Figure 1. Use 0.47µF ceramic capacitors from CSSP
and CSSN to ground. Smaller 0.1µF ceramic capacitors
(C18, C19) can be used on the CSIP and CSIN inputs
to ground since the current into the battery is continuous. Place these capacitors next to the single-point
ground directly under the MAX1772.
Layout and Bypassing
Bypass DCIN with a 1µF to ground (Figure 1). D4 protects the MAX1772 when the DC power source input is
reversed. A signal diode for D4 is adequate because
DCIN only powers the LDO and the internal reference.
Bypass LDO, BST, DLOV, and other pins as shown in
Figure 1.
Good PCB layout is required to achieve specified noise,
efficiency, and stable performance. The PC board layout
artist must be given explicit instructions—preferably, a
pencil sketch showing the placement of the power
switching components and high current routing. Refer to
the PCB layout in the MAX1772 evaluation kit for examples. A ground plane is essential for optimum performance. In most applications, the circuit will be located
on a multilayer board, and full use of the four or more
copper layers is recommended. Use the top layer for
high current connections, the bottom layer for quiet connections (REF, CCV, CCI, CCS, DCIN, and GND), and
the inner layers for an uninterrupted ground plane.
18
• Use >5mm wide traces.
• Connect C1 and C2 to high-side MOSFET
(10mm max length).
• LX node (MOSFETs, rectifier cathode, inductor
(15mm max length)).
Ideally, surface-mount power components are flush
against one another with their ground terminals
almost touching. These high-current grounds are
then connected to each other with a wide, filled zone
of top-layer copper, so they do not go through vias.
The resulting top-layer subground plane is connected to the normal inner-layer ground plane at the
output ground terminals, which ensures that the
IC’s analog ground is sensing at the supply’s output
terminals without interference from IR drops and
ground noise. Other high current paths should also
be minimized, but focusing primarily on short
ground and current-sense connections eliminates
about 90% of all PCB layout problems.
2) Place the IC and signal components. Keep the
main switching node (LX node) away from sensitive
analog components (current-sense traces and REF
capacitor). Important: the IC must be no further
than 10mm from the current-sense resistors.
Keep the gate drive traces (DHI, DLO, and BST)
shorter than 20mm, and route them away from the
current-sense lines and REF. Place ceramic bypass
capacitors close to the IC. The bulk capacitors can
be placed further away. Place the current-sense
input filter capacitors under the part, connected
directly to the GND pin.
3) Use a single-point star ground placed directly
below the part. Connect the input ground trace,
power ground (subground plane), and normal
ground to this node.
______________________________________________________________________________________
Low-Cost, Multichemistry BatteryCharger Building Block
DESIGNATION
C1, C2, C3, C4
C5
C6, C7
DESCRIPTION
N1
n-channel MOSFET
International Rectifier IRF7805 or
Fairchild FDS6680
1µF, 50V ceramic capacitor (1210)
Murata GRM42-2X7R105K050
N2
n-channel MOSFET
Fairchild FDS6612A
RS1
0.04Ω ±1%, 1W resistor
Dale WSL-2512-R040-F or
IRC LR2512-01-R040-F
RS2
0.05Ω ±1%, 1W resistor
Dale WSL-2512-R050-F or
IRC LR2512-01-R050-F
0.47µF, 25V ceramic capacitors (1210)
Murata GRM42-2X7R474K050
0.01µF ceramic capacitors (0805)
C12, C13
1µF, 10V ceramic capacitors (0805)
Taiyo Yuden LMK212BJ105MG
C11, C14, C15,
C16, C18, C19,
C20
0.1µF, 50V ceramic capacitors (0805)
Taiyo Yuden UMK212BJ104MG or
Murata GRM40-034X7R104M050
D1
Schottky diode (DPAK)
STM-Microelectronics STPS8L30B or
ON Semiconductor MBRD630CT or
Toshiba U5FWK2C42
D3, D4
L1
DESCRIPTION
22µF, 35V low-ESR tantalum capacitors
AVX TPSE226M035R0300 or
Sprague 593D226X0035E2W
C9, C10
D2
DESIGNATION
R5
1kΩ ±5% resistor (0805)
R6
59.0kΩ ±1% resistor (0805)
R7
19.6kΩ ±1% resistor (0805)
R8
1MΩ ±5% resistor (0805)
R9
15.4kΩ ±1% resistor (0805)
R10
12.4kΩ ±1% resistor (0805)
30V, 3A Schottky diode
Nihon EC31QS03L
R11, R12
100mA Schottky diodes (SOT23)
Central Semiconductor CMPSH-3 or
Hitachi HRB0103A
R14, R15
R13
MAX1772
Table 2. Component List
1Ω ±5% resistors (0805)
33Ω ±5% resistor (1206)
4.7Ω ±5% resistors (1206)
R19
29.4kΩ ±1% resistor (0805)
R20, R21, R22
10kΩ ±1% resistors (0805)
22µH power inductor
Sumida CDRH127-220
Package Information
Chip Information
PROCESS: BiCMOS
For the latest package outline information and land patterns, go
to www.maxim-ic.com/packages.
PACKAGE TYPE
PACKAGE CODE
DOCUMENT NO.
28 QSOP
E28-1
21-0055
______________________________________________________________________________________
19
MAX1772
Low-Cost, Multichemistry BatteryCharger Building Block
Revision History
REVISION
NUMBER
REVISION
DATE
DESCRIPTION
PAGES
CHANGED
0
4/07
Initial release
—
4
2/09
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Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
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© 2009 Maxim Integrated Products
Maxim is a registered trademark of Maxim Integrated Products, Inc.