Silan Semiconductors SC9270C/D DTMF RECEIVER DESCRIPTION The SC9270C/D is a complete DTMF receiver integrating both the bandsplit filter and digital decoder functions. The filter section uses switched capacitor techniques for high- and low-group filters and dial-tone rejection. Digital counting techniques are employed in the decoder to detect and decode all 16 DTMF tone-pairs into a 4-bit code. External component count is minimized by on-chip provision of a differential input amplifier, clock-oscillator and latched 3-state bus interface. FEATURES DIP-18 *Complete receiver in an 18-pin package *Excellent performance *CMOS, single 5 volt operation, *Widely operating voltage: 1.2V ~ 5.25V APPLICATIONS *Minimum board area *Paging systems *Central office quality *Repeater systems / Mobile radio *Low power consumption *Credit card systems *Power-Down mode (SC9270D only) *Remote control *Inhibit-mode (SC9270D only) *Personal computers PIN CONFIGURATIONS 18 VDD IN+ 1 18 VDD IN- 2 17 St/GT IN- 2 17 St/GT GS 3 16 ESt GS 3 16 ESt VREF 4 15 StD VREF 4 IC* 5 14 Q4 INH 5 IC* 6 13 Q3 PWDN 6 13 Q3 OSCI 7 12 Q2 OSCI 7 12 Q2 OSCO 8 11 Q1 OSCO 8 11 Q1 VSS 9 10 TOE VSS 9 10 TOE SC9270D 1 SC9270C IN+ 15 StD 14 Q4 * Connect to V SS HANGZHOU SILAN MICROELECTRONICS JOINT-STOCK CO.,LTD Rev: 1.1 1 2001.04.27 Silan Semiconductors SC9270C/D BLOCK DIAGRAM VDD VSS PWDN 18 9 VREF INH 4 5 6 - BIAS CIRCUIT + 11 Q1 Chip ref Chip power IN+ 1 IN- 2 GS Chip bias + - CODE HIGH GROUP FILTER DIGITAL 12 Q2 CONVERTER DETECTION DIAL TONE FILTER AND Zero crossing detectors 13 Q3 ALGORITHM LATCH HIGH GROUP FILTER 3 14 Q4 St Chip clock STEERING LOGIC GT 7 8 17 16 15 10 OSCI OSCO St/GT ESt StD TOE Figure 1. block diagram ABSOLUTE MAXIMUM RATINGS (Notes 1, 2, 3) Characteristic Symbol Value Unit VDD-VSS 6 V Voltage on any pin -- VSS-0.3 ~ VDD+0.3 V Current at any pin -- 10 mA °C Power Supply Voltage Operating temperature Topr -40~+85 Storage Temperature Tstg -65~+150 °C 500 mW Package power dissipation Note: 1. Absolute maximum ratings are those values beyond which damage to the device may occur. 2. Unless otherwise specified, all voltages are referenced to ground. 3. Power dissipation temperature derating: -12 mV / from 65°C to 85°C RECOMMENDED OPERATING CONDITIONS (Note 1) Parameter Positive Supply Voltages Oscillator Clock Frequency Oscillator Frequency Tolerance Symbol VDD Conditions VSS=0V Min Typ(Note 2) Max 1.2 5 -- Unit V fc -- -- 3.579545 -- MHz ∆fc -- -- ±0.1 -- % Note: 1. Voltages are with respect to ground(Vss), unless otherwise stated. 2 .Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing. HANGZHOU SILAN MICROELECTRONICS JOINT-STOCK CO.,LTD Rev: 1.1 2 2001.04.27 Silan Semiconductors SC9270C/D DC ELECTRICAL CHARACTERISTICS Parameter Symbol Conditions Min Typ Max Unit SUPPLY Operating Supply Voltage VDD -- 1.2 -- 5.25 V Operating Supply Current ICC -- -- 3.0 7.0 mA Power Consumption PO f=3.579MHz; VDD=5V -- 15 35 mW Standby Current IS PWDN pin = VDD -- -- 100 µA Low Level Input Voltage VIL -- -- -- 1.5 V High Level Input Voltage VIH -- 3.5 -- -- V µA INPUTS Input Leakage Current IIH/IIL VIN= VSS or VDD -- 0.1 -- Pull up(Source) Current ISO TOE(Pin 10)=0V -- 7.5 15 µA Input Impedance (IN+, IN-) RIN @1kHz -- 10 -- MΩ Steering Threshold Voltage VTSt -- -- 2.35 -- V Low Level Output Voltage VOL No load -- 0.03 -- V High Level Output Voltage VOH No load -- 4.97 -- µA Output Low(Sink) Current IOL VOUT=0.4V 1.0 2.5 -- mA Output High(Source) Current IOH VOUT=4.6V 0.4 0.8 -- mA 2.4 -- 2.7 V -- 10 -- kΩ OUTPUTS VREF Output Voltage VREF No load VREF Output Resistance ROR -- OPERATING CHARACTERISTICS Gain Setting Amplifier Parameter Symbol Conditions Min Typ Max Unit Input Leakage Current IIN VSS < VIN < VDD -- ±100 -- nA Input Resistance RIN -- -- 10 -- MΩ Input Offset Voltage VOS -- -- ±25 -- mV Power Supply Rejection PSRR 1kHz -- 60 -- dB Common Mode Rejection CMRR -3.0V < VIN < 3.0V -- 60 -- dB DC Open Loop Voltage Gain AVOL -- -- 65 -- dB Open Loop Unity Gain Bandwidth fC -- -- 1.5 -- MHz Output Voltage Swing VO RL≥100kΩ to VSS -- 4.5 -- VPP Tolerable capacitive load(GS) CL -- -- 100 -- PF Tolerable resistive load(GS) RL -- -- 50 -- kΩ Common Mode Range VCM No load -- 3.0 -- VPP Notes : 1. All voltages referenced to VDD unless otherwise noted. 2. VDD = 5.0V, VSS = 0V, TA = 25°C . HANGZHOU SILAN MICROELECTRONICS JOINT-STOCK CO.,LTD Rev: 1.1 3 2001.04.27 Silan Semiconductors SC9270C/D AC CHARACTERISTICS (All voltage referenced to Vss otherwise noted; VDD=5.0V, VSS=0V, TA=25°C, fCLK=3.579545 MHz, using test circuit of figure 2 & 3. Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing) Parameter Symbo l Test Conditions Min Typ Max Unit SIGNAL CONDITIONS Valid Input Signal Levels (each tone of composite signal) -- Note:1,2,3,5,6,9,11 -- -- -40 dBm -- Note:1,2,3,5,6,9,11 -- -- 7.75 mVRMS -- Note:1,2,3,5,6,9,11 +1 -- -- dBm -- Note:1,2,3,5,6,9,11 883 -- -- mVRMS Positive Twist Accept -- Note:2,3,6,9,11 -- 10 -- dB Negative Twist Accept -- Note:2,3,6,9,11 -- 10 -- dB Frequency Deviation Accept Limit -- Note:2,3,5,9,11 -- ±1.5%±2Hz -- Frequency Deviation Reject Limit -- Note:2,3,5,11 ±3.5 -- -- Thrid Tone Tolerance -- Note:2,3,4,5,9,13 -18.5 Noise Tolerance -- Note:2,3,4,5,7,9,10 -- -12 Dial Tone Tolerance -- Note:2,3,4,5,8,9,11 -- +18 -- dB -- dB dB TIMING Tone Present Detection Time tDP Refer to Fig. 4. Note:12 5 14 16 ms Tone Absent Detection Time tDA Refer to Fig. 4. Note:12 0.5 4 8.5 ms Tone Duration Accept tREC User adjustable -- -- 40 ms Tone Duration Reject tREC User adjustable 20 -- -- ms Interdigit Pause Accept tID User adjustable -- -- 40 ms Interdigit Pause Reject tDO User adjustable 20 -- -- ms tPQ TOE=VDD -- 8 11 µs Propagation Delay (St to StD) tPSED TOE=VDD -- 12 -- µs Output Data Set Up (Q to Std) tQSED TOE=VDD -- 4.5 -- µs OUTPUTS Propagation Delay (St to Q) Propagation Delay (TOE to Q Enable) tPTE RL=10kΩ, CL=50pf -- 50 -- ns Propagation Delay (TOE to Q Disable) tPTD RL=10kΩ, CL=50pf -- 300 -- ns CLOCK Crystal/Clock Frequency -- 3.5759 3.5759 3.581 MHz Clock Input Rise Time tLHCL Ext. clock -- -- 110 ns Clock Input Fall Time tHLCL Ext. clock -- -- 110 ns Clock Input Duty Time DCCL Ext. clock 40 50 60 % -- -- 30 pf Capacitive Load (OSCO) fC CLO -- Notes: 1. dBm = decibels above or below a reference power of 1mW into a 600 Ohm load. 2. Digit sequences consists of all 16 DTMF tones. HANGZHOU SILAN MICROELECTRONICS JOINT-STOCK CO.,LTD Rev: 1.1 4 2001.04.27 Silan Semiconductors SC9270C/D 3. Tone duration = 40mS Tone pause = 40mS. 4. Nominal DTMF frequencies are used. 5. Both tones in the composite signal have an equal amplitude. 6. Tone pair is deviated by ±1.5% ±2Hz. 7. Bandwidth limited (3kHz) Gaussian Noise. 8. The precise dial tone frequencies are (350Hz and 440Hz) ±2%. 9. For an error rate of less than 1 in 10,000. 10. Referenced to the lowest level frequency component in DTMF signal. 11. Referenced to the minimum valid accept. 12. For guard time calculation purpose. 13. Referenced to Fig.10 Input DTMF Tone level at –25dBm(-28dBm at GS Pin) interference Frequency Range between 480—3400Hz. 5V SC9270C 0.1µf 5V SC9270D 100nf 1 IN+ VDD 18 2 IN- St/GT 17 100nf 1 100nf 100kΩ 100kΩ 3 GS ESt 16 4 VREF StD 15 5 IC Q4 14 6 IC Q3 13 7 OSCI 8 OSCO 9 VSS Q2 Q1 TOE IN+ VDD 18 2 IN- St/GT 17 3 GS ESt 16 4 VREF StD 15 5 INH Q4 14 6 PWDN Q3 13 7 OSCI Q2 12 8 OSCO Q1 11 9 VSS TOE 10 100nf Vin 100kΩ 300kΩ 100kΩ 5V 3.58MHz 0.1µf 12 300kΩ 3.58MHz 11 10 Figure 2. Single ended input cofiguration Figure 3. Single ended input cofiguration HANGZHOU SILAN MICROELECTRONICS JOINT-STOCK CO.,LTD Rev: 1.1 5 2001.04.27 Silan Semiconductors SC9270C/D PIN DESCRIPTION Pin No. Pin Name I/O 1 IN+ I Non-Inverting input Description 2 IN- I Inverting input 3 GS -- 4 VREF O Connections to the front-end differential amplifier. Gain select. Gives access to output of front-end differential amplifier for connection of feedback resistor. Reference voltage output, nominally VDD/2. May be used to bias the inputs at mid-rail (see application diagram). Inhibit (input) logic high inhibit the detection of 1633Hz internal built-in pull down 5 INH I 6 PWDN I 7 OSC1 I Clock Input 3.579545MHz crystal connected between these pins 8 OSC2 O Clock Output completes internal oscillator. 9 VSS -- Negative power supply, normally connected to 0V. 10 TOE I 11~14 Q1 ~ Q4 O resistor. (SC9270D only). (For SC9270C, this pin must be tied to VSS ) Power down (input). Active high power down the device and inhibit the oscillator internal built-in pull down resistor. (SC9270D only). (For SC9270C, this pin must be tied to VSS ) 3-state data output enable. Logic high enables the outputs Q1-Q4. This pin is Internally pulled up. 3-state data outputs. When enabled by TOE, provide the code corresponding to the last valid tone-pair received (see Table 1). When TOE is logic low, the data outputs are high impedance. Delayed steering output. Presents a logic high when a received tone-pair has 15 StD O been registered and the output latch updated; returns to logic low when the voltage on St/GT falls below VTSt. Early steering output. Presents a logic high immediately when the digital 16 ESt O algorithm detects a recognizable tone-pair (signal condition). Any momentary loss of signal condition will cause ESt to return to a logic low. Steering input/guard time output (bi-directional). A voltage greater than VTSt detected at St causes the device to register the detected tone-pair and update 17 St/GT I/O the output latch. A voltage less than VTSt frees the device to accept a new tonepair. The GT output acts to reset the external steering time-constant; its state is a function of ESt and the voltage on St. 18 VDD -- Positive power supply. HANGZHOU SILAN MICROELECTRONICS JOINT-STOCK CO.,LTD Rev: 1.1 6 2001.04.27 Silan Semiconductors SC9270C/D TIMING DIAGRAM D EVENTS A C B tREC E tREC tID TONE # n+1 tDP ESt G TONE DROPOUT tDO TONE # n Vin F TONE # n+1 tDA tGTP tGTA VTst St/GT tPQ DATA OUTPUTS Q1 ~ Q4 DECODED TONE # n -1 DECODED TONE#n HIGH IMPEDANCE DECODED TONE # n+1 tPSTD StD OUTPUT tPTE TOE tPTD Figure 4. Timing diagram EXPLANATION OF EVENTS EXPLANATIONN OF SYMBOLS A. Short tone bursts: detected. Tone duration is invalid. Vin: DTMF composite input signal. tREC B. Tone #n is detected. Tone duration is valid. Decoded :Maximum DTMF signal duration not detected as valid. to outputs. tREC: Minimum DTMF Signal duration required for valid C. End of tone #n is detected and validated. recognition. D. 3 State outputs disabled (high impedance). tID: Minimum time between valid DTMF signals. E. Tone #n + 1 is detected. Tone duration is valid. tDO: Maximum allowable dropout during valid DTMF signal Decoded to outputs. tDP: Time to detect the presence of valid DTMF signals. F. Tristate outputs are enabled. Acceptable drop out of tDP: Time to detect the absence of valid DTMF signals. tone #n + 1 does not negister at outputs. tGTP: Guard Time, Tone present. G. End of tone #n + 1 is detected and validated. tGTP: Guard Time, Tone absent. HANGZHOU SILAN MICROELECTRONICS JOINT-STOCK CO.,LTD Rev: 1.1 7 2001.04.27 Silan Semiconductors SC9270C/D FUNCTION DESCRIPTIONS The SC9270C/D monolithic DTMF receiver offers small size, low power consumption and high performance. Its architecture consists of a bandsplit filter section, which separates the high and low tones of receiver pair, followed by a digital counting section which verifies the frequency and duration of the received tones before passing the corresponding code to the output bus. 1. FILTER SECTION Separation of the low-group and high-group tones is achieved by applying the dual tone signal to the inputs of two filters a sixth order for the high group and an eighth order for the low group. The bandwidths of which correspond to the bands enclosing the low-group and high-group tones (see table 1). The filter section also in corporates notches at 350Hz and 440 Hz for exceptional dial-tone rejection. Each filter output is followed by a second-order switchedcapacitor section which smooth the signals prior to limiting. Limiting is performed by high-gain comparators which are provided with hysteresis to prevent detection of unwanted low-level signals and noise; the outputs of the comparators provide full-rail logic swings at the frequencies of the incoming tones. Flow Fhigh KEY TOE Q4 Q3 Q2 Q1 697 1209 1 H 0 0 0 1 697 1336 2 H 0 0 1 0 697 1477 3 H 0 0 1 1 770 1209 4 H 0 1 0 0 770 1336 5 H 0 1 0 1 770 1477 6 H 0 1 1 0 852 1209 7 H 0 1 1 1 852 1336 8 H 1 0 0 0 852 1477 9 H 1 0 0 1 941 1336 0 H 1 0 1 0 941 1209 * H 1 0 1 1 941 1477 # H 1 1 0 0 697 1633 A H 1 1 0 1 770 1633 B H 1 1 1 0 852 1633 C H 1 1 1 1 941 1633 D H 0 0 0 0 -- -- ANY L Z Z Z Z L=LOGIC LOW, H=LOGIC HIGH, Z=HIGH IMPEDANCE Table 1: Function decode table HANGZHOU SILAN MICROELECTRONICS JOINT-STOCK CO.,LTD Rev: 1.1 8 2001.04.27 Silan Semiconductors SC9270C/D 0 PRECISE DIAL TONES 10 X=350Hz Y=440Hz 20 DTMF TONES FREQUENCY (dB) A=697Hz B=770Hz C=852Hz D=941Hz E=1209Hz F=1336Hz G=1477Hz H=1633Hz 30 40 50 1kHz X Y AB C D E F G H FREQUENCY Figure 5. Filter Response 2. DECODER SECTION The decoder used digital counting techniques to determine the frequencies of the limited tones and to verify that they correspond to standard DTMF frequencies. A complex averaging algorithm(protects) against tone simulation by extraneous signals, such as voice, while providing tolerance to small frequency deviations and variations. This averaging algorithm has been developed to ensure an optimum combination of immunity to “talk-off” and tolerance to the presence of interfering signals (“third tones”) and noise. When the detector recognizes the simultaneous presence of two valid tones (referred to as “signal condition” in some industry specifications), it raises the “early steering” flag (ESt). Any subsequent loss of signal condition will cause ESt to fall. 3. STEERING CIRCUIT Before registration of a decoded tone-pair, the receiver VDD 0.1µf checks for a valid signal duration (referred to as “character- recognition-condition”). This check is performed by an external RC time-constant driven by ESt. A VDD logic high on ESt causes VC (see Fig.4) to rise as the St/GT capacitor discharges. Provided signal-condition is ESt maintained (ESt remains high) for the validation period StD VC tGTA=(RC)ln( VDD ) VTST tGTA=(RC)ln( VDD ) VDD-VTST R (tGTP), Vc reaches the threshold (VTSt) of the steering logic to register the tone-pair, latching its corresponding 4-bit code (see Fig.3) into the output latch. At this point, Figure 6. Basic steering Circuit the GT output is activated and drives VC to VDD. GT HANGZHOU SILAN MICROELECTRONICS JOINT-STOCK CO.,LTD Rev: 1.1 9 2001.04.27 Silan Semiconductors SC9270C/D continues to drive high as long as ESt remains high. Finally after a short delay to allow the output latch to settle, the “delayed-steering” output flag, StD, goes high, signaling that a received tone-pair has been registered.The contents of the output latch are made available on the 4-bit output bus by raising the 3-state control input (TOE) to a logic high. The steering circuit works in reverse to validate the interdigit pause between signals. Thus, as well as rejecting signals too short to be considered valid, the receiver will tolerate signal interruptions (“drop-out”) too short to be considered a valid pause. The facility, together with the capability of selecting the steering time-constants externally, allows the designer to tailor performance to meet a wide variety of system requirements. 4. GUARD TIME ADJUSTMENT In many situations not requiring independent selection of receive and pause, the simple steering circuit of Fig.6 is applicable. Component values are chosen according to the following formulae: tREC = tDP + tGTP tID = tDA + tGTA The value of tDP is a parameter of the device (see table) and tREC is the minimum signal duration to be recognized by the receiver. A value for C of 0.1µF is recommended for most applications, leaving R to be selected by the designer. For example, a suitable value of R for a tREC of 40mS would be 300k. Different steering arrangements may be used to select independently the guard-times for tone-present (tGTP ) and tone-absent (tGTA ). This may be necessary to meet system specifications which place both accept and reject limits on both tone duration and interdigital pause. Guard-time adjustment also allows the designer to tailor system parameters such as talk off and noise immunity. Increasing tREC improves talk-off performance, since it reduces the probability that tones simulated by speech will maintain signal condition for long enough to be registered. On the other hand, a relatively short tREC with a long tDO would be appropriate for extremely noisy environments where fast acquisition time and immunity to drop - outs would be required. Design information for guard-time adjustment is shown in Fig.7. VDD VDD C C St/GT St/GT R1 R1 R2 ESt tGTP =(Rp C)ln( tGTA =(R1 C)ln( VDD ) VDD-VTST VDD tGTP=(Rp C)ln( ) tGTA=(R1 C)ln( VTST Rp= R2 ESt VDD ) VDD-VTST VDD ) VTST R1R2 R1+R2 Rp= a) Decreasing tGTP (tGTP < tGTA) R1R2 R1+R2 b) Decreasing tGTP (tGTP > tGTA) Figure 7. Guard time adjustment HANGZHOU SILAN MICROELECTRONICS JOINT-STOCK CO.,LTD Rev: 1.1 10 2001.04.27 Silan Semiconductors SC9270C/D 5. INPUT CONFIGURATION The input arrangement of the SC9270C/D provides a differential-input operational amplifier as well as a bias source (VREF ) which is used to bias the inputs at mid-rail. Provision is made for connection of a feedback resistor to the op-amp output (GS) for adjustment of gain. In a singleended configuration, the input pins are connected as shown in Fig.2 with the op-amp connected for unity gain and VREF biasing the input at 1/2VDD. Fig.8 shows the differential configuration, which permits the adjustment of gain with the feedback resistor R5. C1 R1 SC9270C/D IN+ + C1=C2=10nF R1=R4=R5=100k R2=60k, R3=37.5k R2*R5 R3= R2+R5 C2 R4 INR5 DIFFERENTIAL INPUT AMPLIFIER GS All resistors are +/- 1% tolerance All capacitors are +/- 5% tolerance VOLTAGE GAIN (Av diff)= R3 R2 VREF R5 R1 INPUT IMPEDANCE(Zi diff)=2 2 R1 + 1 C 2 Figure 8. Differential input configuration 6. POWER – DOWN AND INHIBIT MODE A logic high applied to pin 6 (PWDN) will power the device to minimize the power consumption in a standby mode. It stops the oscillator and the functions of the filters. Inhibit mode is enabled by a logic high input to the pin 5 (INH). It inhibits the detection of 1633 Hz. The output code will remain the same as the previous detected code (see table 2). fLOW Fhigh 697 1209 697 1336 697 1477 770 1209 770 1336 770 1477 852 1209 852 1336 852 1477 941 1336 941 1209 941 1477 697 1633 770 1633 852 1633 941 1633 --- KEY 1 2 3 4 5 6 7 8 9 0 * # A B C D ANY TOE Q4 Q3 H H H H H H H H H H H H H H H H L L L L L L L L H H H H H H H H L Z L L L H H H H L L L L H H H H L Z INH = VSS fLOW Q1 L H 697 H L 697 H H 697 L L 770 L H 770 H L 770 H H 852 L L 852 L H 852 H L 941 H H 941 L L 941 L H 697 H L 770 H H 852 L L 941 Z Z -Table 2: Truth table (Z: high impedance) Q2 Fhigh 1209 1336 1477 1209 1336 1477 1209 1336 1477 1336 1209 1477 1633 1633 1633 1633 -- KEY TOE 1 H 2 H 3 H 4 H 5 H 6 H 7 H 8 H 9 H 0 H * H # H A H B H C H D H ANY L Q4 Q3 Q2 Q1 L L L L L L L H H H H H L L L H H H H L L L L H L H H L L H H L L H H L H L H L H L H L H L H L PREVIOUS DATA Z Z Z INH = VDD HANGZHOU SILAN MICROELECTRONICS JOINT-STOCK CO.,LTD Rev: 1.1 11 Z 2001.04.27 Silan Semiconductors SC9270C/D 6. CRYSTAL OSCILLATOR The internal clock circuit is completed with the addition of To OSCI of next SC9270C/D an external 3.579545MHz crystal and is normally connected as shown in Figure 2. However, it is possible C to configure several SC9270C/D devices employing only X-tal a single oscillator crystal. The oscillator output of the first OSCI device in the chain is coupled through a 30pF capacitor OSCO OSCO OSCI to the oscillator input (OSCI) of the next device. C Subsequent devices are connected in a similar fashion. Refer to Figure 9 for details. The problems associated c=30pF X-tal=3.579545MHz with unbalanced loading are not a concern with the arrangement shown, ie: precision balancing capacitors Figure 9 Oscillator Connection are not required. PACKAGE OUTLINE DIP-18-300-2.54 UNIT: mm 6.40 7.62 0.25 2.54 1.50 15 degree 3.30 5.08 3.51 22.95 0.46 HANGZHOU SILAN MICROELECTRONICS JOINT-STOCK CO.,LTD Rev: 1.1 12 2001.04.27