MOSA ELECTRONICS
MS8870
DTMF Receiver
Features
•
•
•
•
•
Complete DTMF receiver
Low power consumption
Adjustable guard time
Central Office Quality
CMOS, Single 5V operation
O
rdering Information
MS8870 : 18 PIN DIP PACKAGE
Description
The MS8870 is a complete DTMF receiver integrating
both the bandsplit filter and digital decoder functions,
fabricated in double poly technology and is pin and
function compatible with MITEL8870. The filter section
uses switched capacitor techniques for high and low group
filters; the decoder uses digital counting techniques to
detect and decode all 16 DTMF tone-pairs into a 4-bit code.
External component count is minimized by on chip
provision of a differential input amplifier, clock oscillator
and latched 3-state bus interface.
Figure 1. Functional Block Diagram
－ 1 －
MS8870
DTMF Receiver
MOSA ELECTRONICS
Pin Description
Pin #
Name
Description
1
2
3
IN +
IN GS
4
VREF
5
6
7
8
IC
IC
OSC1
OSC2
9
10
11-14
Vss
TOE
Q1-Q4
15
StD
16
ESt
17
St/GT
18
VDD
Non-inverting op-amp input.
Inverting op-amp input.
Gain select. Gives access to output of front end differential amplifier for connection
of feedback resistor.
Reference voltage output, nominally VDD /2 is used to bias inputs at mid-rail (see Fig.
2).
Internal connection. Must be tied to Vss.
Internal connection. Must be tied to Vss.
Clock input.
Clock output. A 3.5795 MHz crystal connected between OSC1 and OSC2 completes
the internal oscillator circuit.
Negative power supply input.
3-state output enable (input). Logic high enables the outputs Q1-Q4 Internal pull up.
3-state data output. When enable by TOE, provide the code corresponding to the last
valid tone-pair received (see Fig. 5).
Delayed steering output. Presents a logic high when a received tone-pair has been
registered and the output latch updated; return to logic low when the voltage on St/GT
falls below VTSt.
Early steering output. Presents a logic high once the digital algorithm has detected a
valid tone pair (signal condition). Any momentary loss of signal condition will cause
ESt to return to a logic low.
Steering input/guard time output (bi-directional). A voltage greater than VTSt detected
at St causes the device to register the detected tone pair and update the output latch. A
Voltage less than VTSt frees the device to accept a new tone pair. The GT output acts
to reset the external steering time-constant; its state is a function of ESt and the
voltage on St.
Positive power supply input.
Absolute Maximum Ratings
Parameter
1
2
3
4
5
6
Power supply voltage VDD-Vss
Voltage on any pin
Current at any pin
Operating temperature
Storage temperature
Package power dissipation
Min
Vss - 0.3
-40
-65
－ 2 －
Max
Units
6
VDD + 0.3
10
+85
+150
1000
V
V
mA
℃
℃
mW
MS8870
DTMF Receiver
MOSA ELECTRONICS
DC Electrical Characteristics
Characteristics
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
S
U
P
P
L
Y
I
N
P
U
T
S
O
U
T
P
U
T
S
Sym
Operating supply voltage
Min
Typ
Max
Units
4.75
5.0
5.25
V
Operating supply current
IDD
3.0
9.0
mA
Power consumption
PO
15
45
mW
High level input
Low level input voltage
Input leakage current
Pull up (source) current
Input impedance (IN+, IN-)
Steering threshold voltage
Low level output voltage
High level output voltage
Output low (sink) current
Output high (source) current
VRef output voltage
VRef output resistance
VIH
VIL
IIH/IIL
ISO
RIN
VTSt
VOL
VOH
IOL
IOH
VRef
ROR
3.5
1.5
0.1
7.5
10
2.2
4.97
1
0.4
2.4
2.5
0.03
2.5
0.8
2.8
10
V
V
µA
µA
MΩ
V
V
V
mA
mA
V
KΩ
Test Conditions
f = 3.58 MHz; VDD= 5V
VIN = Vss or VDD
TOE (pin 10) = 0 V
@ 1 KHz
No load
No load
VOUT = 0.4V
VOUT = 4.6V
No load
Operating Characteristics
Gain Setting Amplifier
Characteristics
Input leakage current
Input resistance
Input offset voltage
Power supply rejection
Common mode rejection
DC open loop voltage gain
Open loop unity gain bandwidth
Output voltage swing
Maximum capacitive load (GS)
Maximum resistive load (GS)
Common mode range
Notes :
Sym
IIN
RIN
Vos
PSRR
CMRR
AVOL
fc
Vo
CL
RL
VCM
Min
Typ
100
10
25
60
60
65
1.5
4.5
100
50
3.0
1. All voltages referenced to Vss unless otherwise noted.
2. Vcc = 5.0V, Vss = 0V, TA = 25 ℃
－ 3 －
Max
Units
nA
MΩ
mV
dB
dB
dB
MHz
Vpp
pF
KΩ
Vpp
Test Conditions
Vss
≤ VIN ≤ VDD
1 KHz
-3.0V ≤ VIN
RL
≤ 3.0V
≥ 100KΩ to Vss
No Load
MS8870
DTMF Receiver
MOSA ELECTRONICS
AC Electrical Characteristics *
Characteristics
S
I
G
N
A
L
C
O
N
D.
T
I
M
I
N
G
O
U
T
P
U
T
S
C
L
O
C
K
Sym
Typ
Max
-29
27.5
Valid input signal levels
(each tone of composite signal)
Positive twist accept
Negative twist accept
Freq. deviation accept
Freq. deviation reject
Third tone tolerance
Noise tolerance
Dial tone tolerance
Tone present detect time
Tone absent detect time
Tone duration accept
Tone duration reject
Interdigit pause accept
Interdigit pause reject
Propagation delay (St to Q)
Propagation delay (St to StD)
Output data set up ( Q to StD)
Propagation delay (TOE to Q
ENABLE)
Propagation delay (TOE to Q
DISABLE)
Crystal / clock frequency
Clock input rise time
Clock input fall time
Clock input duty cycle
Capacitive load (OSC2)
Min
+1
883
10
10
±1.5%±2Hz
±3.5%
tDP
tDA
tREC
/tREC
tID
tDO
tPQ
tPStD
tQStD
tPTE
-16
-12
+22
11
4
5
0.5
20
40
20
8
12
3.4
50
tPTD
fc
tLHCL
tHLCL
DCDL
CLO
14
8.5
40
11
300
3.5759
3.5795
40
* All voltages referenced to Vss unless otherwise noted. Vcc = 5.0V,
test circuit shown in Figure 2
50
dBm
mVRMS
dBm
mVRMS
dB
dB
Nom.
Nom.
dB
dB
dB
ms
ms
ms
ms
ms
ms
µs
µs
µs
ns
ns
3.5831
110
110
60
30
MHz
ns
ns
%
pF
Notes
1,2,3,5,6,9
1,2,3,5,6,9
1,2,3,5,6,9
1,2,3,5,6,9
2,3,6,9
2,3,6,9
2,3,5,9
2,3,5,9
2,3,4,5,9,10
2,3,4,5,7,9,10
2,3,4,5,8,9,11
Refer to Fig. 3
Refer to Fig. 3
User adjustable
User adjustable
User adjustable
User adjustable
TOE = VDD
TOE = VDD
TOE = VDD
RL = 10KΩ
CL = 50 pF
RL = 10KΩ
CL = 50 pF
Ext. clock
Ext. clock
Ext. clock
Vss = 0V, TA = 25℃, Fc = 3.579545 MHz, using
NOTES
1. dBm = decibels above or below a reference power of 1 mW into a 600 ohm load.
2. Digit sequence consists of all 16 DTMF tones.
3. Tone duration = 40 ms, tone pause = 40 ms.
4. Signal condition consists of nominal DTMF frequencies.
5. Both tones in composite signal have an equal amplitude.
6. Tone pair is deviated by ± 1.5% ± 2 Hz.
7. Bandwidth limited (3 KHz) Gaussian noise.
8. The precise dial tone frequencies are ( 350 Hz and 440 Hz) ± 2%.
9. For an error rate of better than 1 in 10,000.
10. Referenced to lowest level frequency component in DTMF signal.
11. Referenced to the minimum valid accept level.
－ 4 －
Units
MS8870
DTMF Receiver
MOSA ELECTRONICS
NOTES :
R1, R2 = 100K 1%
R3 = 300K 1%
C1, C2 = 100nF 5%
X1 = 3.579545 MHz
Figure 2. Single Ended Input Configuration
Figure 3. Timing Diagram
EXPLANATION OF EVENTS
A ) Short tone bursts: detected. Tone duration is invalid.
B ) Tone #n is detected. Tone duration is valid. Decoded to outputs.
C ) End of Tone #n is detected and validated.
D ) 3-State outputs disable ( high impedance).
E ) Tone #n + 1 is detected. Tone duration is valid. Decoded to outputs.
F ) Tristate outputs are enabled. Acceptable drop out of Tone #n + 1 does not register at outputs.
G ) End of Tone #n + 1 is detected and validated.
－ 5 －
MS8870
DTMF Receiver
MOSA ELECTRONICS
Decoder Section
Functional Description
The MS8870 monolithic DTMF receiver offers small
size, low power consumption and high performance. Its
architecture consists of a bandsplit filter section, which
separates the high and low group tones, followed by digital
counting section which verifies the frequency and duration
of the received tones before passing the corresponding
code to the output bus.
Filter Section
Separation of the low-group and high-group tones is
achieved by applying the DTMF signal to the inputs of two
filters － a sixth order for the high group and an eighth
order for the low group. The bandwidths of which
correspond to the low and high group frequencies. The
filter section also incorporates notches at 350 and 440 Hz
for exceptional dial tone rejection (see Fig. 4). Each filter
output is followed by a single order switched capacitor
filter section which smoothes the signals prior to limiting.
Limiting is performed by high-gain comparators which are
provided with hysteresis to prevent detection of unwanted
low-level signals. The outputs of the comparators provide
full rail logic swings at the frequencies of the incoming
DTMF signals.
Figure 4. 6TH Order Bandpass
The decoder uses digital counting techniques to
determine the frequencies of limited tones and to verify
that they correspond to standard DTMF frequencies. A
complex averaging algorithm protects against tone
simulation by extraneous signals, such as voice, while
providing tolerance to small frequency deviations and
variations. This averaging algorithm has been developed to
ensure an optimum combination of immunity to "talk-off"
and tolerance to the presence of interfering signals ("third
tones") and noise. When the detector recognizes the
simultaneous presence of two valid tone (referred to as
"signal condition" in some industry specifications), it
raises the "early steering" flag (ESt). Any subsequent loss
of signal-condition will cause ESt to fall.
FLOW FHIGH NO
TOE
Q4
Q3
Q2
Q1
697
1209
1
H
0
0
0
1
697
1336
2
H
0
0
1
0
697
1477
3
H
0
0
1
1
770
1209
4
H
0
1
0
0
770
1336
5
H
0
1
0
1
770
1477
6
H
0
1
1
0
－ 6 －
852
1209
7
H
0
1
1
1
852
1336
8
H
1
0
0
0
852
1477
9
H
1
0
0
1
941
1336
0
H
1
0
1
0
941
1209
*
H
1
0
1
1
941
1477
#
H
1
1
0
0
697
1633
A
H
1
1
0
1
770
1633
B
H
1
1
1
0
MOSA ELECTRONICS
852
1633
C
H
1
1
1
1
941
1633
D
H
0
0
0
0
ANY
L
Z
Z
Z
Z
MS8870
DTMF Receiver
shown in Fig. 6 is applicable. Component values are
chosen according to the formula : tREC = tPD + tGPT
tID = tDA + tGTA
The value of tDP is a device parameter (see table) and
tREC is the minimum signal duration to be recognized by
the receiver. A value for C of 0.1 µF is recommended
for most applications, leaving R to be selected by the
designer.
L = LOGIC LOW, H = LOGIC HIGH, Z = HIGH IMPEDANCE
Figure 5. Functional Decode Table
Figure 6. Basic Steering Circuit
Steering Circuit
Before registration of a decoded tone pair, the receiver
checks for a valid signal duration (referred to as character
recognition condition). This check is performed by an
external RC time constant driven by ESt. A logic high on
ESt causes Vc (see Fig. 6) to rise as the capacitor
discharges.
Provided signal condition is maintained (ESt remains
high) for the validation period (tGTP), Vc reaches the
threshold (VTSt) of the steering logic to register the tone
pair, latching its corresponding 4-bit code (see Fig. 5) into
the output latch. At this point the GT output is activated
and drives Vc to VDD. GT continues to drive high as long
as ESt remains high. Finally, after a short delay to allow
the output latch to settle, the delayed steering output flag
(StD) goes high, signaling that a received tone pair has
been registered. The contents of the output latch are made
available on the 4-bit output bus by raising the three state
control input (TOE) to a logic high. The steering circuit
works in reverse to validate the interdigit pause between
signals. Thus, as well as rejecting signals too short to be
considered valid, the receiver will tolerate signal
interruptions (drop out) too short to be considered a valid
pause. This facility, together with the capability of
selecting the steering time constants externally, allows the
designer to tailor performance to meet a wide variety of
system requirements.
Figure 7. Guard Time Adjustment
Different steering arrangements may be used to select
independently the guard times for tone present (tGTP) and
tone absent (tGTA). This may be necessary to meet system
specifications which place both accept and reject limits on
both tone duration and interdigital pause. Guard time
adjustment also allows the designer to tailor system
parameters such as talk off and noise immunity. Increasing
tREC improves talk-off performance since it reduces the
probability that tones simulated by speech will maintain
signal condition long enough to be registered.
Alternatively, a relatively short tREC with noisy
environments where fast acquisition time and immunity to
tone drop-outs are required. Design information for guard
time adjustment is shown in Figure 7.
Differential Input Configuration
Guard Time Adjustment
In many situations not requiring selection of tone
duration and interdigital pause, the simple steering circuit
－ 7 －
MOSA ELECTRONICS
MS8870
DTMF Receiver
The input arrangement of the MS8870 provides a
differential-input operational amplifier as well as a bias
source (VRef) which is used to bias the inputs at mid-rail.
Provision is made for connection of a feedback resistor to
the op-amp output (GS) for adjustment of gain. In a singleended configuration, the input pins are connected as shown
in Fig. 2 with the op-amp connected for unity gain and
VRef biasing the input at ½ VDD. Fig. 8 shows the
differential configuration, which permits the adjustment of
gain with the feedback resistor R5.
DIFFERENTIAL INPUT AMPUT AMPLIFIER
C1 = C2 = 10nF
R1 = R4 = R5 = 100 K
All resistors are +/- 1% tolerence
Ω
R2 = 60 K Ω , R3 = 37.5K Ω
All capacitors are +/- 5% tolerence
R2 x R5
R2 + R5
R3 =
R5
R1
VOLTAGE GAIN (Av diff) =
INPUT IMPEDENCE
(Z
INDIFF
) = 2
R
2
1
+
1
ωC
2
Figure 8. Differential Input Configuration
－ 8 －