CM8870/70C CALIFORNIA MICRO DEVICES CMOS Integrated DTMF Receiver Features Applications • Full DTMF receiver • PABX • Less than 35mW power consumption • Central office • Industrial temperature range • Mobile radio • Uses quartz crystal or ceramic resonators • Remote control • Adjustable acquisition and release times • Remote data entry • 18-pin DIP, 18-pin DIP EIAJ, 18-pin SOIC, 20-pin PLCC • Call limiting • CM8870C • Paging systems • Telephone answering systems — Power down mode — Inhibit mode — Buffered OSC3 output (PLCC package only) • CM8870C is fully compatible with CM8870 for 18-pin devices by grounding pin 5 and pin 6. Product Description tone rejection. The CM8870/70C decoder uses digital counting techniques for the detection and decoding of all 16 DTMF tone pairs into a 4-bit code. This DTMF receiver minimizes external component count by providing an on-chip differential input amplifier, clock generator, and a latched three-state interface bus. The on-chip clock generator requires only a low cost TV crystal or ceramic resonator as an external component. The CAMD CM8870/70C provides full DTMF receiver capability by integrating both the band-split filter and digital decoder functions into a single 18-pin DIP, SOIC, or 20-pin PLCC package. The CM8870/70C is manufactured using state-of-the-art CMOS process technology for low power consumption (35mW, MAX) and precise data handling. The filter section uses a switched capacitor technique for both high and low group filters and dial Block Diagram VDD VSS VREF INH – BIAS CIRCUIT PD CHP POWER IN+ + IN– – + Q1 CHP BIAS CHIP REF DIAL TONE FILTER HIGH GROUP FILTER Q2 ZERO CROSSING DETECTORS DIGITAL DETECTION ALGORITHM CODE CONVERTER AND LATCH Q3 LOW GROUP FILTER GS Q4 TO ALL CHIP CLOCKS St GT OSC 1 OSC 2 OSC 3 St/GT ESt STEERING LOGIC StD TOE C1581000 © 2000 California Micro Devices Corp. All rights reserved. 215 Topaz Street, Milpitas, California 95035 11/07/2001 Tel: (408) 263-3214 Fax: (408) 263-7846 www.calmicro.com 1 CM8870/70C CALIFORNIA MICRO DEVICES Absolute Maximum Ratings: (Note 1) This device contains input protection against damage due to high static voltages or electric fields; however, precautions should be taken to avoid application of voltages higher than the maximum rating. Notes: 1. Exceeding these ratings may cause permanent damage, functional operation under these conditions is not implied. Absolute Maximum Ratings Symbol Parameter Value VDD Power Supply Voltage (V DD /V SS ) 6V MAX Vdc Voltage on any Pin V SS – 0.3V to V DD + 0.3V IDD Current on any Pin 10mA MAX TA Operating Temperature –40˚C to 85˚C TS Storage Temperature –65˚C to 150˚C DC Characteristics: All voltages referenced to VSS, VDD = 5V ±5%, TA = –40°C to 85°C unless otherwise noted. DC Characteristics Symbol VDD Parameter Operating Supply Voltage IDD Operating Supply Current IDDQ Test Conditions Standby Supply Current PO Power Consumption f = 3.579 MHz; VDD = 5V Low Level Input Voltage VDD = 5V VIH TYP MAX 5.25 UNIT V 3.0 7.0 mA 25 µA 35 mW 1.5 V PD = VDD VIL IIH/LIL MIN 4.75 High Level Input Voltage VDD = 5V Input Leakage Current VIN = VSS = VDD (Note 1) 15 3.5 V 0.1 ISO Pull Up (Source) Current on TOE TOE = 0V, VDD = 5V RIN Input Impedance, (IN+, IN–) @ 1KHz 8 6.5 VTst Steering Threshold Voltage VDD = 5V 2.2 VOL Low Level Output Voltage VDD = 5V, No Load VOH High Level Output Voltage VDD = 5V, No Load 4.97 IOL Output Low (Sink) Current VOUT = 0.4V 1.0 2.5 IOH 0.8 Output High (Source) Current VOUT = 4.6V 0.4 VREF Output Voltage VDD = 5.0V, No Load 2.4 ROR Output Resistance VREF µA 20 10 µA MΩ 2.5 V 0.03 V V mA mA 2.7 10 V kΩ Operating Characteristics: All voltages referenced to VSS, VDD = 5V ±5%, T A = –40°C to 85°C unless otherwise noted. Gain Setting Amplifier Operating Characteristics Symbol IIN Parameter Input Leakage Current RIN Input Resistance VOS Input Offset Voltage Test Conditions V SS < V IN < V DD MIN TYP MAX ±100 10 UNIT nA MΩ ±25 mV PSRR Power Supply Rejection 1 KHz (Note 12) 50 dB CMRR Common Mode Rejection –3V < V IN < 3V 40 dB AVOL DC Open Loop Voltage Gain 32 dB fc Open Loop Unity Gain Bandwidth 0.3 MHz VO Output Voltage Swing CL Maximum Capacitive Load (GS) RL Maximum Resistive Load (GS) Vcm Common Mode Range (No Load) R L ≥ 100 KW to V SS 4 VP-P 100 50 No Load 2.5 pF KΩ VP-P ©2000 California Micro Devices Corp. All rights reserved. 2 215 Topaz Street, Milpitas, California 95035 Tel: (408) 263-3214 Fax: (408) 263-7846 www.calmicro.com 11/07/2001 CM8870/70C CALIFORNIA MICRO DEVICES AC Characteristics: All voltages referenced to VSS, VDD = 5.0V ±5%, TA = –40°C to +85°C, fCLK = 3.579545 MHz using test circuit in Figure 1 unless otherwise noted. AC Characteristics Symbol Parameter Valid Input Signal Levels (each tone of composite signal) Notes MIN –29 1, 2, 3, 4, 5, 8 Positive Twist Accept TYP 27.5 2, 3, 4, 8 Negative Twist Accept MAX 1 UNIT dBm 869 mVRMS 10 dB 10 dB 1.5%±2Hz Norm. Freq. Deviation Aceept Limit 2, 3, 5, 8, 10 Freq. Deviation Reject Limit 2, 3, 5 Third Tone Tolerance 2, 3, 4, 5, 8, 9, 13, 14 –16 dB Noise Tolerance 2, 3, 4, 5, 6, 8, 9 –12 dB ±3.5% Norm. Dial Tone Tolerance 2, 3, 4,5, 7, 8, 9 tDP Tone Present Detection Time Refer to Timing Diagram 5 8 14 ms tDA Tone Absent Dectection Time Refer to Timing Diagram 0.5 3 8.5 ms MIN Tone Duration Accept 15 40 ms 40 ms 6 11 µs 16 µs tREC tID MAX Tone Duration Reject 15 MIN Interdigit Pause Accept 15 tDO MAX Interdigit Pause Reject 15 tPQ Propagation Delay (St to Q) TOE = VDD 22 dB 20 ms 20 µs tPStD Propagation Delay (St to StD) TOE = VDD 9 tQStD Output Data Set Up (Q to StD) TOE = VDD 3.4 µs tPTE Propagation Delay (TOE to Q) tPTD fCLK Crystal/Clock Frequency CLO Clock Ouput (OSC 2) Enable RL = 10KΩ 50 ns Disable CL = 50pf 300 ns 3.5759 3.5795 Capacitive Load 3.5831 MHz 30 pF Notes: 1. dBm = decibels above or below a reference power of 1mW into a 600Ω load. 2. Digit sequence consists of all 16 DTMF tones. 3. Tone duration = 40ms. Tone pause = 40ms. 4. Nominal DTMF frequencies are used. 5. Both tones in the composite signal have an equal amplitude. 6. Bandwidth limited (0 to 3KHz) Gaussian Noise. 7. The precise dial tone frequencies are (350Hz and 440Hz) ±2%. 8. For an error rate of better than 1 in 10,000 9. Referenced to lowest level frequency component in DTMF signal. 10. Minimum signal acceptance level is measured with specified maximum frequency deviation. 11. Input pins defined as IN+, IN–, and TOE. 12. External voltage source used to bias VREF. 13. This parameter also applies to a third tone injected onto the power supply. 14. Referenced to Figure 1. Input DTMF tone level at –28dBm. 15. Times shown are obtained with circuit in Figure 1 (User adjustable). © 2000 California Micro Devices Corp. All rights reserved. 215 Topaz Street, Milpitas, California 95035 11/07/2001 Tel: (408) 263-3214 Fax: (408) 263-7846 www.calmicro.com 3 CM8870/70C CALIFORNIA MICRO DEVICES Timing Diagram D EVENTS A B C E F G INTERDIGIT PAUSE tREC tREC VIN tID TONE # N tDO TONE DROPOUT TONE # N+1 tDP TONE # N+1 tDA ESt tGTA tGTP VTSt St/Gt DATA OUTPUTS Q1-Q4 tPQ DECODED TONE # N+1 DECODED TONE # N DECODED TONE # n+1 HIGH IMPEDANCE tPStD StD OUTPUT tPTD TOE tPTE tQStD Explanation of Events Explanation of Symbols A. Tone bursts detected, tone duration invalid, outputs not updated. VIN ESt B. Tone #n detected, tone duration valid, tone decoded and latched in outputs. St/GT C. End of tone #n detected, tone absent duration valid, outputs remain latched until next valid tone. D. Outputs switched to high impedance state. Q1-Q4 StD E. Tone #n + 1 detected, tone duration valid, tone decoded and latched in outputs (currently high impedance). TOE F. Acceptable dropout of tone #n + 1, tone absent duration invalid, outputs remain latched. tREC G. End of tone #n + 1 detected, tone absent duration valid, outputs remain latched until next valid tone. tREC tID tDO tDP tDA tGTP tGTA DTMF composite input signal. Early Steering Output. Indicates detection of valid tone frequencies. Steering input/guard time output. Drives external RC timing circuit. 4-bit decoded tone output. Delayed Steering Output. Indicates that valid frequencies have been present/absent for the required guard time, thus constituting a valid signal. Tone Output Enable (input). A low level shifts Q1-Q4 to its high impedance state. Maximum DTMF signal duration not detected as valid. Minimum DTMF signal duration required for valid recognition. Minimum time between valid DTMF signals. Maximum allowable drop-out during valid DTMF signal. Time to detect the presence of valid DTMF signals. Time to detect the absence of valid DTMF signals. Guard time, tone present. Guard time, tone absent. ©2000 California Micro Devices Corp. All rights reserved. 4 215 Topaz Street, Milpitas, California 95035 Tel: (408) 263-3214 Fax: (408) 263-7846 www.calmicro.com 11/07/2001 CM8870/70C CALIFORNIA MICRO DEVICES Functional Description The CAMD CM8870/70C DTMF Integrated Receiver provides the design engineer with not only low power consumption, but high performance in a small 18-pin DIP, SOIC, or 20-pin PLCC package configuration. The CM8870/70C’s internal architecture consists of a band-split filter section which separates the high and low tones of the received pair, followed by a digital decode (counting) section which verifies both the frequency and duration of the received tones before passing the resultant 4-bit code to the output bus. Filter Section Separation of the low-group and high-group tones is achieved by applying the dual-tone signal to the inputs of two 9th-order switched capacitor bandpass filters. The bandwidths of these filters correspond to the bands enclosing the low-group and high-group tones (See Figure 3). The filter section also incorporates notches at 350Hz and 440Hz which provides excellent dial tone rejection. Each filter output is followed by a single order switched capacitor section which smooths the signals prior to limiting. Signal limiting is performed by high-gain comparators. These comparators are provided with a hysteresis to prevent detection of unwanted low-level signals and noise. The outputs of the comparators provide full-rail logic swings at the frequencies of the incoming tones. Decoder Section The CM8870/70C decoder uses a digital counting technique to determine the frequencies of the limited tones and to verify that these tones correspond to standard DTMF frequencies. A complex averaging algorithm is used to protect against tone simulation by extraneous signals (such as voice) while providing tolerance to small frequency variations. The averaging algorithm has been developed to ensure an optimum combination of immunity to “talk-off” and tolerance to the presence of interfering signals (third tones) and noise. When the detector recognizes the simultaneous presence of two valid tones (known as “signal condition”), it raises the “Early Steering” flag (ESt). Any subsequent loss of signal condition will cause ESt to fall. Steering Circuit Before the registration of a decoded tone pair, the receiver checks for a valid signal duration (referred to as “character-recognition-condition”). This check is performed by an external RC time constant driven by ESt. A logic high on ESt causes VC (See Figure 4) to rise as the capacitor discharges. Providing signal condition is maintained (ESt remains high) for the validation period (tGTP), VC reaches the threshold (VTSt) of the steering logic to register the tone pair, thus latching its corresponding 4-bit code (See Figure 2) into the output latch. At this point, the GT output is activated and drives VC to VDD. GT continues to drive high as long as ESt remains high, signaling that a received tone pair has been registered. The contents of the output latch are made available on the 4-bit output bus by raising the three-state control input (TOE) to a logic high. The steering circuit works in reverse to validate the interdigit pause between signals. Thus, as well as rejecting signals too short to be considered valid, the receiver will tolerate signal interruptions (drop outs) too short to be considered a valid pause. This capability together with the capability of selecting the steering time constants externally, allows the designer to tailor performance to meet a wide variety of system requirements. Guard Time Adjustment In situations which do not require independent selection of receive and pause, the simple steering circuit of Figure 4 is applicable. Component values are chosen according to the following formula: tREC = tDP + tGTP tGTP = 0.67 RC The value of tDP is a parameter of the device and tREC is the minimum signal duration to be recognized by the receiver. A value for C of 0.1µF is recommended for most applications, leaving R to be selected by the designer. For example, a suitable value of R for a tREC of 40ms would be 300K. A typical circuit using this steering configuration is shown in Figure 1. The timing requirements for most telecommunication applications are satisfied with this circuit. Different steering arrangements may be used to select independently the guard-times for tone-present (tGTP) and tone absent (tGTA). This may be necessary to meet system specifications which place both accept and reject limits on both tone duration and interdigit pause. Guard time adjustment also allows the designer to tailor system parameters such as talk-off and noise immunity. Increasing tREC improves talk-off performance, since it reduces the probability that tones simulated by speech will maintain signal condition for long enough to be registered. On the other hand, a relatively short tREC with a long tDO would be appropriate for extremely noisy environments where fast acquisition time and immunity to drop-outs would be requirements. Design information for guard time adjustment is shown in Figure 5. © 2000 California Micro Devices Corp. All rights reserved. 215 Topaz Street, Milpitas, California 95035 11/07/2001 Tel: (408) 263-3214 Fax: (408) 263-7846 www.calmicro.com 5 CM8870/70C CALIFORNIA MICRO DEVICES Input Configuration Clock Circuit The input arrangement of the CM8870/70C provides a differential input operational amplifier as well as a bias source (VREF) which is used to bias the inputs at mid-rail. The internal clock circuit is completed with the addition of a standard television color burst crystal or ceramic resonator having a resonant frequency of 3.579545MHz. The CM8870C in a PLCC package has a buffered oscillator output (OSC3) that can be used to drive clock inputs of other devices such as a microprocessor or other CM887X’s as shown in Figure 7. Multiple CM8870/70Cs can be connected as shown in figure 8 such that only one crystal or resonator is required. Provision is made for connection of a feedback resistor to the op-amp output (GS) for adjustment of gain. In a single-ended configuration, the input pins are connected as shown in Figure 1, with the op-amp connected for unity gain and VREF biasing the input at ½ VDD. Figure 6 shows the differential configuration, which permits the adjustment of gain with the feedback resistor R5. Pin Function Name IN+ Function Non-inverting input Discription Connection to the front-end differential amplifier IN– Inverting input Connection to the front-end differential amplifier GS Gain select Gives access to output of front-end differential amplifier for connection of feedback resistor. VREF Reference output Voltage (nominally VDD/2) May be used to bias the inputs at mid-rail. INH Inhibits detection of tones Represents keys A, B, C, and D OSC3 Digital buffered oscillator output PD Power down Logic high powers down the device and inhibits the oscillator. OSC1 Clock input 3.579545MHz crystal connected between these pins completes internal oscillator OSC2 Clock output 3.579545MHz crystal connected between these pins completes internal oscillator VSS Negative power supply Normally connected to OV TOE Three-state output enable (Input) Logic high enables the outputs Q1-Q4. Internal pull-up. Three-state ouputs When enabled by TOE, provides the code corresponding to the last valid tone pair received. (See Figure 2). StD Delayed Steering output Presents a logic high when a received tone pair has been registered and the output latch is updated. Returns to logic low shen the voltage on St/GT falls below VTSt. ESt Early steering output Presents logic high immediately when the digital algorithm detects a recongnizable tone pair (signal condition). Any momentary loss of signal condition will cause ESt to return to a logic low. St/Gt Steering input/guard time output (bidirectional) A voltage greater than VTSt detected at St causes the device to register the dectected tone pair. The GT output acts to reset the external steering time constrant, and its state is a function of ESt and the voltage on St. (See Figure 2). VDD Positve power supply Q1 Q2 Q3 Q4 IC Internal connection Must be tied to VSS (for 8870 configuration only). ©2000 California Micro Devices Corp. All rights reserved. 6 215 Topaz Street, Milpitas, California 95035 Tel: (408) 263-3214 Fax: (408) 263-7846 www.calmicro.com 11/07/2001 CM8870/70C CALIFORNIA MICRO DEVICES 5V CM8870 1 0.1µF 100KΩ 2 3 4 100KΩ 5 6 7 3.58 MHz 8 9 0.1µF IN+ VDD IN– St/GT GS ESt VREF StD INH Q4 PD Q3 OSC 1 Q2 OSC 2 Q1 TOE VSS 18 17 16 300KΩ 15 14 13 12 11 10 5V CM8870C 1 0.1µF 100KΩ 2 3 4 100KΩ 5 6 7 3.58 MHz 8 9 IN+ 0.1µF VDD IN– St/GT GS ESt VREF StD INH Q4 PD Q3 OSC 1 Q2 OSC 2 Q1 VSS TOE 18 17 16 300KΩ 15 14 13 12 11 10 All resistors are ±1% tolerance. All capacitors are ±5% tolerance. Figure 1. Single Ended Input Configuration Functional Diode Table F LOW 697 F HIGH 1209 KEY 1 TOW H Q4 0 Q3 0 Q2 0 Q1 1 697 1336 2 H 0 0 1 0 697 1477 3 H 0 0 1 1 770 1209 4 H 0 1 0 0 770 1336 5 H 0 1 0 1 770 1477 6 H 0 1 1 0 852 1209 7 H 0 1 1 1 852 1336 8 H 1 0 0 0 852 1477 9 H 1 0 0 1 941 1336 0 H 1 0 1 0 941 1209 * H 1 0 1 1 941 1477 # H 1 1 0 0 697 1633 A H 1 1 0 1 770 1633 B H 1 1 1 0 852 1633 C H 1 1 1 1 941 1633 D H 0 0 0 0 - - ANY L Z Z Z Z L Logic Low, H = Logic, Z = High Impedance Figure 2. Functional Decode Table © 2000 California Micro Devices Corp. All rights reserved. 215 Topaz Street, Milpitas, California 95035 11/07/2001 Tel: (408) 263-3214 Fax: (408) 263-7846 www.calmicro.com 7 CM8870/70C CALIFORNIA MICRO DEVICES ATTENUATION dB 0 VDD tGTP = (R1C) In C 10 tGTA = (RPC) In St/GT 20 VDD VDD – VTST VDD VTST R1 30 R2 RP = 40 R1R2 R1 + R2 ESt (A.) Decreasing tGTA (tGTP > tGTA) 50 0 X Y 1K AB C D E F FREQUENCY Hz PRECISE DIAL TONES X = 350Hz y = 440Hz 2K G H VDD DTMF TONES A = 607Hz B = 770Hz C = 852Hz D = 841Hz tGTP = (RPC) In C E = 1209Hz F = 1336Hz G = 1477Hz H = 1633Hz tGTA = (R1C) In St/GT VDD VDD – VTST VDD VTST R1 R2 Figure 3. Typical Filter Characteristic RP = R1R2 R1 + R2 ESt (B.) Decreasing tGTP (tGTP < tGTA) Figure 5. Guard Time Adjustment VDD C VDD St/GT R VC ESt C1 StD R1 IN+ tGTA = (RC) In tGTP = (RC) In + VDD VTST VDD VDD – VTST – C2 R4 CM8870 IN– R5 R3 Figure 4. Basic Steering Circuit GS R2 VREF All resistors are –1% tolerance. All capacitors are –5% tolerance. DIFFERENTIAL INPUT AMPLIFIER C1 = C2 = 10nF R1 = R4 = R4 =100 KΩ R2 = 60KΩ, R3 = 37.5KΩ R3 = R2R5 R2 + R5 VOLTAGE GAIN (Av diff) = R5 R1 IMPUT IMPEDANCE (Xxxx) = 2 R2 + 1 wC 2 Figure 6. Differential Input Configuration ©2000 California Micro Devices Corp. All rights reserved. 8 215 Topaz Street, Milpitas, California 95035 Tel: (408) 263-3214 Fax: (408) 263-7846 www.calmicro.com 11/07/2001 CM8870/70C CALIFORNIA MICRO DEVICES OSC1 OSC2 OSC1 OSC2 OSC3 OSC1 OSC2 OSC1 OSC2 OSC1 of other CM887X's Clock input of other devices 3.58MHz 30pF St/GT GS 3 16 ESt GS 3 16 ESt VREF 4 15 StD VREF 4 15 StD INH 5 14 Q4 IC* 5 14 Q4 VREF 5 IC* 6 13 Q3 IC* 6 13 Q3 OSC 1 7 12 Q2 OSC 1 7 12 OSC 2 8 11 Q1 OSC 2 8 VSS 9 10 TOE VSS 9 18 ESt GS 4 17 StD VREF 5 IC* 6 16 NC PD 6 16 NC Q2 IC* 7 15 Q4 OSC 3 7 15 Q4 11 Q1 OSC 1 8 14 Q3 OSC 1 8 14 Q3 10 TOE P – Plastic DIP (18) P – Plastic DIP (18) PE – PLCC (20) F – Plastic SOP EIAJ (18) F – Plastic SOP EIAJ (18) *– S – SPIC (18) S – SOIC (18) 18 ESt 17 StD Q2 13 Q1 12 9 OSC 2 TOE 11 CM8870C Q2 13 Q1 12 TOE 11 9 OSC 2 VSS 10 CM8870 VSS 10 GS 4 19 St/GT VDD 17 1 IN– 18 2 20 VDD 1 IN– 3 GS IN+ St/GT 2 IN+ VDD 17 19 St/GT 18 2 1 IN– 1 IN– 20 VDD 3 NC IN+ 2 IN+ Pin Assignments CM8870 30pF Figure 8. CM8870/70C Crystal Connection Figure 7. CM8870C Crystal Connection (PLCC Package Only) CM8870C 30pF PE – PLCC (20) Connected to VSS Ordering Information Example: CM8870 CM8870C P I Product Identification Number Package P — Plastic Dip (18) F — Plastic SOP EIAJ (18) PE — PLCC (20) S — SOIC (18) Temperature/Processing None — 0˚C to 70˚C, ±5% P.S. Tol. I — –40˚C to 85˚C, ±5% P.S. Tol. © 2000 California Micro Devices Corp. All rights reserved. 215 Topaz Street, Milpitas, California 95035 11/07/2001 Tel: (408) 263-3214 Fax: (408) 263-7846 www.calmicro.com 9