APA2178 100mW Stereo Cap-Free Headphone Driver Features • • • • • • • • • • • • General Description No Output Capacitor Required The APA2178 is a stereo, fixed gain, Cap-Free headphone driver which is available in a WLCSP2x2-16 package. Operating Voltage: 1.8V~4.5V The APA2178 is a ground-reference output, and doesn’t need the output capacitors for DC blocking. The advan- Supply Current – IDD=5mA at VDD=3.3V tages of eliminating the output capacitor are saving the cost, PCB’s space, and component height. Low Shutdown Current – IDD=1µA at VDD=3.3V The built-in gain setting can minimize the external component counts and save the PCB space. High PSRR pro- Meeting VISTA Requirements Output Power at 1% THD+N – 70mW, at VDD=3.3V, RL = 16Ω at 10% THD+N – 100mW, at VDD=3.3V, RL = 16Ω vides increased immunity to noise and RF rectification. In addition to these features, a fast startup time and small package size make the APA2178 an ideal choice for portable multimedia device. Moreover, the APA2178 is also equipped other features. For example, it is capable of driving 100mW at 3.3V into Less External Components Required High PSRR: 78dB at 217Hz 16Ω, at THD+N=10% and provides thermal and short circuit protection. Short-Circuit and Thermal Protection ± 8KV ESD Performance Applications Surface-Mount Packaging – WLCSP2x2-16 • • • • Lead Free and Green Devices Available (RoHS Compliant) Handsets PDAs Portable multimedia devices Notebooks Simplified Application Circuit R-CH Input RIN ROUT L-CH Input Stereo Headphone LIN APA2178 LOUT Shutdown Control RSD LSD ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and advise customers to obtain the latest version of relevant information to verify before placing orders. Copyright ANPEC Electronics Corp. Rev. A.3 - Jul., 2009 1 www.anpec.com.tw APA2178 Ordering and Marking Information APA2178 Package Code HA : WLCSP2x2-16 Operating Ambient Temperature Range I : -40 to 85 oC Handling Code TR : Tape & Reel Assembly Material G : Halogen and Lead Free Device Assembly Material Handling Code Temperature Range Package Code AP78 X APA2178 HA : X - Date Code Note: ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which are fully compliant with RoHS. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J-STD-020C for MSL classification at lead-free peak reflow temperature. ANPEC defines “Green” to mean lead-free (RoHS compliant) and halogen free (Br or Cl does not exceed 900ppm by weight in homogeneous material and total of Br and Cl does not exceed 1500ppm by weight). Pin Configuration CP+ (A4) PGND (B4) CP(C4) CVSS (D4) PVDD (A3) NC (B3) NC (C3) VSS (D3) GND (A2) LSD (B2) ROUT (C2) LOUT (D2) RIN (A1) RSD (B1) LIN (C1) VDD (D1) X Date Code Marking PIN A1 Copyright ANPEC Electronics Corp. Rev. A.3 - Jul., 2009 2 www.anpec.com.tw APA2178 Absolute Maximum Ratings (Note 1) (Over operating free-air temperature range unless otherwise noted.) Symbol Parameter Rating Unit VPVDD_VDD PVDD to VDD Voltage -0.3 to 0.3 V VPGND_GND PGND to GND Voltage -0.3 to 0.3 V PVDD, VDD Supply Voltage (VDD and PVDD to GND and PGND) -0.3 to 5.5 V VRSD, VLSD Input Voltage (RSD and LSD to GND) GND-0.3 to VDD+0.3 V VSS, CVSS VSS and CVSS to GND and PGND Voltage -5.5 to 0.3 V VSS-0.3 to VDD+0.3 V V VROUT, VLOUT ROUT and LOUT to GND Voltage VCP+ CP+ to PGND Voltage PGND-0.3 to PVDD+0.3 VCP- CP- to PGND Voltage PVSS-0.3 to PGND+0.3 TA Operating Ambient Temperature Range TJ Maximum Junction Temperature TSTG TSDR PD Storage Temperature Range Maximum Soldering Temperature Range, 10 Seconds Power Dissipation V -40 to 85 ο 150 ο -65 to +150 ο 260 ο C C C C Internally Limited W Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Thermal Characteristics Symbol θJA Parameter Junction-to-Ambient Resistance in Free Air Typical Value Unit (Note 2) WLCSP2x2-16 160 o C/W Note 2: Please refer to “Thermal Pad Consideration”. 2 layered 5 in2 printed circuit boards with 2oz trace and copper through several thermal vias. The thermal pad is soldered on the PCB. Recommended Operating Conditions (Note 3) Symbol Parameter VDD Supply Voltage VIH High Level Threshold Voltage VIL Low Level Threshold Voltage VICM Common Mode Input Voltage RSD, LSD RSD, LSD Range Unit 1.8 ~ 4.5 V 0.6VDD ~ VDD V 0 ~ 0.3VDD ~ VDD-0.5 V V TA Ambient Temperature -40 ~ 85 o TJ Junction Temperature -40 ~ 125 o RL Headphone Resistance 14 ~ C C Ω Note 3 : Refer to the typical application circuit. Copyright ANPEC Electronics Corp. Rev. A.3 - Jul., 2009 3 www.anpec.com.tw APA2178 Electrical Characteristics Unless otherwise specified, these specifications apply over VDD=PVDD=3.3V, VPGND=VGND=0V, and CCPO=CCPF=1µF. Typical values are at TA=25oC. Symbol Parameter AP2178 Test Conditions Unit Min. Typ. Max. 1.8 - 4.5 V VDD Supply Voltage IDD Supply Current - 5 10 mA ISD Shutdown Current RSD =LSD= 0V - 1 2 µA Input Current RSD, LSD - 0.1 - µA 440 520 580 kHz 6 7 9 Ω Rising VDD Threshold 1.67 1.7 1.73 V Falling VDD Threshold 1.57 1.6 1.63 V -1.55 -1.5 -1.45 V/V Ii CHARGE PUMP FOSC Switching Frequency Charge Pump Requirement Req Resistance POWER-ON-RESET AMPLIFIERS AV ∆AV Internal Voltage Gain No Load Gain Match Ri Input Resistance SR Slew Rate VOS Output Offset Voltage Vn Noise Output Voltage VDD=1.8V to 4.5V, RL = 32Ω - 1 - % 12 14 16 kΩ - 2.5 - V/µs -5 - 5 mV - 15 - µVrms - dB - pF VDD=1.8V to 4.5V,Vrr=200mVrms PSRR Power Supply Rejection Ratio fin= 217Hz - fin=1kHz fin= 20kHz CL Tstart-up OUTR, OUTL 78 75 55 - 400 Start-up Time - 120 - µs ESD Protection - ±8 - kV 150 - Maximum Capacitive Load VDD=4.5V, TA=25° C THD+N = 1%, fin=1kHz RL = 16Ω PO Output Power (Stereo, in Phase) 120 RL = 32Ω 145 mW THD+N = 10%, fin=1kHz 215 RL = 16Ω 180 RL = 32Ω - 205 fin = 1kHz 0.03 PO = 105mW, RL = 16Ω THD+N Total Harmonic Distortion Pulse Noise Copyright ANPEC Electronics Corp. Rev. A.3 - Jul., 2009 PO = 100mW, RL = 32Ω - 0.02 VO = 2.2Vrms, RL = 300Ω 0.005 VO = 2.2Vrms, RL = 10kΩ 0.003 4 - % www.anpec.com.tw APA2178 Electrical Characteristics (Cont.) Unless otherwise specified, these specifications apply over VDD=PVDD=3.3V, VPGND=VGND=0V, and CCPO=CCPF=1µF. Typical values are at TA=25oC. Symbol Parameter Test Conditions APA2178 Min. Typ. Max. Unit VDD=4.5V, TA=25° C (CONT.) fin = 1kHz 75 PO = 15mW, RL = 16Ω Crosstalk Channel Separation PO = 15mW, RL = 32Ω - 80 VO = 0.31Vrms, RL = 300Ω 95 VO = 0.31Vrms, RL = 10kΩ 100 - dB - dB With A-weighting Filter S/N Signal-to-Noise Ratio PO = 100mW, RL = 32Ω - 100 105 VO = 3.1Vrms, RL = 10kΩ VDD=3.3V, TA=25° C THD+N = 1%, fin=1kHz 70 RL = 16Ω PO Output Power (Stereo, in Phase) 55 RL = 32Ω - 70 mW THD+N = 10%, fin=1kHz 100 RL = 16Ω 80 RL = 32Ω - 100 fin = 1kHz 0.03 PO = 50mW, RL = 16Ω THD+N Total Harmonic Distortion Pulse Noise PO = 50mW, RL = 32Ω - 0.02 VO = 1.6Vrms, RL = 300Ω 0.005 VO = 1.6Vrms, RL = 10kΩ 0.003 - % - dB - dB fin = 1kHz 75 PO = 7mW, RL = 16Ω Crosstalk Channel Separation PO = 7mW, RL = 32Ω - 85 VO = 0.23Vrms, RL = 300Ω 95 VO = 0.23Vrms, RL = 10kΩ 95 With A-weighting Filter S/N Signal-to-Noise Ratio PO = 50mW, RL = 32Ω - 95 100 VO = 2.3Vrms, RL = 10kΩ VDD=1.8V, TA=25° C THD+N = 1%, fin=1kHz PO Output Power (Stereo, in Phase) RL = 32Ω 10 13 15 20 THD+N = 10%, fin=1kHz RL = 32Ω mW - fin = 1kHz THD+N Total Harmonic Distortion Pulse Noise Copyright ANPEC Electronics Corp. Rev. A.3 - Jul., 2009 PO = 9mW, RL = 32Ω - 0.03 VO = 0.85Vrms, RL = 300Ω 0.007 VO = 0.85Vrms, RL = 10kΩ 0.005 5 - % www.anpec.com.tw APA2178 Electrical Characteristics (Cont.) Unless otherwise specified, these specifications apply over VDD=PVDD=3.3V, VPGND=VGND=0V, and CCPO=CCPF=1µF. Typical values are at TA=25oC. Symbol Parameter Test Conditions APA2178 Min. Typ. Max. Unit VDD=1.8V, TA=25° C (CONT.) fin = 1kHz Crosstalk Channel separation PO = 1.3mW, RL = 32Ω - 80 VO = 0.12Vrms, RL = 300Ω 85 VO = 0.12Vrms, RL = 10kΩ 90 - dB - dB With A-weighting Filter S/N Signal-to-Noise Ratio PO = 9mW, RL = 32Ω VO =1.2Vrms, RL = 10kΩ Copyright ANPEC Electronics Corp. Rev. A.3 - Jul., 2009 6 - 95 95 www.anpec.com.tw APA2178 Typical Operating Characteristics THD+N vs. Output Voltage 10 THD+N vs. Output Power 10 VDD=4.5V fin=1kHz Cin=1µF BW<80kHz 1 VDD=4.5V RL=16Ω Cin=1µF BW<80kHz RL=32Ω 0.1 RL=16Ω 0.01 0.001 THD+N (%) THD+N (%) 1 fin=20kHz 0.1 fin=1kHz RL=300Ω 0 500m 1 2 Output Voltage (V) RL=10kΩ 3 4 0.01 fin=20Hz 1m 10m THD+N vs. Output Power 10 THD+N vs. Frequency Stereo, 180o out of Phase VDD=4.5V RL=16Ω Cin=1µF PO=105mW BW<22kHz 1 THD+N (%) THD+N (%) 600m 10 VDD=4.5V fin=1kHz RL=16Ω Cin=1µF BW<80kHz 1 100m Output Power (W) Stereo, in Phase 0.1 0.1 Left Channel Mono Right Channel 0.01 0.01 0 70m 140m 210m 280m 0.006 350m 20 100 Output Power (W) Crosstalk vs. Frequency -30 -40 -50 -60 50µ VDD=4.5V RL=16Ω Cin=1µF PO=15mW BW<80kHz -70 -80 -90 -100 Left to Right Right to Left 10µ -110 -120 20 100 10k 20k Output Noise Voltage vs. Frequency Output Noise Voltage (Vrms) Crosstalk (dB) +0 -10 -20 1k Frequency (Hz) 1k Frequency (Hz) Copyright ANPEC Electronics Corp. Rev. A.3 - Jul., 2009 1µ 10k 20k 7 VDD=4.5V RL=16Ω Cin=1µF A-Weighting 20 100 1k Frequency (Hz) 10k 20k www.anpec.com.tw APA2178 Typical Operating Characteristics (Cont.) THD+N vs. Output Power THD+N vs. Output Power 10 10 VDD=4.5V fin=1kHz RL=32Ω Cin=1µF BW<80kHz VDD=4.5V RL=32Ω Cin=1µF BW<80kHz 1 THD+N (%) THD+N (%) 1 fin=20kHz 0.1 Stereo, in Phase Stereo, 180o out of Phase 0.1 Mono fin=1kHz 0.01 fin=20Hz 1m 10m 100m 0.01 300m 0 70m Output Power (W) THD+N vs. Frequency +0 -10 -20 Crosstalk (dB) THD+N (%) VDD=4.5V RL=32Ω Cin=1µF 1 PO=100mW BW<22kHz 0.1 Left Channel 0.01 Right Channel 100 1k Frequency (Hz) VDD=4.5V RL=32Ω Cin=1µF PO=15mW BW<80kHz -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 20 10k 20k Left to Right Right to Left 20 50µ 1k Frequency (Hz) 10k 20k 10 VDD=4.5V RL=300Ω Cin=1µF BW<80kHz 1 THD+N (%) Output Noise Voltage (Vrms) 100 THD+N vs. Output Voltage Output Noise Voltage vs. Frequency 10µ VDD=4.5V RL=32Ω Cin=1µF A-Weighting 1µ 350m Crosstalk vs. Frequency 10 0.001 140m 210m 280m Output Power (W) 20 100 1k Frequency (Hz) Copyright ANPEC Electronics Corp. Rev. A.3 - Jul., 2009 0.1 fin=20kHz 0.01 0.001 10k 20k fin=1kHz fin=20Hz 0 800m 1.6 2.4 3.2 4 Output Voltage (V) 8 www.anpec.com.tw APA2178 Typical Operating Characteristics (Cont.) THD+N vs. Output Power 10 +0 -10 -20 Crosstalk (dB) VDD=4.5V RL=300Ω Cin=1µF VO=2.2Vrms BW<22kHz 1 THD+N (%) Crosstalk vs. Frequency 0.1 0.01 0.001 1k Frequency (Hz) Left to Right Right to Left -110 Right Channel 100 -30 -40 -50 -60 -70 -80 -90 -100 Left Channel 20 VDD=4.5V RL=300Ω Cin=1µF VO=0.31Vrms BW<80kHz -120 10k 20k 20 100 10 THD+N (%) 20 0.1 fin=1kHz 0.01 VDD=4.5V RL=300Ω Cin=1µF A-Weighting 0.001 fin=20Hz 1.6 2.4 Output Voltage (V) THD+N vs. Frequency Crosstalk vs. Frequency 1k 10k 20k +0 -10 -20 VDD=4.5V RL=10kΩ Cin=1µF VO=2.2Vrms BW<22kHz 0.1 0.01 Left Channel 0.001 Right Channel -30 -40 -50 -60 0 800m 20 100 1k -70 -80 -90 -100 -120 10k 20k Frequency (Hz) Copyright ANPEC Electronics Corp. Rev. A.3 - Jul., 2009 9 3.2 4 VDD=4.5V RL=10kΩ Cin=1µF VO=0.31Vrms BW<80kHz Left to Right Right to Left -110 0.0001 fin=20kHz Frequency (Hz) 100 Crosstalk (dB) Output Noise Voltage (Vrms) 10µ 1 THD+N (%) VDD=4.5V RL=10kΩ Cin=1µF BW<80kHz 1 10 10k 20k THD+N vs. Output Voltage Output Noise Voltage vs. Frequency 50µ 1µ 1k Frequency (Hz) 20 100 1k Frequency (Hz) 10k 20k www.anpec.com.tw APA2178 Typical Operating Characteristics (Cont.) Output Noise Voltage vs. Frequency THD+N vs. Output Voltage 10 VDD=3.3V fin=1kHz Cin=1µF BW<80kHz 1 THD+N (%) Output Noise Voltage (Vrms) 50µ 10µ VDD=4.5V RL=10kΩ Cin=1µF A-Weighting 1µ 20 100 RL=32Ω 0.1 RL=16Ω 0.01 1k Frequency (Hz) RL=300Ω RL=10kΩ 0.001 10k 20k 0 500m 2 2.5 3 THD+N vs. Output Power 10 VDD=3.3V RL=16Ω Cin=1µF BW<80kHz VDD=3.3V fin=1kHz RL=16Ω Cin=1µF BW<80kHz 1 THD+N (%) 1 THD+N (%) 1.5 Output Voltage (V) THD+N vs. Output Power 10 1 fin=20kHz 0.1 Stereo, in Phase Stereo, 180o out of Phase Mono 0.1 fin=1kHz fin=20Hz 0.01 1m 10m Output Power (W) 0.01 100m 300m 0 VDD=3.3V RL=16Ω Cin=1µF PO=50mW BW<22kHz Crosstalk (dB) THD+N (%) 1 0.1 0.01 Left Channel 0.001 80m 120m Output Power (W) 160m 200m Crosstalk vs. Frequency THD+N vs. Frequency 10 40m Right Channel +0 -10 VDD=3.3V RL=16Ω -20 Cin=1µF -30 P =7mW O -40 BW<80kHz -50 -60 -70 -80 -90 -100 Left to Right Right to Left -110 0.0001 20 100 1k -120 20 10k 20k 1k 10k 20k Frequency (Hz) Frequency (Hz) Copyright ANPEC Electronics Corp. Rev. A.3 - Jul., 2009 100 10 www.anpec.com.tw APA2178 Typical Operating Characteristics (Cont.) Output Noise Voltage vs. Frequency THD+N vs. Output Power 10 VDD=3.3V RL=32Ω Cin=1µF BW<80kHz 1 THD+N (%) Output Noise Voltage (Vrms) 50µ 10µ 20 100 0.1 fin=20Hz VDD=3.3V RL=16Ω Cin=1µF A-Weighting 1µ fin=20kHz 1k Frequency (Hz) 0.01 10k 20k 1m 1 THD+N (%) THD+N (%) Stereo, in Phase Stereo, 180o out of Phase 0.1 100m 200m THD+N vs. Frequency 10 VDD=3.3V fin=1kHz RL=32Ω Cin=1µF BW<80kHz 1 10m Output Power (W) THD+N vs. Output Power 10 fin=1kHz Mono VDD=3.3V RL=32Ω Cin=1µF PO=50mW BW<22kHz 0.1 Left Channel 0.01 Right Channel 0.01 0 40m 80m 120m Output Power (W) 0.001 160m Output Noise Voltage (Vrms) Crosstalk (dB) -50 -60 Left to Right Right to Left -110 20 100 1k Frequency (Hz) 10k 20k 50µ +0 VDD=3.3V -10 RL=32Ω -20 C =1µF in -30 PO=7mW -40 BW<80kHz -120 100 Output Noise Voltage vs. Frequency Crosstalk vs. Frequency -70 -80 -90 -100 20 1k Frequency (Hz) Copyright ANPEC Electronics Corp. Rev. A.3 - Jul., 2009 10k 20k 10µ VDD=3.3V RL=32Ω Cin=1µF 1µ A-Weighting 20 100 1k 10k 20k Frequency (Hz) 11 www.anpec.com.tw APA2178 Typical Operating Characteristics (Cont.) THD+N vs. Output Voltage THD+N vs. Frequency 10 10 0.1 fin=20Hz 0.01 fin=20kHz 0 600m 1.2 1.8 0.1 0.01 fin=1kHz 0.001 VDD=3.3V RL=300Ω Cin=1µF VO=1.6Vrms BW<22kHz 1 THD+N (%) THD+N (%) VDD=3.3V RL=300Ω Cin=1µF 1 BW<80kHz 2.4 0.001 3 Left Channel Right Channel 20 100 1k Output Voltage (V) Output Noise Voltage vs. Frequency Crosstalk vs. Frequency 50µ VDD=3.3V RL=300Ω Cin=1µF VO=0.23Vrms BW<80kHz -30 -40 -50 -60 -70 -80 -90 -100 Output Noise Voltage (Vrms) Crosstalk (dB) +0 -10 -20 Left to Right Right to Left 10µ VDD=3.3V RL=300Ω Cin=1µF A-Weighting -110 -120 20 100 1k Frequency (Hz) 1µ 10k 20k 20 1k Frequency (Hz) 10k 20k 10 10 VDD=3.3V RL=10kΩ Cin=1µF 1 V =1.6Vrms O BW<22kHz THD+N (%) VDD=3.3V RL=10kΩ Cin=1µF BW<80kHz 1 THD+N (%) 100 THD+N vs. Frequency THD+N vs. Output Voltage 0.1 fin=20kHz 0.01 0.1 0.01 Left Channel fin=1kHz 0.001 10k 20k Frequency (Hz) fin=20Hz 0 600m 1.2 1.8 2.4 20 Output Voltage (V) Copyright ANPEC Electronics Corp. Rev. A.3 - Jul., 2009 Right Channel 0.0006 3 100 1k 10k 20k Frequency (Hz) 12 www.anpec.com.tw APA2178 Typical Operating Characteristics (Cont.) Output Noise Voltage vs. Frequency +0 VDD=3.3V -10 R =10kΩ -20 CL =1µF in -30 VO=0.23Vrms -40 BW<80kHz 50µ Output Noise Voltage (Vrms) Crosstalk (dB) Crosstalk vs. Frequency -50 -60 -70 -80 -90 -100 Left to Right Right to Left -110 -120 20 100 1k Frequency (Hz) 10k 20k 10µ VDD=3.3V RL=10kΩ Cin=1µF 1µ A-Weighting 20 100 1k Frequency (Hz) THD+N vs. Output Power THD+N vs. Output Voltage 10 VDD=1.8V RL=32Ω Cin=1µF BW<80kHz 1 RL=300Ω THD+N (%) THD+N (%) 10 VDD=1.8V fin=1kHz Cin=1µF BW<80kHz 1 0.1 RL=32Ω fin=20kHz 0.1 fin=1kHz 0.01 fin=20Hz RL=10kΩ 0.001 0 400m 800m 1.2 Output Voltage (V) 0.01 1.6 1m 10 60m 10 VDD=1.8V fin=1kHz RL=32Ω Cin=1µF 1 BW<80kHz 1 THD+N (%) Stereo, in Phase 10m Output Power (W) THD+N vs. Frequency THD+N vs. Output Power THD+N (%) 10k 20k Stereo, 180o out of Phase Mono 0.1 VDD=1.8V RL=32Ω Cin=1µF PO=9mW BW<22kHz 0.1 Left Channel 0.01 Right Channel 0.01 0 6m 12m 18m 24m Output Power (W) Copyright ANPEC Electronics Corp. Rev. A.3 - Jul., 2009 30m 0.001 36m 13 20 100 1k Frequency (Hz) 10k 20k www.anpec.com.tw APA2178 Typical Operating Characteristics (Cont.) Crosstalk vs. Frequency 50µ VDD=1.8V RL=32Ω Cin=1µF PO=1.3mW BW<80kHz -30 -40 -50 -60 -70 -80 -90 -100 Output Noise Voltage (Vrms) Crosstalk (dB) +0 -10 -20 Output Noise Voltage vs. Frequency Left to Right Right to Left 10µ VDD=1.8V RL=32Ω Cin=1µF A-Weighting -110 -120 20 100 1k 1µ 10k 20k 20 100 1k Frequency (Hz) Frequency (Hz) THD+N vs. Frequency THD+N vs. Output Voltage 10 10 VDD=1.8V RL=300Ω Cin=1µF VO=0.85Vrms BW<22kHz 1 THD+N (%) THD+N (%) VDD=1.8V RL=300Ω Cin=1µF 1 BW<80kHz fin=20kHz 0.1 fin=1kHz 0.01 0.1 0.01 Left Channel fin=20Hz 0.001 0 300m 600m 0.9 Right Channel 1.2 0.001 1.5 20 100 Output Voltage (V) -50 -60 Left to Right Right to Left 10µ -110 20 100 10k 20k 50µ +0 VDD=1.8V -10 RL=300Ω -20 C =1µF in -30 VO=0.1Vrms -40 BW<80kHz -120 1k Frequency (Hz) Output Noise Voltage vs. Frequency Output Noise Voltage (Vrms) Crosstalk (dB) Crosstalk vs. Frequency -70 -80 -90 -100 10k 20k 1k Frequency (Hz) Copyright ANPEC Electronics Corp. Rev. A.3 - Jul., 2009 1µ 10k 20k 14 VDD=1.8V RL=300Ω Cin=1µF A-Weighting 20 100 1k Frequency (Hz) 10k 20k www.anpec.com.tw APA2178 Typical Operating Characteristics (Cont.) THD+N vs. Output Voltage THD+N vs. Frequency 10 10 VDD=1.8V RL=10kΩ Cin=1µF VO=0.85Vrms BW<22kHz 1 THD+N (%) 0.1 fin=20kHz 0.01 0.1 0.01 fin=1kHz 0.001 Left Channel fin=20Hz 0 300m 600m 0.9 1.2 0.001 1.5 20 100 Output Voltage (V) Crosstalk vs. Frequency Output Noise Voltage vs. Frequency VDD=1.8V RL=10kΩ Cin=1µF VO=0.12Vrms BW<80kHz -30 -40 -50 -60 -70 -80 -90 -100 Left to Right Right to Left 10µ VDD=1.8V RL=10kΩ Cin=1µF A-Weighting -110 -120 20 100 1k Frequency (Hz) 1µ 10k 20k 20 100 +250 +230 Gain +3 +210 +2 Phase +1 +0 10 100 VDD=3.3V RL=10kΩ +5 C =1µF in VO=0.23Vrms +4 BW<80kHz 1k 10k Frequency (Hz) Copyright ANPEC Electronics Corp. Rev. A.3 - Jul., 2009 +190 Gain (dB) Gain (dB) +4 10k 20k +6 Phase (Deg) +5 +270 VDD=3.3V RL=32Ω Cin=1µF PO=10mW BW<80kHz 1k Frequency (Hz) Frequency Response Frequency Response +6 10k 20k 50µ Output Noise Voltage (Vrms) Crosstalk (dB) +0 -10 -20 Right Channel 1k Frequency (Hz) +250 +230 Gain +210 +3 +2 +170 +1 +150 200k +0 15 +270 +190 Phase Phase (Deg) THD+N (%) VDD=1.8V RL=10kΩ Cin=1µF 1 BW<80kHz +170 10 100 1k 10k Frequency (Hz) 200k +150 www.anpec.com.tw APA2178 Typical Operating Characteristics (Cont.) Input Voltage vs. Output Voltage 2 Iutput Voltage (Vrms) 3 VDD=3.3V RL=16Ω fin=1kHz Cin=1µF Mono 1.5 Stereo, in Phase 1 500m 0 0 500m 1 1.5 Output Voltage (Vrms) VDD=3.3V RL=10kΩ fin=1kHz Cin=1µF 2.4 Iutput Voltage (Vrms) 2.5 Input Voltage vs. Output Voltage 2 -10 1.2 600m 0 0 2.5 -10 -20 -30 -30 -40 -40 -50 -60 -50 -60 Left Channel -80 Right Channel -90 20 100 Right Channel -90 1k Frequency (Hz) -100 10k 20k Supply Current vs. Supply Voltage 20 100 1k Frequency (Hz) 10k 20k Shutdown Current vs. Supply Voltage 2.0 6 No Load RSD=LSD=GND No Load Shutdown Current (µA) 5 Supply Current (mA) VDD=3.3V RL=10kΩ Cin=1µF Vrr=200mVrms -70 Left Channel -80 -100 3 PSRR vs. Frequency VDD=3.3V RL=16Ω Cin=1µF Vrr=200mVrms -70 600m 1.2 1.8 2.4 Output Voltage (Vrms) +0 PSRR (dB) PSRR (dB) -20 Stereo, in Phase 1.8 PSRR vs. Frequency +0 Mono 4 3 2 1 0 1.0 1.5 2.0 2.5 3.0 3.5 4.0 1.0 0.5 0.0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 Supply Voltage (V) 4.5 Supply Voltage (V) Copyright ANPEC Electronics Corp. Rev. A.3 - Jul., 2009 1.5 16 www.anpec.com.tw APA2178 Typical Operating Characteristics (Cont.) Power Dissipation vs. Output Power Power Dissipation vs. Output Power 175 300 Power Dissipation (mW) Power Dissipation (mW) 150 RL=16Ω 250 200 150 RL=32Ω 100 VDD=4.5V fin=1kHz Cin=1µF Mono 50 0 0 50 RL=16Ω 125 100 75 RL=32Ω 50 VDD=3.3V fin=1kHz Cin=1µF Mono 25 0 100 150 200 250 300 350 400 Output Power (mW) 0 Power Dissipation vs. Output Power 200 Mono THD+N=10% Mono THD+N=1% 40 Output Power (mW) Power Dissipation (mW) 50 75 100 125 150 175 200 Output Power (mW) Output Power vs. Load Resistance 50 30 RL=32Ω 20 VDD=1.8V fin=1kHz Cin=1µF Mono 10 0 0 10 20 30 40 Output Power (mW) 150 100 50 Stereo, in Phase THD+N=1% 0 50 60 10 1000 vs. Supply Voltage 15 CCPF：Charge Pump flying capacitor CCPO：Charge Pump output capacitor CCPF=CCPO=2.2µF 80 CCPF=CCPO=1µF Load Resistance (Ω) 12 CCPF=CCPO=0.68µF 60 9 6 3 0 1.8 2.1 2.4 2.7 3.0 3.3 3.6 3.9 4.2 4.5 1000 Load Resistance (Ω) Copyright ANPEC Electronics Corp. Rev. A.3 - Jul., 2009 100 Load Resistance (Ω) Charge Pump Output Resistance Charge Pump Capacitance CCPF=CCPO =0.47µF 40 V =3.3V DD fin=1kHz Cin=1µF 20 BW<80kHz THD+N=10% 0 Stereo, in Phase 10 100 VDD=3.3V fin=1kHz Cin=1µF BW<80kHz Stereo, in Phase THD+N=10% Output Power vs. Load Resistance & Output Power (mW) 25 Supply Voltage (V) 17 www.anpec.com.tw APA2178 Typical Operating Characteristics (Cont.) GSM Power Supply Rejection vs. Frequency +0 -50 Output Voltage (dBV) -100 -150 +0 Supply Voltage (dBV) GSM Power Supply Rejection vs. Time 1 VDD VROUT -50 2 -100 -150 0 400 800 1.2k 1.6k 2k CH1: VDD, 500mV/Div, DC, V DD Offset=3.3V CH2: VROUT, 20mV/Div, DC TIME: 20ms/Div Frequency (Hz) Copyright ANPEC Electronics Corp. Rev. A.3 - Jul., 2009 18 www.anpec.com.tw APA2178 Operating Waveforms Output Transient at Turn On Output Transient at Turn Off VDD VDD 1 1 VROUT VROUT 2 2 CH1: VDD, 2V/Div, DC CH2: VROUT, 20mV/Div, DC TIME: 200ms/Div CH1: VDD, 2V/Div, DC CH2: VROUT, 20mV/Div, DC TIME: 20ms/Div Output Transient at Shutdown Release Output Transient at Shutdown Active RSD RSD 1 1 VROUT VROUT 2 2 CH1: RSD, 2V/Div, DC CH2: VROUT, 20mV/Div, DC TIME: 20ms/Div Copyright ANPEC Electronics Corp. Rev. A.3 - Jul., 2009 CH1: RSD, 2V/Div, DC CH2: VROUT, 20mV/Div, DC TIME: 20ms/Div 19 www.anpec.com.tw APA2178 Operating Waveforms (Cont.) Shutdown Release RSD 1 2 VROUT CH1: VDD, 2V/Div, DC CH2: VROUT, 1V/Div, DC TIME: 200µs/Div Copyright ANPEC Electronics Corp. Rev. A.3 - Jul., 2009 20 www.anpec.com.tw APA2178 Pin Description PIN I/O/P FUNCTION NO. MANE A1 RIN I Right channel audio signal input pin. A2 GND P Ground connection for circuitry. A3 PVDD P Charge pump power supply voltage input pin. A4 CP+ I/O Charge pump flying capacitor positive connection. Right channel shutdown mode control pin. A low-level voltage applied on this pin shuts off the right channel headphone driver. Left channel shutdown mode control pin. A low-level voltage applied on this pin shuts off the left channel headphone driver. B1 RSD I B2 LSD I B3,C3 NC - No Connection. B4 PGND P Charge pump ground. C1 LIN I Left channel audio signal input pin. C2 ROUT O Right channel output for headphone. C4 CP- I/O Charge pump flying capacitor negative connection. D1 VDD P Supply voltage input pin. D2 LOUT O Left channel output for headphone. D3 VSS P Connect this pin to CVSS. D4 CVSS O Charge pump output. Block Diagram RIN ROUT LIN LOUT GND PVDD CP+ RSD LSD Shutdown Circuit GND Copyright ANPEC Electronics Corp. Rev. A.3 - Jul., 2009 PGND Power and Depop Circuit VSS VDD 21 Charge Pump CP- CVSS www.anpec.com.tw APA2178 Typical Application Circuit 1 µF R-Ch Input RIN CiR 1 µF L-CH Input ROUT LIN CiL LOUT PVDD GND Shutdown Control Headphone Jack RSD LSD Shutdown Circuit GND PGND VDD Power and Depop Circuit VSS VDD CS 1µF/X5R Copyright ANPEC Electronics Corp. Rev. A.3 - Jul., 2009 22 Charge Pump VDD CCPB CP+ 1 µF /X5R CCPF 1µF/X5R CP- VSS CVSS CCPO 1µF/X5R www.anpec.com.tw APA2178 Function Description VDD voltage PVDD to provide maximum device performance. By switching the both RSD and LSD pins to low level, the VDD/2 amplifier enters a low-consumption current circumstance, with charge pump disabled, and very small IDD for the GND APA2178. The charge pump is enabled once either RSD or LSD pin is pulled to high. In normal operating, the VOUT APA2178 RSD and LSD pins should be pulled to high level to keep the IC out of the shutdown mode. The RSD Conventional Headphone amplifier and LSD pins should be tied to a definite voltage to avoid unwanted mode changing. VDD VOUT GND VSS Cap-free Headphone amplifier Figure 1. Cap-free Operation The APA2178 is a stereo, fixed gain, and cap-free headphone driver. The gain is set by internal resistors, input resistors (R i), and feedback resistors (R f) with -1.5V/V (See Typical Application Circuit). The APA2178 headphone drivers use a charge pump to invert the positive power supply (PVDD) to negative power supply (CVSS), see figure 1. The headphone drivers operate at this bipolar power supply (VDD and VSS) and the outputs reference refers to the ground. This feature eliminates the output capacitors which are used in conventional single-ended headphone amplifiers. Compared with the single power supply amplifiers, the power supply voltage is almost double. Shutdown Function In order to reduce power consumption, the APA2178 contains two shutdown signal input pins (LSD for left channel and RSD for right channel) to allow the respective shutdown which turns off the bias current of the amplifier. This shutdown feature turns the amplifier off when logic low is placed on the RSD or LSD pin for the APA2178. The trigger point between a logic high and a logic low level is typically 0.6VDD and 0.3VDD. It is highly recommended to switch between the ground and the supply Copyright ANPEC Electronics Corp. Rev. A.3 - Jul., 2009 23 www.anpec.com.tw APA2178 Application Information The value of Ci must be considered carefully because it directly affects the low frequency performance of the circuit. Charge Pump Flying Capacitor (CCPF) The flying capacitor (CCPF) affects the load transient of the Consider the example where Ri is 14kΩ and the specification that calls for a flat bass response down to 10Hz. charge pump. If the capacitor’s value is too small, and then this increases charge pump’s output resistance and The equation is reconfigured as below: degrades the performance of headphone amplifier. Increasing the flying capacitor’s value improves the load Ci = transient of charge pump. It is recommend to use the low E S R c e r am i c c apac i t o rs ( X5 R o r X7R t yp e i s 1 2πRifC (2) When input resistance variation is considered, the Ci is recommended) above 1µF. 1µF. Therefore, a value in the range of 1µF to 2.2µF would be chosen. A further consideration for this capacitor is the Charge Pump Output Capacitor (CCPO) leakage path from the input source through the input network (Ri + Rf, Ci) to the load. The charge pump needs an output capacitor(CCPO) to filter the negative output current pulse flowing into CVSS This leakage current creates a DC offset voltage at the input to the amplifier that reduces useful headroom, es- pin as well as reduces the output voltage ripple(CVSS). The capacitor also sucks in surge current flowing from pecially in high gain applications. For this reason, a lowleakage tantalum or ceramic capacitor is the best choice. the VSS pin, the negative power input pin for the amplifiers. The output ripple is determined by the capacitance, ESR, When polarized capacitors are used, the negative side of the capacitor should face the amplifiers’ inputs in most and current ripple of the output capacitor. Increasing the value of output capacitor and decreasing the ESR can applications because the DC level of the amplifiers’ inputs are held at 0V. Please note that it is important to reduce the voltage ripple. Using a low-ESR ceramic capacitor greater than 1µF is recommended. For reducing confirm the capacitor polarity in the application. the parasitic inductance and improving the noise decoupling, place the capacitor near the CVSS and PGND Power Supply Decoupling (CS) pins as close as possible. The APA2178 is a high-performance CMOS audio amplifier that requires adequate power supply decoupling to Charge Pump Bypass Capacitor (CCPB) The bypass capacitor(CCPB) connected with PVDD pin sup- ensure the output total harmonic distortion (THD+N) as low as possible. Power supply decoupling also prevents plies the charge pump with surge current as well as reduces the voltage ripple on PVDD pin. Using a low-ESR the oscillations being caused by long lead length between the amplifier and the speaker. ceramic capacitor 1µF(typical) is recommended. For reducing the parasitic inductance and improving the noise The optimum decoupling is achieved by using two different types of capacitor that target on different types of noise on the power supply leads. For higher frequency decoupling, place the capacitor near the PVDD and PGND pins as close as possible. transients, spikes, or digital hash on the line, a good low equivalent-series- resistance (ESR) ceramic capacitor, Input Capacitor (Ci) typically 0.1µF, is placed as close as possible to the device VDD lead for the best performance. For filtering lower In the typical application, an input capacitor (Ci) is required to allow the amplifier to bias the input signal to the proper DC level for optimum operation. In this case, Ci and the frequency noise signals, a large aluminum electrolytic capacitor of 10µF or greater placed near the audio power input impedance Ri from a high-pass filter with the cutoff frequency are determined in the following equation: amplifier is recommended. fC(highpass) = 1 2πRiCi Copyright ANPEC Electronics Corp. Rev. A.3 - Jul., 2009 Thermal Consideration Linear power amplifiers dissipate a significant amount (1) of heat in the package in normal operating condition. The first consideration to calculate maximum ambient tem24 www.anpec.com.tw APA2178 Application Information (Cont.) 16 x Φ0.275mm Thermal Consideration (Cont.) peratures is the numbers from the Power Dissipation vs. Output Power graphs are per channel values, so the dissipation of the IC heat needs to be doubled for two-channel operation. Given θJA, the maximum allowable junction temperature (TJMax), the total internal dissipation (PD), and the maximum ambient temperature can be calculated with the following equation. The maximum recommended junction temperature for the APA2178 is 150oC. The internal dissipation figures are taken from the Power Dissipation vs. Output Power graphs. The APA2178 is designed with a thermal shutdown protection that turns the device off when the junction temperature surpasses 0.5mm 150°C to prevent damaging the IC. Layout Consideration 0.5mm 1. All components should be placed close to the APA2178. Figure 2. WLCSP2x2-16 land pattern recommendation For example, the input capacitor (CiR, CiL) should be close to APA2178 input pins to avoid causing noise coupling to APA2178 high impedance inputs; the decoupling capacitor (C S ) should be placed by the CCPF APA2178 power pin to decouple the power rail noise. 2. The output traces should be short, wide (>50mil), and CCPB symmetric. 3. The input trace should be short and symmetric. PIN A1 4. The power trace width should be greater than 50mil. 5. The input trace and output trace should be away from output trace CCPF and CCPB possible. CiR CiL Figure 3. APA2178 Layout Suggestion Copyright ANPEC Electronics Corp. Rev. A.3 - Jul., 2009 25 www.anpec.com.tw APA2178 Package Information E WLCSP2x2-16 PIN 1 D A1 e e/2 b A e/2 S Y M B O L e WLCSP2x2-16 MILLIMETERS MIN. INCHES MAX. A MIN. MAX. 0.625 0.025 A1 0.15 0.35 0.006 0.014 b 0.25 0.35 0.010 0.014 D 1.97 2.03 0.077 0.080 E 1.97 2.03 0.077 0.080 e Copyright ANPEC Electronics Corp. Rev. A.3 - Jul., 2009 0.50 BSC 0.020 BSC 26 www.anpec.com.tw APA2178 Carrier Tape & Reel Dimensions P0 P2 P1 A B0 W F E1 OD0 K0 A0 A OD1 B B T SECTION A-A SECTION B-B H A d T1 Application WLCSP2x2-16 A H T1 C d D W E1 F 178.0±2.00 50 MIN. 8.4+2.00 -0.00 13.0+0.50 -0.20 1.5 MIN. 20.2 MIN. 8.0±0.30 1.75±0.10 3.5±0.05 P0 P1 P2 D0 D1 T A0 B0 K0 2.0±0.05 1.5+0.10 -0.00 1.5 MIN. 0.6+0.00 -0.40 2.20±0.20 2.20±0.20 0.90±0.20 4.0±0.10 4.0±0.10 (mm) Devices Per Unit Package Type Unit Quantity WLCSP2x2-16 Tape & Reel 3000 Copyright ANPEC Electronics Corp. Rev. A.3 - Jul., 2009 27 www.anpec.com.tw APA2178 Taping Direction Information WLCSP2x2-16 USER DIRECTION OF FEED Classification Profile Copyright ANPEC Electronics Corp. Rev. A.3 - Jul., 2009 28 www.anpec.com.tw APA2178 Classification Reflow Profiles Profile Feature Sn-Pb Eutectic Assembly Pb-Free Assembly 100 °C 150 °C 60-120 seconds 150 °C 200 °C 60-120 seconds 3 °C/second max. 3°C/second max. 183 °C 60-150 seconds 217 °C 60-150 seconds See Classification Temp in table 1 See Classification Temp in table 2 Time (tP)** within 5°C of the specified classification temperature (Tc) 20** seconds 30** seconds Average ramp-down rate (Tp to Tsmax) 6 °C/second max. 6 °C/second max. 6 minutes max. 8 minutes max. Preheat & Soak Temperature min (Tsmin) Temperature max (Tsmax) Time (Tsmin to Tsmax) (ts) Average ramp-up rate (Tsmax to TP) Liquidous temperature (TL) Time at liquidous (tL) Peak package body Temperature (Tp)* Time 25°C to peak temperature * Tolerance for peak profile Temperature (Tp) is defined as a supplier minimum and a user maximum. ** Tolerance for time at peak profile temperature (tp) is defined as a supplier minimum and a user maximum. Table 1. SnPb Eutectic Process – Classification Temperatures (Tc) Package Thickness <2.5 mm ≥2.5 mm Volume mm <350 235 °C 220 °C 3 Volume mm ≥350 220 °C 220 °C 3 Table 2. Pb-free Process – Classification Temperatures (Tc) Package Thickness <1.6 mm 1.6 mm – 2.5 mm ≥2.5 mm Volume mm <350 260 °C 260 °C 250 °C 3 Volume mm 350-2000 260 °C 250 °C 245 °C 3 Volume mm >2000 260 °C 245 °C 245 °C 3 Reliability Test Program Test item SOLDERABILITY HOLT PCT TCT HBM MM Latch-Up Method JESD-22, B102 JESD-22, A108 JESD-22, A102 JESD-22, A104 MIL-STD-883-3015.7 JESD-22, A115 JESD 78 Copyright ANPEC Electronics Corp. Rev. A.3 - Jul., 2009 29 Description 5 Sec, 245°C 1000 Hrs, Bias @ 125°C 168 Hrs, 100%RH, 2atm, 121°C 500 Cycles, -65°C~150°C VHBM≧2KV VMM≧200V 10ms, 1tr≧100mA www.anpec.com.tw APA2178 Customer Service Anpec Electronics Corp. Head Office : No.6, Dusing 1st Road, SBIP, Hsin-Chu, Taiwan, R.O.C. Tel : 886-3-5642000 Fax : 886-3-5642050 Taipei Branch : 2F, No. 11, Lane 218, Sec 2 Jhongsing Rd., Sindian City, Taipei County 23146, Taiwan Tel : 886-2-2910-3838 Fax : 886-2-2917-3838 Copyright ANPEC Electronics Corp. Rev. A.3 - Jul., 2009 30 www.anpec.com.tw