APA2058 2.4W Stereo Fully Differential Audio Power Amplifier With Stereo Class AB Cap-free Headphone Driver and LDO Features • • General Description TM Meeting VISTA Requirement The APA2058 is a stereo fully differential audio power amplifier with stereo Class-AB cap-free headphone driver Fully Differential Power Amplifier with and LDO available in a TQFN5X5-32A pins package. The built-in gain setting at power amplifier can minimize Excellent RF Rectification Immunity • No Output Capacitor Required for Head the external component counts. For the flexible application, the gain can be set to 4-steps, 10, 12, 15.6, and 21.6dB by Phone Driver • gain control pins (GAIN0 and GAIN1). The power amplifier’s fully differential architecture provides high PSRR, in- Integrated LDO (Low Dropout Regulator) for Audio Codec (3.3V) • • creased immunity to noise and RF rectification. Adjustable Gain Setting for Power Amplifier The APA2058 power amplifiers are capable of driving AV=-1.5V/V Fixed Gain Setting for Headphone 2.4W at VDD=5V into 4Ω speaker, the cap-free headphone drivers can provide 180mW at HV DD =3.3V into16Ω Driver • • • • • • headphones, and the LDO has a maximum 200mA(3.3V) driver current for audio codec. The APA2058 provides ther- Fast Start-up Time Integrated De-Pop Circuitry mal and over-current protections. The cap-free headphone driver eliminates the DC block- High PSRR (Power Supply Rejection Ratio) Thermal and Over-Current Protections Less External Components Required ing capacitors at outputs, save the PCB space. The integration of fully differential power amplifier, cap-free head- Space Saving Package phone driver, and LDO is a best solution for VISTATM requirement and it can lower the total BOM costs. – TQFN5x5-32A • Lead Free and Green Devices Available (RoHS Compliant) +0 • • • Common Mode Rejection Ratio (dB) Applications LCD Monitor Notebook Protable DVD Simplified Application Circuit Audio Codec Stereo Speakers -10 -20 -30 -40 VDD=5.0V RL=4Ω AV=10dB Vin=0.2VPP Ci=0.47µF Input Short AMP Mode -50 -60 -70 -80 -90 -100 20 100 1k 10k 20k Frequency (Hz) Stereo Headphone LDO (Low Drop -Out Regulator) ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and advise customers to obtain the latest version of relevant information to verify before placing orders. Copyright ANPEC Electronics Corp. Rev. A.3 - Aug., 2008 1 www.anpec.com.tw APA2058 Ordering and Marking Information (Note 1) Package Code QB : TQFN5x5-32A Operating Ambient Temperature Range I : -40 to 85 °C Handling Code TR : Tape & Reel Assembly Material L : Lead Free Device G : Halogen and Lead Free Device APA2058 Assembly Material Handling Code Temperature Range Package Code APA2058 QB : XXXXX - Date Code APA2058 XXXXX Note 1 : ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which are fully compliant with RoHS. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J-STD020C for MSL classification at lead-free peak reflow temperature. ANPEC defines “Green” to mean lead-free (RoHS compliant) and halogen free (Br or Cl does not exceed 900ppm by weight in homogeneous material and total of Br and Cl does not exceed 1500ppm by weight). 17 HVDD 18 PVDD 20 ROUTP 19 ROUTN 22 HP_EN 21 PGND 24 BIAS 23 AMP_EN Pin Configuration LDO_EN 25 16 HP_LO RIN_H 26 15 HP_RO 14 HVSS LIN_H 27 GND 28 13 CVSS TQFN5x5-32A (Top View) LDOUT 29 12 CPN 11 CGND VDD 30 PVDD 8 LOUTN 7 PGND 5 LOUTP 6 LINP_A 3 9 NC LINN_A 4 GAIN1 32 RINN_A 1 10 CPP RINP_A 2 GAIN0 31 =Thermal-Pad (connected the Thermal-Pad to GND plane for better heat dissipation) Absolute Maximum Ratings Symbol VDD (Note 2) Parameter Rating Supply Voltage (VDD to GND, PVDD to PGND) -0.3 to 6 HVDD Supply Voltage (HVDD to GND) -0.3 to 6 VSS Supply Voltage (HVSS to GND) -6 to +0.3 Input Voltage (RINN_A, RINP_A, LINN_A, LINP_A to GND) Input Voltage (RIN_H, LIN_H to GND) V VSS-0.3 to HVDD+0.3 Input Voltage (GAIN0, GAIN1, LDO_EN, AMP_EN, HP_EN to GND) Input Voltage (PGND, CGND to GND) Copyright ANPEC Electronics Corp. Rev. A.3 - Aug., 2008 -0.3 to VDD+0.3 Unit -0.3 to VDD+0.3 -0.3 to +0.3 2 www.anpec.com.tw APA2058 Absolute Maximum Ratings (Cont.) Symbol TJ Parameter Rating Maximum Junction Temperature Unit 150 TSTG Storage Temperature Range TSDR Maximum Lead Soldering Temperature, 10 Seconds PD (Note 2) ο -65 to +150 C 260 Power Dissipation Internally Limited W Notes 2: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Thermal Characteristics Symbol Parameter θJA Thermal Resistance -Junction to Ambient θJC Thermal Resistance -Junction to Case Typical Value TQFN5X5-32A (Note 3) (Note 4) 40 Unit ο C /W 8 TQFN5X5-32A Note 3: Please refer to “ Layout Recommendation”, the Thermal-Pad on the bottom of the IC should soldered directly to the PCB’s Thermal-Pad area that with several thermal vias connect to the ground plan, and the PCB is a 2-layer, 5-inch square area with 2oz copper thickness. Note 4: The case temperature is measured at the center of the Thermal-Pad on the underside of the TQFN5X5-32A package. Recommended Operating Conditions Symbol Parameter Range VDD Supply Voltage 4.5 ~ 5.5 HVDD Supply Voltage 3.0 ~ 3.6 VIH High Level Input Voltage GAIN0, GAIN1, LDO_EN, AMP_EN, HP_EN 2 ~ VDD VIL Low Level Input Voltage GAIN0, GAIN1, LDO_EN, AMP_EN, HP_EN 0 ~ 0.5 VIC Common Mode Input Voltage Unit V ILDOUT For Power Amplifier 0.5 ~ VDD-0.5 For Headphone Amplifier HVSS ~ HVDD Output Current (LDOUT) 0 ~ 200 TA Ambient Temperature Range -40 ~ 85 TJ Junction Temperature Range -40 ~ 125 mA ο C COUT LDO Output Capacitor (MLCC type) 1 ~ 100 RL Speaker Resistance 4~ RL Headphone Resistance 16 ~ Copyright ANPEC Electronics Corp. Rev. A.3 - Aug., 2008 3 µF Ω www.anpec.com.tw APA2058 Electrical Characteristics o Refer to the typical application circuits. VDD=5V, HVDD=3.3V, Gnd=0V, TA=25 C (unless otherwise noted) Symbol IDD(HVDD) Parameter V AMP_EN =0V , Supply Current IDD(VDD) IAMP(HVDD) Power Amplifier Supply Current VHP_EN=VLDO_EN=5V V AMP_EN =VHP_EN=VLDO_EN=0V IAMP(VDD) IHP(HVDD) V AMP_EN =VHP_EN=5V, Headphone Driver Supply Current IHP(VDD) ILDO(HVDD) VLDO_EN=0V V AMP_EN =VLDO_EN=5V, LDO Supply Current APA2058 Test Conditions Unit Min. Typ. Max. HVDD - 2.5 4 VDD - 9 15 HVDD - 0.1 0.2 VDD - 4.5 7.5 HVDD - 2.5 4 VDD - 6 10 HVDD - 0.1 0.2 ILDO(VDD) VHP_EN=0V VDD - 0.4 0.65 ISD(HVDD) V AMP EN =5V, HVDD - - 2 VHP_EN=VLDO_EN=0V VDD Shutdown Current ISD(VDD) II Input Current mA - - 5 GAIN0, GAIN1, LDO_EN, AMP_EN, HP_EN - - 1 CB=0.47µF - 25 - ms AV=10dB - 76 - kΩ AV=12dB - 60 - AV=15.6dB - 40 - µA SPEAKER MODE, AV =10dB TSTART-UP Ri AV Start-Up Time from Shutdown Input Resistor Closed-Loop Gain VOS Output Offset Voltage PO Output Power THD+N Crosstal k Total Harmonic Distortion Pulse Noise Channel Separation AV=21.6dB 17 20 - VGAIN0=VGAIN1=0V. 9.5 10 10.5 VGAIN0=0V, VGAIN1=VDD. 11.5 12 12.5 VGAIN0=VDD, VGAIN1=0V. 15.1 15.6 16.1 VGAIN0=VGAIN1=VDD. 21.1 21.6 22.1 - 5 20 1.9 1.3 - 1 - 2.4 1.5 - - 0.07 0.05 - - -110 -110 - RL = 8Ω THD+N=1%, fin=1kHz RL=4Ω RL=8Ω THD+N=10%, fin= kHz RL=4Ω RL=8Ω fin=1kHz RL=4Ω ,PO=1.4W RL=8Ω, PO=0.9W fin=1kHz RL=4Ω, Po=200mW RL=8Ω, Po=130mW Power Supply Rejection Ratio fin=217Hz, Vrr=0.2Vrms,RL=8Ω - -75 - CMRR Common Mode Rejection Ratio fin=1kHz, Vin=0.2Vrms.,RL=8Ω fin=20~20kHz With A-weighting Filter RL=4Ω, PO=1.4W, RL=8Ω, PO=0.9W, fin=20~20kHz,With A-weighting Filter RL=8Ω - -65 - - 100 100 - - 22 - Signal-to-Noise Ratio Vn Noise Output Voltage Copyright ANPEC Electronics Corp. Rev. A.3 - Aug., 2008 4 mV W PSRR S/N dB % dB µVrms www.anpec.com.tw APA2058 Electrical Characteristics (Cont.) o Refer to the typical application circuits. VDD=5V, HVDD=3.3V, Gnd=0V, TA=25 C (unless otherwise noted) Symbol Parameter APA2058 Test Conditions Unit Min. Typ. Max. HEADPHONE MODE, AV = -1.5V/V, CPF=CPO=1µF(X5R type) TSTART-UP Start-Up Time from shutdown Ri Input Resistor AV Closed-Loop Gain VOS Output Offset Voltage PO VO THD+N Crosstalk PSRR Output Power Output Swing Voltage Total Harmonic Distortion Pulse Noise Channel Separation Power Supply Rejection Ratio S/N Signal-to-Noise Ratio Vn Noise Output Voltage CB=0.47µF RL = 32Ω THD+N=1%, fin=1kHz RL=16Ω RL=32Ω THD+N=10%, fin=1kHz RL=16Ω RL=32Ω THD+N=1%, fin=1kHz RL=320Ω, RL=10kΩ, THD+N=10%, fin=1kHz RL=320Ω, RL=10kΩ, fin=1kHz RL=16Ω , PO=125mW RL=32Ω, PO=88mW RL=320Ω, VO=1.5V RL=10kΩ, VO=1.6V fin=1kHz RL=16Ω , PO=16mW RL=32Ω, PO=12mW RL=320Ω, VO=0.22V RL=10kΩ, VO=0.22V fin=217Hz,Vrr=0.2Vrms RL=32Ω, fin=20~20kHz, With A-weighting Filter RL=16Ω , PO=125mW RL=32Ω, PO=88mW RL=320Ω, VO=1.5V RL= 10kΩ, VO=1.6V fin=20~20kHz, With A-weighting Filter RL=32Ω - 10 - 17 20 - kΩ -1.45 -1.5 -1.55 V/V - 1 5 mV 140 120 - 100 - 150 180 160 1.8 2.0 2.1 - - 2.45 2.6 - - - - - - 0. 03 0. 02 0. 005 0. 004 -82 -82 -77 -77 -80 99 100 100 100 15 ms mW V - % dB - - - µVrms LDO (LOW DROP-OUT REGULATOR) IO Output Current VO Output Voltage IO=1mA Line Regulation Load Regulation PSRR RDIS Power Supply Rejection Ratio Discharge Resistor - - 200 mA 3.2 3.3 3.4 V IO=1mA, VDD=4.5V to 5.5V - 1.5 5 mV IO=1mA to 200mA - 0.03 0.1 mV/mA IO=1mA,fin=120Hz,Vrr=0.2Vrms - -50 - dB - 170 - Ω CHARGE PUMP, CPF=CPO=1µF(X5R type) FOSC Oscillator Frequency - 450 - kHz REQ Equivalent Resistance - 10 - Ω CVss Negative Output Voltage -5.1 -5 -4.9 V RDIS Discharge Resistor - 5 - kΩ Copyright ANPEC Electronics Corp. Rev. A.3 - Aug., 2008 No load 5 www.anpec.com.tw APA2058 Block Diagram LOUTP LINN_A LINP_A LOUTN GAIN1 PVDD Gain Control GAIN0 PGND ROUTN RINP_A RINN_A ROUTP - LIN_H HP_LO + HVDD GND HVSS + HP_RO RIN_H VDD PVDD LDO Charge Pump AMP_EN CPP HP_EN Control LDO_EN CPN BIAS Copyright ANPEC Electronics Corp. Rev. A.3 - Aug., 2008 VDD LDOUT 6 CVSS CGND www.anpec.com.tw APA2058 Pin Description PIN FUNCTION I/O/P NO. NAME 1 RINN_A I The inverting input pin of right channel power amplifier. 2 RINP_A I The non-inverting input pin of right channel power amplifier. 3 LINP_A I The non-inverting input pin of left channel power amplifier. 4 LINN_A I The inverting input pin of left channel power amplifier. 5,21 PGND P Power amplifier’s ground 6 LOUTP O The positive output pin of left channel power amplifier. 7 LOUTN O The negative output pin of left channel power amplifier. 8,18 PVDD P Power amplifier’s supply voltage pin. 9 NC - No Connection. 10 CPP I/O 11 CGND P 12 CPN I/O Charge pump flying capacitor negative connection. 13 CVSS O Charge pump output pin, connect this pin to the “HVSS”. 14 HVSS P Headphone driver’s negative supply voltage pin. 15 HP_RO O The output pin of right channel headphone driver. 16 HP_LO O The output pin of left channel headphone driver. 17 HVDD P Headphone driver’s positive supply voltage pin. 19 ROUTN O The negative output pin of right channel power amplifier. 20 ROUTP O The positive output pin of right channel power amplifier. 22 HP_EN I Headphone drivers enable input pin; High=Enable. 23 AMP_EN I Power amplifiers enable input pin; Low=Enable. 24 BIAS P Bias voltage for power amplifiers. 25 LDO_EN I LDO (Low Drop-Out Regulator) enables input pin; High=Enable. 26 RIN_H I The input pin of right channel headphone driver. 27 LIN_H I The input pin of left channel headphone driver. 28 GND P Control block’s ground, connect this pin to CGND and PGND. 29 LDOUT O LDO (Low Drop-Out Regulator)’s output pin. 30 VDD P Control block and LDO supply voltage pin. 31 GAIN0 I Control pin for internal gain setting, MSB, Bit 1. 32 GAIN1 I Control pin for internal gain setting, LSB, Bit 0. Copyright ANPEC Electronics Corp. Rev. A.3 - Aug., 2008 Charge pump flying capacitor positive connection. Charge pump’s ground. 7 www.anpec.com.tw APA2058 Typical Application Circuit Differential input mode VDD Regulator Output CO2 CO1 Ci5 1µF Gnd 1µF Gain Control (Amplifier) Ci1 RINN_A 0.47µF Ci2 RINP_A 0.47µF Ci3 LINP_A 0.47µF Ci4 LINN_A 0.47µF Right Channel Input Signal (Amplifier) Left Channel Input Signal (Amplifier) 26 RIN_H 27 LIN_H 28 GND 29 LDOUT 1 Headphone Driver Input Signals Regulator Enable Ci6 1µF 24 BIAS CB 2 23 AMP_EN 3 22 HP_EN 4 21 PGND APA2058 Gnd 20 ROUTP LOUTP 6 19 ROUTN LOUTN 7 18 PVDD PVDD 8 17 HVDD VDD Gnd Power Amplifier Enable Headphone Driver Enable 0.47µF PGND 5 Gnd 30 VDD 31 GAIN0 32 GAIN1 0.1µF 2.2µF 25 LDO_EN CS3 VDD HVDD CPO 1µF HP_LO 16 CS5 0.1µF 2.2µF Gnd Headphone Jack 1µF HP_RO 15 CPF HVSS 14 CPN 12 CVSS 13 0.1µF 10µF CPP 10 CS1 CS2 CGND 11 NC 9 CS4 VSS Gnd Tip Sleeve Ring Single-ended input mode VDD Regulator Output CO2 CO1 Ci5 1µF Gnd 1µF Gain Control (Amplifier) Ci1 Right Channel GndC Input Signal i2 (Amplifier) C Left i3 Channel Ci4 Input Signal (Amplifier) Gnd Gnd 26 RIN_H 27 LIN_H 28 GND 29 LDOUT 30 VDD 31 GAIN0 32 GAIN1 0.1µF 2.2µF 25 LDO_EN CS3 RINN_A 1 Headphone Driver Input Signals Regulator Enable Ci6 1µF 24 BIAS 0.47µF CB Gnd Power Amplifier Enable Headphone Driver Enable 0.47µF RINP_A 2 23 AMP_EN 0.47µF LINP_A 3 22 HP_EN 0.47µF LINN_A 4 21 PGND APA2058 0.47µF PGND 5 LOUTP 6 19 ROUTN LOUTN 7 18 PVDD PVDD 8 17 HVDD VDD Gnd 20 ROUTP VDD HVDD CPO 1µF HP_LO 16 HP_RO 15 HVSS 14 VSS Gnd Tip Sleeve Copyright ANPEC Electronics Corp. Rev. A.3 - Aug., 2008 8 CS5 0.1µF 2.2µF Gnd Headphone Jack 1µF CPN 12 CPF CVSS 13 0.1µF 10µF CGND 11 CS1 CPP 10 CS2 NC 9 CS4 Ring www.anpec.com.tw APA2058 Typical Operating Characteristics (TA = +25°C, unless otherwise noted.) THD+N vs. Frequency THD+N vs. Output Power 10 PO=0.14W PO=0.7W 0.1 THD+N (%) 1 THD+N (%) 1 RL=4Ω fin=1kHz Ci=0.47µF AV=10dB BW<22kHz AMP Mode VDD=4.5V 0.1 VDD=5.0V PO=1.4W 0.01 VDD=5.5V 0.01 10m 100m 1 VDD=5.0V RL=4Ω Ci=0.47µF AV=10dB BW<22kHz AMP Mode 0.001 20 5 100 +0 TT V TTT TT =5.0V Common Mode Rejection Ratio (dB) DD RL=4Ω AV=10dB Ci=0.47µF -40 PO=200mW AMP Mode Crosstalk (dB) -20 -60 -80 Right to Left -100 Left to Right -120 100 1k -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 20 10k 20k VDD=5.0V RL=4Ω AV=10dB Vin=0.2VPP Ci=0.47µF Input Short AMP Mode 100 THD+N vs. Output Power THD+N vs. Frequency PO=0.09W 0.1 VDD=4.5V 0.1 VDD=5.0V 0.01 VDD=5.5V 0.01 10m 10k 20k 1 RL=8Ω fin=1kHz Ci=0.1µF AV=10dB BW<22kHz AMP Mode THD+N (%) THD+N (%) 1 1k Frequency (Hz) Frequency (Hz) 10 10k 20k CMRR vs. Frequency Crosstalk vs. Frequency +0 -140 20 1k Frequency (Hz) Output Power (W) 100m 1 0.001 20 5 PO=0.9W VDD=5.0V RL=8Ω AV=10dB Ci=0.47µF BW<22kHz AMP Mode 100 1k 10k 20k Frequency (Hz) Output Power (W) Copyright ANPEC Electronics Corp. Rev. A.3 - Aug., 2008 PO=0.45W 9 www.anpec.com.tw APA2058 Typical Operating Characteristics (Cont.) (TA = +25°C, unless otherwise noted.) Crosstalk vs. Frequency CMRR vs. Frequency +0 +0 TTTVTTT=5.0V T Common Mode Rejection Ratio (dB) -60 -80 Right to Left -100 Left to Right -120 -140 20 VDD=5.0V RL=8Ω AV=10dB -20 Vin=0.2VPP -30 Ci=0.47µF Input Short -40 AMP Mode -10 -50 -60 -70 -80 -90 -100 100 1k 20 10k 20k 100 +22 +200 +21 +180 Phase VDD=5.0V RL=8Ω AV=10dB Ci=0.47µF AMP Mode +7 10 100 1k 10k Gain (dB) Gain (dB) +9 +220 Phase (deg) Gain +8 +220 Gain +180 Phase +160 +19 +140 200k +18 VDD=5.0V RL=8Ω AV=21.6dB Ci=0.47µF AMP Mode 10 100 Output Noise Voltage vs. Frequency 1k +140 200k 10k Crosstalk vs. Frequency +0 Left channel -40 10u VDD=5.0V RL=8Ω AV=10dB Cin=0.47µF A-Wighting AMP Mode 20 100 VDD=5.0V HVDD=3.3V RL=4Ω(AMP) RL=10kΩ(HP) PO=200mW(AMP) AMP(active) mode HP mode -20 Crosstalk (dB) Output Noise Voltage (Vrms) +160 Frequency (Hz) Right channel 1u +200 +20 Frequency (Hz) 50u 10k 20k Frequency Response Frequency Response +11 +10 1k Frequency (Hz) Frequency (Hz) Phase (deg) Crosstalk (dB) DD RL=8Ω -20 AV=10dB Ci=0.47µF -40 PO=130mW AMP Mode -60 -80 Left(AMP) to Right(HP) -100 Right(AMP) to Right(HP) -120 1k -140 20 10k 20k 100 Right(AMP) to Left(HP) 1k 10k 20k Frequency (Hz) Frequency (Hz) Copyright ANPEC Electronics Corp. Rev. A.3 - Aug., 2008 Left(AMP) to Left(HP) 10 www.anpec.com.tw APA2058 Typical Operating Characteristics (Cont.) (TA = +25°C, unless otherwise noted.) THD+N vs. Output Voltage 10 10 VDD=5.0V HVDD=3.3V fin=1kHz Ci=1µF BW<22kHz In Phase HP Mode 0.1 VDD=5.0V HVDD=3.3V RL=16Ω fin=1kHz Ci=1µF BW<22kHz HP Mode 1 THD+N (%) 1 THD+N (%) THD+N vs. Output Power RL=16Ω In Phase Mono 0.1 RL=32Ω RL=320Ω 0.01 RL=10KΩ 0.01 10m 0.001 0 500m 1 1.5 2 2.5 3 100m THD+N vs. Frequency Crosstalk vs. Frequency 1 +0 VDD=5.0V HVDD=3.3V RL=16Ω Ci=1µF BW<22kHz HP Mode 0.1 PO=13mW -40 PO=63mW PO=125mW 0.01 VDD=5.0V HVDD=3.3V RL=16Ω PO=16mW Ci=1µF HP Mode -20 Crosstalk (dB) THD+N (%) 500m Output Power (W) Output Voltage (Vrms) -60 Right to Left -80 Left to Right -100 -120 0.001 -140 20 100 1k 10k 20k 20 100 1 VDD=5.0V HVDD=3.3V RL=32Ω fin=1kHz Ci=1µF BW<22kHz HP Mode VDD=5.0V HVDD=3.3V RL=32Ω Ci=1µF BW<22kHz HP Mode 0.1 In Phase 0.1 THD+N (%) THD+N (%) 1 10k 20k THD+N vs. Frequency THD+N vs. Output Power 10 1k Frequency (Hz) Frequency (Hz) Mono PO=9mW PO=88mW 0.01 PO=44mW 0.01 10m 100m 0.001 300m Output Power (mW) Copyright ANPEC Electronics Corp. Rev. A.3 - Aug., 2008 20 100 1k 10k 20k Frequency (Hz) 11 www.anpec.com.tw APA2058 Typical Operating Characteristics (Cont.) (TA = +25°C, unless otherwise noted.) Output Noise Voltage vs. Frequency Crosstalk vs. Frequency 50u +0 Crosstalk (dB) -40 VDD=5.0V HVDD=3.3V RL=32Ω PO=12mW Ci=1µF HP Mode Output Noise Voltage (Vrms) -20 -60 Right to Left -80 Left to Right -100 -120 -140 20 100 1k Left channel VDD=5.0V HDD=3.3V RL=32Ω Ci=1µF A-Weighting HP Mode 1u 10k 20k Right channel 10u 20 100 Frequency (Hz) +0 +220 Gain T VT =5.0V DD HVDD=3.3V RL=8Ω(AMP) RL=16Ω(HP) PO=16mW(HP) AMP Mode HP(active) Mode +200 +2 +180 Phase VDD=5.0V HVDD=3.3V RL=32Ω Ci=1µF HP Mode +0 10 100 -40 Crosstalk (dB) +3 Phase (deg) Gain (dB) -20 +1 -60 Left(HP) to Right(AMP) -80 Right(HP) to Left(AMP) -100 Right(HP) to Right(AMP) Left(HP) to Left(AMP) +160 -120 -140 1k 10k 200k 20 +140 100 THD+N vs. Frequency 10k 20k Crosstalk vs. Frequency +0 1 VDD=5.0V HVDD=3.3V RL=320Ω Ci=1µF BW<22kHz HP Mode -20 -40 Crosstalk (dB) THD+N (%) 1k Frequency (Hz) Frequency (Hz) 0.1 10k 20k Crosstalk vs. Frequency Frequency Response +4 1k Frequency (Hz) VO=0.15V 0.01 VDD=5.0V HVDD=3.3V RL=320Ω VO=0.22Vrms Ci=1µF HP Mode -60 Right to Left -80 Left to Right -100 VO=0.75V -120 VO=1.5V 0.001 20 100 1k -140 20 10k 20k Copyright ANPEC Electronics Corp. Rev. A.3 - Aug., 2008 100 1k 10k 20k Frequency (Hz) Frequency (Hz) 12 www.anpec.com.tw APA2058 Typical Operating Characteristics (Cont.) (TA = +25°C, unless otherwise noted.) THD+N vs. Frequency VDD=5.0V HVDD=3.3V RL=10kΩ Ci=1µF BW<22kHz HP Mode -40 VO=0.16V 0.01 -60 Right to Left -80 Left to Right -100 VO=1.6V 0.001 20 VDD=5.0V HVDD=3.3V RL=10kΩ VO=0.22Vrms Ci=1µF HP Mode -20 -120 VO=0.8V 100 1k -140 20 10k 20k 100 Output Noise Voltage vs. Frequency 10k 20k Frequency Response +4 50u +220 Gain +3 Left channel Right channel 10u Gain (dB) Output Noise Voltage (Vrms) 1k Frequency (Hz) Frequency (Hz) VDD=5.0V HDD=3.3V RL=10kΩ Ci=1µF A-Weighting HP Mode +2 +180 Phase VDD=5.0V HVDD=3.3V RL=10kΩ Ci=0.47µF HP Mode +1 +0 1u 20 +200 100 1k 10k 20k 10 100 Phase (deg) THD+N (%) 0.1 Crosstalk vs. Frequency +0 Crosstalk (dB) 1 +160 1k +140 200k 10k Frequency (Hz) Frequency (Hz) HP Attenuation vs. Frequency AMP Attenuation vs. Frequency +0 -10 AMP Attenuation (dB) -30 -40 -50 -10 VDD=5.0V RL=8Ω AV=10dB Ci=0.47µF VO=2Vrms (AMP enable) AMP Mode (disable) -20 -30 HP Attenuation (dB) -20 -60 -70 -80 Left channel -90 -40 -50 VDD=5.0V HVDD=3.3V RL=32Ω Ci=1µF VO=1Vrms (HP enable) HP Mode (disable) -60 -70 -80 -90 -100 Right channel -110 -110 Left channel -120 20 -120 20 Right channel -100 100 1k 10k 20k Copyright ANPEC Electronics Corp. Rev. A.3 - Aug., 2008 100 1k 10k 20k Frequency (Hz) Frequency (Hz) 13 www.anpec.com.tw APA2058 Typical Operating Characteristics (Cont.) (TA = +25°C, unless otherwise noted.) HP Attenuation vs. Frequency PSRR vs. Frequency -20 +0 -10 AMP Attenuation (dB) -30 -40 -50 Power Supply Rejection Ratio (dB) VDD=5.0V HVDD=3.3V RL=10kΩ Ci=1µF VO=1Vrms (HP enable) HP Mode (disable) -20 -60 Right channel -70 -80 Left channel -90 T VDD=5.0V RL=8Ω AV=10dB Ci=0.47µF Vrr=0.2Vrms AMP Mode -30 -40 -50 -60 -70 -80 -90 -100 -100 -110 -110 -120 TT 20 100 1k Vrr:Ripple Voltage on VDD -120 10k 20k 20 100 Frequency (Hz) PSRR vs. Frequency -20 -40 -50 Power Supply Rejection Ratio (dB) VDD=5.0V HVDD=3.3V RL=32Ω Ci=1µF Vrr=0.2Vrms HP Mode -30 -60 -70 -80 -90 -100 -110 Vrr:Ripple Voltage on HVDD Power Supply Rejection Ratio (dB) -120 20 100 1k VDD=5.0V HVDD=3.3V RL=10kΩ Ci=1µF Vrr=0.2Vrms HP Mode -40 -50 -60 -70 -80 -90 -100 -110 Vrr:Ripple Voltage on HVDD -120 10k 20k 20 100 1k 10k 20k Frequency (Hz) Frequency (Hz) PSRR vs. Frequency LDO Output Voltage vs. Supply Voltage 3.35 VDD=5.0V -10 I =10mA O Vrr=0.2Vrms -20 LDO Mode 3.34 -40 -50 -60 -70 1k 3.31 3.30 IO=100mA IO=10mA 3.29 IO=200mA 3.28 3.27 3.25 4.5 10k 20k 4.7 4.9 5.1 5.3 5.5 Supply Voltage (Volt) Frequency (Hz) Copyright ANPEC Electronics Corp. Rev. A.3 - Aug., 2008 3.32 3.26 Vrr:Ripple Voltage on VDD 100 LDO Mode 3.33 -30 20 TTT TT TT -30 +0 -80 10k 20k PSRR vs. Frequency -20 T Output Voltage (Volt) Power Supply Rejection Ratio (dB) TTTTT TT 1k Frequency (Hz) 14 www.anpec.com.tw APA2058 Typical Operating Characteristics (Cont.) (TA = +25°C, unless otherwise noted.) LDO Drop-Out Voltage vs. Output Current 0.15 2.0 1.8 1.6 0.12 Power Dissipation (W) Drop-Out Voltage (Volt) LDO Mode Power Dissipation vs. Output Power 0.09 0.06 0.03 1.4 VDD=5.5V 1.2 VDD=5.0V 1.0 VDD=4.5V 0.8 0.6 RL=4Ω fin=1kHz Mono AMP Mode 0.4 0.2 0 0 0.1 0.2 0.0 0.0 0.3 0.5 1.0 Output Current (A) 1.5 2.0 2.5 3.0 Output Power (W) Power Dissipation vs. Output Power 300 1.0 Power Dissipation vs. Output Power 0.9 250 Power Dissipation (mW) Power Dissipation (W) 0.8 0.7 0.6 VDD=5.5V 0.5 150 VDD=5.0V 0.4 VDD=4.5V 0.3 0.1 0.5 1.0 RL=32Ω 100 RL=8Ω fin=1kHz Mono AMP Mode 0.2 0.0 0.0 RL=16Ω 200 1.5 VDD=5.0V HVDD=3.3V fin=1kHz Mono HP Mode 50 0 2.0 0 25 50 Output Power vs. Supply Voltage RL=4Ω AV=10dB fin=1kHz Mono AMP Mode 1.8 2.4 2.2 THD+N=10% 2.0 175 200 RL=8Ω AV=10dB fin=1kHz Mono AMP Mode 1.6 THD+N=10% 1.4 1.2 1.8 1.6 150 2.0 Output Power (W) Output Power (W) 2.6 100 125 Output Power vs. Supply Voltage 3.0 2.8 75 Output Power (mW) Output Power (W) THD+N=1% THD+N=1% 1.0 1.4 4.5 4.6 4.7 4.8 4.9 5.0 5.1 5.2 5.3 5.4 5.5 0.8 4.5 4.6 4.7 Supply Voltage (V) Copyright ANPEC Electronics Corp. Rev. A.3 - Aug., 2008 15 4.8 4.9 5.0 5.1 5.2 Supply Voltage (V) 5.3 5.4 5.5 www.anpec.com.tw APA2058 Typical Operating Characteristics (Cont.) (TA = +25°C, unless otherwise noted.) Supply Cuttent vs. Output Power Supply Cuttent vs. Output Power 0.8 VDD=5.5V 0.7 0.45 VDD=5.0V 0.6 0.5 0.4 0.3 RL=4Ω AV=10dB fin=1kHz Mono AMP Mode 0.2 0.1 0.0 0.0 0.5 1.0 VDD=5.5V 0.40 VDD=4.5V Supply Current (A) Supply Current (A) 0.50 1.5 2.0 2.5 VDD=5.0V 0.35 VDD=4.5V 0.30 0.25 0.20 RL=8Ω AV=10dB fin=1kHz Mono AMP Mode 0.15 0.10 0.05 0.00 0.0 3.0 0.5 Output Power (W) Output Power vs. Load Resistance 1.5 2.0 Output Power vs. Load Resistance 2.6 250 VDD=5.0V AV=10dB fin=1kHz Mono AMP Mode 2.2 2.0 1.8 1.6 THD+N=10% 1.4 VDD=5.0V HVDD=3.3V fin=1kHz Mono HP Mode 200 Output Power (W) 2.4 Output Power (W) 1.0 Output Power (W) 1.2 1.0 150 THD+N=10% 100 THD+N=1% 50 0.8 THD+N=1% 0.6 0.4 4 8 12 16 20 24 28 0 10 32 100 Supply Current vs. Supply Voltage Supply Current (mA) 10 Supply Current vs. Supply Voltage 3.0 HVDD=3.3V No Load 2.5 Supply Current (mA) 11 9 8 AMP,HP enable IHVDD=2.2mA 7 6 1000 Load Resistance (Ω) Load Resistance (Ω) AMP enable IHVDD=0.1mA HP enable IHVDD=2.2mA AMP,HP enable IVDD=9.3mA 1.5 HP enable IVDD=5.0mA 1.0 0.0 3.3 4 4.5 4.6 4.7 4.8 4.9 5.0 5.1 5.2 5.3 5.4 5.5 AMP enable IVDD=4.9mA 3.4 3.4 3.5 3.5 3.6 3.6 Supply Voltage(V) Supply Voltage(V) Copyright ANPEC Electronics Corp. Rev. A.3 - Aug., 2008 2.0 0.5 5 VDD=5.0V No Load 16 www.anpec.com.tw APA2058 Operating Waveforms Power On Power Off VDD VDD 1 1 2 2 VROUT VROUT 3 3 VHP_RO VHP_RO CH1: VDD, 2V/Div, DC CH2: VROUT, 20mV/Div, DC CH3: VHP_RO, 20mV/Div, DC CH1: VDD, 2V/Div, DC TIME: 5ms/Div TIME: 20ms/Div CH2: VROUT, 20mV/Div, DC CH3: VHP_RO, 20mV/Div, DC Speaker Enable Speaker Disable VAMP_EN VAMP_EN 1 1 VOUTP VOUTP 2 2 CH1: VAMP_EN, 2V/Div, DC CH1: VAMP_EN, 2V/Div, DC CH2: VOUTP, 1V/Div, AC CH2: VOUTP, 1V/Div, AC TIME: 5ms/Div TIME: 1ms/Div Copyright ANPEC Electronics Corp. Rev. A.3 - Aug., 2008 17 www.anpec.com.tw APA2058 Operating Waveforms (Cont.) Headphone Disable Headphone Enable VHP_EN VHP_EN 1 1 VHP_RO VHP_RO 2 2 CH1: VHP_EN, 2V/Div, DC CH1: VHP_EN, 2V/Div, DC CH2: VHP_LO, 1V/Div, AC CH2: VHP_LO, 1V/Div, AC TIME: 5ms/Div TIME: 1ms/Div LDO Power On LDO Power Off VDD VDD 1 1 VLDOUT VLDOUT 2 2 CH1: VDD, 2V/Div, DC CH1: VDD, 2V/Div, DC CH2: VLDOUT, 2V/Div, DC CH2: VLDOUT, 2V/Div, DC TIME: 200µs/Div TIME: 20ms/Div Copyright ANPEC Electronics Corp. Rev. A.3 - Aug., 2008 18 www.anpec.com.tw APA2058 Operating Waveforms (Cont.) LDO Disable LDO Enable VLDO_EN VLDO_EN 1 1 VLDOUT VLDOUT 2 2 CH1: VLDO_EN, 2V/Div, DC CH1: VLDO_EN, 2V/Div, DC CH2: VLDOUT, 1V/Div, DC CH2: VLDOUT, 1V/Div, DC TIME: 1ms/Div TIME: 1ms/Div LDO Load Transient LDO Line Transient 1 VDD ILDOUT 1 2 VLDOUT VLDOUT 2 CH1: ILDOUT, 200mA/Div, DC CH2: VLDOUT, 5mV/Div, DC VLDOUT Offset = 3.3V TIME: 200µs/Div CH1: VDD, 1V/Div, DC VDD Offset = 5.5V CH2: VLDOUT, 10mV/Div, DC VLDOUT Offset = 3.3V TIME: 200µs/Div Copyright ANPEC Electronics Corp. Rev. A.3 - Aug., 2008 19 www.anpec.com.tw APA2058 Operating Waveforms (Cont.) GSM Power Supply Rejection vs. Frequency GSM Power Supply Rejection vs. Time 1 AMP Output Voltage (dBV) -50 VROUT 2 VHP_RO 3 CH1: V DD, 500mV/Div, DC VDD Offset = 5.0V CH2: V ROUT , 20mV / Div, DC -100 -150 +0 Supply Voltage (dBV) +0 VDD -50 -100 -150 0 400 800 1.2k 1.6k 2k Frequency (Hz) CH3: VHP_RO , 20mV / Div, DC TIME: 2ms/Div +0 -50 HP Output Voltage (dBV) -100 -150 +0 Supply Voltage (dBV) GSM Power Supply Rejection vs. Frequency -50 -100 -150 0 400 800 1.2k 1.6k 2k Frequency (Hz) Copyright ANPEC Electronics Corp. Rev. A.3 - Aug., 2008 20 www.anpec.com.tw APA2058 Function Description Fully Differential Amplifier The Cap-free headphone drivers use a charge pump to The APA2058’s power amplifier is a fully differential amplifier with differential inputs and outputs. The fully invert the positive power supply (VDD) to negative power supply (VSS) (see Figure 1). The headphone amplifiers differential amplifier has some advantages versus traditional amplifier. Firstly, don’t need the input coupling ca- operate at this bipolar power supply, and the outputs reference refers to the ground. This feature eliminates the pacitors because the common-mode feedback will compensate the input bias. The inputs can be biased from output capacitor that using in conventional single-ended headphone amplifiers. In addition, the power supply rail 0.5V~VDD-0.5V, and the outputs are still biased at midsupply voltage of the power amplifier. If the inputs are for Cap-free headphone drivers has almost 1.5X compare to the single power supply rail headphone drivers. biased out of the input range, the coupling capacitors are required. Secondly, the fully differential amplifier has out- Thermal Protection The thermal protection circuit limits the junction temperature of the APA2058. When the junction tempera- standing immunity against supply voltage ripple (217Hz) caused by GSM RF transmitters’ signal, which is better ture exceeds TJ = +150oC, a thermal sensor turns off the amplifier, allowing the devices to cool. The thermal sen- than the typical audio amplifier. Gain Setting Function For the convenient uses, the APA2058’s power amplifiers provide four gain setting options by GAIN0 and GAIN1 sor allows the amplifier to start-up after the junction temperature down about 125 oC. The thermal protection is designed with a 25 o C hysteresis to lower the average TJ during continuous thermal overload conditions, increas- pins. GAIN0 GAIN1 AV(dB) 0 0 10 0 1 12 1 0 15.6 1 1 21.6 ing lifetime of the ICs. Over-Current Protection (OCP) • The power amplifier monitors the output buffers’current. When the over current occurs, the output buffers’current will be reduced and limited to a fold-back current level. The power amplifier will go back to normal operation until the over-current current situation has been removed. In Headphone Mode Operation VOUT Conventional Headphone Driver HVDD addition, if the over-current period is long enough and the IC’s junction temperature reaches the thermal protection HVDD/2 threshold, the IC enters thermal protection mode. • The LDO regulator provides a current-limit circuitry, which monitors and controls P-channel MOS’s gate Gnd voltage, limiting the output current to 0.4A. For reliable operation, the device should not be operated in current- HVDD VOUT Cap-free Headphone Driver limit for extended period time. When the output voltage drops below 0.6V, which is caused by the over load or Gnd short circuit, the internal short circuit current-limit circuitry limits the output current down to 250mA. The short circuit current-limit is used to reduce the power dissipation during short circuit condition. The short circuit current-limit VSS has a blanking time feature after the under-voltage lockout threshold is reached, therefore, it will avoid the output Figure 1: The Cap-Free Headphone Driver’s Operation causing short circuit current-limit protection during startup; the blanking time is about 600µs. Copyright ANPEC Electronics Corp. Rev. A.3 - Aug., 2008 21 www.anpec.com.tw APA2058 Function Description (Cont.) Over-Current Protection (OCP) (Cont.) • The charge pump monitors the output voltage (V SS ). In addition, it has an over voltage protection to avoid over current occuring on headphone driver’s output. When the output voltage (VSS) is greater than –2V, the charge pump will turn off the charge pump’s output. The charge pump’s output will turn on again if the situation has been removed. Typical under voltage protection threshold is -2V with 0.5V hysteresis. Low Drop-Out (LDO) Regulator The LDO regulator’s output provides maximum 200mA drive capacity for external audio codec. A 2.2µF decoupling capacitor with 0.1µf capacitor (filtering the high frequency noise) is recommended at LDO regulator ‘s output. The LDO regulator has built-in under-voltage lockout circuits to keep the output shuting off until internal circuitry is operating properly. The under-voltage lockout function initiates a soft-start process after input voltage exceeds its rising under-voltage lockout threshold during power on. The internal soft-start circuit controls the rise rate of the output voltage and limits the current surge during startup. Approximate 20µs delay time after the VDD is over the under-voltage lockout threshold; the LDO regulator’s output voltage starts the soft-start. The typical soft-start interval is about 130µs and the under-voltage lockout threshold is 2.5V with 0.15V hysteresis. Enable Mode The APA2058 provides the independent enable control functions and allows user disable any main circuit blocks when not in using, and these can save the power consumption. In addition, if either the power amplifier or the headphone driver is disabled, the released time will happen immediately when enable the power amplifier or the headphone driver. However, if both the power amplifier and the headphone driver are disabled at the same time, the released time will be the TSTART-UP Time when enable one of them. Disable all blocks ( V AMP_EN =5V, VHP_EN= VLDO_EN=0V), The APA2058 enters the shutdown mode, and only consumption 5µA(Max.) at VDD supply current and 2µA(Max.) at HVDD supply current. Copyright ANPEC Electronics Corp. Rev. A.3 - Aug., 2008 22 www.anpec.com.tw APA2058 Application Information Windows VistaTM Premium Mobile Requirement Device Type Requirement Value Full Scale Output voltage THD+N Analog Line Output Jack (RL=10kΩ) Line output cross-talk Noise level during system activity Full Scale Output voltage Analog Headphone Output Jack (RL=320Ω) THD+N Headphone output cross-talk Noise level during system activity Full Scale Output voltage Analog Headphone Output Jack (RL=32Ω) 2.3Vrms -70dB 20Hz~20kHz -70dB 20Hz~20kHz ≤-65dBFS 100Hz~20kHz ≤-50 dB 100Hz~15kHz ≤-80dBFS A-weighting ≥0.3Vrms -78dB 100Hz~20kHz -75 dB 100Hz~15kHz -100dBFS A-weighting 2.0Vrms -68dB 100Hz~20kHz -70 dB 100Hz~15kHz ≤-45dBFS 100Hz~20kHz ≤-50dB 100Hz~15kHz ≤-80dBFS A-weighting THD+N Headphone output cross-talk Noise level during system activity APA2058 typical performance ≥0.707Vrms ≤-65dBFS 20Hz~20kHz ≤-50dB, 20Hz~15kHz ≤-80dBFS A-weighting ≥0.707Vrms -100dBFS A-weighting 2.3Vrms -100dBFS A-weighting Input Capacitor (Ci) leakage tantalum or ceramic capacitor is the best choice. In the typical application, an input capacitor, Ci, is required When polarized capacitors are used, the positive side of the capacitors should face the amplifiers’ inputs in most to allow the amplifier to bias the input signal to the proper DC level for optimum operation. In this case, Ci and the applications because the DC level of the amplifiers’ inputs are held at VDD/2. Please note that it is important to minimum input impedance Ri form a high-pass filter with the corner frequency is determined in the following equation: fC(highpass ) = 1 2 πR iC i confirm the capacitor polarity in the application. Power Supply Decoupling Capacitor, Cs (1) The APA2058 is a high-performance CMOS audio ampli- The value of Ci must be considered carefully because it directly affects the low frequency performance of the circuit. fier that requires adequate power supply decoupling to ensure the output total harmonic distortion (THD) to be Consider the example where Ri is 20kΩ and the specification calls for a flat bass response down to 40Hz. The as low as possible. Power supply decoupling also prevents the oscillations caused by long lead length between equation is reconfigured below : 1 Ci = 2 π R i fc the amplifier and the speaker. The optimum decoupling is achieved by using two different types of capacitors that target on different types of (2) Consider the variation of input resistance (Ri), the value noise on the power supply leads. For higher frequency transients, spikes, or digital hash on the line, a good low of Ci should be 0.2µF. Therefore, it’s better to choose a value in the range from 0.22µF to 1.0µF. A further consid- equivalent-series- resistance (ESR) ceramic capacitor, (0.1µF typically) placed as close as possible to the device eration for this capacitor is the leakage path from the input source through the input network (Ri + Rf, Ci) to the VDD lead works best. load. This leakage current creates a DC offset voltage at the input to the amplifier that reduces useful headroom, es- For filtering lower frequency noise signals, a large aluminum electrolytic capacitor of 10µF or greater placed near the audio power amplifier is recommended. pecially in high gain applications. For this reason, a lowCopyright ANPEC Electronics Corp. Rev. A.3 - Aug., 2008 23 www.anpec.com.tw APA2058 Application Information (Cont.) Charge Pump Flying Capacitor (CPF) 2. The output traces should be short, wide ( >50mil), and The flying capacitor affects the load transient of the charge pump. If the capacitor’s value is too small, it will degrade symmetric. 3. The input trace should be short and symmetric. the charge pump’s current driver capability and the performance of headphone amplifier. Increasing the flying 4. The power trace width should greater than 50 mil. 5. The TQFN5x5-32A thermal pad should be soldered capacitor’s value will improve the load transient of charge pump. Recommend using the low ESR ceramic capaci- on PCB, and the ground plane needs solded mask (to avoid short circuit) except the thermal pad area. tors (X5R type is recommended) above 1µf. Charge Pump Output Capacitor (CPO) The output capacitor’s value affects the power ripple directly at VSS. Increasing the value of output capacitor will reduce the power ripple. The ESR of output capacitor affects the load transient of VSS. Low ESR and greater than 1µf ceramic capacitor (X5R type is recommended) is recommendation. Layout Recommendation ThermalVia diameter 0.3mm X 9 1.15mm 0.25mm 3.6mm 4.1mm 0.5mm 3.6mm Solder Mask to Prevent Short Circuit TQFN5X5-32A Land Pattern Recommendation Ground plane for ThermalP AD Figure 5. TQFN5X5-32A Land Pattern Recommendation 1. All components should be placed close to the APA2058. For example, the input capacitor (Ci) should be close to APA2058’s input pins to avoid causing noise coupling to APA2058’s high impedance inputs; the decoupling capacitor (CS ) should be placed by the APA2058’s power pin to decouple the power rail noise. Copyright ANPEC Electronics Corp. Rev. A.3 - Aug., 2008 24 www.anpec.com.tw APA2058 Package Information TQFN5x5-32A D b E A D2 A1 A3 L K E2 Pin 1 Corner e S Y M B O L TQFN5x5-32A MILLIMETERS INCHES MIN. MAX. MIN. MAX. A 0.70 0.80 0.028 0.031 A1 0.00 0.05 0.000 0.002 A3 0.20 REF 0.008 REF b 0.18 0.30 0.007 0.012 D 4.90 5.10 0.193 0.201 D2 3.10 3.50 0.122 0.138 E 4.90 5.10 0.193 0.201 3.50 0.122 0.138 0.45 0.014 E2 3.10 e 0.50 BSC L 0.35 K 0.20 Copyright ANPEC Electronics Corp. Rev. A.3 - Aug., 2008 0.020 BSC 0.018 0.008 25 www.anpec.com.tw APA2058 Carrier Tape & Reel Dimensions P0 P2 P1 A B0 W F E1 OD0 K0 A0 A OD1 B B T SECTION A-A SECTION B-B H A d T1 Application A H 330.0±2.00 50 MIN. TQFN5x5-32A T1 C d D W E1 12.4+2.00 13.0+0.50 -0.00 -0.20 1.5 MIN. 20.2 MIN. 12.0±0.30 1.75±0.10 P0 P1 P2 4.0±0.10 8.0±0.10 2.0±0.10 D0 1.5+0.10 -0.00 D1 1.5 MIN. F 5.5±0.10 T A0 B0 K0 0.6+0.00 -0.40 5.30±0.20 5.30±0.20 1.30±0.20 (mm) Devices Per Unit Package Type TQFN5x5-32A Unit Tape & Reel Copyright ANPEC Electronics Corp. Rev. A.3 - Aug., 2008 Quantity 2500 26 www.anpec.com.tw APA2058 Taping Direction Information TQFN5x5-32A USER DIRECTION OF FEED Reflow Condition (IR/Convection or VPR Reflow) tp TP Critical Zone TL to TP Ramp-up Temperature TL tL Tsmax Tsmin Ramp-down ts Preheat 25 t 25°C to Peak Time Reliability Test Program Test item SOLDERABILITY HOLT PCT TST ESD Latch-Up Method MIL-STD-883D-2003 MIL-STD-883D-1005.7 JESD-22-B,A102 MIL-STD-883D-1011.9 MIL-STD-883D-3015.7 JESD 78 Copyright ANPEC Electronics Corp. Rev. A.3 - Aug., 2008 27 Description 245°C, 5 sec 1000 Hrs Bias @125°C 168 Hrs, 100%RH, 121°C -65°C~150°C, 200 Cycles VHBM > 2KV, VMM > 200V 10ms, 1tr > 100mA www.anpec.com.tw APA2058 Classification Reflow Profiles Profile Feature Average ramp-up rate (TL to TP) Preheat - Temperature Min (Tsmin) - Temperature Max (Tsmax) - Time (min to max) (ts) Time maintained above: - Temperature (TL) - Time (tL) Peak/Classification Temperature (Tp) Time within 5°C of actual Peak Temperature (tp) Ramp-down Rate Sn-Pb Eutectic Assembly Pb-Free Assembly 3°C/second max. 3°C/second max. 100°C 150°C 60-120 seconds 150°C 200°C 60-180 seconds 183°C 60-150 seconds 217°C 60-150 seconds See table 1 See table 2 10-30 seconds 20-40 seconds 6°C/second max. 6°C/second max. 6 minutes max. 8 minutes max. Time 25°C to Peak Temperature Note: All temperatures refer to topside of the package. Measured on the body surface. Table 1. SnPb Eutectic Process – Package Peak Reflow Temperatures Volume mm3 ≥350 225 +0/-5°C 225 +0/-5°C 3 Package Thickness <2.5 mm ≥2.5 mm Volume mm <350 240 +0/-5°C 225 +0/-5°C Table 2. Pb-free Process – Package Classification Reflow Temperatures 3 3 3 Volume mm Volume mm Volume mm <350 350-2000 >2000 <1.6 mm 260 +0°C* 260 +0°C* 260 +0°C* 1.6 mm – 2.5 mm 260 +0°C* 250 +0°C* 245 +0°C* ≥2.5 mm 250 +0°C* 245 +0°C* 245 +0°C* * Tolerance: The device manufacturer/supplier shall assure process compatibility up to and including the stated classification temperature (this means Peak reflow temperature +0°C. For example 260°C+0°C) at the rated MSL level. Package Thickness Customer Service Anpec Electronics Corp. Head Office : No.6, Dusing 1st Road, SBIP, Hsin-Chu, Taiwan, R.O.C. Tel : 886-3-5642000 Fax : 886-3-5642050 Taipei Branch : 2F, No. 11, Lane 218, Sec 2 Jhongsing Rd., Sindian City, Taipei County 23146, Taiwan Tel : 886-2-2910-3838 Fax : 886-2-2917-3838 Copyright ANPEC Electronics Corp. Rev. A.3 - Aug., 2008 28 www.anpec.com.tw