APA2051 2.4W Stereo Audio Power Amplifier (with Gain Setting) & Capfree Headphone Driver Features • • • • General Description Operating Voltage – HVDD= 3.0~3.6V The APA2051 is a monolithic integrated circuit, which combines a stereo power amplifier and a stereo output – VDD= 4.5~5.5V No Output Capacitor at Headphone Amplifier capacitor-less headphone amplifier. The stereo power amplifier provides 19-steps gain setting for flexible Required Meeting VISTA Requirement application. The headphone amplifier is ground-reference output, and no need the output capacitors for DC Low Distortion AMP Mode blocking. The advantages of eliminating the output capacitor are saving cost, PCB’s space, and component – THD+N=56dB, at VDD = 5V, RL = 4Ω, PO=1.5W – THD+N=64dB, at VDD = 5V, RL = 8Ω, PO=0.9W height. Both the de-pop circuitry and the thermal shutdown protection circuitry are integrated in the APA2051, which re- HP Mode – THD+N=73dB, at HVDD=3.3V, RL=16Ω duces pops and clicks noise during power on/off and in shutdown mode. Thermal shutdown protects the chip PO=125mW – THD+N=77dB, at HVDD=3.3V, RL=32Ω, from being destroyed by over-temperature failure. To simplify the audio system design in notebook computer PO=88mW – THD+N=85dB, at HVDD=3.3V, RL=10kΩ, • • • • • • • • applications, the APA2051 provides the internal gain setting, and these features can minimize components VO=1.7Vrms Output Power at 1% THD+N and PCB area. The APA2051 is available in TQFN4x4-28 package. This – 1.9W, at VDD = 5V, AMP Mode, RL = 4Ω – 1.2W, at VDD = 5V, AMP Mode, RL = 8Ω package is characterized by space saving and thermal efficiency. at 10% THD+N –2.4W at VDD = 5V, AMP Mode, RL = 4Ω Simplified Application Circuit –1.5W at VDD = 5V, AMP Mode, RL = 8Ω Depop Circuitry Integrated Internal 19-Steps Gain Setting for Flexible Appli cation Thermal Shutdown Protection and Over-Current Protection Circuitry Stereo Speakers High Supply Voltage Ripple Rejection Surface-Mount Packaging Audio Codec – TQFN4x4-28 (with Enhanced Thermal Pad) Lead Free and Green Devices Available (RoHS Compliant) Stereo Headphone Applications • • Note Book PCs LCD Monitor ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and advise customers to obtain the latest version of relevant information to verify before placing orders. Copyright ANPEC Electronics Corp. Rev. A.4 - Aug., 2009 1 www.anpec.com.tw APA2051 Ordering and Marking Information Package Code QB : TQFN4x4-28 Operating Ambient Temperature Range I : -40 to 85 oC Handling Code TR : Tape & Reel Assembly Material G : Halogen and Lead Free Device APA2051 Assembly Material Handling Code Temperature Range Package Code APA2051 QB : XXXXX - Date Code APA2051 XXXXX Note: ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which are fully compliant with RoHS. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J-STD-020D for MSL classification at lead-free peak reflow temperature. ANPEC defines “Green” to mean lead-free (RoHS compliant) and halogen free (Br or Cl does not exceed 900ppm by weight in homogeneous material and total of Br and Cl does not exceed 1500ppm by weight). 15 HVDD 16 HP_L 17 PVDD 18 ROUT- 19 ROUT+ 20 PGND 21 HP_EN Pin Configuration 14 NC BIAS 22 13 HP_R SET 23 12 VSS AMP_EN 24 APA2051 VDD 25 11 CP10 CGND GND 26 PVDD 7 LOUT- 6 LOUT+ 5 PGND 4 CVDD NC 3 CP+ 8 INL_A 1 9 INL_H 2 INR_A 27 INR_H 28 (TQFN4X4-28) (Top view) Absolute Maximum Ratings (Note 1) (Over operating free-air temperature range unless otherwise noted.) Symbol VDD HVDD, VSS VSET, VAMP_EN, VHP_EN Parameter Rating Supply Voltage (PVDD, CVDD, VDD) -0.3 to 6 Supply Voltage (HVDD) Supply Voltage (VSS) +0.3 to -6 Input Voltage TA Operating Ambient Temperature Range TJ Maximum Junction Temperature V V 0 to VDD+0.3V TSTG Storage Temperature Range TSDR Maximum Lead Soldering Temperature, 10 Seconds PD Unit Power Dissipation -40 to 85 °C 150 °C -65 to +150 °C 260 °C Internally Limited W Note 1 : Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Copyright ANPEC Electronics Corp. Rev. A.4 - Aug., 2009 2 www.anpec.com.tw APA2051 Thermal Characteristics Symbol θJA Parameter Thermal Resistance - Junction to Ambient Typical Value Unit (Note 2) o 45 TQFN4x4-28 C/W Note 2 : 3.42 in2 printed circuit board with 2OZ trace and copper through 10 vias of 15mil diameter vias. The thermal pad on the TQFN4x428 packages with solder on the printed circuit board. Recommended Operating Conditions Symbol Parameter VDD Supply Voltage HVDD Supply Voltage Range Unit 4.5 ~ 5.5 V 3.0 ~ 3.6 V VIH High Level Threshold Voltage AMP_EN, HP_EN 2~ V VIL Low Level Threshold Voltage AMP_EN, HP_EN ~ 0.8 V Vicm Common Mode Input Voltage for Amplifier ~ VDD-1 for Headphone Amplifier Shutdown VSET Input Voltage V ~ HVDD-1 ~ 0.8 Gain Setting Fix Gain 2 ~ 4.2 V 4.5 ~ V Electrical Characteristics VDD = 5V, HVDD = 3.3V, GND = PGND = CPGND = 0V, TA= 25°C (unless otherwise noted). Symbol VDD HVDD Parameter APA2051 Test Conditions Unit Min. Typ. Max. Supply Voltage 4.5 - 5.5 V Headphone Amplifier Supply Voltage 3.0 - 3.6 V VDD Supply Current Only Speaker mode, - 17.5 29 IHVDD HVDD Supply Current AMP_EN = HP_EN = 0V - 0.15 1 IVDD IVDD VDD Supply Current Only Headphone mode, - 12 20 IHVDD HVDD Supply Current HP_EN = AMP_EN = 5V - 3 5 IVDD VDD Supply Current - 20 35 IHVDD HVDD Supply Current All Enable, HP_EN=5V and AMP_EN = 0V ISD(HVDD) HVDD Shutdown Current ISD(VDD) VDD Shutdown Current SET = 0V - 3 5 - 50 90 - 1 10 mA µA IAMP_EN Input Current AMP_EN - 1 - µA IHP_EN Input Current HP_EN - 10 15 µA THD+N =1%, fin =1kHz RL =4Ω RL =8Ω 1.9 1.2 - 1.0 THD+N =10%, fin =1kHz RL =4Ω RL =8Ω 2.4 1.5 - 1.3 - - 10 SPEAKER MODE PO VOS Output Power Output Offset Voltage Copyright ANPEC Electronics Corp. Rev. A.4 - Aug., 2009 RL =8Ω, Gain =10.5dB 3 W mV www.anpec.com.tw APA2051 Electrical Characteristics (Cont.) VDD = 5V, HVDD = 3.3V, GND = PGND = CPGND = 0V, TA= 25°C (unless otherwise noted). Symbol Parameter APA2051 Test Conditions Unit Min. Typ. Max. fin =1kHz PO = 1.5W, RL =4Ω PO = 0.9W, RL =8Ω - 0.15 0.06 - % fin =1kHz, CB=2.2µF, RL=8Ω, PO=0.92W - 80 - dB fin =1kHz, CB=2.2µF, RL =4Ω, PO=1.5W - 83 - CB =2.2µF, RL =8Ω, fin =120Hz - 70 - dB PO =0.8W, RL =8Ω, A-weighting Filter - 90 - dB Gain =10.5dB, RL =8Ω, CB =2.2µF - 80 - µV (rms) THD+N = 1%, fin =1kHz RL = 16Ω RL = 32Ω 160 120 - 100 THD+N = 10%, fin =1kHz RL =16Ω RL =32Ω 200 165 - 150 THD+N=10% - 2.9 - THD+N=1% - 2.4 - SPEAKER MODE (CONT.) THD+N Crosstalk PSRR Total Harmonic Distortion Plus Noise Channel Separation Power Supply Rejection Ratio S/N Vn Noise Output Voltage HEADPHONE MODE Po Vo Vos THD+N Crosstalk PSRR Output Power Output Voltage Swing RL =10kΩ mW Output Offset Voltage RL =32Ω Total Harmonic Distortion Plus Noise fin = 1kHz PO = 125mW, RL =16Ω PO = 88mW, RL =32Ω VO=1.7Vrms, RL=10kΩ - fin =1kHz, RL =16Ω, PO =125mW - 80 - fin =1kHz, RL =32Ω, PO =88mW - 85 - fin =1kHz, RL=10kΩ, VO =1.7Vrms - 105 - CB = 2.2µF, RL=32Ω, fin =120Hz - 80 - Channel Separation Power Supply Rejection Ratio -10 With A-weighting Filter PO = 70mW, RL =32Ω VO =1.2Vrms, RL=10kΩ S/N +10 mV - % 0.02 0.02 0.005 95 92 Vrms - dB dB dB - 30 - µV (rms) Input Feedback Resistance 38 40 42 kΩ Fosc Switching Frequency 460 540 620 kHz CVSS Charge Dump (CVSS) - -0.98 VDD - V Req Charge Pump Requirement Resistance - 9 12 Ω Vn Noise Output Voltage Rf CB =2.2µF CHARGE PUMP Copyright ANPEC Electronics Corp. Rev. A.4 - Aug., 2009 No load 4 www.anpec.com.tw APA2051 Electrical Characteristics (Cont.) VDD = 5V, HVDD = 3.3V, GND = PGND = CPGND = 0V, TA= 25°C (unless otherwise noted). Symbol Parameter APA2051 Test Conditions Unit Min. Typ. Max. RL = 32Ω, VO = 1.1Vrms, fin = 1kHz - 115 - RL = 10kΩ, VO = 1.1Vrms, fin = 1kHz - 85 - dB RL = 8Ω, VO = 2Vrms, fin = 1kHz - 112 - dB RL = 4Ω, VO = 2Vrms, fin = 1kHz - 112 - dB - 90 - dB - 100 - dB - 85 - dB - 80 - dB - 120 - msec ATTENUATION Att (HP_EN) Att (AMP_EN) HP Disable Attenuation AMP Disable Attenuation Att_SD (HP_EN) Shutdown Active Att_SD(AMP_EN) Shutdown Active RL = 10kΩ on the Headphone Mode, VO = 1.1Vrms, fin = 1kHz RL = 8Ω on the AMP Mode, VO = 1Vrms, fin = 1kHz dB HEADPHONE TO SPEAKER CROSSTALK AMP_EN = 0V, RL = 8Ω Crosstalk Channel Separation HP_EN = 5V, RL = 16Ω, fin = 1kHz, PO = 125mW SPEAKER TO HEADPHONE CROSSTALK HP_EN = 5V, RL = 10kΩ Crosstalk Channel Separation AMP_EN = 0V, RL = 4Ω, fin = 1kHz, PO = 1.5W AMPLIFIER START-UP TIME Tstart-up Start-Up Time Gain Setting Table _AMP Mode (VDD=5V) Input Voltage (VSET) Hysteresis (mV) Recommended Voltage (V) 2.00 SD 0.00 2.12 47 2.08 2.15 2.24 36 2.20 2.28 2.35 41 2.31 -1 2.39 2.47 41 2.43 1 2.51 2.58 35 2.54 3 2.62 2.70 41 2.66 4 2.74 2.81 48 2.78 5 2.86 2.92 43 2.89 6 2.97 3.04 47 3.01 7 3.09 3.15 45 3.12 8 3.21 3.27 54 3.24 Gain (dB) Low (V) High (V) -70 0 -7 2.04 -5 -3 9 3.33 3.39 59 3.36 10 3.45 3.51 64 3.48 11 3.56 3.62 53 3.59 12 3.68 3.73 59 3.70 13 3.80 3.85 66 3.82 Copyright ANPEC Electronics Corp. Rev. A.4 - Aug., 2009 5 www.anpec.com.tw APA2051 Gain Setting Table _AMP Mode (Cont.) Input Voltage (VSET) Gain (dB) (VDD=5V) Hysteresis (mV) Recommended Voltage (V) 3.96 69 3.94 4.07 64 4.05 Low (V) High (V) 14 3.92 15 4.02 16 4.15 4.17 76 4.16 10.5 4.26 5.00 94 5.00 Recommend Resistance’s Value for Gain Setting Gain (dB) R1 (1%) R# (1%) -70 10k 0 -7 18k 13k -5 20k 16k -3 18k 16k -1 16k 15k 1 15k 16k 3 13k 15k 4 24k 30k 5 13k 18k 6 13k 20k 7 13k 22k 8 16k 30k 9 13k 27k 10 13k 30k 11 15k 39k 12 13k 39k 13 13k 43k 14 13k 50k 15 15k 68k 16 13k 68k 10.5 10k >90k Copyright ANPEC Electronics Corp. Rev. A.4 - Aug., 2009 6 www.anpec.com.tw APA2051 Typical Operating Characteristics THD+N vs. Output Power THD+N vs. Output Power 10 VDD =5V fin=1kHz Cin=2.2µF BW<80kHz AMP mode VDD =5V RL=4Ω Cin=2.2µF BW<80kHz AMP mode RL=8Ω 1 THD+N (%) THD+N (%) 10 RL=4Ω 1 fin=20kHz fin=20Hz 0.1 fin=1kHz 0.05 0 0.5 1 1.5 2 2.5 0.1 3 0.01 0.1 Output Power (W) THD+N vs. Frequency 2 5 Crosstalk vs. Frequency +0 VDD =5V RL=4Ω Cin=2.2µF PO=1.5W BW<80kHz AMP mode VDD =5V RL=4Ω Cin=2.2µF PO=1.5W AMP mode -10 -20 Crosstalk (dB) THD+N (%) 10 1 Output Power (W) 1 -30 -40 -50 Right to Left -60 -70 Left to Right -80 Right Channel -90 Left Channel 0.1 20 100 1k -100 10k 20k 20 100 Frequency (Hz) 1k 10k 20k Frequency (Hz) Output Noise Voltage vs. Frequency Frequency Response 100µ +11 +30 +25 +10 10µ 20 100 +9 +8 Phase +20 +15 +10 +5 VDD =5V RL=4Ω Cin=2.2µF A-weighting AMP mode 1µ VDD =5V Cin =2.2µF RL=4Ω PO=0.2W AMP mode Phase (deg) Gain (dB) Output Noise Voltage (Vrms) Gain +7 +0 1k +6 10 10k 20k 1k 10k -5 100k 200k Frequency (Hz) Frequency (Hz) Copyright ANPEC Electronics Corp. Rev. A.4 - Aug., 2009 100 7 www.anpec.com.tw APA2051 Typical Operating Characteristics (Cont.) THD+N vs. Output Power THD+N vs. Frequency 10 VDD =5V RL=8Ω Cin=2.2µF BW<80kHz AMP mode THD+N (%) THD+N (%) 10 1 fin=20kHz 0.1 fin=20Hz VDD =5V RL=8Ω Cin=2.2µF PO=0.92W BW<80kHz AMP mode 1 Left Channel 0.1 fin=1kHz Right Channel 0.05 0.05 0.01 0.1 1 20 5 100 Output Power (W) Crosstalk vs. Frequency Output Noise Voltage vs. Frequency 100µ +0 -20 VDD =5V RL=8 Ω Cin=2.2µF PO=0.92W AMP mode Output Noise Voltage (Vrms) -10 Crosstalk (dB) -30 -40 -50 -60 -70 Left to Right -80 Right to Left 10µ VDD =5V RL=8Ω Cin=2.2µF A-weighting AMP mode -90 -100 20 1µ 1k 100 10k 20 20k Frequency (Hz) Frequency Response Crosstalk vs. Frequency +11 +0 +30 Gain -10 +25 -20 +10 +15 +10 +8 -30 Crosstalk (dB) +9 +20 Phase (deg) VDD =5V Cin =2.2µF RL=8Ω PO=0.13W AMP mode +5 -40 VDD =5V RL=4Ohm (AMP) RL=10kΩ(HP) Cin=2.2µF (AMP) PO=1.5W(AMP) AMP (active) mode HP Mode -50 -60 -70 Right(AMP) to Right(HP) Left(AMP) to Left(HP) Left(AMP) to Right(HP) -80 -90 Phase +7 -100 +0 -110 +6 10 100 1k 10k 20k 1k 100 Frequency (Hz) Gain (dB) 10k 20k 1k Frequency (Hz) 10k -5 100k 200k -120 20 100 10k 20k 1k Frequency (Hz) Frequency (Hz) Copyright ANPEC Electronics Corp. Rev. A.4 - Aug., 2009 Right(AMP) to Left(HP) 8 www.anpec.com.tw APA2051 Typical Operating Characteristics (Cont.) AMP Attenuation vs. Frequency AMP Attenuation vs. Frequency +0 +0 VDD =5V RL=4Ω Cin=2.2µF VO=2Vrms(f in=1kHz, AMP enable) AMP mode (disable) AMP Attenuation (dB) -20 -30 VDD =5V RL=8Ω Cin=2.2µF VO=2Vrms(f in=1kHz,AMP enable) AMP mode (disable) -10 -20 AMP Attenuation (dB) -10 -40 -50 -60 -70 -80 -90 -100 -30 -40 -50 -60 -70 -80 -90 -100 -110 -110 -120 20 1k 100 -120 10k 20k 20 Frequency (Hz) Shutdown Attenuation vs. Frequency -20 -30 -40 Shutdown Attenuation vs. Frequency +0 VDD =5V RL=4Ω Cin=2.2µF VO=1Vrms(fin=1kHz) Shutdown active AMP mode -50 -60 -70 -80 -90 -100 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -110 -120 20 VDD =5V RL=8Ω Cin=2.2µF VO=1Vrms(fin=1kHz) Shutdown active AMP mode -10 Shutdown Attenuation (dB) Shutdown Attenuation (dB) +0 -10 -120 100 1k 10k 20k 20 100 Input Voltage vs. Output Voltage 3.5 Output Voltage (Vrms) Output Voltage (Vrms) VDD =5V RL=4Ω Cin=2.2µF fin=1kHz AMP mode 2 1.5 1 0.5 0 10k 20k Input Voltage vs. Output Voltage 4 3.5 2.5 1k Frequency (Hz) Frequency (Hz) 3 10k 20k 1k 100 Frequency (Hz) 3 VDD =5V RL=8Ω Cin=2.2µF fin=1kHz AMP mode 2.5 2 1.5 1 0.5 0.3 0.6 0.9 1.2 0 1.5 Copyright ANPEC Electronics Corp. Rev. A.4 - Aug., 2009 0.3 0.6 0.9 1.2 1.5 Input Voltage (Vrms) Input Voltage (Vrms) 9 www.anpec.com.tw APA2051 Typical Operating Characteristics (Cont.) THD+N vs. Output Power THD+N vs. Output Voltage 10 T 10 VDD =5V HVDD=3.3V RL=16Ω Rin=39kΩ Cin=3.3µF BW<80kHz HP mode RL=300Ω THD+N (%) THD+N (%) VDD =5V HVDD=3.3V fin=1kHz Cin=3.3µF 1 BW<80kHz HP mode RL=32Ω 0.1 RL=16Ω 1 fin=20kHz 0.1 0.01 fin=20Hz RL=10kΩ 0.001 0 0.5 1 1.5 2 2.5 fin=1kHz 0.01 1m 3 10m Output Voltage (Volt) THD+N vs. Output Power 10 1 THD+N (%) THD+N (%) THD+N vs. Frequency 10 VDD=5V HVDD=3.3V RL=16Ω Rin=39kΩ Cin=3.3µF fin=1kHz BW<80kHz HP mode 1 Stereo, in phase 0.1 300m 100m Output Power (W) VDD =5V HVDD=3.3V RL=16Ω Rin=39kΩ Cin=3.3µF PO=125mW HP mode BW<80kHz 0.1 Stereo, 180O out of phase BW<22kHz 0.01 Mono 0.01 0 50m 100m 150m 200m 0.005 20 250m 100 Output Power (W) Crosstalk vs. Frequency +0 10k 20k Output Noise Voltage vs. Frequency 100µ VDD=5V Output Noise Voltage (Vrms) -10 HVDD=3.3V RL=16Ω -20 Rin=39kΩ Cin=3.3µF Crosstalk (dB) 1k Frequency (Hz) -30 PO=125mW HP mode -40 -50 -60 -70 Right to Left -80 Right channel Left channel 10µ Left to Right -90 -100 20 100 1k 1µ 20 10k 20k 100 10k 20k 1k Frequency (Hz) Frequency (Hz) Copyright ANPEC Electronics Corp. Rev. A.4 - Aug., 2009 VDD =5V HVDD =3.3V RL=16Ω Rin=39kΩ Cin=3.3µF A-weighting HP mode 10 www.anpec.com.tw APA2051 Typical Operating Characteristics (Cont.) Frequency Response THD+N vs. Output Power +0.2 +190 +180 VDD=5V HVDD=3.3V RL=16Ω Rin=39kΩ Cin=3.3µF PO=28mW HP mode -0.1 -0.2 10 THD+N (%) Phase -0 VDD=5V HVDD=3.3V RL=32Ω Rin=39kΩ Cin=3.3µF BW<80kHz HP mode +185 Gain Phase (deg) Gain(dB) +0.1 10 1 fin=20kHz 0.1 +175 fin=20Hz 1k 100 fin=1kHz +170 100k 200k 10k 0.01 1m 10 VDD=5V HVDD=3.3V RL=32Ω Rin=39kΩ Cin=3.3µF fin=1kHz BW<80kHz HP mode VDD=5V HVDD=3.3V RL=32Ω Rin=39kΩ Cin=3.3µF PO=88mW HP mode 1 THD+N (%) 1 THD+N (%) THD+N vs. Frequency THD+N vs. Output Power 10 Stereo, 180o out of phase 0.1 100m 200m 10m Output Power (W) Frequency (Hz) Stereo, in phase 0.1 BW<80kHz BW<22kHz 0.01 Mono 0.01 0 50m 100m 0.001 20 200m 150m 100 Output Power (W) Crosstalk vs. Frequency Output Noise Voltage vs. Frequency -30 VDD=5V HVDD=3.3V RL=32Ω Rin=39kΩ Cin=3.3µF PO=88mW HP mode Output Noise Voltage (V) Crosstalk (dB) -20 -40 -50 -60 -70 Right to Left Right channel Left channel 10µ -80 Left to Right -90 -100 20 10k 20k 100µ +0 -10 1k Frequency (Hz) 100 1k 1µ 20 10k 20k 100 10k 20k 1k Frequency (Hz) Frequency (Hz) Copyright ANPEC Electronics Corp. Rev. A.4 - Aug., 2009 VDD =5V HVDD=3.3V RL=32Ω Rin=39kΩ Cin=3.3µF A-weighting HP mode 11 www.anpec.com.tw APA2051 Typical Operating Characteristics (Cont.) Frequency Response THD+N vs. Output Voltage +190 +0.2 +0.1 +185 +180 VDD =5V HVDD=3.3V RL=32Ω Rin=39kΩ Cin=3.3µF PO=13mW HP mode -0.1 +175 100 0.1 fin=20kHz fin=20Hz 0.01 fin=1kHz -0.2 10 THD+N (%) Phase -0 VDD=5V HVDD=3.3V RL=300Ω Rin=39kΩ Cin=3.3µF BW<80kHz HP mode 1 Phase (deg) Gain (dB) 10 Gain 10k 1k +170 100k 200k 0.001 0 0.5 THD+N vs. Frequency 2.5 3 Crosstalk vs. Frequency +0 VDD=5V HVDD=3.3V RL=300Ω Rin=39kΩ Cin=3.3µF VO=1.7Vrms BW<80kHz HP mode -10 -20 -30 -40 Crosstalk (dB) THD+N (%) 2 Output Voltage (Vrms) 10 1 1.5 1 Frequency (Hz) 0.1 -50 -60 -70 -80 Right to Left -90 Right Channel 0.01 VDD=5V HVDD=3.3V RL=300Ω Rin=39kΩ Cin=3.3µF VO=1.7Vrms BW<80kHz HP mode -100 Left Channel -110 -120 0.001 20 100 1k 10k 20k Left to Right 20 100 Frequency (Hz) Frequency Response Output Noise Voltage vs. Frequency 100µ +195 +0.4 Left channel 10µ 1µ 20 VDD =5V HVDD=3.3V RL=300Ω Rin=39kΩ Cin=3.3µF A-weighting HP mode 100 +190 VDD =5V HVDD=3.3V RL=300Ω Rin=39kΩ Cin=3.3µF VO=240mVrms HP mode +0 +185 Phase (deg) Gain +0.2 Right channel Gain (dB) Output Noise Voltage (Vrms) 10k 20k 1k Frequency (Hz) Phase -0.2 1k 10k -0.4 20k 10 100 1k 10k +175 100k 200k Frequency (Hz) Frequency (Hz) Copyright ANPEC Electronics Corp. Rev. A.4 - Aug., 2009 +180 12 www.anpec.com.tw APA2051 Typical Operating Characteristics (Cont.) THD+N vs. Output Voltage THD+N (%) 1 THD+N vs. Frequency 10 VDD =5V HVDD=3.3V RL=10kΩ Rin=39kΩ Cin=3.3µF BW<80kHz HP mode VDD =5V HVDD=3.3V RL=10kΩ Rin=39kΩ Cin=3.3µF VO=1.7Vrms BW<80kHz HP mode 1 THD+N (%) 10 0.1 fin=20Hz fin=20kHz 0.01 0.1 Right channel 0.01 Left channel fin=1kHz 0.001 0 0.5 1.5 1 2 2.5 0.001 20 3 Output Voltage (Volt) -40 -50 Output Noise Voltage (Vrms) VDD=5V HVDD=3.3V RL=10kΩ Rin=39kΩ Cin=3.3µF VO=1.7Vrms BW<80kHz HP mode -30 Crosstalk (dB) Output Noise Voltage vs. Frequency 100µ -20 -60 -70 -80 Left to Right -90 -100 Right to Left -110 Right channel Left channel 10µ VDD=5V HVDD=3.3V RL=10kΩ Rin=39kΩ Cin=3.3µF A-weighting HP mode -120 1µ 20 100 1k 10k 20k 20 100 Frequency (Hz) Crosstalk vs. Frequency +195 +0.4 +0 -10 Gain +0 -20 +190 Crosstalk (dB) VDD=5V HVDD=3.3V RL=10kΩ Rin=39kΩ Cin=3.3µF VO=240mVrms HP mode Phase (deg) +0.2 +185 Phase -0.2 10k 20k 1k Frequency (Hz) Frequency Response Gain (dB) 10k 20k 1k Frequency (Hz) Crosstalk vs. Frequency +0 -10 -130 100 -30 -40 -50 -60 -70 +180 VDD =5V HVDD=3.3V RL=16Ω (HP) RL=8Ω(AMP) Rin=39kΩ(HP) Cin=3.3µF (HP) PO=125mW(HP) AMP (active) mode HP Mode Left (HP) to Left (AMP) Right (HP) to Left (AMP) -80 -90 -0.4 10 100 1k 10k +175 100k 200k -100 20 100 Right (HP) to Right (AMP) 10k 20k 1k Frequency (Hz) Frequency (Hz) Copyright ANPEC Electronics Corp. Rev. A.4 - Aug., 2009 Left (HP) to Right (AMP) 13 www.anpec.com.tw APA2051 Typical Operating Characteristics (Cont.) HP Attenuation vs. Frequency +0 -20 -30 -20 -40 -50 -60 -70 -80 -90 -40 -50 -60 -70 Right channel Right channel -100 20 1k 100 10k 20k Frequency (Hz) 20 -30 -40 -50 -20 -60 -70 -80 -90 -100 Left channel -110 -120 -130 -30 -40 -50 -60 -70 -80 -100 -110 -130 100 Left channel -90 Right channel -120 Right channel -140 20 10k 20k 1k 20 20k Input Voltage vs. Output Voltage 3 VDD =5V HVDD=3.3V RL=16Ω Rin=39kΩ Cin=3µF fin=1kHz HP mode Output Voltage (Vrms) Mono Stereo, in phase 1.5 1 0.5 0 10k Frequency (Hz) Input Voltage vs. Output Voltage 2 1k 100 Frequency (Hz) 2.5 20k VDD =5V HVDD=3.3V RL=10kΩ Cin=3.3µF VO=1Vrms(f in=1kHz) Shutdown active HP mode -10 Shutdown attenuation (dB) -20 10k Shutdown Attenuation vs. Frequency +0 VDD =5V HVDD=3.3V RL=32Ω Cin=3.3µF VO=1Vrms(fin=1kHz) Shutdown active HP mode -10 1k 100 Frequency (Hz) Shutdown Attenuation vs. Frequency +0 Output Voltage (Vrms) Left channel -90 -120 Shutdown attenuation (dB) -30 -80 Left channel -100 -110 VDD =5V HVDD=3.3V RL=10kΩ Cin=3.3µF VO=1Vrms(f in=1kHz HP enable) HP mode (disable) -10 HP attenuation (dB) -10 HP attenuation (dB) HP Attenuation vs. Frequency +0 VDD =5V HVDD=3.3V RL=32Ω Cin=3.3µF VO=1Vrms(fin=1kHz HP enable) HP mode (disable) VDD =5V HVDD=3.3V RL=32Ω Rin=39kΩ Cin=3µF fin=1kHz HP mode 2.5 2 Mono Stereo, in phase 1.5 1 0.5 0 0.5 1 1.5 2 0 2.5 0.5 1 1.5 2 2.5 3 Input Voltage (Vrms) Input Voltage (Vrms) Copyright ANPEC Electronics Corp. Rev. A.4 - Aug., 2009 0 14 www.anpec.com.tw APA2051 Typical Operating Characteristics (Cont.) Input Voltage vs. Output Voltage Output Voltage (Vrms) 2.5 2 Input Voltage vs. Output Voltage 3 VDD =5V HVDD=3.3V RL=300Ω Rin=39kΩ Cin=3µF fin=1kHz HP mode 2.5 Stereo, in phase 1.5 1 0.5 0 VDD =5V HVDD=3.3V RL=10kΩ Rin=39kΩ Cin=3µF fin=1kHz HP mode Mono Output Voltage (Vrms) 3 2 Mono & Stereo, in phase 1.5 1 0.5 0 0.5 1 1.5 2 2.5 0 3 0 0.5 1 Input Voltage (Vrms) PSRR vs. Frequency +0 VDD=5V -10 RL=4Ω -10 Cin=2.2µF -20 Vrr=200mVrms -20 -30 -30 -40 -40 PSRR (dB) PSRR (dB) AMP mode -50 -60 Right channel -50 -60 Right channel 100 1k Left channel -90 Vrr: Ripple Voltage on VDD -100 20 -100 10k 20k Vrr: Ripple Voltage on VDD 20 100 Frequency (Hz) PSRR vs. Frequency PSRR vs. Frequency +0 VDD =5V HVDD=3.3V RL=32Ω Rin=39kΩ Cin=3.3µF Vrr=200mVrms HP mode -10 -20 -30 PSRR (dB) PSRR (dB) -30 -40 -50 -60 VDD =5V HVDD=3.3V RL=10kΩ Rin=39kΩ Cin=3.3µF Vrr=200mVrms HP mode -40 -50 -60 -70 -70 Left channel -80 -90 -100 10k 20k 1k Frequency (Hz) -20 3 VDD =5V RL=8Ω Cin=2.2µF Vrr=200mVrms AMP mode -80 Left channel -90 -10 2.5 -70 -80 +0 2 PSRR vs. Frequency +0 -70 1.5 Input Voltage (Vrms) Right channel 20 100 Left channel -80 -90 Right channel Vrr: Ripple Voltage on HVDD 1k -100 10k 20k Frequency (Hz) Copyright ANPEC Electronics Corp. Rev. A.4 - Aug., 2009 20 100 Vrr: Ripple Voltage on HVDD 1k 10k 20k Frequency (Hz) 15 www.anpec.com.tw APA2051 Typical Operating Characteristics (Cont.) Supply Current vs. Supply Voltage Shutdown Current vs. Supply Voltage 20 50 16 *HP Mode disable HVDD=3.3V IHVDD=0.15mA 14 12 10 8 **AMP Mode disable VDD=5V IVDD=12mA 6 Amp mode HP mode No Load AMP Mode No Load Shutdown Current (µA) Supply Current (mA) 18 4 40 ISD(VDD) 30 20 10 HP Mode 2 3.0 3.5 ISD(HVDD) 4.5 4.0 5.0 Supply Voltage (Volt) 0 5.5 3.0 4.0 4.5 5.0 5.5 Supply Voltage (Volt) Power Dissipation vs. Output Power Power Dissipation vs. Output Power 400 1.4 350 1.2 RL=16Ω RL=4Ω Power Dissipation (mW) Power Dissipation (W) 3.5 1.0 0.8 0.6 RL=8Ω 0.4 VDD =5V THD+N <1% AMP mode 0.2 0.0 0.0 300 250 RL=32Ω 200 150 100 VDD =5V HVDD=3.3V THD+N <1% HP mode 50 0 0.5 1.0 0 2.0 1.5 50 Output Power (W) 150 100 200 Output Power (mW) Output Power vs. Load Resistance & Output Power vs. Load Resistance 250 Mono, THD+N=10% 200 VDD =5V HVDD=3.3V fin=1kHz BW<80kHZ HP mode 150 100 Mono, THD+N=1% 250 150 100 50 0 0 100 CF=CCO=1µF THD+N=1%; Stereo, in phase CF :Charge pump flying capacitor CCO:Charge pump output capacitor 10 1000 Load Resistance (Ω) Copyright ANPEC Electronics Corp. Rev. A.4 - Aug., 2009 CF=CCO=1µF THD+N=1%; Mono 200 50 10 VDD =5V fin=1kHz BW<80kHZ HP mode CF=CCO=2.2µF THD+D=1%; Mono & Stereo, in phase 300 Output Power (mW) Output Power (mW) Charge Pump Capacitance 350 300 20 30 40 50 60 70 80 90 100 Load Resistance (Ω) 16 www.anpec.com.tw APA2051 Typical Operating Characteristics (Cont.) Input Resistance vs. Amplifier's Gain Input Resistance (kΩ)_AMP Mode 37.5 VDD =5V fin=1kHz BW<80kHZ No Load AMP mode 35.0 32.5 30.0 27.5 25.0 22.5 20.0 17.5 15.0 -8 -6 -4 -2 0 2 4 6 8 10 12 14 16 Gain (dB)_AMP Mode Copyright ANPEC Electronics Corp. Rev. A.4 - Aug., 2009 17 www.anpec.com.tw APA2051 Operating Waveforms Output transient at Shutdown Release Output Transient at Turn On VDD 5V/div HP_Out 5V/div SD 10mV/div HP_Out 10mV/div AMP_Out AMP_Out 20mV/div ((Out+)-(Out-)) 20mV/div ((Out+)-(Out-)) 20ms/div 20ms/div Output Transient at Turn Off Output transient at Shutdown Active VDD 5V/div HP_Out 5V/div SD HP_Out 10mV/div 10mV/div AMP_Out AMP_Out 20mV/div ((Out+)-(Out-)) 200ms/div Copyright ANPEC Electronics Corp. Rev. A.4 - Aug., 2009 20mV/div ((Out+)-(Out-)) 20ms/div 18 www.anpec.com.tw APA2051 Pin Description PIN FUNCTION NO. NAME 1 INL_A Left channel input terminal for speaker amplifier 2 INL_H Left channel input terminal for headphone driver 3,14 N.C. No Connection 4,20 PGND Power ground 5 LOUT+ Left channel positive output for speaker 6 LOUT- Left channel negative output for speaker 7,17 PVDD Power amplifier power supply 8 CVDD Charge pump power supply 9 CP+ 10 CGND 11 CP- 12 HVSS Charge pump flying capacitor positive connection Charge pump ground Charge pump flying capacitor negative connection Charge pump output and Headphone amplifier negative power supply pin 13 HP_R Right channel output for headphone 15 HV DD Headphone amplifier positive power supply 16 HP_L Left channel output for headphone 18 ROUT- Right channel negative output for speaker 19 ROUT+ Right channel positive output for speaker 21 HP_EN Headphone driver enable pin, pull high to enable headphone mode 22 BIAS Bias voltage generator 23 SET It has 19 steps gain setting control from 2.0~4.2V; pull high to 5V is 10.5dB fix gain and pull low to 0V, the APA2051 enter shutdown mode. ISD = 80µA 24 AMP_EN 25 VDD Power supply for control section 26 GND Ground Speaker driver enable pin, pull low to enable speaker mode 27 INR_A Right channel input terminal for speaker amplifier 28 INR_H Right channel input terminal for headphone driver Copyright ANPEC Electronics Corp. Rev. A.4 - Aug., 2009 19 www.anpec.com.tw APA2051 Block Diagram ROUT+ INR_A ROUTInternal gain setting LOUT+ INL_A LOUTSET SET BIAS AMP_EN SPK EN Rf(HP_R) HP_EN HP EN *40kΩ INR_H HP_R Rf(HP_L) *40kΩ INL_H HP_L CVDD HVDD CP+ CP- Charge Pump Power Management PVDD VDD CGND , * The internal Rf s value has 10% variation by process Copyright ANPEC Electronics Corp. Rev. A.4 - Aug., 2009 VSS 20 PGND GND www.anpec.com.tw APA2051 Typical Application Circuit ROUT+ R_CH Ci(AMP_R) R_ch INR_A 4Ω for AMP 2.2µF Ci(AMP_L) L_ch ROUT- Internal gain setting LOUT+ L_CH INL_A for AMP 4 Ω 2.2µF VDD(5V) LOUT- 10kΩ R1 SET 10nF SET 2.2µF BIAS Shutdown AMP_EN R# SPK EN CB Rf(HP_R) HP_EN SET R_ch 3.3µF for HP Ci(HP_R) HP_R Rf(HP_L) Sleeve Ri(HP_R) Ri(HP_L) L_ch Ring INR_H 39kΩ Ci(HP_L) Pull-high HP_EN to enable headohone driver HP EN *40kΩ 510kΩ 0.47nF Recommended for de-pop Tip *40kΩ INL_H Headphone Jack HP_L for HP 3.3µF 39kΩ VDD(5V) CVDD VDD(5V) CCPB CCPF CP+ 1µF 1µF CP- Power Management Charge Pump PVDD VDD CGND CS(VDD) VSS # R : For the gain setting of speaker driver that , you need, refer to the Gain Setting Table s recommended voltage, and setting this voltage , # # at SET pin s voltage =5R /(R +10k). R1<=25kΩ. Copyright ANPEC Electronics Corp. Rev. A.4 - Aug., 2009 HVDD(3.3V) HVDD CCPO PGND GND CS(PVDD) 0.1µF 10µF CS(HVDD) 0.1µF 0.1µF VSS 1µF 21 www.anpec.com.tw APA2051 Application Information Headphone Mode Operation Amplifier Mode Operation The APA2051 has two pairs of operational amplifiers internally, which allows different amplifier configurations. HVDD VOUT - OUT+ + Pre-amplifier Output signal HVDD/2 GND OP1 Conventional Headphone amplifier Vbias HVDD - VOUT DIFF_AMP_CONFIG + OUT- GND OP2 Figure 1. APA2051 Internal Configuration (each channel) The OP1 and OP2 are all differential drive configurations. The differential drive configurations doubling the voltage VSS Cap-free Headphone amplifier Figure 2. Cap-free Operation swing on the load. Compare with the single-ending configuration, the differential gain for each channel is 2X The APA2051’s headphone amplifiers uses a charge (Gain of SE mode). pump to invert the positive power supply (CVDD) to negative power supply (CVSS), see Figure 2. The headphone By driving the load differentially through outputs OUT+ and OUT-, an amplifier configuration commonly referred amplifiers operate at this bipolar power supply (HVDD & VSS), and the outputs reference refers to the ground. This to all differential mode is established. All differential mode operation is different from the classical single-ended SE feature eliminates the output capacitor which is using in conventional single-ended headphone amplifier. The amplifier configuration where one side of its load is connected to the ground. headphone amplifier internal supply voltage comes from HVDD and VSS. For good AC performance, the HVDD con- A differential amplifier design has a few distinct advantages over the SE configuration, as it provides differential nected to 3.3V is recommended. It can avoid the output over voltage for line out application. drive to the load, thus it is doubling the output swing for a specified supply voltage. The output power can be 4 times Charge Pump Flying Capacitor greater than the SE amplifier working under the same condition. A differential configuration, similar as the one The flying capacitor (CCPF) affects the load transient of the used in APA2051, also creates a second advantage over SE amplifiers. Since the differential outputs, ROUT+, charge pump. If the capacitor’s value is too small, and then that will degrade the charge pump’s current driver ROUT-, LOUT+, and LOUT- are biased at half-supply, it’s not necessary for DC voltage to be across the load. This capability and the performance of headphone amplifier. eliminates the need for an output coupling capacitor which is required in a single supply, SE configuration. load transient of charge pump. It is recommended to use the low ESR ceramic capacitors (X7R type is Increasing the flying capacitor’s value will improve the recommended) above 1µF. Copyright ANPEC Electronics Corp. Rev. A.4 - Aug., 2009 22 www.anpec.com.tw APA2051 Application Information (Cont.) drive. Both amplifier and headphone “ON” mode: Pull low Charge Pump Output Capacitor • The output capacitor (C CPO)’s value affects the power ripple directly at CVSS(VSS). Increasing the value of output the AMP_EN and pull high the HP_EN control pins, and then turn on both speaker drivers and head- capacitor reduces the power ripple. The ESR of output capacitor affects the load transient of CVSS(VSS). Lower phone drivers Both amplifier and headphone “OFF” mode: Pull • ESR and greater than 1µf ceramic capacitor (X7R type is recommended) is a recommendation. high the AMP_EN and pull low the HP_EN control pins, and then turn off both speaker drivers and Charge Pump Bypass Capacitor headphone drivers The bypass capacitor (CCPB) relates with the charge pump If the AMP_EN and HP_EN are connected together, this switching transient. The capacitor’s value is the same as flying capacitor (1µF). Place it close to the CVDD and PGND. pin will be connected to headphone jack’s control pin (Figure 3), the APA2051 is switchable between “Amplifier Headphone Detection Input mode (Headphone mute), or Headphone mode (Amplifier mute). HP_R Control pin Ring Gain Setting 1KΩ The gain for speaker drivers can be adjustable by applyHPD_Switch HP_EN ing DC voltage to the SET pin. The APA2051 control consists of 19 step gain settings from 2.0V to 4.2V, and the HP_L gain is from -7dB to 16dB. Each gain step corresponds to a specific input voltage range, as shown in the “Gain Set- 1KΩ Sleeve Tip ting Table”. To minimize the effect of noise on the gain setting control, which can affect the selected gain level, Headphone Detection Headphone Jack with swich Figure 3. HPD Configurations The HP_EN will detect the voltage. If the voltage is less hysteresis and clock delay are implemented. For the highest accuracy, the voltage shown in the “recommended than 0.8V, the headphone amplifiers will be disabled; if the voltage is greater than 2V, the headphone amplifier voltage” column of the table is used to select a desired gain. This recommended voltage is exactly halfway be- will be enabled. In Figure 3, phone-jack with the control pin is used and tween the two nearest transitions. The amount of hysteresis corresponds to half of the step width, as shown in connected to HP_EN input from control pin. When a headphone plug is inserted, the HP_EN will pull high inter- Figure 4. Apply 0V to SET pin will place the APA2051 into shutdown mode, and when SD =5V, it allows the speaker nally which enables headphone amplifiers; without headphone plug, the HP_EN is pulled to the GND. driver at a fixed gain (AV=10.5dB). 20 10 Operation Mode Forward Backward 0 Gain (dB) The APA2051 amplifier has two pairs of independent amplifier. One for stereo speaker is BTL structure, and the other for headphone is cap-less structure. Each pair has independent input pin; INR_A and INA_L are for stereo speaker drivers, and INR_H and INL_H are for stereo -10 -20 -30 -40 headphone drivers. -50 • Amplifier mode operation: Pull low the AMP_EN control pin can enable the stereo speaker driver. -60 • Headphone mode operation: Pull high the HP_EN control pin can enable the cap-less headphone Copyright ANPEC Electronics Corp. Rev. A.4 - Aug., 2009 -70 0.0 1.0 2.0 3.0 4.0 5.0 DC Volume (V) Figure 4. APA2051 Gain setting vs. SET pin Voltage 23 www.anpec.com.tw APA2051 Application Information (Cont.) For headphone driver, the internal feedback resistor is important to confirm the capacitor polarity in the application. 40kΩ (Rf(HP) external, 10% variation by process), therefore, the headphone driver’s gain is set by the input resistor Note: The headphone dirver’s input is ground reference, so please check the Ci(HP)’s polarized at design. (Ri(HP) external), the Table 1 lists the reference gain settings with external resistor for headphone driver (HP Effective Bias Capacitor, CB Gain Setting (Cont.) As with any power amplifier, proper supply bypassing is critical for low noise performance and high power supply Mode). HP Mode Gain Setting Table for Reference Ri(HP),external *Rf(HP),internal HP OUT (V/V) HP Gain(dB) (kΩ) (kΩ) 62 40 0.65 -3.8 50 40 0.80 -1.9 39 40 1.03 0.2 30 40 1.33 2.5 24 40 1.67 4.4 20 40 2.00 6.0 *The internal Rf's value has 10% variation by process. rejection. The capacitor location on both the bypass and power supply pins should be as close to the device as possible. The effect of a larger bypass capacitor is improved PSRR due to increased 1.8V bias voltage stability. Typical applications employ a 5V regulator with 2.2µF and a 0.1µF bypass capacitor, which aids in supply filtering. This does not eliminate the need for bypassing the supply nodes of the APA2051. The selection of bypass capacitors, espe- Table 1. Gain Setting Table for Reference Input Capacitor, Ci cially CB, is thus dependent upon desired PSRR requirements and click-and-pop performance. In the typical application, an input capacitor, Ci, is required to allow the amplifier to bias the input signal to the proper DC level for optimum operation. In this case, Ci and the Power Supply Decoupling, Cs The APA2051 is a high-performance CMOS audio ampli- minimum input impedance Ri from a high-pass filter with the corner frequency are determined by the following fier that requires adequate power supply decoupling to ensure the output total harmonic distortion (THD+N) is equation: F C (highpass) = 1 (2 πR i(MIN) ×C i ) as low as possible. Power supply decoupling also prevents the oscillations caused by long lead length between (1) The value of Ci must be considered carefully because it directly affects the low frequency performance of the the amplifier and the speaker. The optimum decoupling is achieved by using two different types of capacitor that circuit. Consider the example where Ri is 10kΩ and the specification calls for a flat bass response down to 10Hz. target on different types of noise on the power supply leads. For higher frequency transients, spikes, or digital The equation is reconfigured as below: 1 Ci = (2 πR iFc) hash on the line, a good low equivalent-series-resistance (ESR) ceramic capacitor, typically 0.1µF, is placed as (2) close as possible to the device VDD lead works best (the pin1 (V DD) and pin2 (GND)’s capacitor must short less When the input resistance variation is considered, the Ci is 1.6µF, so a value in the range of 2.2µF to 3.3µF would than 1cm). For filtering lower-frequency noise signals, a large aluminum electrolytic capacitor of 10µF or greater be chosen. A further consideration for this capacitor is the leakage path from the input source through the input net- is placed near the audio power amplifier is recommended. work (Ri+Rf, Ci) to the load. This leakage current creates a DC offset voltage at the input to the amplifier that re- Shutdown Function duces useful headroom, especially in high gain applications. For this reason, a low-leakage tantalum or In order to reduce power consumption while not in use, the APA2051 contains a shutdown pin to externally turn off the amplifier bias circuitry. This shutdown feature turns ceramic capacitor is the best choice. When polarized capacitors are used, the positive side of the capacitor the amplifier off when a logic low is placed on the SET pin. The trigger point between a logic high and logic low should face the amplifiers’input because the DC level of the amplifiers’input is held at VDD/2. Please note that it is Copyright ANPEC Electronics Corp. Rev. A.4 - Aug., 2009 24 www.anpec.com.tw APA2051 Application Information (Cont.) Shutdown Function (Cont.) level is typically 2.0V. It is the best to switch between the ground and the supply VDD to provide maximum device performance. By switching the SET pin to low, the amplifier enters a low-current consumption state, I DD<80µA. In normal Po (W) Efficiency (%) IDD(A) VPP(V) PD (W) 0.25 31.25 0.16 2.00 0.55 0.50 47.62 0.21 2.83 0.55 1.00 66.67 0.30 4.00 0.5 1.25 78.13 0.32 4.47 0.35 **High peak voltages cause the THD D+N to increase. to increase operating, the SET pin is pulled to high level to keep the IC out of the shutdown mode. The SET pin should be tied Table 2. Efficiency vs. Output Power in 5-V/8W Differential Amplifier Systems. to a definite voltage to avoid unwanted state changing. The wake-up time of shutdown is about 150ms, and the A final point to remember about linear amplifiers is how to manipulate the terms in the efficiency equation to the shutdown release’s pop is caused by the operational amplifier’s offset. utmost advantage when possible. Note that in equation, VDD is in the denominator. This indicates that as VDD goes Speaker Driver Amplifier Efficiency down, efficiency goes up. In other words, using the efficiency analysis to choose the correct supply voltage and An easy-to-use equation to calculate efficiency starts out speaker impedance for the application. as being equal to the ratio of power from the power supply to the power delivered to the load. The following equa- Power Dissipation tions are the basis for calculating amplifier efficiency. Efficiency = PO Psup Whether the power amplifier is operated in BTL or SE modes, power dissipation is a major concern. Teh equation 8 states the maximum power dissipation point for a SE mode operating at a given supply voltage and driving (3) Where: VOrms * VOrms (V * VP ) = P RL 2RL VP VOrms = 2 2VP Psup = VDD * IDD (AVG) = VDD * πRL PO = a specified load. (4) SE mode: (5) VDD 2 2π2RL (8) In BTL mode operation, the output voltage swing is doubled as in SE mode. Thus, the maximum power dis- (6) sipation point for a BTL mode operating at the same given conditions is 4 times as in SE mode. Efficiency of a Differential configuration: (V * V ) PO 2VP πRL = P P / VDD * = Psup 2RL πRL 4VDD PD,MAX = 2 BTL mode: PD,MAX = 4V2DD (7) 2π RL (9) Since the APA2051 is a dual channel power amplifier, the maximum internal power dissipation is 2 times that both Table 1 calculates efficiencies for four different output power levels. Note that the efficiency of the amplifier is of equations depending on the mode of operation. Even with this substantial increasing in power dissipation, the quite low for lower power levels and rises sharply as power to the load is increased resulting in nearly flat in- APA2051 does not require extra heatsink. The power dissipation from equation 9, assuming a 5V-power supply ternal power dissipation over the normal operating range. Note that the internal dissipation at full output power is and an 8Ω load, must not be greater than the power dissipation that results from the equation 9: less than in the half power range. Calculating the efficiency for a specific system is the key to proper power PD,MAX = supply design. For a stereo 1W audio system with 8W loads and a 5V supply, the maximum draw on the power TJ,MAX - TA θJA (10) supply is almost 3W. Copyright ANPEC Electronics Corp. Rev. A.4 - Aug., 2009 25 www.anpec.com.tw APA2051 Application Information (Cont.) Power Dissipation (Cont.) ThermalVia diameter 0.3mm X 9 For TQFN4x4-28 package with thermal pad, the thermal resistance (θJA) is equal to 45oC/W. 1.0mm Since the maximum junction temperature (TJ,MAX) of 0.25mm 2.2mm 0.45mm dissipation that the IC package is able to handle can be obtained from equation10. Once the power dissipation 3.2mm APA2051 is 150°C and the ambient temperature (TA) is defined by the power system design, the maximum power is greater than the maximum limit (PD,MAX), either the supply voltage (VDD) must be decreased, the load impedance (R L) must be increased or the ambient temperature should be reduced. 2.2mm Solder Mask to Prevent Short Circuit Thermal Pad Consideration The thermal pad must be connected to the ground. The Ground plane for ThermalPAD Figure 5. TQFN4X4-28 Land Pattern Recommendation package with thermal pad of the APA2051 requires special attention on the thermal design. If the thermal design Thermal Consideration issues are not properly addressed, the APA2051 4Ω will go into thermal shutdown when driving a 4Ω load. The Linear power amplifiers dissipate a significant amount of heat in the package under normal operating conditions. thermal pad on the bottom of the APA2051 should be soldered down to a copper pad on the circuit board. Heat In the Power Dissipation vs. Output Power graph, the APA2051 is operating at a 5V supply and a 4Ω speaker can be conducted away from the thermal pad through the copper plane to ambient. If the copper plane is not on the that 2W output power peaks are available. The vertical axis gives the information of power dissipation (PD) in the top surface of the circuit board, 8 to 10 vias of 15 mil or smaller in diameter should be used to thermally couple IC with respect to each output driving power (PO) on the horizontal axis. the thermal pad to the bottom plane. For good thermal conduction, the vias must be plated through and solder This is valuable information when attempting to estimate the heat dissipation of the IC requirements for the amplifier system. filled. The copper plane used to conduct heat away from the thermal pad should be as large as practical. Using the power dissipation curves for a 5V/4Ω system, If the ambient temperature is higher than 25°C, a larger the internal dissipation in the APA2051 and maximum ambient temperatures is shown in Table 3. copper plane or forced-air cooling will be required to keep the APA2051 junction temperature below the thermal shutdown temperature (150°C). In higher ambient temperature, higher airflow rate and/or larger copper area will be required to keep the IC out of the thermal shutdown. See Demo Board Circuit Layout as an example for PCB layout. Peak output power (W) Average output power (W) Power Max. TA (°C) dissipation (W/channel) With thermal pad 2 1.95 1.25 37 2 1.17 1.25 37 2 0.74 1.19 43 2 0.43 1.05 55 2 0.19 0.8 78 Table 3. APA2051 Power information, 5V/4Ω, Stereo, Differential mode Copyright ANPEC Electronics Corp. Rev. A.4 - Aug., 2009 26 www.anpec.com.tw APA2051 Application Information (Cont.) Thermal Consideration (Cont.) Package θJA TQFN4x4 -28 45°C/W Table 4. Thermal resistance Table This parameter is measured with the recommended copper heat sink pattern on a 2-layer PCB, 23cm 2 in 5.7mmx4mm in PCB, 2oz. Copper, 100mm2 coverage. Airflow 0 CFM the maximum ambient temperature depends on the heat sink ability of the PCB system. To calculate maximum ambient temperatures, first consideration is that the numbers from the dissipation graphs are per channel values, so the dissipation of the IC heat needs to be doubled for two-channel operation. Given θJA, the maximum allowable junction temperature (TJ,Max), and the total intemal dissipation (PD), the maximum ambient temperature can be calculated with the following equation. The maximum recommended junction temperature for the APA2051 is 150°C. The internal dissipation figures are taken from the Power Dissipation vs. Output Power graph. TA,Max = TJ,Max - θJAPD (11) 150 - 45(0.8*2) = 78°C (with thermal pad) NOTE: Internal dissipation of 0.8W is estimated for a 2W system with 15-dB headroom per channel. Table 3 shows that for some applications, no airflow is required to keep junction temperatures in the specified range. The APA2051 is designed with a thermal shutdown protection that turns the device off when the junction temperature surpasses 150°C to prevent IC from damaging. The information in table 3 was calculated for maximum listen volume with limited distortion. When the output level is reduced, the numbers in the table change significantly. Also, using 8Ω speakers will dramatically increase the thermal performance by increasing amplifier efficiency. Copyright ANPEC Electronics Corp. Rev. A.4 - Aug., 2009 27 www.anpec.com.tw APA2051 Package Information TQFN4x4-28 A E D b Pin 1 A1 D2 A3 L K E2 Pin 1 Corner e TQFN4x4-28 S Y M B O L MIN. MAX. MIN. MAX. A 0.70 0.80 0.028 0.031 A1 0.00 0.05 0.000 0.002 0.17 0.27 0.007 D 3.90 4.10 0.154 0.161 D2 2.10 2.50 0.083 0.098 E 3.90 4.10 0.154 0.161 E2 2.10 2.50 0.083 0.098 MILLIMETERS A3 b INCHES 0.20 REF e 0.008 REF 0.45 BSC 0.011 0.018 BSC L 0.35 0.45 0.014 0.018 K 0.20 - 0.008 - Copyright ANPEC Electronics Corp. Rev. A.4 - Aug., 2009 28 www.anpec.com.tw APA2051 Carrier Tape & Reel Dimensions P0 P2 P1 A B0 W F E1 OD0 K0 A0 A OD1 B B T SECTION A-A SECTION B-B H A d T1 Application TQFN4x4-28 A H 330.0±2.00 50 MIN. P0 P1 4.0±0.10 T1 C 12.4+2.00 13.0+0.50 -0.00 -0.20 8.0±0.10 P2 D0 2.0±0.05 1.5+0.10 -0.00 d D 1.5 MIN. 20.2 MIN. W E1 12.0±0.30 1.75±0.10 F 5.5±0.05 D1 T A0 B0 K0 1.5 MIN. 0.6+0.00 -0.40 4.30±0.20 4.30±0.20 1.30±0.20 (mm) Devices Per Unit Package Type TQFN 4x4-28 Unit Tape & Reel Copyright ANPEC Electronics Corp. Rev. A.4 - Aug., 2009 Quantity 3000 29 www.anpec.com.tw APA2051 Taping Direction Information TQFN4x4-28 USER DIRECTION OF FEED Classification Profile Copyright ANPEC Electronics Corp. Rev. A.4 - Aug., 2009 30 www.anpec.com.tw APA2051 Classification Reflow Profiles Profile Feature Sn-Pb Eutectic Assembly Pb-Free Assembly 100 °C 150 °C 60-120 seconds 150 °C 200 °C 60-120 seconds 3 °C/second max. 3°C/second max. 183 °C 60-150 seconds 217 °C 60-150 seconds See Classification Temp in table 1 See Classification Temp in table 2 Time (tP)** within 5°C of the specified classification temperature (Tc) 20** seconds 30** seconds Average ramp-down rate (Tp to Tsmax) 6 °C/second max. 6 °C/second max. 6 minutes max. 8 minutes max. Preheat & Soak Temperature min (Tsmin) Temperature max (Tsmax) Time (Tsmin to Tsmax) (ts) Average ramp-up rate (Tsmax to TP) Liquidous temperature (TL) Time at liquidous (tL) Peak package body Temperature (Tp)* Time 25°C to peak temperature * Tolerance for peak profile Temperature (Tp) is defined as a supplier minimum and a user maximum. ** Tolerance for time at peak profile temperature (tp) is defined as a supplier minimum and a user maximum. Table 1. SnPb Eutectic Process – Classification Temperatures (Tc) 3 Package Thickness <2.5 mm Volume mm <350 235 °C Volume mm ≥350 220 °C ≥2.5 mm 220 °C 220 °C 3 Table 2. Pb-free Process – Classification Temperatures (Tc) Package Thickness <1.6 mm 1.6 mm – 2.5 mm ≥2.5 mm Volume mm <350 260 °C 260 °C 250 °C 3 Volume mm 350-2000 260 °C 250 °C 245 °C 3 Volume mm >2000 260 °C 245 °C 245 °C 3 Reliability Test Program Test item SOLDERABILITY HOLT PCT TCT HBM MM Latch-Up Copyright ANPEC Electronics Corp. Rev. A.4 - Aug., 2009 Method JESD-22, B102 JESD-22, A108 JESD-22, A102 JESD-22, A104 MIL-STD-883-3015.7 JESD-22, A115 JESD 78 31 Description 5 Sec, 245°C 1000 Hrs, Bias @ 125°C 168 Hrs, 100%RH, 2atm, 121°C 500 Cycles, -65°C~150°C VHBM≧2KV VMM≧200V 10ms, 1tr≧100mA www.anpec.com.tw APA2051 Customer Service Anpec Electronics Corp. Head Office : No.6, Dusing 1st Road, SBIP, Hsin-Chu, Taiwan Tel : 886-3-5642000 Fax : 886-3-5642050 Taipei Branch : 2F, No. 11, Lane 218, Sec 2 Jhongsing Rd., Sindian City, Taipei County 23146, Taiwan Tel : 886-2-2910-3838 Fax : 886-2-2917-3838 Copyright ANPEC Electronics Corp. Rev. A.4 - Aug., 2009 32 www.anpec.com.tw