ETC PD5019

Telephone Ring Generator
Controller
PD5019
US Patent No. 5,828,558
PD5019
TELEPHONE RING GENERATOR CONTROLLER
FEATURES
♦
♦
♦
♦
♦
♦
♦
♦
♦
♦
Integrated Overload and Short Circuit Protection
Programmable Large Swing Output Amplitude
Digitally Selectable Ringing Frequencies; 16.7/20/25 or 50Hz
Line Regulated Output Amplitude, 45-93Vrms
Overload Protection with Adaptive Output Amplitude
High Output Load Indication Signal
Zero Crossing Synchronization Output
Operates from a Single 5V Supply
Open Loop Flyback Topology Reduces Component Count
Total Bill of Material Cost as Low as $5 Including the PD5019
for 2W Ring Generator Applications
♦ 90 Days Warranty
APPLICATIONS
♦
♦
♦
♦
♦
♦
♦
♦
♦
1 to 3 Watt Low Cost Sine Wave Ring Generators
3 to 6 Watt advanced Sine Wave Ring Generators
Large Variety of Customized Sine Wave Ring Generators
Ring Generator for PBX, PABX, DCL, CTI and Key Systems
Ring Generator for Rural Telephony and Wireless Local Loop Systems
Ring Generator for Integrated Access Devices
Ring Generator for VoIP Gateways
Ring Generator for Short/Long Loop Applications
Ring Generator for Telecom Test Equipment
INHIBIT
1
16
Vcc
FS
2
15
PWM_Out
F1
3
14
WDO
F0
4
13
CL
OHD
5
12
CAD_In
XTAL1
6
11
PAD_Out
XTAL2
7
10
BRC
GND
8
9
SYNC
SOW-16 Package
GENERAL DESCRIPTION
The PD5019 is a unique pulse width modulator controller, designed primarily for a variety of high voltage sinusoidal telephone ring generator
applications. The PD5019 is suitable for applications requiring up to 6 Watt and provides all necessary controls for implementing advanced
overload protection, zero crossing relay switching synchronization, Off-Hook detection, multiple ringing frequency selection and output
amplitude adjustment.
The power train, designed to be used with the PD5019, is an isolated, open loop flyback topology. The PD5019 generates a PWM signal,
which drives a FET transistor that switches the primary of a flyback transformer. This produces a rectified half sine wave on the secondary
side of the transformer. An additional control signal synchronizes a 4-output transistor bridge, which converts the rectified half sine wave to full
sine wave. In order to maintain the ring generator’s input to output isolation, the synchronization signals control the bridge via an opto coupler
pair. The controller also includes overload protection, A/D function for measuring the input voltage, and a report signal for indicating over
current.
The PD5019 is a cost-effective solution for applications using more than 10,000 units. For quantities less than 10,000 units, the most
economical solution is a modular sine wave ring generator (PCR-SIN01A Series or the PCR-SIN06 Series).
INTERNAL BLOCK DIAGRAM
PD5019
CL
OHD
Vcc
Over-Current
Sensing
Mechanism
Overload
Protection
GND
CAD_In
PAD_Out
XTAL1
XTAL2
FS
INHIBIT
F0
Vin
Sense
A/D
PWM
Unit
Transfer Function
Reset
Clock
Circuitry
Clock
Sine
Generator
F1
BRC
SYNC
PowerDsine Ltd.
PowerDsine, Inc.
PowerDsine Europe
Tel: +972-9-775-5100 • Fax: +972-9-775-5111 • Email: [email protected]
Tel: +1-631-756-4680 • Fax: +1-631-756-4691 • Email: [email protected]
Tel: +49-6187-900-849 • Fax: +49-6187-292848 • Email: [email protected]
PWM_Out
PD5019
TELEPHONE RING GENERATOR CONTROLLER
PIN DESCRIPTION
Pin
Symbol
1
INHIBIT
2
3
FS
F1
Function
Remote On/Off and Reset Control.
(Referenced to GND terminal)
PWM output frequency selection input.
Ringing frequency selection input.
Pin
Symbol
4
F0
Ringing frequency selection input.
12
CAD_In
5
OHD
13
CL
6
XTAL1
14
WDO
Watchdog Output.
7
XTAL2
15
PWM_Out
Main PWM output signal.
8
GND
Off-Hook/Overload reporting output.
Oscillator’s high gain amplifier input.
Crystal or ceramic resonator or an
external clock source may be applied.
Oscillator’s amplifier output. Required
when a crystal or a ceramic resonator is
used.
This terminal should be left unconnected
when using an external clock source.
Ground terminal.
Function
Ringing signal zero crossing induction
output. (2-2.5ms before crossing)
Bridge synchronization control output.
A/D reference control signal.
Input signal from the external A/D
comparator.
(Optional line regulation circuit)
Current Limit pulse counter input.
9
SYNC
10
11
BRC
PAD_Out
16
VCC
5V DC Supply voltage.
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Value
Units
Vcc
DC Supply Voltage (Referenced to GND)
-0.5 to 6
V
CAD_In, FS, INHIBIT, F0, F1, CL,
DC Input Voltage (Referenced to GND)
-0.5 to Vcc+0.5
V
XTAL1, XTAL2.
Tstg
Storage Temperature
-40 to 125
°C
Note: These are stress ratings. Exposure of the device to any of these conditions may adversely effect long-term reliability. Proper operation
other than those specified in the ELECTRICAL SPECIFICATIONS is not implied.
ELECTRICAL SPECIFICATIONS
Unless otherwise stated, these specifications apply for: Vcc = +5V, 0°C ≤ TA ≤ +70°C.
DC CHARACTERISTICS
Pin Symbol
Parameter
Vcc
Supply Voltage
Input Current
@ Continuous
@ Surge of 200nsec every 3µsec
GND
Output Current @ Continuous
@ Surge of 200nsec every 3µsec
INHIBIT
Schmitt Trigger Input
Input Voltage Level
VT+
VTInternal Pull Down
F0 , F1
CMOS 5V Input Buffer
Input Voltage High Level
Input Voltage Low Level
Internal Pull Up
FS
Schmitt Trigger Input
Input Voltage Level
VT+
VTInternal Pull Down
BRC
Output Source Current @ 4.5v
Output Sink Current
@ 0.5v
SYNC
Output Source Current @ 4.5v
Output Sink Current
@ 0.5v
OHD
Output Source Current @ 4.5v
Output Sink Current
@ 0.5v
PWM_Out
Output High Level
@ Iout=20 mA
Output Low Level
@ Iout=-20 mA
Output Source/Sink Current
@ Continuous
@ Surge of 200nsec every 3µsec
PD5019
Min
4.75
Typ
2.65
1.35
Max
5.25
35
110
50
125
Units
V
mA
mA
mA
mA
3.35
1.95
V
V
KΩ
Vcc+0.5
0.3•Vcc
V
V
KΩ
3.35
1.95
0.5
V
V
KΩ
mA
mA
mA
mA
mA
mA
V
V
48
mA
mA
100
0.7•Vcc
-0.5
5
0
100
2.65
1.35
100
5
5
1.5
5
1.5
5
10
10
2
10
2
10
Vcc-0.5
20
US Patent No.
5,828,558
PD5019
TELEPHONE RING GENERATOR CONTROLLER
Pin Symbol
WDO
Parameter
Output High Level
@ Iout=1mA
Output Low Level
@ Iout=-1mA
Output Source/Sink Current
@ Continuous
Output High Level
Output Low Level
Output Source/Sink Current
CMOS 5V Input Buffer
Input Voltage High Level
Input Voltage Low Level
internal Pull Up
CMOS 5V Input Buffer
Input Voltage High Level
Input Voltage Low Level
internal Pull Up
PAD_Out
CAD_In
CL
Min
Vcc-0.5
Typ
Max
0.5
Units
V
V
0.2
2
mA
V
V
mA
1
Vcc-0.2
1.5
0.7•Vcc
-0.5
5
0
100
Vcc+0.5
0.3•Vcc
V
V
KΩ
0.7•Vcc
-0.5
5
0
100
Vcc+0.5
0.3•Vcc
V
V
KΩ
CLOCK CHARACTERISTICS
Pin Symbol
Parameter
Min
Typ
Max
Units
XTAL1
Oscillator Input Pad
XTAL2
Oscillator Output Pad
Clock Frequency
10
20
MHz
Total Frequency Accuracy
1
%
(Total Frequency Accuracy is identical to the Crystal/Ceramic Resonator or external clock source frequency accuracy)
The Clock Oscillator works with a Crystal or a Ceramic Resonator or an external clock source.
OPERATING TEMPERATURE
Symbol
Parameter
TA
Ambient temperature
Tj
Maximum Junction Temperature
OUTPUT RINGING & PWM FREQUENCIES
FS
Oscillator
Frequency
(Main Clock)
12.28MHz
0
0
0
0
19.66MHz
1
1
1
1
Min
-40
Typ
25
Max
85
125
F1
F0
PWM
Frequency
Output
Frequency
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
96KHz
96KHz
96KHz
96KHz
307.2KHz
307.2KHz
307.2KHz
307.2KHz
50Hz
16.7Hz
25Hz
20Hz
50Hz
16.7Hz
25Hz
20Hz
Units
°C
°C
Output
Frequency
Accuracy
2% max.
2% max.
2% max.
2% max.
2% max.
2% max.
2% max.
2% max.
INHIBIT OPERATION
Operating State
Output Enabled
Output Disabled
INHIBIT OPERATION DELAY
FS
X
PowerDsine Ltd.
PowerDsine, Inc.
PowerDsine Europe
Inhibit State
0
1
Inhibit Input
Operating State
Inhibit Response Time
Output Enabled
40mS typical
0
Output Disabled
Wait for end of ½ sine cycle,
30mS maximum
1
Output Disabled
Immediate
Tel: +972-9-775-5100 • Fax: +972-9-775-5111 • Email: [email protected]
Tel: +1-631-756-4680 • Fax: +1-631-756-4691 • Email: [email protected]
Tel: +49-6187-900-849 • Fax: +49-6187-292848 • Email: [email protected]
PD5019
TELEPHONE RING GENERATOR CONTROLLER
SYNC OUTPUT
F1
0
0
1
1
F0
0
1
0
1
Output Frequency
50
16.7
25
20
SYNC Pulse Width mS
4
5
5
5
INPUT VOLTAGE SAMPLING A/D CONVERTER
Unless otherwise stated, these specifications apply for: Vcc = +5V, -40C° ≤ TA ≤ +85°C, PAD_Out current ≤ 3mA.
INTERNAL FUNCTIONAL PARAMETERS
Main Clock
A/D
Resolution
19.66MHz
12.28MHz
8 bit
8 bit
A/D PWM
Frequency
PAD_Out
76.77KHz
47.97KHz
CAD_In
Sampling
Rate
9.6KHz
6.0KHz
Full Scale
Response
Time
24.89mS
39.83mS
Vsample
Sensitivity
58.6mV
58.6mV
A/D BEHAVIORAL PARAMETERS
Symbol
Parameters
Min
A/D input operation voltage
Normal A/D operation
0.332
(Vsample)
A/D not used*
0
*CAD_In = “0” AND THE A/D REACHED ITS MINIMUM OPERATION VALUE (Minimum A/D Duty Cycle).
Max
4.98
0.293
Units
Vdc
Vdc
PWM UNIT
OPERATING RANGE
CL Input = ‘1’
Main Clock
FS
Output
PWM
PWM Frequency
Resolution
12.28MHz
0
96KHz
7 bit
19.66MHz
1
307.2KHz
6 bit
*Duty Cycle = Ratio between the time the signal’s On duration to the On + Off duration.
PWM
Duty Cycle * Min
0%
0%
PWM
Duty Cycle * Max
92.18%
92.18%
PWM UNIT OPERATION AT OVERLOAD CONDITION
PD5019
FS
0
PWM Turn Off Delay When CL
Main Clock
12.28Mhz
1
19.66Mhz
PWM Turn Off Delay When CL
Min
Max
1 Main Clock
2 Main Clocks
81.43ns
162.86ns
1 Main Clock
2 Main Clocks
50.86ns
101.72ns
US Patent No. 5,828,558
PD5019
TELEPHONE RING GENERATOR CONTROLLER
V(+)
+
R1
V(-)
R2
A/D
Vsample
T1
+
O2
-
O1
CAD_ IN
FS
Frequency
Selection
PAD_Out
INHIBIT
PWM Out
Buf
OUTPUT BRIDGE
F1
F0
CL
Synchronous
Switch Control
+
Overload
OHD
Zero
Crossing
Sync.
SYNC
BRC
PD5019
CURRENT
LIMITER
REF
OPTO
COUPLER
Typical Operating Circuit
PowerDsine Ltd.
PowerDsine, Inc.
PowerDsine Europe
Tel: +972-9-775-5100 • Fax: +972-9-775-5111 • Email: [email protected]
Tel: +1-631-756-4680 • Fax: +1-631-756-4691 • Email: [email protected]
Tel: +49-6187-900-849 • Fax: +49-6187-292848 • Email: [email protected]
PD5019
TELEPHONE RING GENERATOR CONTROLLER
DETAILED DESCRIPTION
VCC
CLOCK
XTAL1, XTAL2: The oscillator generates the internal PD5019 clock
frequency.
A Crystal, Ceramic Resonator, or an external clock source may be
used to generate the clock’s basic frequency.
When a Crystal or a Ceramic Resonator is used, it should be
connected between XTAL1 and XTAL2 terminal. For an external
clock source, connect the source to XTAL1, leaving XTAL2
unconnected.
When using a Ceramic Resonator, use the product’s specification
connection recommendations.
When using a Crystal or Ceramic Resonator, a 1Mohm 1% bias
resistor must be connected in parallel.
C1 and C2 recommended values for the different frequency sources
are specified in the table below.
Oscillator type
Frequency
C1
C2
Crystal
12.28MHz
22pF
22pF
Crystal
19.66MHz
10pF
10pF
Ceramic Resonator
12.28MHz
10pF
56pF
Inhibit
signal
C3
Inhibit
100K
VCC
C4
FS
2
100K
100KHz PWM Output POR Configuration
The value of C3 and C4 will be determined according to the Supply
Voltage Rise Time and the Inhibit delay operation.
When using a 100KHz PWM output configuration the value of C4
should be 20 times smaller than C3.
[τ (FS) < τ (Inhibit)].
Ceramic Resonator
19.66MHz
10pF
56pF
When using an external clock source, C1 and C2 and the Resistor
should not be installed and XTAL2 should be left open.
For the oscillator frequency, refer to the OUTPUT RINGING & PWM
FREQUENCIES Table.
1
4.7K
VCC
C3
Inhibit
signal
1
4.7K
100K
VCC
XTAL1
6
2
100K
1MΩ
1%
XTAL2
C2
FS
7
C1
Oscillator Typical Configuration
TURN ON RESET OF THE PD5019
For proper operation, the PD5019 controller must be reset after
power is applied. Reset is performed by setting the Inhibit and the FS
terminals to a high logic level for longer than 1µ sec.
The Inhibit and the FS terminals are connected to an internal Schmitt
input buffer with an internal 100KOhm pull down resistor.
To enable Power On Reset (POR) and proper inhibit operation, a
series resistor and pull up capacitors must be connected to the
INHIBIT terminal. The value of the resistor and the pull up capacitors
determine the reset duration, and delay of the inhibit operation.
300KHz PWM Output POR Configuration
INHIBIT: The Inhibit input serves to turn the device’s output On/Off
by using digital control levels.
High logic level (“1”) disables the device’s output.
When the 96KHz configuration is utilized (FS=”0”), the Inhibit shut
down response is internally delayed until the end of the current half
sine cycle, to the nearest output zero crossing.
When the 307KHz configuration is utilized (FS=”1”), the Inhibit shut
down response is immediate.
FS: This line selects between 96KHz and 307KHz main PWM
frequency.
FS= ”0” = 96KHz
FS= ”1” = 307KHz
The 96KHz PWM frequency is suitable for medium power sine wave
generators, with synchronous switching at the secondary.
In low cost, low power, ring generator applications, the synchronous
switching circuitry may be eliminated. In order to maintain reasonable
efficiency while not employing synchronous switching, the 307KHz
PWM frequency is employed.
PD5019
US Patent No.
5,828,558
PD5019
TELEPHONE RING GENERATOR CONTROLLER
FREQUENCY SELECTION
F0, F1: Selection of a single output ringing frequency between the
four available options of 16.7, 20, 25 or 50Hz is achieved by the F0
and F1 inputs.
The state of F0 and F1 inputs must be set and stable prior to
powering the PD5019. Changing the input state while the
PD5019 is operating may not effect the output frequency, and
may cause the controller to become unstable state.
The frequency selection should be made according to the OUTPUT
RINGING & PWM FREQUENCIES table on page 45.
These inputs are CMOS standard and can be driven directly from
CMOS components, or the frequency selection can be achieved by
tying them to GND or Vcc.
Note: The PD5019 operation may be affected by excessive noise
surges on F0 and F1 terminals while operating.
VCC
100K
F1 3
VCC
F0
4
100K
CAD_In: This input line should be connected to the output of the A/D
circuit’s external comparator. CAD_In = “1” will increase the PWM
duty cycle at the PAD_Out line. CAD_In = “0” will decrease the PWM
duty cycle at the PAD_Out line. When the sampled voltage is stable,
the A/D PWM duty cycle will change up and down by 1 bit and the
comparator output will vibrate. These 1-bit vibrations are ignored by
the A/D.
Applications that use highly regulated power supplies may eliminate
the A/D external portions. In this event, the CAD_In should be
permanently connected to GND. Note that no output voltage
regulations based on input voltage changes will be performed.
LOW PASS NETWORK
The network is connected between the PAD_Out and the negative
input of the comparator, built from R3 & C1.
The low pass network is designed to average the PWM signal into a
DC Level. This DC level is compared to the sampled voltage.
It is recommended to calculate the Low Pass network components
values according to the following:
τ(Recommended) = C1 • R3 = 89.1µS @ 96KHz Operation
τ(Recommended) = C1 • R3 = 52µS @ 307KHz Operation
* For timing details refer to A/D CONVERTER, INTERNAL
FUNCTIONAL PARAMETERS TABLE.
Vin
Frequency Selection Inputs
LINE REGULATION (A/D UNIT)
The ring generator circuit design is based on an open loop flyback
topology. In order to regulate the output for input voltage changes, a
forward compensation mechanism is used.
This mechanism is based on a digital sampling of the input voltage
by the A/D unit, and correction of the main PWM duty cycle
according to the internal transfer function.
The input voltage is sampled by an 8bit A/D unit, which is composed
of external analog components and the internal PD5019 logic.
The internal portion of the A/D generates a PWM signal (PAD_Out)
with a changing duty cycle according to the voltage sampled by the
CAD_In terminal.
The sampled input voltage information influences the ringer output
voltage amplitude in such a way that changes in Vin generates only a
small change in Vout.
PAD_Out: PWM output for the external A/D circuit. The PWM
frequency is the oscillator frequency divided by 8.
This line is connected to an external Low pass network that averages
the PWM pulses to a DC voltage. The level of this DC voltage is
proportional to the duty cycle of the PWM signal. The Low pass
network is connected to the negative input of an external comparator.
This DC voltage tracks the sampled voltage that is connected to the
positive input of the comparator. If the DC voltage is lower than the
sampled voltage, the internal A/D circuit will increase the PWM duty
cycle. This will increase the DC level. The opposite happens when
the sampled voltage is lower than the DC voltage.
PD5019
R1
Vsample
3
2
+
CMP_IN
1
R3
R2
PAD_OUT
INTERNAL
A/D
8Bit Data to Transfer
Function
C1
A/D Circuit Implementation
♦ The comparator inputs for the A/D function must operate in the
range of 0 to 5V.
♦ The Vsample sampling is synchronized for the sine wave peak.
Voltage Divider: The voltage divider connects to the positive input of
the comparator and is built of R1 & R2.
The voltage divider is required when an input voltage, Vin, higher
than 5V is used. Design the Vsample voltage divider to deliver 2.5V
for typical Vin Value is recommended.
OUTPUT PROTECTION MECHANISM
The overload and short circuit protection mechanisms support three
protection levels:
1. Immediate pulse by pulse, input current limiting.
2. Power reduction, by output amplitude reduction.
3. Shut down for limited periods, to reduce heat dissipation.
The input of the protection unit is the CL input, connected to external
current sense circuit output.
CL - Current Limiting Pulse Counter:
When the CL input changes to a Low due to excessive switch
current, the PWM output immediately changes to Low until the end of
the current PWM cycle. This will terminate the current through the
switching FET and the CL input will return to a high level.
PowerDsine Ltd.
PowerDsine, Inc.
PowerDsine Europe
Tel: +972-9-775-5100 • Fax: +972-9-775-5111 • Email: [email protected]
Tel: +1-631-756-4680 • Fax: +1-631-756-4691 • Email: [email protected]
Tel: +49-6187-900-849 • Fax: +49-6187-292848 • Email: [email protected]
PD5019
TELEPHONE RING GENERATOR CONTROLLER
Output Amplitude Reduction Mechanism
During overload conditions, the PD5019 reduces the circuit output
voltage, while maintaining a clean sine wave, to a level that delivers
the allowed maximum output power. The protection unit counts the
number of CL pulses which are received during a single half sine
wave cycle and compares the result to an internal threshold. The
numbers of CL pulses that exceed the threshold indicate overload
conditions. Reduction of the output sine wave amplitude, in one step
resolution, is accomplished according to the following equation.
Vout peak = VpeakNomin al × 16
Step
During normal operating conditions, the step number is 16. In
overload conditions, the step number can reach 31.
The amplitude can be reduced to about half of the nominal
amplitude.
In each step there will be less current limit indications.
If the overload is removed and there are no CL pulses at all, the
amplitude will begin to rise back, step by step. Each step takes one
half of a sine wave cycle.
The OHD Output that reports an overload situation is activated based
on the step number.
Reduction of the output amplitude, by more than 16 table steps, will
be indicated by OHD change to High (“1”).
When the protection unit raises the amplitude back to step 16, the
amplitude will remain at this step at least a single sine period and
this line will go back to Low (“0”).
♦ High level (OHD=”1”) means the output is overloaded.
♦ Minimum pulse length = 1 sine cycle.
♦ Maximum time for Over Load detection = ½ sine cycle time,
(30mS at 16.7Hz ringing frequency).
♦ Over load required duration, for detection = ½ sine cycle time.
This line can be useful for overload problem reports in medium size
ringers, and can be used for off hook detection in small size ringers
when there are few telephones connected to one line.
Output Shut Down
If the output load of the ring generator is high, and the output
amplitude has reached its minimal level, an internal counter will start
to count 300mS.
If the overload has not been removed after 300mS, the protection will
shut down the PWM for 4.86 sec.
After the shutdown period, the PD5019 will begin operating at
minimum amplitude level.
If there are still CL pulses, the internal counter will start to count
300mS again and shut down for 4.86 sec again.
However if the load is removed after the shutdown period, the output
amplitude will start to increase, step by step.
Vin
♦ Maximum amplitude reduction/incremental
response time = ½ sine cycle time.
♦ Time for overload shut down = (8 • sine cycle time)+300mS.
Max.
♦ Shut down period = 4.86Sec.
Timing accuracy is derived from the main oscillator frequency
accuracy.
DETERMINING THE OUTPUT AMPLITUDE
The topology of the ring generator is an open loop flyback. In this
topology, the output amplitude is determined by the PWM duty cycle.
The PD5019 changes its PWM duty cycle according to an internal
sine wave reference table and a known mathematical transfer
function.
To determine the maximum amplitude of the output sine wave, use
the following equation:
R1 + R2
Vout rms = (2.773 • n) • (
)
R2
♦ R1 and R2 are the voltage divider resistors used in the Vin
sampling A/D.
♦ n is the winding turn ratio of the transformer.
♦ It is recommended to change the output voltage amplitude by
changing R1 or R2 while using the typical rated n. A highresolution potentiometer can be used to obtain the proper
resistor values during the circuit design.
CHOOSING n:
1. Define the input voltage range.
2. Calculate the average input voltage according to the following
equation.
Vin mid =
Vin min+ Vin max
2
3.
Choose the parameter nVin according to the following table.
Parameter
Min.
Recommended
Max.
42
48
54
nVin
4.
Calculate n (winding turns ratio) according to the following
equation.
n=
nVin (choosed from the table)
Vin mid
ADJUSTING OUTPUT AMPLITUDE WITHOUT A/D
When the input voltage sampling the A/D is not used (CAD_In = ”0”),
the maximum output amplitude is determined according to the input
voltage and turns ratio.
T1
Vout rms = 1.4731• n • Vin
PD5019
100 OHM
PWM OUT
Q1
BUK 582-100 A
Note: When the input voltage sampling A/D is not used, the CAD_In
terminal must be grounded.
R3
VCC
PWM_Out: This is the PWM output signal. This output is capable of
directly driving a FET.
Vin
R2
1KΩ
CL
REF
1
U1A
8 LM339
3
+
- 2
C18
1nF 50 V
4
R1
Typical current sense circuit configuration
PD5019
US Patent No.
5,828,558
PD5019
TELEPHONE RING GENERATOR CONTROLLER
SYNCHRONIZATION SIGNALS
BRC: The BRC output controls the ring generator’s output power
bridge. The bridge converts the half sine rectified wave to a full sine
wave at the output.
The BRC signal is a logic level square wave at the same frequency
of the output sine wave.
SYNC: The SYNC output is used to synchronize output ringing
relays switching with the ring generator’s output voltage zero
crossing. The SYNC output produces a high logic level pulse to
indicate zero crossing. The SYNC pulse rises a short time prior to
the output signal’s zero crossing in order to allow for the relay
response time. Exact signal timing are indicated in the ELECTRICAL
CHARACTERISTICS SYNC OUTPUT parameters.
to SLIC Audio Line
Relay
O2
TIP
PD5019
Based Ring
Generator
RING
O1
VBAT = -48v
SYNC
Control
Zero crossing relay control utilizing the SYNC output
LOAD REGULATION
Load regulation refers to the degree of output voltage deviations as a
function of output rms current variations. The load regulation
capability of a ring generator built around the PD5019 will be effected
by a number of design and component selection criteria:
♦
The quality of the transformers’ primary to secondary coupling
and winding leakage. Good coupling and low leakage will
improve load regulation.
♦
Impedance of the transformer winding and core losses. Low
impedance and low core losses will improve load regulation.
♦
Input capacitor ESR. Low ESR will reduce input voltage ripple,
which will improve the input voltage A/D sampling accuracy.
Since the input voltage A/D sensing directly effects the device’s
output voltage, high sampling accuracy will improve load
regulation.
♦
FET dropout voltage. Low main switching and synchronous
switching FETs dropout voltage will improve load regulation.
♦
Output bridge transistor’s dropout voltage. Low dropout voltage
will improve load regulation.
In proper design, load regulation of 6% for loads varying from 10% to
100%, and 10% regulation for loads varying from no load to 100% of
the circuit’s rated load, can be achieved. Rated load is defined as the
equivalent loading that does not cause the PD5019 to decrease the
ring generator’s output voltage, or trigger the overload/short circuit
protection.
PowerDsine Ltd.
PowerDsine, Inc.
PowerDsine Europe
Tel: +972-9-775-5100 • Fax: +972-9-775-5111 • Email: [email protected]
Tel: +1-631-756-4680 • Fax: +1-631-756-4691 • Email: [email protected]
Tel: +49-6187-900-849 • Fax: +49-6187-292848 • Email: [email protected]
PD5019
TELEPHONE RING GENERATOR CONTROLLER
O1
Vcc
R4
1K
Output Ringing
Signal
D1
V(+)
T1
C2
1
8
2
7
MMBTA 92
MMBTA 92
U2A
R3
0.22uF/200V
R2
14.5K 1W
C3
D4
D2
BAS21
O2
U2B
3
6
Q3
MMBTA42
4
US1G
5
Q4
D3
BAS21
MMBTA42
R5
1K
R21
Q5
MOCD217
Q1
Q2
200K 1/4W
C1
.
0.22uF/200V
US1G
+
BUK 582-100A
100R
V(-)
Vcc
5V
C6
0.01uF
U1
Inhibit
1
2
F1
3
F0
4
5
6
R6
1M
C8
4.7nF
C7
4.7nF
XT1
C4
10pF
7
8
PD5019
INHIBIT
Vcc
FS
PWM Out
F1
WDO
F0
CL
OHD
CAD_ IN
XTAL2
PAD_Out
XTAL1
BRC
GND
SYNC
16
15
14
13
12
11
10
9
C5
10pF
Typical Application – 2 REN Sine Wave Ring Generator
PD5019
US Patent No.
5,828,558
PD5019
TELEPHONE RING GENERATOR CONTROLLER
V(+)
O1
47uF/25V
C2 +
Vcc=5V
RINGING
SIGNAL
OUTPUT
O2
D3
Q2
R13
51.1R
10 R
US1G
Q6
BAT54A
Y
B
MMBT2907A
Q15
D12
BAV 70
Vaux
Q5
IRFR310
D5
SB3040
.
US1G
R22
10K
Q9
U3
2
F0
4
OHD
5
CL
OHD
GND
SYNC
10
9
C9
D14
BAS21
R16
0.1R
Vaux
C23
4.7nF/50V
4.7nF/50V
10pF/50V
C22
Vcc
V(+)
V(+)
R42
51.1R
R3
18.2K
8
R1
1K
VCC
6
C10
4
U4B
LM2903D
R17
5.11K
5
39nF/25V
+
-
V(-)
R6
2.7K
C7
10nF/50V
Typical Application - 3 to 6REN Sine Wave Ring Generator
PowerDsine Ltd.
PowerDsine, Inc.
PowerDsine Europe
U1A
R14
1K
BRC
R18
2,49K
R40
5.11K
7
SYNC
MOCD217
U1B
4
C17
D10
BAS21
BRC
3
10pF/50V
C18
C25
PD5019
C16
2
Q4
MMBT5551
Q3
MMBT5551
1
BRC
MMBTA 92
2
XTAL1
-
11
R8
10K
Q10
D7
8
PAD_Out
13
12
3
Vaux
7
8
XTAL2
U4A
LM2903D
+
1
R39
5.11K
5
7
CAD_ IN
15
14
6
12.28MHz
WDO
D9
R21
1K
4
XT1
PWM Out
F1
F0
6
R34
1M
FS
D6
MMBTA 92
V(+)
16
8
3
F1
Vcc
2.2uF/16V
1K
INHIBIT
0,1uF/50V
1
Vz=15V
Vcc
R38
1nF/50V
Inhibit
D13
BAV 70
L2
BAS21
Q14
R35
A
BUK 582-100A
MMBT2222A
Vcc
Q12
D4
C19
0.1uF/25V
U5
R20
30.1K
Q8
Q1
D11
MMBT5551
D2
MMBT5551
MMBT5551
Q7
BAS21
Q11
C5
T1
Vcc
BAS21
MMBT5551
R5
MMBT5551
R9
329R
30.1K
0,22uF/200V
R7
10K
C6
0,33uF/10V
0.1uF/10V
C13
0.1uF/10V
C15
MMBT5551
Vcc
Tel: +972-9-775-5100 • Fax: +972-9-775-5111 • Email: [email protected]
Tel: +1-631-756-4680 • Fax: +1-631-756-4691 • Email: [email protected]
Tel: +49-6187-900-849 • Fax: +49-6187-292848 • Email: [email protected]
R15
1K
PD5019
TELEPHONE RING GENERATOR CONTROLLER
MECHANICAL DETAILS
Top View
A
Rx45°
8
1
M
B
J
P
F
9
16
D
C
G
DIM
A
B
C
D
F
G
J
K
M
P
K
MILLIMETERS
MAX
MIN
10.20
10.35
7.40
7.60
2.40
2.65
0.35
0.51
0.40
0.90
1.27 BSC
0.23
0.32
0.10
0.30
0°
8°
10.10
10.60
0.25
0.75
K
BASE
PLANE
SEATING
PLANE
INCHES
MIN
MAX
.402
.408
.292
.298
.094
.104
.0138
.020
.016
.035
0.50 BSC
.0091
.0125
.0040
.0118
0°
8°
.398
.416
.010
.029
Notes:
1. Dimensions and tolerance per ANSI Y14.5M 1982
2. Controlling dimensions: millimeter.
3. Dimensions “A” and “B” do not include mold protrusion.
4. Maximum mold protrusion 0.15mm (0.006”) per side.
5. Dimension “D” does not include dambar protrusion. Allowable dambar protrusion shall be 0.13mm (0.005”) total in excess of “D”
dimension at maximum metrical condition.
6. Package type: SOW-16
PowerDsine application engineers will provide technical assistance integrating the PD5019 for customers using more than 10,000 units. For
quantities lower than 10,000 units, use of a modular sine wave ring generator is recommended (PCR-SIN06 Series). To receive PowerDsine
PD5019 applications notes or to obtain technical assistance, please contact your local representative or PowerDsine’s main offices, detailing
your application requirements.
PD5019
US Patent No.
5,828,558
PD5019
TELEPHONE RING GENERATOR CONTROLLER
PD5019 V08 0900