KINGBRIGHT KD125

King Billion Electronics Co., Ltd
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KD125
LCD Driver Series
- Table of Contents 1. General Description_______________________________________________________________2
2. Features________________________________________________________________________2
3. Block Diagram___________________________________________________________________3
4. Pin Description __________________________________________________________________3
5. Control Registers _________________________________________________________________3
6. LCD Power System_______________________________________________________________3
7. Relationship between Display Data and LCD Driver Pins __________________________________3
8. Multi-Chip Connection ____________________________________________________________3
9. Timing Chart of Cascade Connection _________________________________________________3
10. Common Connection______________________________________________________________3
11. Mixed Mode Connection ___________________________________________________________3
12. Precautions _____________________________________________________________________3
13. LCD Waveform __________________________________________________________________3
14. Pin Locations ____________________________________________________________________3
15. Absolute Maximum Rating _________________________________________________________3
16. Recommended Operating Conditions _________________________________________________3
17. AC/DC Characteristics ____________________________________________________________3
18. Application Circuit for module ______________________________________________________3
19. Updated Record__________________________________________________________________3
January 20, 2005
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KD125
LCD Driver Series
1. General Description
The KD125 is a member of LCD driver IC series developed by King Billion Electronics Co. It’s a
120-output common/segment LCD driver IC suitable for driving small/medium scale dot matrix LCD
panels, used in PDA or electronic dictionary. The KD125 is good as a segment driver, common driver or
common/segment driver, and it can create a low power consuming, high-resolution LCD. The KD125
have eight modes can selected to set common and segment numbers by control register. The KD125 also
has built- in analog regulator and DC/DC converter and they can be enabled or disabled to use external
LCD power system for larger LCD panel.
2. Features
Ø Number of LCD drive outputs: 120 COM/SEG
Ø Supply voltage for LCD drive: Max +16V
Ø Supply voltage for the logic system: +2.4 to +4 V
Ø LCD display duty selectable by control register
Ø 8 LCD Configurations: 0COM/120SEG, 32COM/88SEG, 48COM/72SEG, 64COM/56SEG,
80COM/40SEG, 96COM/24SEG, 112COM/8SEG, 120COM/0SEG.
Ø Low power consumption and low output impedance
Ø Built- in LCD voltage regulator and booster circuit (with Boost ratio of 2X/3X/4X/5X/6X)
Ø Bias configuration: 1/6 ~ 1/12 bias.
Ø Bus width selectable: 1-bit series / 4-bit parallel modes.
Ø Package: 154-pin COB (Pad Size:80um×80um, Pad Pitch: 95um×95um).
(Segment mode)
Ø Shift clock frequency
15 MHz (MAX.): VDD = +3.0 to + 4 V
12 MHz (MAX.): VDD = +2.4 to + 3.0 V
Ø 4-bit parallel / serial input modes are selectable with a mode (P/S) pin
Ø Automatic transfer function of an enable signal
Ø Automatic counting function which, in the chip selection mode, causes the internal clock to be
stopped by automatically counting 88、72、56 、40、24、8 or 120 bits of input data
Ø Line latch circuits are reset when XDISPOFF active
(Common mode )
Ø Shift clock frequency: 4 MHz (MAX.)
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KD125
LCD Driver Series
Ø Built- in X-bit shift register
Ø Available in a single mode
Ø Y1 ->YX Single mode
YX->Y1 Single mode
X=32、48、64、80、96、112、120
Ø Shift register circuits are reset when XDISPOFF active
(16 Levels Gray Display)
Ø B/W, 4 and 16 gray levels can be displayed by the pulse width modulation.
3. Block Diagram
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KD125
LCD Driver Series
4. Pin Description
Pin Name
I/O
Description
Y[119..0]/CMSG[119:0] O LCD driver Common/Segment outputs
V[5:1]
P
Power supply for LCD driver, Connect a capacitor between this terminal
and GND.V5 ≧ V4 ≧ V3 ≧ V2 ≧ V1 ≧ GND.
DC/DC charge pump voltage, connect a capacitor between this terminal
LVP
P
LCAP1A
O DC/DC charge pump converter pad.
LCAP1B
O DC/DC charge pump converter pad.
LCAP2A
O DC/DC charge pump converter pad.
LCAP2B
O DC/DC charge pump converter pad.
LCAP3A
O DC/DC charge pump converter pad.
LCAP4A
O DC/DC charge pump converter pad.
LCAP5A
O DC/DC charge pump converter pad.
LGS1
I
Regulator voltage setting pin(adjust V5 voltage)
LGS2
I
Regulator voltage setting pin(adjust V5 voltage)
VAG
O Internal reference voltage.
VDD
P
RSTn
I
January 20, 2005
and GND. .LVP ≧ V5
Positive Power Input. Adding 0.1 µF capacitor as by-pass capacitor on
power pins is necessary.(within 1 cm distance)
System Reset pin .When low level active.
The XRST L PULSE timing min value is 200us and max value is 0.5s
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I/O
GND x2
P
DI[3:0]
B
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LCD Driver Series
Description
Power ground pads.
Command/Data I/O port. All these pins are in push-pull mode
DIO[3:0] pin is used for nibble mode data transferring.
This is the parallel data input/serial data input switch terminal.
P/Sn
B
P/S=”H”: Parallel data input.
P/S=”L”: Serial data input.
Input pin for selecting the reading direction of display data
L/R
I
When set to GND level "L", data is read sequentially from Y119 to Y0.
When set to VDD level "H", data is read sequentially from Y0 to Y119.
EIO2, EIO1
I/O
Input/output for chip selection at segment mode and FLM input output
function at COM/SEG mix mode or common mode.
XGCK
I
Clock input for 16 level clock source
XCK
I
Clock input for taking display data at segment mode
XDISPOFF
I
Control input for output of non-select level
LP
I
Latch pulse input for display data at segment mode/
Shift clock input for shift register at common mode
FR
I
AC-converting signal input for LCD drive waveform
XCS
I
SDI
I
The series command data input pin.
SCLK
I
The series command clock input pin.
This is the command mode select pin.
When XCS=”L” then write command to the LCD.
5. Control Registers
There are 97 control bits used to configure the KD125. The charge-pump and current follower bias circuit
are included in KD125. These 97 control bits are written by the series interface of XCS, SDI, SCLK. The
timing is shown as below diagram, and the function descriptions of control bits are summarized in
following table.
Bit[14:13]
Bit12
January 20, 2005
Bit11
Bit10
Bit9
Bit[8:6]
5
Bit[5:3]
Bit[2:0]
Reset Value
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Gray[1:0]
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KD125
LCD Driver Series
BLANK BUFE CPUMPE PDOWN VADJ[2:0] Bias[2:0] COM[2:0] 0000_0000_0000
Bit[39:35]
Bit[34:30]
Bit[29:25]
Bit[24:20]
Bit[19:15]
Reset Value
GRAY4[4:0] GRAY3[4:0] GRAY2[4:0] GRAY1[4:0] GRAY0[4:0] 0000_0000_0000
Bit[64:60]
Bit[59:55]
Bit[54:50]
Bit[49:45]
Bit[44:40]
Reset Value
GRAY9[4:0] GRAY8[4:0] GRAY7[4:0] GRAY6[4:0] GRAY5[4:0] 0000_0000_0000
Bit[89:85]
Bit[84:80]
Bit[79:75]
Bit[74:70]
Bit[69:65]
Reset Value
GRAY14[4:0] GRAY13[4:0] GRAY12[4:0] GRAY11[4:0] GRAY10[4:0] 0000_0000_0000
Bit[96:95]
Bit[94:90]
Reset Value
CPCK[1:0] GRAY15[4:0] 0000_0000_0000
Name
Description
Charge pump clock select
00:32k
Cpck[1:0]
01:64k
10:128k
11:256k
The mapping register between the levels selected in shift data and the real gray scale
if the content of GRAY1 is 0x01, when value of a certain pixel is 1 the displayed
GRAY0[4:0]
~
GRAY15[4:0]
effect will correspond to actual gray level 1, the 16 gray scale display use all 16
registers GRAY0 ~ GRAY15 to select among 32 available gray levels to correspond
to level 0 ~ 15, when 4 gray scale display utilizes registers GRAY0 ~ GRAY3 to
select among 32 gray levels to correspond to level 0 ~ 15.
“00”: Black/White display.
Gray[1:0]
“01”: 4 levels gray display.
“10”:16 levels gray display.
“11”:Reserved
BLANK
0: Normal Display
1: LCD display blanked. The COM signals of LCD driver output inactive levels (V4
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LCD Driver Series
Description
and V1) while SEG signals output normal display patterns.
PDOWN
1:LCD charge pump disable
0:LCD charge pump enable
BUFE
1: Disable internal bias network buffer, LV1~5 are provided externally.
0: Enable internal bias network buffer.
CPUMPE
1: Internal charge-pump is disabled and LCD power is supplied externally.
0: Internal charge-pump is enabled.
LCD Contrast Adjustment (±10%)
“111”:-10% Darkest,
“110”:-7%
“101”:-4%
VADJ[2:0]
“100”:-1%
“011 ”:+1%
“010::+4%
“001”:+7%
“000”: +10% Lightest.
LCD Power System Bias Configuration
“000”: Reserved
“001”: 1/6 Bias
“010”: 1/7 Bias
Bias[2:0]
“011 ”: 1/8 Bias
“100”: 1/9 Bias
“101”: 1/10 Bias
“110”: 1/11 Bias
“111”:1/12 Bias
LCD COM/SEG Output Configuration Mode
“000”: 128 SEG
COM[2:0]
“001”: 32 COM × 88 SEG
“010”: 48 COM × 72 SEG
“011 ”: 64 COM × 56 SEG
“100”: 80 COM × 40 SEG
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LCD Driver Series
Description
“101”: 96 COM × 24 SEG
“110”: 112 COM × 8 SEG
“111”: 120 COM
SCLK
1
2
3
4
5
6
7
92
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
93
94
95
Bit92
Bit 93 Bit 94
96
97
Bit 95
Bit 96
XCS
SDI
Bit 91
Control Register Write Timing
6. LCD Power System
The internal regulator, charge-pump and current follower bias circuits are built in to provide the LCD
power system, when the internal LCD power system is used by set CPUMPE and BUFE bits. If the
external LCD power is provided, the internal LCD power system shall be disabled by clear the CPUMPE
bit. The following table shows the relationship of LCD power system.
Bit[14:13
Bit10
]
Bit12
Bit11
Gray[1:0]
BLAN
BUF
K
E
Bit9
Bit[8:6]
Bit[5:3]
Bit[2:0]
Reset Value
CPUMP
PDOW
VADJ[2:0
Bias[2:0
COM[2:0
0000_0000_000
E
N
]
]
0
]
PDOWN CPUMPE BUFE
0
0
0
Function
Internal charge-pump and current follower Bias circuit are enabled to supply
the LCD display power.
0
0
1
Internal charge-pump system is enabled, but the current follower Bias circuit
is disabled, and the external power sources are applied LV5~LV1.
0
1
January 20, 2005
0
Internal charge-pump system is disabled, but the current follower Bias circuit
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KD125
LCD Driver Series
is enabled.
The single external power is applied to LVP, and internal bias circuit will
generate the LV5~LV1 voltages.
0
1
1
Internal charge-pump and current follower Bias circuit are disabled, and the
external power sources are applied to LVP and LV5~LV1 pads.
1
0
0
The lcd power system is disable, but the LVP is applied to VDD and
LV5~LV1 is applied to high impedance.
1
0
1
The lcd power system is disable, but the LVP is applied to VDD and
LV5~LV1 is applied to high impedance.
1
1
0
The lcd power system is disable, but the LVP and LV5~LV1 is applied to
high impedance.
1
1
1
The lcd power system is disable, but the LVP and LV5~LV1 is applied to
high impedance.
The boost circuit charge pump regulated voltage to LCD highest voltage LVP (3~6 times of VDD
voltage).The set-up voltage generated at LVP output the V5 through the voltage regulator circuit.
The LCD voltage(V5) can also be fine-tuned (in ±10% range) through the VADJ[2:0] bits. The LCD
voltage levels V1~V5 shall be configured properly by the Bias[2:0] bits based on the LCD duty and LCD
highest voltage. The following table is a general configuration relationship for the LCD duty and bias.
Duty
Bias
1/32
1/6 or 1/7
1/48
1/7 or 1/8
1/64
1/8 or 1/9
1/80
1/8 or 1/9
1/96
1/9 or 1/10
1/112
1/10 or 1/11
1/120
1/11 or 1/12
Voltage charge pump: The VDD voltage is then boosted up by 3, 4, 5, or 6 times to generate LVP,
depending on external capacitors configurations as shown below. Please note that LVP must be lower than
maximum operation voltage to prevent chip from break-down. The capacitance of capacitors connected to
LVP and V1~V5 shall be increased in an appropriate amount based on the LCD panel size. For small size
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LCD Driver Series
LCD pane l, the 0.1uF capacitors are enough, but (1uF~10uF) or bigger capacitors may be necessary for
larger LCD size application..
.The
setup-up voltage circuits
3X set-up voltage circuit
C2
C2
R2
I1
LVP
VAG
R2
I27
VAG
R1
I2
C2
R1
I26
C2
4X set-up voltage circuit
LVP
LGS2
C2
LGS2
C2
LGS1
C2
V5
C2
V3
C2
V2
C2
V4
C2
V3
C2
V5
C2
V4
C2
LGS1
C2
V2
C2
V1
V1
LCAP2B
LCAP2B
LCAP1B
LCAP1B
LCAP5A
LCAP5A
LCAP4A
LCAP4A
C1
LCAP3A
C1
C1
LVP=3XVDD=9V
VDD=3V
LCAP1A
LVP=4XVDD=12V
VDD=3V
GND
January 20, 2005
LCAP3A
LCAP2A
C1
LCAP1A
GND
GND
C1
LCAP2A
GND
10
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5X set-up voltage circuit
C2
C2
LVP
LGS2
C2
V4
V3
C2
V2
C2
V5
C2
V3
C2
LGS1
C2
V4
C2
LGS2
C2
V5
C2
LVP
C2
LGS1
C2
VAG
R2
I38
R2
I1
VAG
R1
I2
C2
LCD Driver Series
6X set-up voltage circuit
R1
I37
C2
司
V2
C2
V1
V1
LCAP2B
LCAP2B
LCAP1B
C1
C1
C1
LCAP1B
C1
LCAP5A
C1
LCAP4A
C1
LCAP3A
C1
LCAP2A
C1
GND
GND
LVP=5XVDD=15V
LCAP4A
LCAP3A
LCAP2A
C1
LCAP1A
LCAP5A
LCAP1A
LVP=6XVDD=15V
VDD=3V
VDD=2.5V
GND
GND
C1 and C2 are determined by the size of the LCD being driven (0.1u~10u)
.The
voltage regulator circuit:
VADJ[2:0]
000
001
010
011
100
101
110
111
ADJ
+10%
+7%
+4%
+1%
-1%
-4%
-7%
-10%
Charge pump times
6X
V5=(1+R2/R1)*(1V±Vref*ADJ)
Vref
Condition : VDD =
3.3V
1.7
5X
4X
1.2
1.2
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3X
Use LVP (external power)
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LCD Driver Series
1.2
0.9
The R1 resistor is connected between LGS2 and ground and R2 is connected to LGS1 and LGS2.
LGS1 pin is sensitive to noise. Vref will change if LGS1 pin is coupled with noise. Please take care in
PCB layout. The metal wire between LGS1 to R1 R2 resistor is as short as possible.
7. Relationship between Display Data and LCD Driver Pins
16-level Gray Scale Display with PWM
DISPLAY DATA
DI[3] DI[2] DI[1]
0
0
0
0
0
0
0
0
1
0
0
1
0
1
0
0
1
0
0
1
1
0
1
1
1
0
0
1
0
0
1
0
1
1
0
1
1
1
0
1
1
0
1
1
1
1
1
1
DI[0]
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
GRAY SCALE REGISTER
GRAY0(GRAY LEVEL0)
GRAY1(GRAY LEVEL1)
GRAY2(GRAY LEVEL2)
GRAY3(GRAY LEVEL3)
GRAY4(GRAY LEVEL4)
GRAY5(GRAY LEVEL5)
GRAY6(GRAY LEVEL6)
GRAY7(GRAY LEVEL7)
GRAY8(GRAY LEVEL8)
GRAY9(GRAY LEVEL9)
GRAY10(GRAY LEVEL10)
GRAY11(GRAY LEVEL11)
GRAY12(GRAY LEVEL12)
GRAY13(GRAY LEVEL13)
GRAY14(GRAY LEVEL14)
GRAY15(GRAY LEVEL15)
4-level Gray Scale Display with PWM
DISPLAY DATA
DI[3]/DI[1] DI[2]/DI[0]
0
0
0
1
1
0
1
1
GRAY SCALE REGISTER
GRAY0(GRAY LEVEL0)
GRAY1(GRAY LEVEL1)
GRAY2(GRAY LEVEL2)
GRAY3(GRAY LEVEL3)
-Gray Scale REGISTER of 32 PWM (Pulse Width Modulate)
DEC
0
1
2
3
4
5
… .
GRAY SCALE REGISTER(5 BIT)
00000
00001
00010
00011
00100
00101
… … .
January 20, 2005
PWM NOTE
0
BRIGHTER
2/32
3/32
4/32
5/32
6/32
12
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… .
… .
… .
28
29
30
31
億
電
… … .
… … .
… … .
11100
11101
11110
11111
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LCD Driver Series
29/32
30/32
31/32
1
DARKER
Segment Mode
Black/White Display (4-bit Parallel Input Mode)
L/R
L
H
EIO1
Output
Input
EIO2
Input
Output
Data
Number of Clocks
Input
30 CLOCK
29 CLOCK
28 CLOCK
…
3 CLOCK
2 CLOCK
1 CLOCK
DI[0]
Y0
Y4
Y8
…
Y108
Y112
Y116
DI[1]
Y1
Y5
Y9
…
Y109
Y113
Y117
DI[2]
Y2
Y6
Y10
…
Y110
Y114
Y118
DI[3]
Y3
Y7
Y11
…
Y111
Y115
Y119
DI[0]
Y119
Y115
Y111
…
Y11
Y7
Y3
DI[1]
Y118
Y114
Y110
…
Y10
Y6
Y2
DI[2]
Y117
Y113
Y109
…
Y9
Y5
Y1
DI[3]
Y116
Y112
Y108
…
Y8
Y4
Y0
Black/White Display (1-bit Series Input Mode)
L/R
L
H
EIO1
Output
Input
EIO2
Input
Output
Data
Number of Clocks
Input
120 CLOCK
119 CLOCK
118 CLOCK
…
3 CLOCK
2 CLOCK
1 CLOCK
DI[0]
Y0
Y1
Y2
…
Y117
Y118
Y119
DI[1]
x
x
x
x
x
x
x
DI[2]
x
x
x
x
x
x
x
DI[3]
x
x
x
x
x
x
x
DI[0]
Y119
Y118
Y117
…
Y2
Y1
Y0
DI[1]
x
x
x
x
x
x
x
DI[2]
x
x
x
x
x
x
x
DI[3]
x
x
x
x
x
x
x
x: Don't care, should be fixed to "H" or "L", avoiding floating.
4 Levels Gray Display (4-bit Parallel Input Mode)
L/R
L
EIO1
Output
EIO2
Input
January 20, 2005
Data
Number of Clocks
Input
60 CLOCK
59 CLOCK
58 CLOCK
…
3 CLOCK
2 CLOCK
1 CLOCK
DI[0]
Y0 (0)*
Y2 (0)
Y4 (0)
…
Y114 (0)
Y116 (0)
Y118 (0)
DI[1]
Y0 (1)*
Y2 (1)
Y4 (1)
…
Y114 (1)
Y116 (1)
Y118 (1)
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H
Input
Output
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LCD Driver Series
DI[2]
Y1 (0)
Y3 (0)
Y5 (0)
…
Y115 (0)
Y117 (0)
Y119 (0)
DI[3]
Y1 (1)
Y3 (1)
Y5 (1)
…
Y115 (1)
Y117 (1)
Y119 (1)
DI[0]
Y119 (0)
Y117 (0)
Y115 (0)
…
Y5 (0)
Y3 (0)
Y1 (0)
DI[1]
Y119 (1)
Y117 (1)
Y115 (1)
…
Y5 (1)
Y3 (1)
Y1 (1)
DI[2]
Y118 (0)
Y116 (0)
Y114 (0)
…
Y4 (0)
Y2 (0)
Y0(0)
DI[3]
Y118 (1)
Y116 (1)
Y114 (1)
…
Y4 (1)
Y2 (1)
Y0(1)
(1): 2nd bit, msb; (0): 1st bit, lsb.
4 Levels Gray Display (1-bit Series Input Mode)
L/R
L
H
EIO1
Output
Input
EIO2
Input
Output
Data
Number of Clocks
Input
240 CLOCK
239 CLOCK
238 CLOCK
…
3 CLOCK
2 CLOCK
1 CLOCK
DI[0]
Y0 (0)*
Y0 (1)*
Y1 (0)
…
Y118 (1)
Y119 (0)
Y119 (1)
DI[1]
x
x
x
x
x
x
x
DI[2]
x
x
x
x
x
x
x
DI[3]
x
x
x
x
x
x
x
DI[0]
Y119 (0)
Y119 (1)
Y118 (0)
…
Y1 (1)
Y0 (0)
Y0 (1)
DI[1]
x
x
x
x
x
x
x
DI[2]
x
x
x
x
x
x
x
DI[3]
x
x
x
x
x
x
x
(1): 2nd bit, msb; (0): 1st bit, lsb. x: Don't care, should be fixed to "H" or "L", avoiding floating.
16 Levels Gray Display (4-bit Parallel Input Mode)
L/R
L
H
EIO1
Output
Input
EIO2
Input
Output
Data
Number of Clocks
Input
120 CLOCK
119 CLOCK
118 CLOCK
…
3 CLOCK
2 CLOCK
1 CLOCK
DI[0]
Y0 (0)*
Y1 (0)
Y2 (0)
…
Y117 (0)
Y118 (0)
Y119 (0)
DI[1]
Y0 (1)*
Y1 (1)
Y2 (1)
…
Y117 (1)
Y118 (1)
Y119 (1)
DI[2]
Y0 (2)*
Y1 (2)
Y2 (2)
…
Y117 (2)
Y118 (2)
Y119 (2)
DI[3]
Y0 (3)*
Y1 (3)
Y2 (3)
…
Y117 (3)
Y118 (3)
Y119 (3)
DI[0]
Y119 (0)
Y118 (0)
Y117 (0)
…
Y2 (0)
Y1 (0)
Y0 (0)
DI[1]
Y119 (1)
Y118 (1)
Y117 (1)
…
Y2 (1)
Y1 (1)
Y0 (1)
DI[2]
Y119 (2)
Y118 (2)
Y117 (2)
…
Y2 (2)
Y1 (2)
Y0 (2)
DI[3]
Y119 (3)
Y118 (3)
Y117 (3)
…
Y2 (3)
Y1 (3)
Y0 (3)
3 CLOCK
2 CLOCK
1 CLOCK
(3): 4th bit, msb; (2): 3rd bit; (1): 2nd bit; (0): 1st bit, lsb.
16 Levels Gray Display (1-bit Series Input Mode)
L/R
EIO1
EIO2
January 20, 2005
Data
Input
Number of Clocks
480 CLOCK
479 CLOCK
14
478 CLOCK
…
V1.10
This specification is subject to change without notice. Please contact sales person for the latest version before use.
KD125
King Billion Electronics Co., Ltd
駿
L
H
Output
Input
Input
Output
億
電
子
股
份
有
限
公
司
LCD Driver Series
DI[0]
Y0 (0)*
Y0 (1)*
Y0 (2)*
…
Y119 (1)
Y119 (2)
Y119 (3)
DI[1]
x
x
x
x
x
x
x
DI[2]
x
x
x
x
x
x
x
DI[3]
x
x
x
x
x
x
x
DI[0]
Y119 (0)
Y119 (1)
Y119(2)
…
Y0 (1)
Y0 (2)
Y0 (3)
DI[1]
x
x
x
x
x
x
x
DI[2]
x
x
x
x
x
x
x
DI[3]
x
x
x
x
x
x
x
(3): 4th bit, msb; (2): 3rd bit; (1) 2nd bit; (0): 1st bit, lsb. x: Don't care, should be fixed to "H" or "L",
avoiding floating.
Common Mode
L/R
Data Transfer Direction
EIO1
EIO2
L
Y119 à Y0
Output
Input
H
Y0 à Y119
Input
Output
Mixed Mode (Common/Segment Mode)
For example: When (SEL2, SEL1, SEL0) = (0, 0, 1), Select the 32 COM/88 SEG MODE, then segment
side of mixed mode.
Black/White Display (4-bit Parallel Input Mode)
L/R
L
H
EIO1
Output
Input
EIO2
Input
Output
Data
Number of Clocks
Input
22 CLOCK
21 CLOCK
20 CLOCK
…
3 CLOCK
2 CLOCK
1 CLOCK
DI[0]
Y0
Y4
Y8
…
Y76
Y80
Y84
DI[1]
Y1
Y5
Y9
…
Y77
Y81
Y85
DI[2]
Y2
Y6
Y10
…
Y78
Y82
Y86
DI[3]
Y3
Y7
Y11
…
Y79
Y83
Y87
DI[0]
Y119
Y115
Y111
…
Y43
Y39
Y35
DI[1]
Y118
Y114
Y110
…
Y42
Y38
Y34
DI[2]
Y117
Y113
Y109
…
Y41
Y37
Y33
DI[3]
Y116
Y112
Y108
…
Y40
Y36
Y32
2 CLOCK
1 CLOCK
Black/White Display (1-bit Series Input Mode)
L/R
EIO1
EIO2
January 20, 2005
Data
Input
Number of Clocks
88 CLOCK
87 CLOCK
86 CLOCK
15
…
3 CLOCK
V1.10
This specification is subject to change without notice. Please contact sales person for the latest version before use.
KD125
King Billion Electronics Co., Ltd
駿
L
H
Output
Input
Input
Output
億
電
子
股
份
有
限
公
司
LCD Driver Series
DI[0]
Y0
Y1
Y2
…
Y85
Y86
Y87
DI[1]
x
x
x
x
x
x
x
DI[2]
x
x
x
x
x
x
x
DI[3]
x
x
x
x
x
x
x
DI[0]
Y119
Y118
Y117
…
Y34
Y33
Y32
DI[1]
x
x
x
x
x
x
x
DI[2]
x
x
x
x
x
x
x
DI[3]
x
x
x
x
x
x
x
x: Don't care, should be fixed to "H" or "L", avoiding floating.
4 Levels Gray Display (4-bit Parallel Input Mode)
L/R
L
H
EIO1
Output
Input
EIO2
Input
Output
Data
Number of Clocks
Input
44 CLOCK
43 CLOCK
42 CLOCK
…
3 CLOCK
2 CLOCK
1 CLOCK
DI[0]
Y0 (0)*
Y2 (0)
Y4 (0)
…
Y82 (0)
Y84 (0)
Y86 (0)
DI[1]
Y0 (1)*
Y2 (1)
Y4 (1)
…
Y82 (1)
Y84 (1)
Y86 (1)
DI[2]
Y1 (0)
Y3 (0)
Y5 (0)
…
Y83 (0)
Y85 (0)
Y87 (0)
DI[3]
Y1 (1)
Y3 (1)
Y5 (1)
…
Y83 (1)
Y85 (1)
Y87 (1)
DI[0]
Y119 (0)
Y117 (0)
Y115 (0)
…
Y37 (0)
Y35 (0)
Y33 (0)
DI[1]
Y119 (1)
Y117 (1)
Y115 (1)
…
Y37 (1)
Y35 (1)
Y33 (1)
DI[2]
Y118 (0)
Y116 (0)
Y114 (0)
…
Y36 (0)
Y34 (0)
Y32 (0)
DI[3]
Y118 (1)
Y116 (1)
Y114 (1)
…
Y36 (1)
Y34 (1)
Y32 (1)
(1): 2nd bit, msb; (0): 1st bit, lsb.
4 Levels Gray Display (1-bit Series Input Mode)
L/R
L
H
EIO1
Output
Input
EIO2
Input
Output
Data
Number of Clocks
Input
176 CLOCK
175 CLOCK
174 CLOCK
…
3 CLOCK
2 CLOCK
1 CLOCK
DI[0]
Y0 (0)*
Y0 (1)*
Y1 (0)
…
Y86 (1)
Y87 (0)
Y87 (1)
DI[1]
X
x
x
x
X
x
x
DI[2]
X
x
x
x
X
x
x
DI[3]
X
x
x
x
X
x
x
DI[0]
Y119 (0)
Y119 (1)
Y118 (0)
…
Y33 (1)
Y32 (0)
Y32 (1)
DI[1]
x
x
x
x
x
x
x
DI[2]
x
x
x
x
x
x
x
DI[3]
x
x
x
x
x
x
x
(1): 2nd bit, msb; (0): 1st bit, lsb. x: Don't care, should be fixed to "H" or "L", avoiding floating.
16 Levels Gray Display (4-bit Parallel Input Mode)
January 20, 2005
16
V1.10
This specification is subject to change without notice. Please contact sales person for the latest version before use.
KD125
King Billion Electronics Co., Ltd
駿
L/R
L
H
EIO1
Output
Input
EIO2
Input
Output
億
電
子
股
份
Data
有
限
公
司
LCD Driver Series
Number of Clocks
Input
88 CLOCK
87 CLOCK
86 CLOCK
…
3 CLOCK
2 CLOCK
1 CLOCK
DI[0]
Y0 (0)*
Y1 (0)
Y2 (0)
…
Y85 (0)
Y86 (0)
Y87 (0)
DI[1]
Y0 (1)*
Y1 (1)
Y2 (1)
…
Y85 (1)
Y86 (1)
Y87 (1)
DI[2]
Y0 (2)*
Y1 (2)
Y2 (2)
…
Y85 (2)
Y86 (2)
Y87 (2)
DI[3]
Y0 (3)*
Y1 (3)
Y2 (3)
…
Y85 (3)
Y86 (3)
Y87 (3)
DI[0]
Y119 (0)
Y118 (0)
Y117 (0)
…
Y34 (0)
Y33 (0)
Y32 (0)
DI[1]
Y119 (1)
Y118 (1)
Y117 (1)
…
Y34 (1)
Y33 (1)
Y32 (1)
DI[2]
Y119 (2)
Y118 (2)
Y117 (2)
…
Y35 (2)
Y33 (2)
Y32 (2)
DI[3]
Y119 (3)
Y118 (3)
Y117 (3)
…
Y35 (3)
Y33 (3)
Y32 (3)
(3): 4th bit, msb; (2): 3rd bit; (1): 2nd bit; (0): 1st bit, lsb.
16 Levels Gray Display (1-bit Series Input Mode)
L/R
L
H
EIO1
Output
Input
EIO2
Input
Output
Data
Number of Clocks
Input
352 CLOCK
351 CLOCK
350 CLOCK
…
3 CLOCK
2 CLOCK
1 CLOCK
DI[0]
Y0 (0)*
Y0 (1)*
Y0 (2)*
…
Y87 (1)
Y87 (2)
Y87 (3)
DI[1]
x
x
X
x
x
x
x
DI[2]
x
x
X
x
x
x
x
DI[3]
x
x
X
x
x
x
x
DI[0]
Y119 (0)
Y119 (1)
Y119(2)
…
Y32 (1)
Y32 (2)
Y32 (3)
DI[1]
x
x
x
x
x
x
x
DI[2]
x
x
x
x
x
x
x
DI[3]
x
x
x
x
x
x
x
(3): 4th bit, msb; (2): 3rd bit; (1) 2nd bit; (0): 1st bit, lsb. x: Don't care, should be fixed to "H" or "L",
avoiding floating.
Common Side of Mixed Mode
L/R
Data Transfer Direction
EIO1
EIO2
L
Y119 à Y88
Seg_end output
Input
H
Y0 à Y119
Input
Seg_end output
January 20, 2005
17
V1.10
This specification is subject to change without notice. Please contact sales person for the latest version before use.
King Billion Electronics Co., Ltd
駿
億
電
子
股
份
有
限
公
司
KD125
LCD Driver Series
8. Multi-Chip Connection
January 20, 2005
18
V1.10
This specification is subject to change without notice. Please contact sales person for the latest version before use.
King Billion Electronics Co., Ltd
駿
億
電
子
股
份
有
限
公
司
KD125
LCD Driver Series
9. Timing Chart of Cascade Connection
January 20, 2005
19
V1.10
This specification is subject to change without notice. Please contact sales person for the latest version before use.
King Billion Electronics Co., Ltd
駿
億
電
子
股
份
有
限
公
司
KD125
LCD Driver Series
10. Common Connection
January 20, 2005
20
V1.10
This specification is subject to change without notice. Please contact sales person for the latest version before use.
King Billion Electronics Co., Ltd
駿
億
電
子
股
份
有
限
公
司
KD125
LCD Driver Series
11. Mixed Mode Connection
January 20, 2005
21
V1.10
This specification is subject to change without notice. Please contact sales person for the latest version before use.
King Billion Electronics Co., Ltd
駿
January 20, 2005
億
電
子
股
份
22
有
限
公
司
KD125
LCD Driver Series
V1.10
This specification is subject to change without notice. Please contact sales person for the latest version before use.
KD125
King Billion Electronics Co., Ltd
駿
億
電
子
股
份
有
限
公
司
LCD Driver Series
12. Precautions
Precautions when connecting or disconnecting the power supply
This IC has a high-voltage LCD driver, so a high current that may flow if voltage is supplied to the LCD drive power
supply while the logic system power supply is floating may permanently damage it. The details are as follows, when
connecting the power supply, connect the LCD drive power after connecting the logic system power.
Furthermore, when disconnecting the power, disconnect the logic system power after disconnecting the LCD drive
power and when connecting the logic power supply, the logic condition of this IC inside is insecure. Therefore
connect the LCD drive power supply after resetting logic condition of this IC inside on /DISPOFF function.
After that, cancel the /DISPOFF function after the LCD drive power supply has become stable. Furthermore, when
disconnecting the power, set the LCD drive output pins to level Vss on /DISPOFF function. Then disconnect the
logic system power after disconnecting the LCD drive power.
When connecting the power supply, follow the recommended sequence shown here
13. LCD Waveform
Frame Period
Frame Period
//
FR
//
LP
January 20, 2005
...
...
23
V1.10
This specification is subject to change without notice. Please contact sales person for the latest version before use.
King Billion Electronics Co., Ltd
駿
億
電
子
股
份
有
限
公
司
KD125
LCD Driver Series
Type B LCD COM and SEG waveform
LV5
LV4
LV3
LV2
LV1
GND
SEG Waveform
1st Frame
2nd Frame
3rd Frame
LV5
LV4
LV3
LV2
LV1
GND
COM Waveform
Type B LCD COM/SEG waveform
LV5
LV4
LV3
LV2
LV1
GND
SEG Waveform
1st Frame
January 20, 2005
2nd Frame
24
3rd Frame
V1.10
This specification is subject to change without notice. Please contact sales person for the latest version before use.
KD125
King Billion Electronics Co., Ltd
駿
億
電
子
股
份
有
限
公
司
LCD Driver Series
14. Pin Locations
1 CMSG[31]
2 CMSG[30]
3 CMSG[29]
4 CMSG[28]
5 CMSG[27]
6 CMSG[26]
7 CMSG[25]
8 CMSG[24]
9 CMSG[23]
10 CMSG[22]
11 CMSG[21]
12 CMSG[20]
13 CMSG[19]
14 CMSG[18]
15 CMSG[17]
16 CMSG[16]
17 CMSG[15]
18 CMSG[14]
19 CMSG[13]
20 CMSG[12]
21 CMSG[11]
22 CMSG[10]
23 CMSG[9]
24 CMSG[8]
25 CMSG[7]
26 CMSG[6]
27 CMSG[5]
28 CMSG[4]
29 CMSG[3]
30 CMSG[2]
31 CMSG[1]
32 CMSG[0]
33 VSSA
34 LVL1
35 LVL2
36 LVL3
37 LVL4
38 LVL5
January 20, 2005
X=
X=
X=
X=
X=
X=
X=
X=
X=
X=
X=
X=
X=
X=
X=
X=
X=
X=
X=
X=
X=
X=
X=
X=
X=
X=
X=
X=
X=
X=
X=
X=
X=
X=
X=
X=
X=
X=
-3618 Y=
-3618 Y=
-3618 Y=
-3618 Y=
-3618 Y=
-3618 Y=
-3618 Y=
-3618 Y=
-3618 Y=
-3618 Y=
-3264.9 Y=
-3169.9 Y=
-3074.9 Y=
-2979.9Y=
-2884.9 Y=
-2789.9 Y=
-2694.9 Y=
-2599.9 Y=
-2504.9 Y=
-2409.9 Y=
-2314.9 Y=
-2219.9 Y=
-2124.9 Y=
-2029.9 Y=
-1934.9 Y=
-1839.9 Y=
-1744.9 Y=
-1649.9 Y=
-1554.9 Y=
-1459.9 Y=
-1364.9 Y=
-1269.9 Y=
-1101.4 Y=
-1001.1 Y=
-906.12 Y=
-811.12 Y=
-716.12 Y=
-621.12 Y=
420
325
230
135
39.5
-55.5
-151
-246
-341
-436
-819
-819
-819
-819
-819
-819
-819
-819
-819
-819
-819
-819
-819
-819
-819
-819
-819
-819
-819
-819
-819
-819
-819
-819
-819
-819
-819
-819
79CMSG[109]
80CMSG[108]
81CMSG[107]
82CMSG[106]
83CMSG[105]
84CMSG[104]
85CMSG[103]
86CMSG[102]
87CMSG[101]
88CMSG[100]
89CMSG[99]
90CMSG[98]
91CMSG[97]
92CMSG[96]
93CMSG[95]
94CMSG[94]
95CMSG[93]
96CMSG[92]
97CMSG[91]
98CMSG[90]
99CMSG[89]
100CMSG[88]
101CMSG[87]
102CMSG[86]
103CMSG[85]
104CMSG[84]
105CMSG[83]
106CMSG[82]
107CMSG[81]
108CMSG[80]
109CMSG[79]
110CMSG[78]
111CMSG[77]
112CMSG[76]
113CMSG[75]
114CMSG[74]
115CMSG[73]
116CMSG[72]
25
X=
X=
X=
X=
X=
X=
X=
X=
X=
X=
X=
X=
X=
X=
X=
X=
X=
X=
X=
X=
X=
X=
X=
X=
X=
X=
X=
X=
X=
X=
X=
X=
X=
X=
X=
X=
X=
X=
3618.05 Y=
3618.05 Y=
3618.05 Y=
3618.05 Y=
3618.05 Y=
3618.05 Y=
3618.05 Y=
3618.05 Y=
3618.05 Y=
3618.05 Y=
3219.9 Y=
3124.9 Y=
3029.9 Y=
2934.9 Y=
2839.9 Y=
2744.9 Y=
2649.9 Y=
2554.9 Y=
2459.9 Y=
2364.9 Y=
2269.9 Y=
2174.9 Y=
2079.9 Y=
1984.9 Y=
1889.9 Y=
1794.9 Y=
1699.9 Y=
1604.9 Y=
1509.9 Y=
1332.9 Y=
1237.9 Y=
1142.9 Y=
1047.9 Y=
952.9 Y=
857.9 Y=
762.9 Y=
667.9 Y=
572.9 Y=
-437
-342
-247
-152
-57
38
133
228
323
418
819
819
819
819
819
819
819
819
819
819
819
819
819
819
819
819
819
819
819
819
819
819
819
819
819
819
819
819
V1.10
This specification is subject to change without notice. Please contact sales person for the latest version before use.
KD125
King Billion Electronics Co., Ltd
駿
39 LVP
X=
40 LCAP1A X=
41 LCAP1B X=
42 LCAP2A X=
43 LCAP2B X=
44 LCAP3A X=
45 LCAP4A X=
46 LCAP5A X=
47 LGS1
X=
48 LGS2
X=
49 VAG
X=
50 VDD
X=
51 RSTN
X=
52 DI[3]
X=
53 DI[2]
X=
54 DI[1]
X=
55 DI[0]
X=
56 P_SN
X=
57 L_R
X=
58 EIO1
X=
59 EIO2
X=
60 CLK32
X=
61 XCK
X=
62 XDISPOFF X=
63 LP
X=
64 FR
X=
65 XCS
X=
66 SDI
X=
67 SCLK
X=
68 GND
X=
69 CMSG[119]X=
70 CMSG[118]X=
71 CMSG[117]X=
72 CMSG[116]X=
73 CMSG[115]X=
74 CMSG[114]X=
75 CMSG[113]X=
76 CMSG[112]X=
77 CMSG[111]X=
78 CMSG[110]X=
January 20, 2005
億
-526.12 Y=
-431.12 Y=
-336.12 Y=
-241.12 Y=
-146.12 Y=
-51.12Y=
43.88Y=
138.88 Y=
233.88 Y=
328.88 Y=
423.88 Y=
525.13 Y=
620.13 Y=
715.13 Y=
810.13 Y=
906.38 Y=
1000.13Y=
1095.13Y=
1190.13Y=
1285.13Y=
1380.13Y=
1480.6 Y=
1575.6 Y=
1670.6 Y=
1765.6 Y=
1860.6 Y=
1955.6 Y=
2050.6 Y=
2145.6 Y=
2240.6 Y=
2409.1 Y=
2504.1 Y=
2599.1 Y=
2694.1 Y=
2789.1 Y=
2884.1 Y=
2979.1 Y=
3074.1 Y=
3169.1 Y=
3264.1 Y=
電
子
-819
-819
-819
-819
-819
-819
-819
-819
-819
-819
-819
-819
-819
-819
-819
-819
-819
-819
-819
-819
-819
-819
-819
-819
-819
-819
-819
-819
-819
-819
-819
-819
-819
-819
-819
-819
-819
-819
-819
-819
股
份
有
限
117CMSG[71]
118CMSG[70]
119CMSG[69]
120CMSG[68]
121CMSG[67]
122CMSG[66]
123CMSG[65]
124CMSG[64]
125CMSG[63]
126CMSG[62]
127CMSG[61]
128CMSG[60]
129CMSG[59]
130CMSG[58]
131CMSG[57]
132CMSG[56]
133CMSG[55]
134CMSG[54]
135CMSG[53]
136CMSG[52]
137CMSG[51]
138CMSG[50]
139CMSG[49]
140CMSG[48]
141CMSG[47]
142CMSG[46]
143CMSG[45]
144CMSG[44]
145CMSG[43]
146CMSG[42]
147CMSG[41]
148CMSG[40]
149CMSG[39]
150CMSG[38]
151CMSG[37]
152CMSG[36]
153CMSG[35]
154CMSG[34]
155CMSG[33]
156CMSG[32]
X=
X=
X=
X=
X=
X=
X=
X=
X=
X=
X=
X=
X=
X=
X=
X=
X=
X=
X=
X=
X=
X=
X=
X=
X=
X=
X=
X=
X=
X=
X=
X=
X=
X=
X=
X=
X=
X=
X=
X=
26
公
司
477.9 Y=
382.9 Y=
287.9 Y=
192.9 Y=
97.9 Y=
2.9 Y=
-92.1 Y=
-187.1 Y=
-282.1 Y=
-377.1 Y=
-472.1 Y=
-567.1 Y=
-662.1 Y=
-757.1 Y=
-852.1 Y=
-947.1 Y=
-1042.1 Y=
-1137.1 Y=
-1232.1 Y=
-1327.1 Y=
-1422.1 Y=
-1517.1 Y=
-1612.1 Y=
-1707.1 Y=
-1802.1 Y=
-1897.1 Y=
-1992.1 Y=
-2087.1 Y=
-2182.1 Y=
-2277.1 Y=
-2372.1 Y=
-2467.1 Y=
-2562.1 Y=
-2657.1 Y=
-2752.1 Y=
-2847.1 Y=
-2942.1 Y=
-3037.1 Y=
-3132.1 Y=
-3227.1 Y=
LCD Driver Series
819
819
819
819
819
819
819
819
819
819
819
819
819
819
819
819
819
819
819
819
819
819
819
819
819
819
819
819
819
819
819
819
819
819
819
819
819
819
819
819
V1.10
This specification is subject to change without notice. Please contact sales person for the latest version before use.
KD125
King Billion Electronics Co., Ltd
駿
億
電
子
股
份
有
限
公
司
LCD Driver Series
15. Absolute Maximum Rating
Item
Sym.
Rating
Condition
Supply Voltage
VDD
-0.5V ~ 4V
Input Voltage
VIN
-0.5V ~ VDD+0.5V
Output Voltage
VO
-0.5V ~ VDD+0.5V
Operating Temperature
TOP
0°C ~ 70°C
Storage Temperature
TST
-50°C ~ 100°C
16. Recommended Operating Conditions
Item
Sym.
Rating
Supply Voltage
VDD
2.4V ~ 4V
LCD operating voltage
VV5
< 16V
Input Voltage
VIH
0.9 VDD ~ VDD
VIL
0.0V ~ 0.1VDD
Operating Temperature
TOP
0°C ~ 70°C
Storage Temperature
TST
-50°C ~ 100°C
January 20, 2005
27
Condition
V1.10
This specification is subject to change without notice. Please contact sales person for the latest version before use.
KD125
King Billion Electronics Co., Ltd
駿
億
電
子
股
份
有
限
公
司
LCD Driver Series
17. AC/DC Characteristics
Test Condition: Temperature: 25℃, VDD: 3V±10%
Parameters
Supply Current
Standby mode current
Symbol Min. Typ. Max.
IDD
300
ISTBY
Input high voltage
VIH
Input low voltage
VIL
Input leakage current
IIL
Unit
350
μA
1
μA
0.8
0.2
20
Condition
VDD
Input pins
VDD
Input pins
μA
VIL = GND, VDD
Input pins Threshold=2/3VDD(input
Input hysteresis width
VHYS
1/3
VDD
from low to high)
Threshold=1/3VDD(input from high
to low)
Output source current
IOH
2.0
mA
RD[7..0], VOL=2.0V
Output sink current
IOL
2.0
mA
RD[7..0], VOL=0.4V
18. Application Circuit for module
January 20, 2005
28
V1.10
This specification is subject to change without notice. Please contact sales person for the latest version before use.
KD125
King Billion Electronics Co., Ltd
駿
V4
司
LCD Driver Series
V3
C2
V2
C2
V1
C2
LCAP2B
LVP
V5
V3
V4
SEG[239:120]
V2
C1
V1
C1
LCAP1A
LVP
C1
LCAP2A
V5
C1
LCAP3A
V4
C1
LCAP4A
V3
LCAP5A
SEG[119:0]
LCAP1B
January 20, 2005
29
Y[119:0]
VAG
EIO3
VDD
VDD
XCK
DI[3:0]
LCAP2B
LCAP1B
FR
V1
LP
V2
XDISPOFF
XGCK
V3
EIO1
V4
EIO2
V5
L/R
P/SN
LGS1
XCK
LGS2
DI[3:0]
LVP
FR
LP
XIDSPOFF
XGCK
LCAP5A
LCAP4A
SCLK
SDI
XCS
SCLK
SDI
XCS1
LCAP3A
LCAP2A
LCAP1A
Y[119:0]
LVP
VAG
LGS2
LGS1
VDD
VDD
XCK
DI[3:0]
EIO1
EIO2
L/R
P/SN
XCK
DI[3:0]
GND
LCAP2B
LCAP1B
FR
LP
XDISPOFF
XGCK
FR
LP
XIDSPOFF
XGCK
LCAP5A
SCLK
SDI
XCS1
SCLK
SDI
XCS
LCAP3A
LCAP4A
LCAP2A
LCAP1A
GND
LCAP1A
C2
V5
LCAP2A
C2
V4
V2
LCAP3A
V5
V4
LCAP4A
公
120 COM X 240 SEG
V3
LCAP5A
限
C2
V1
LCAP1B
有
C2
LGS1
V5
LCAP2B
I37
R1
LGS2
XGCK
V3
XDISPOFF
V2
LP
FR
V1
XCS
SDI
SCLK
份
V2
XCS0
SDI
SCLK
LGS1
股
V1
FLM
XGCK
XIDSPOFF
LP
FR
LGS2
LVP
I38
R2
LVP
DI[3:0]
XCK
P/SN
L/R
EIO2
EIO1
子
C2
VAG
DI[3:0]
XCK
VDD
VDD
電
COM[119:0]
Y[119:0]
FROM LCD CONTROL
億
V1.10
This specification is subject to change without notice. Please contact sales person for the latest version before use.
KD125
King Billion Electronics Co., Ltd
駿
億
電
子
股
份
有
限
公
司
LCD Driver Series
COM[111:0]
Y[119:0]
FROM LCD CONTROL
SEG[7:0],COM[111:0]
FLM
XGCK
XIDSPOFF
LP
FR
XCS0
SDI
SCLK
LGS2
LGS1
V5
V4
XGCK
XDISPOFF
LP
FR
XCS
SDI
SCLK
V3
V2
V1
LGS2
I37
R1
DI[3:0]
XCK
P/SN
L/R
EIO2
EIO1
LVP
I38
R2
LVP
DI[3:0]
XCK
VDD
VDD
112 COM X 128 SEG
C2
VAG
C2
C2
LGS1
V5
C2
V4
C2
V3
C2
V2
C2
V1
C2
LCAP2B
LCAP2B
LCAP1B
LCAP1B
C1
SEG[127:8]
LVP
LCAP1A
V5
C1
LCAP1A
Y[119:0]
LVP
VAG
LGS2
V5
LGS1
V4
EIO2
VDD
VDD
XCK
DI[3:0]
EIO1
EIO2
L/R
P/SN
XCK
DI[3:0]
LCAP2B
FR
LP
XDISPOFF
XGCK
FR
LP
XIDSPOFF
XGCK
LCAP5A
LCAP1B
LCAP4A
SCLK
SDI
XCS1
SCLK
SDI
XCS
LCAP3A
LCAP1A
LCAP2A
GND
LCAP2A
V4
C1
LCAP2A
V2
V3
C1
V1
LCAP4A
LCAP3A
V2
V3
LCAP3A
V1
LCAP4A
SEG[7:0]
LCAP5A
19. Updated Record
Version
V1.0
Date
Update History
12/9/2004 First release version
Modify setup-up voltage circuits and application circuit. Add a capacitor
V1.1
19/1/2005 between LGS1 and GND.
January 20, 2005
30
V1.10
This specification is subject to change without notice. Please contact sales person for the latest version before use.