SITRONIX ST8009

ST
ST8009
96 Output LCD Common/ Segment Driver IC
Notice: Sitronix Technology Corp. reserves the right to change the contents in this document without prior notice.
specification. Some parameters are subject to change.
1. DESCRIPTION
This is not a final
Low-power liquid crystal display power supply circuit
The ST8009 is a 96-output segment/common driver IC
equipped internally.
suitable for driving small/medium scale dot matrix LCD
Booster circuit (with Boost ratio of 2X/3X/4X/5X/6X)
panels, and is used in PDA or electronic dictionary.
Regulator circuit
The ST8009 is good as a segment driver, a common
Follower circuit
Package: 124-pin COB.
driver or a common/segment driver, and it can create
low power consumption, high-resolution LCD. The
ST8009 have eight modes can selected to set
(Segment mode)
Shift clock frequency
common and segment numbers by selecting register.
The ST8009 also have analog DC/DC converter to
- 20 MHz (MAX.): VDD = +5.0 ± 0.5 V
use.
- 15 MHz (MAX.): VDD = +3.0 to + 4.5 V
- 12 MHz (MAX.): VDD = +2.5 to + 3.0 V
2. FEATURES
Adopts a data bus system
Number of LCD drive outputs: 96
4-bit parallel / serial input modes are selectable by
Supply voltage for LCD drive (VOUT): Max +16V
programmable.
Supply voltage for logic system (VDD): +2.5 ~ +5.5V
Automatic transfer function of an enable signal
Low power consumption and low output impedance
Automatic counting function which, in the chip
Display duty selectable by internal select register
selection mode, causes the internal clock to be
DU2,DU1,DU0
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
Abundant command functions
stopped by automatically counting 16、32、48、64、
DUTY
--1/16
1/32
1/48
1/64
1/80
1/96
1/96
80、96 bits of input data
Line latch circuits are reset when XDISPOFF active
(Common mode)
Shift clock frequency: 4 MHz (MAX.)
Built-in X-bit shift register
Available in a single mode
CS0 CSX Single mode
LCD bias set, electronic volume, VSS voltage
regulation internal resistor ratio and booster
CSX CS0 Single mode
frequency.
PS:X=15、31、47、63、79、95
The above 4 shift directions are register selectable
All Functions have initial value, user can set by
Shift register circuits are reset when XDISPOFF
programmed.
active
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3. PAD ARRANGEMENT
Chip size: 5070.0(um) x1790.0 (um)
Pad size：80 (um) x80 (um)
Pad pin pitch: 100 (um) ~ 140 (um)
Origin : chip center (0,0)
Chip Thickness：19 mil
Substrate Connect to VSS.
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4. PAD CONFIGURATION
Pad No.
Function
1
CS[86]
2450
2
CS[87]
3
V1.1
X
Y
Pad No.
Function
810
33
SCLK
-850
810
2310
810
34
FR
-950
810
CS[88]
2180
810
35
LP2
-1050
810
4
CS[89]
2060
810
36
LP1
-1150
810
5
CS[90]
1950
810
37
VSS
-1250
810
6
CS[91]
1850
810
38
VDD
-1350
810
7
CS[92]
1750
810
39
CS[0]
-1450
810
8
CS[93]
1650
810
40
CS[1]
-1550
810
9
CS[94]
1550
810
41
CS[2]
-1650
810
10
CS[95]
1450
810
42
CS[3]
-1750
810
11
VOUT
1350
810
43
CS[4]
-1850
810
12
CAP3P
1250
810
44
CS[5]
-1950
810
13
CAP1N
1150
810
45
CS[6]
-2060
810
14
CAP1P
1050
810
46
CS[7]
-2180
810
15
CAP2P
950
810
47
CS[8]
-2310
810
16
CAP2N
850
810
48
CS[9]
-2450
810
17
CAP4P
750
810
49
CS[10]
-2450
680
18
CAP5P
650
810
50
CS[11]
-2450
560
19
V0
550
810
51
CS[12]
-2450
450
20
V1
450
810
52
CS[13]
-2450
350
21
V2
350
810
53
CS[14]
-2450
250
22
V3
250
810
54
CS[15]
-2450
150
23
V4
150
810
55
CS[16]
-2450
50
24
ED[3]
50
810
56
CS[17]
-2450
-50
25
ED[2]
-50
810
57
CS[18]
-2450
-150
26
ED[1]
-150
810
58
CS[19]
-2450
-250
27
ED[0]
-250
810
59
CS[20]
-2450
-350
28
EIO1
-350
810
60
CS[21]
-2450
-450
29
EIO2
-450
810
61
CS[22]
-2450
-560
30
XCK
-550
810
62
CS[23]
-2450
-680
31
XDISPOFF
-650
810
63
CS[24]
-2450
-810
32
SID
-750
810
64
CS[25]
-2310
-810
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Pad No.
Function
65
CS[26]
-2180
66
CS[27]
67
V1.1
X
Y
Pad No.
Function
Function
-810
98
CS[59]
1150
-810
-2060
-810
99
CS[60]
1250
-810
CS[28]
-1950
-810
100
CS[61]
1350
-810
68
CS[29]
-1850
-810
101
CS[62]
1450
-810
69
CS[30]
-1750
-810
102
CS[63]
1550
-810
70
CS[31]
-1650
-810
103
CS[64]
1650
-810
71
CS[32]
-1550
-810
104
CS[65]
1750
-810
72
CS[33]
-1450
-810
105
CS[66]
1850
-810
73
CS[34]
-1350
-810
106
CS[67]
1950
-810
74
CS[35]
-1250
-810
107
CS[68]
2060
-810
75
CS[36]
-1150
-810
108
CS[69]
2180
-810
76
CS[37]
-1050
-810
109
CS[70]
2310
-810
77
CS[38]
-950
-810
110
CS[71]
2450
-810
78
CS[39]
-850
-810
111
CS[72]
2450
-680
79
CS[40]
-750
-810
112
CS[73]
2450
-560
80
CS[41]
-650
-810
113
CS[74]
2450
-450
81
CS[42]
-550
-810
114
CS[75]
2450
-350
82
CS[43]
-450
-810
115
CS[76]
2450
-250
83
CS[44]
-350
-810
116
CS[77]
2450
-150
84
CS[45]
-250
-810
117
CS[78]
2450
-50
85
CS[46]
-150
-810
118
CS[79]
2450
50
86
CS[47]
-50
-810
119
CS[80]
2450
150
87
CS[48]
50
-810
120
CS[81]
2450
250
88
CS[49]
150
-810
121
CS[82]
2450
350
89
CS[50]
250
-810
122
CS[83]
2450
450
90
CS[51]
350
-810
123
CS[84]
2450
560
91
CS[52]
450
-810
124
CS[85]
2450
680
92
CS[53]
550
-810
93
CS[54]
650
-810
94
CS[55]
750
-810
95
CS[56]
850
-810
96
CS[57]
950
-810
97
CS[58]
1050
-810
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ST8009
5. PIN DESCRIPTION
V1.1
SYMBOL
I/O
DESCRIPTION
No of Num
CS0~CS95
O
LCD drive output
96
V0~V4
P
Power supply for LCD drive
5
VDD
P
Power supply for logic system (+2.5 to +5.5 V)
1
EIO2, EIO1
I/O
DI0~DI3
I
Display data input at segment mode
4
XCK
I
Clock input for taking display data at segment mode
1
XDISPOFF
I
Control input for output of ground level
1
LP1
I
Latch pulse input for display data at segment mode
1
LP2
I
Shift clock input for shift register at common mode
1
FR
I
AC-converting signal input for LCD drive waveform
1
VSS
P
Ground (0 V)
1
CAP1-
O
CAP1+
O
CAP2-
O
CAP2+
O
CAP3+
O
CAP4+
O
CAP5+
O
VOUT
O
SID
I
The command data. See Figure1
1
SCLK
I
The serial clock input. See Figure1
1
Input/output for chip selection at segment mode and FLM input output
function at com/seg mix mode or common mode
DC/DC voltage converter. Connect a capacitor between this terminal
and the CAP2- terminal.
DC/DC voltage converter. Connect a capacitor between this terminal
and the CAP1- terminal.
DC/DC voltage converter. Connect a capacitor between this terminal
and the CAP2- terminal.
DC/DC voltage converter. Connect a capacitor between this terminal
and the CAP2- terminal.
DC/DC voltage converter. Connect a capacitor between this terminal
and the CAP1- terminal.
DC/DC voltage converter. Connect a capacitor between this terminal
and the CAP2- terminal.
2
1
1
1
1
1
1
DC/DC voltage converter. Connect a capacitor between this terminal
and the CAP1- terminal.
DC/DC voltage converter. Connect a capacitor between this terminal
and VSS.
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6. BLOCK DIAGRAM
V1.1
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7. INPUT/OUTPUT CIRCUITS
V DD
I
T o In te rn a l C irc u it
A p p lic a b le P in s
D I3 ~ D I0 ,
X D IS P O F F , L P 1 ,L P 2 , F R
S C L K ,S ID
V s s (0 V )
Input Circuit (1)
V
DD
To Internal
Circuit
I/O
Control Signal
Vss (0V)
Vss (0V)
V DD
Output Signal
Application Pins
EIO
1
, EIO
2
Control Signal
Vss (0V)
Input/Output Circuit
V1.1
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8. PIN FUNCTIONAL DESCRIPTION
8.1 Pin Functions
(Segment mode)
SYMBOL
FUNCTION
VDD
Logic system power supply pin, connected to +2.5 to +5.5 V.
VSS
Ground pin, connected to 0 V.
When the internal power supply circuit turns on
The internal power supply circuit will produce the LCD bias voltage set( V0 ~ V4 ), and those
V0 , V1
V2 , V3
V4
voltages are setting by the “LCD Bias Set” register.
When the internal power supply circuit turns off
Supply the bias voltages set by a resistor divider externally , and had better use follower circuit to
hold those voltages.
Ensure that voltages are set such that V0 ≧V1 ≧V2 ≧V3 ≧V4 ≧VSS
Input pins for display data
In 4-bit parallel input mode, connect data to the 4 pins, DI3-DI0.
DI3~DI0
In serial input mode, connect data to the DI0 pin, and DI3-DI1 must be connected to VSS .
Refer to "RELATIONSHIP BETWEEN THE DISPLAY DATA AND LCD DRIVE OUTPUT
PINS" in Functional Operations.
LP1
XCK
Latch pulse input pin for display data
Data is latched at the falling edge of the clock pulse.
Clock input for taking display data at segment mode
The switch for turn on or turn off the LCD display
The input signal is level-shifted from logic voltage level to LCD drive voltage level, and controls the
LCD drive circuit.
When set to VSS level "L", the LCD drive output pins (CS0-CS95) are set to level VSS.
XDISPOFF
When set to "L", the contents of the line latch are reset, but the display data are read in the
data latch regardless of the condition of XDISPOFF. When the XDISPOFF function is canceled,
the driver outputs non-select level (V2 or V3), then outputs the contents of the data latch at the
next falling edge of the LP. At that time, if XDISPOFF removal time does not correspond to what is
shown in AC characteristics, it cannot output the reading data correctly.
Table of truth-values is shown in "TRUTH TABLE" in Functional Operations.
AC signal input pin for LCD drive waveform
The input signal is level-shifted from logic voltage level to LCD drive voltage level, and controls the
LCD drive circuit.
FR
Normally it inputs a frame inversion signal.
The LCD drive output pins' output voltage levels can be set using the line latch output signal and
the FR signal.
Table of truth-values is shown in "TRUTH TABLE" in Functional Operations.
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Input/output pins for chip selection.
When L/R register is set ‘0’ , EIO1 is set for output, and EIO2 is set for input(connect to VSS).
When L/R register is set ‘1’, EIO1 is set for input(connect to VSS), and EIO2 is set for output.
EIO1, EIO2
During output, set to "H" while LP • XCK is "H" and after 96 bits of data have been read, set
to "L” for one cycle (from falling edge to failing edge of XCK), after which it returns to "H".
During input, the chip is selected while El is set to "L" after the LP signal is input. The chip is
non-selected after 96 bits of data have been read.
LCD drive output pins
Corresponding directly to each bit of the data latch, one level (V0, V2 ,V3, VSS) is selected and
CS0~CS95
output.
Table of truth values is shown in "TRUTH TABLE" in Functional Operations.
CAP1-
DC/DC voltage converter. Connect a capacitor between this terminal and the CAP2- terminal.
CAP1+
DC/DC voltage converter. Connect a capacitor between this terminal and the CAP1- terminal.
CAP2-
DC/DC voltage converter. Connect a capacitor between this terminal and the CAP2- terminal.
CAP2+
DC/DC voltage converter. Connect a capacitor between this terminal and the CAP2- terminal.
CAP3+
DC/DC voltage converter. Connect a capacitor between this terminal and the CAP1- terminal.
CAP4+
DC/DC voltage converter. Connect a capacitor between this terminal and the CAP2- terminal.
VOUT
DC/DC voltage converter. Connect a capacitor between this terminal and VSS.
SID
The serial command data. See Figure1
SCLK
The serial clock input. See Figure1
(Common mode)
SYMBOL
FUNCTION
VDD
Logic system power supply pin, connected to +2.5 to +5.5 V.
VSS
Ground pin, connected to 0 V.
When the internal power supply circuit turns on
The internal power supply circuit will produce the LCD bias voltage set( V0 ~ V4 ), and those
V0, V1
V2, V3
V4
voltages are setting by the “LCD Bias Set” register.
When the internal power supply circuit turns off
Supply the bias voltages set by a resistor divider externally , and had better use follower circuit to
hold those voltages.
Ensure that voltages are set such that V0 ≧V1 ≧V2 ≧V3 ≧V4 ≧VSS
DI3-DI0
Not used. Connect DI3-DI0 to VSS, not floating.
Shift clock pulse input pin for bi-directional shift register
LP2
* Data is shifted at the falling edge of the clock pulse.
When use gray scale mode, then must use the pin.
When use monochrome mode, then the pin should be shorted to LP1.
XCK
V1.1
Not used
Not let it floating , connect to VSS
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The switch for turn on or turn off the LCD display
The input signal is level-shifted from logic voltage level to LCD drive voltage level, and controls the
LCD drive circuit.
When set to VSS level "L", the LCD drive output pins (CS0-CS95) are set to level VSS.
XDISPOFF
When set to "L”, the contents of the shift register are reset to not reading data. When the
/DISPOFF function is canceled, the driver outputs non-select level (V1 or V4), and the shift data is
read at the next falling edge of the LP. At that time, if /DISPOFF removal time does not correspond
to what is shown in AC characteristics, the shift data is not read correctly.
Table of truth-values is shown in "TRUTH TABLE" in Functional Operations.
AC signal input pin for LCD drive waveform
The input signal is level-shifted from logic voltage level to LCD drive voltage level, and controls the
LCD drive circuit.
FR
Normally it inputs a frame inversion signal.
The LCD drive output pins' output voltage levels can be set using the shift register output signal
and the FR signal.
Table of truth-values is shown in "TRUTH TABLE" in Functional Operations.
LCD drive output pins
CS0 ~CS95
Corresponding directly to each bit of the shift register, one level (V0 V1, V4, or VSS) is selected and
output.
Table of truth-values is shown in "TRUTH TABLE" in Functional Operations.
Shift data Input/output pins for shift register
EIO1 is output pin when L/R is at VSS level “L”, EIO1 is input pin when L/R is at VDD level “H”
When L/R register =’1’, EIO1 is used as input pin, it will be connect to FLM.
When L/R register =’0’, EIO1 is used as output pin, it won’t be connect to FLM.
EIO1, EIO2
EIO2 is input pin when L/R is at VSS level “L”, EIO1 is output pin when L/R is at VDD level “H”
When L/R register =’1’, EIO2 is used as output pin, it won’t be connect to FLM,
When L/R register =’0’, EIO2 is used as input pin, it will be connect to FLM
Refer to “RELATIONSHIP BETWEEN THE DISPLAY DATA AND LCD DRIVE OUTPUT PINS” in
Functional Operations.
CAP1-
DC/DC voltage converter. Connect a capacitor between this terminal and the CAP2- terminal.
CAP1+
DC/DC voltage converter. Connect a capacitor between this terminal and the CAP1- terminal.
CAP2-
DC/DC voltage converter. Connect a capacitor between this terminal and the CAP2- terminal.
CAP2+
DC/DC voltage converter. Connect a capacitor between this terminal and the CAP2- terminal.
CAP3+
DC/DC voltage converter. Connect a capacitor between this terminal and the CAP1- terminal.
CAP4+
DC/DC voltage converter. Connect a capacitor between this terminal and the CAP2- terminal.
VOUT
DC/DC voltage converter. Connect a capacitor between this terminal and VSS.
SID
The serial command data. See Figure1
SCLK
V1.1
The serial clock input. See Figure1
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(common /segment mix mode)
SYMBOL
FUNCTION
VDD
Logic system power supply pin, connected to +2.5 to +5.5 V.
VSS
Ground pin, connected to 0 V.
When the internal power supply circuit turns on :
The internal power supply circuit will produce the LCD bias voltage set( V0 ~ V4 ), and those
V0 , V1
V2 , V3
V4
voltages are setting by the “LCD Bias Set” register.
When the internal power supply circuit turns off :
Supply the bias voltages set by a resistor divider externally , and had better use follower circuit to
hold those voltages.
Ensure that voltages are set such that V0 ≧V1 ≧V2 ≧V3 ≧V4 ≧VSS
Input pins for display data
In 4-bit parallel input mode, input data into the 4 pins, DI3~DI0.
DI3~DI0
In serial input mode, connect data to the DI0 pin, and DI3-DI1 must be connected to VSS .
Refer to "RELATIONSHIP BETWEEN THE DISPLAY DATA AND LCD DRIVE OUTPUT
PINS" in Functional Operations.
XCK
LP1
Clock input pin for taking display data
Data is read at the falling edge of the clock pulse.
Latch pulse input pin for display data
Data is latched at the falling edge of the clock pulse.
Shift clock pulse input pin for bi-directional shift register
LP2
Data is shifted at the falling edge of the clock pulse.
When use gray scale mode, then must use the pin.
When use monochrome mode, then the pin should be shorted to LP1.
The switch for turn on or turn off the LCD display
The input signal is level-shifted from logic voltage level to LCD drive voltage level, and controls the
LCD drive circuit.
When set to VSS level "L", the LCD drive output pins (CS0-CS95) are set to level VSS.
XDISPOFF
When set to "L", the contents of the line latch are reset, but the display data are read in the
data latch regardless of the condition of XDISPOFF. When the XDISPOFF function is canceled,
the driver outputs non-select level (V2 or V3), then outputs the contents of the data latch at the
next falling edge of the LP. At that time, if XDISPOFF removal time does not correspond to what is
shown in AC characteristics, it cannot output the reading data correctly.
Table of truth-values is shown in "TRUTH TABLE" in Functional Operations.
AC signal input pin for LCD drive waveform
The input signal is level-shifted from logic voltage level to LCD drive voltage level, and controls the
FR
LCD drive circuit.
The LCD drive output pins' output voltage levels can be set using the line latch output signal and
the FR signal, and it inputs a frame inversion signal normally.
Table of truth-values is shown in "TRUTH TABLE" in Functional Operations.
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Input/output pins for chip selection
When L/R register is ‘0’, EIO1 is set output, and EIO2 is set for input.
EIO1 : segment chip enable output, as default segment is enabled internally and be non-selected
after 16,32,48,64 or 80 bits of data have been read. Depend on select mode.
ElO2 :common shift data input, no sift data output
When L/R register is ‘1’, EIO1 is set for input, and EIO2 is set for output.
EIO1, EIO2
EIO1 :common shift data, no shift data output
ElO2 : segment chip enable output, as default segment is enabled internally and be non-selected
after 16,32,48,64 or 80 bits of data have been read. Depend on select mode.
During output, set to "H" while LP • XCK is "H" and after 96 bits of data have been read, set
to "L” for one cycle (from falling edge to failing edge of XCK), after which it returns to "H".
During input, the chip is selected while El is set to "L" after the LP signal is input. The chip is
non-selected after 96 bits of data have been read.
LCD drive output pins
CS0 ~CS95
Corresponding directly to each bit of the data latch, one level (V0, V2, V3, VSS) is selected and
output.
Table of truth values is shown in "TRUTH TABLE" in Functional Operations.
CAP1-
DC/DC voltage converter. Connect a capacitor between this terminal and the CAP2- terminal.
CAP1+
DC/DC voltage converter. Connect a capacitor between this terminal and the CAP1- terminal.
CAP2-
DC/DC voltage converter. Connect a capacitor between this terminal and the CAP2- terminal.
CAP2+
DC/DC voltage converter. Connect a capacitor between this terminal and the CAP2- terminal.
CAP3+
DC/DC voltage converter. Connect a capacitor between this terminal and the CAP1- terminal.
CAP4+
DC/DC voltage converter. Connect a capacitor between this terminal and the CAP2- terminal.
VOUT
XCS
SID
SCLK
V1.1
DC/DC voltage converter. Connect a capacitor between this terminal and VSS.
This is the command mode select pin. When XCS=”L” then write command to the LCD, when not
used the command mode then must fixed to VDD . See Figure1
The command data. See Figure1
The serial clock input. See Figure1
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8.2 Functional Operations
8.2.1 TRUTH TABLE
(Segment Mode)
FR
LATCH DATA
/DISPOFF
LCD DRIVE OUTPUT VOLTAGE LEVEL (CS0-CS95)
L
L
H
V3
L
H
H
VSS
H
L
H
V2
H
H
H
V0
X
X
L
VSS
FR
LATCH DATA
/DISPOFF
LCD DRIVE OUTPUT VOLTAGE LEVEL (CS0-CS95)
L
L
H
V4
L
H
H
V0
H
L
H
V1
H
H
H
VSS
X
X
L
VSS
(Common Mode)
NOTES:
L : VSS (0 V), H : VDD (+2.5 to +5.5 V), X : Don't care
"Don't care" should be fixed to "H" or "L", avoiding floating.
There are two kinds of power supply (logic level voltage and LCD drive voltage) for the LCD driver.
Supply regular voltage that is assigned by specification for each power pin.
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8.2.2 RELATIONSHIP BETWEEN THE DISPLAY DATA AND LCD DRIVE OUTPUT PINS
(Segment Mode)
(A) 4-bit Parallel Input Mode
L/R
L
EIO1
EIO2
DATA
INPUT 24 CLOCK 23 CLOCK 22 CLOCK … 3 CLOCK 2 CLOCK 1 CLOCK
Output Input
H
Input
NUMBER OF CLOCKS
Output
DI0
CS0
CS4
CS8
…
CS84
CS88
CS92
DI1
CS1
CS5
CS9
…
CS85
CS89
CS93
DI2
CS2
CS6
CS10
…
CS86
CS90
CS94
DI3
CS3
CS7
CS11
…
CS87
CS91
CS95
DI0
CS95
CS91
CS87
…
CS11
CS7
CS3
DI1
CS94
CS90
CS86
…
CS10
CS6
CS2
DI2
CS93
CS89
CS85
…
CS9
CS5
CS1
DI3
CS92
CS88
CS84
…
CS8
CS4
CS0
(B) Serial Input Mode
L/R
L
H
EIO1
EIO2
Output Input
Input Output
DATA
NUMBER OF CLOCKS
INPUT 120 CLOCK 119 CLOCK 118 CLOCK …
3 CLOCK
2 CLOCK
1 CLOCK
DI0
CS0
CS1
CS2
…
CS93
CS94
CS95
Dl1
X
X
X
X
X
X
X
DI2
X
X
X
X
X
X
X
DI3
X
X
X
X
X
X
X
DI0
CS95
CS94
CS93
…
CS2
CS1
CS0
Dl1
X
X
X
X
X
X
X
DI2
X
X
X
X
X
X
X
DI3
X
X
X
X
X
X
X
(Common Mode)
V1.1
L/R
DATA TRANSFER DIRECTION
EIO1
EIO2
L
CS95 → CS0
Output
Input
H
CS0 → CS95
Input
Output
14/43
2006/11/1
ST8009
MIX MODE(SEGMENT/ COMMON MODE)
When (DU2,DU1,DU0)=(0,1,0) SELECT THE 32 COM / 64 SEGMENT MODE
THEN SEGMENT SIDE OF MIX MODE
(A) 4-bit Parallel Input Mode
L/R
L
H
EIO1
EIO2
DATA
INPUT 16 CLOCK 15 CLOCK 14 CLOCK … 3 CLOCK 2 CLOCK 1 CLOCK
Seg_end Com_FLM
Output
Input
Com_FLM Seg_end
Input
NUMBER OF CLOCKS
Output
DI0
CS0
CS4
CS8
…
CS52
CS56
CS60
Dl1
CS1
CS5
CS9
…
CS53
CS57
CS61
DI2
CS2
CS6
CS10
…
CS54
CS58
CS62
DI3
CS3
CS7
CS11
…
CS55
CS59
CS63
DI0
CS95
CS91
CS87
…
CS43
CS39
CS35
Dl1
CS94
CS90
CS86
…
CS42
CS38
CS34
DI2
CS93
CS89
CS85
…
CS41
CS37
CS33
DI3
CS92
CS88
CS84
…
CS40
CS36
CS32
(B) Serial Input Mode
L/R
L
H
EIO1
EIO2
DATA
NUMBER OF CLOCKS
INPUT 64 CLOCK 63 CLOCK 62CLOCK …
3 CLOCK 2 CLOCK 1 CLOCK
DI0
CS0
CS1
CS2
…
CS61
CS62
CS63
Seg_end
Com_FLM
Dl1
X
X
X
X
X
X
X
Output
Input
DI2
X
X
X
X
X
X
X
DI3
X
X
X
X
X
X
X
DI0
CS95
CS94
CS93
…
CS34
CS33
CS32
Com_FLM
Seg_end
Dl1
X
X
X
X
X
X
X
Input
Output
DI2
X
X
X
X
X
X
X
DI3
X
X
X
X
X
X
X
COMMON SIDE OF MIX MODE
L/R
DATA TRANSFER DIRECTION
EIO1
EIO2
L
CS95 → CS62
Seg_end output
Input
H
CS0 → CS31
Input
Seg_end output
NOTES:
L : VSS (0 V), H : VDD (+2.5 to +5.5 V), X : Don't care
"Don't care" should be fixed to "H" or "L", avoiding floating.
V1.1
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ST8009
8.2.3 Connection examples of plural segment drivers in 4-bits interface( 288 segment )
(a) When the L/R register set “L” level
Top data
Last data
Y95
Y0
Y95
Y0
Y95
Y0
EIO2
EIO1
EIO2
EIO1
EIO2
EIO1
DI0~DI3
FR
LP
XCK
DI0~DI3
FR
LP
XCK
DI0~DI3
FR
LP
XCK
Vss
XCK
LP
FR
DATA
4
PS:Y CS
(b) When the L/R register set “H” level
Top data
Last data
Y0
Y95
Y0
Y95
Y0
Y95
EIO1
EIO2
EIO1
EIO2
EIO1
EIO2
DI0~DI3
FR
LP
XCK
DI0~DI3
FR
LP
XCK
DI0~DI3
FR
LP
XCK
Vss
XCK
LP
FR
DATA
4
PS:Y CS
V1.1
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2006/11/1
ST8009
8.2.4 Timing chart of 4-device cascade connection of segment drivers
FR
LP
XCK
TOP DATA
DI3 - DI0
n*
1
2
LAST DATA
n*
device A
1
2
n*
1
2
device B
n*
device C
1
2
n*
1
2
device D
EI
(device A)
EO
(device A)
EO
(device B)
EO
(device C)
*n = 24 in 4-bit parallel input mode
*n = 96 in serial input mode
V1.1
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ST8009
8.2.5 Connection examples for signal common drivers ( 96 common)
(c) When the L/R register set “L” level
The first
Y95
Y0
EIO2
EIO1
DI0~DI3
FR
LP
XCK
FLM
Vss
LP
FR
Vss
4
PS:Y CS
(d) When the L/R register set “H” level
The first
Y0
Y95
EIO1
EIO2
DI0~DI3
FR
LP
XCK
FLM
Vss
LP
FR
Vss
4
PS:Y CS
V1.1
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2006/11/1
ST8009
8.2.6 Connection examples for plural common/segment (mix mode) drivers
The mix mode is 1/16, 1/32, 1/48, 1/64, 1/80, 1/96 duty mode
(e) When the L/R register set “L” level
Data flow
SEG
COM
Y95
SEG
Yx+1 Yx
EIO2
Y0
EIO1
Y95
Y0
EIO2
EIO1
DI0~DI3
FR
LP
XCK
DI0~DI3
FR
LP
XCK
FLM
XCK
LP
FR
DATA
4
PS:Y CS
(f)
When the L/R register set “H” level
Data flow
SEG
COM
Y0
Yx
SEG
Yx+1 Y95
EIO1
EIO2
Y0
Y95
EIO1
EIO2
DI0~DI3
FR
LP
XCK
DI0~DI3
FR
LP
XCK
FLM
XCK
LP
FR
DATA
4
PS:Y CS
V1.1
19/43
2006/11/1
ST8009
9. PRECAUTIONS
Precautions when connecting or disconnecting
And when connecting the logic power supply, the logic
the power supply
condition of this IC inside is insecure. Therefore
This IC has a high-voltage LCD driver, so a high
connect the LCD drive power supply after resetting
current that may flow if voltage is supplied to the LCD
logic condition of this IC inside on XDISPOFF function.
drive power supply while the logic system power
After that, cancel the XDISPOFF function after the
supply is floating may permanently damage it. The
LCD
details are as follows,
Furthermore, when disconnecting the power, set the
When connecting the power supply, connect the LCD
LCD drive output pins to level VSS on XDISPOFF
drive power after connecting the logic system power.
function. Then disconnect the logic system power after
Furthermore,
disconnecting the LCD drive power.
when
disconnecting
the
power,
drive
power
supply
has
become
disconnect the logic system power after disconnecting
When connecting the power supply, follow the
the LCD drive power
recommended sequence shown here
stable.
VDD
VDD
VSS
VDD
XDISPOFF
VSS
V0
V0
VSS
V1.1
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2006/11/1
ST8009
10. HARDWARE CIRCUIT DESCRIPTION
The LCD Data Bus Interface
The Command Registers Setting Interface
There are two kinds of interfaces for LCD data bus.
The command registers for ST8009 is setting by serial
One is 4-bit parallel data interface and the other is the
interface, SCLK and SID. The timing of serial interface
serial interface. These two kinds of interfaces are
is shown in Fig.1 and Fig.2 Both SCLK and SID must
selected by setting the P/S bit in the “Interface Control
be connected to pull-up resistors.
Selection” register, and see detail in the Table 1. D1~D3
on data bus must be fixed to ground when “1” for P/S bit
START AND STOP CONDITIONS
is selected.
Both SID and SCLK must be kept at high when the bus
Table 1
is not busy, and if SCLK is high at the falling edge of
SID, ST8009 will enter the “Start Condition” for
P/S
Data Bus Mode
1
Parallel Interface(D0~D3)
0
Serial Interface (D0)
beginning to receive command. Otherwise, if SCLK is
high at the rising edge of SID, ST8009 will enter the
“Stop Condition” for finishing command transfer. The
start and stop conditions are illustrated in Fig.3
1
2
4
3
5
6
8
7
9
10
12
11
13
14
15
16
SCLK
SID
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
Fig .1 Write command timing diagram
SDI
SCLK
data line
stable;
data valid
change
of data
allowed
Fig .2 Bit transfer
SDI
SCLK
S
P
START con dition
STOP con dition
Fig .3 Definition of START and STOP conditions
V1.1
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2006/11/1
ST8009
The Power Supply Circuits
The power supply circuits generate the LCD bias for
supply circuits can turn on or turn off the booster circuit,
LCD drive. The power supply circuits are consisted of
voltage regulator circuit, and voltage follower circuit
booster circuit, voltage regulator circuit, and voltage
independently by setting the “Power Control Set”
follower circuit. They only enabled when ST8009 is in
register. Table 2 shows the detail for “Power Control
common mode or common/segment mode. The power
Set” register.
Table2
Bit
Function
Status
“1”
“0”
D2
D1
D0
Booster circuit control bit
ON
OFF
D2
D1
D0
Voltage regulator circuit control bit (V/R circuit)
ON
OFF
D2
D1
D0
Voltage follower circuit control bit (V/F circuit)
ON
OFF
The Step-up Voltage Circuits
By applying the step-up voltage circuit for ST8009, it is
and the 4X step-up application circuit only can be used
possible to produce a voltage which is 2, 3, 4, 5, or 6
when VDD inside +4V. If the voltage of VOUT which is
times of VDD level. Here must notice that the 6X
generated by ST8009 internal booster circuit is almost
step-up application only support for VDD less than
over absolute maximum voltage( +16V ) , we suggest
+2.7V, or the ST8009 may be damaged permanently by
using the external voltage regulator to stabilize the VDD
VOUT over +16V. By the same reason, the 5X step-up
power, or the VOUT may be over the absolute maximum
application only can be used when VDD inside +3.3V,
voltage( +16V ) when the VDD power is not stable.
Fig 4.1
V1.1
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2006/11/1
ST8009
ST8009
ST8009
ST8009
Fig 4.2
* The VDD voltage range must be set properly so that the voltage on VOUT does not exceed the absolute maximum rated value.
The Voltage Regulator Circuit
There is a high-accuracy digital to analog circuit with
controlled by command register alone (without adding
64-level electronic volume function and variable
any external resistors), and making it possible to adjust
resistor inside ST8009. Systems can be constructed
the liquid crystal display brightness. The V0 voltage can
without high-accuracy voltage regulator circuit, if the
be calculated using following equation over the range
voltage on VOUT terminal is much less than absolute
where | V0 | < | VOUT|
maximum voltage.(VREG thermal gradients approximate
VREG is the IC-internal fixed voltage supply, and its
-0.15%/°C). Through using the V0 voltage regulator
voltage at Ta = 25°C is as shown in Table 4.
internal resistors and the electronic volume function,
the liquid crystal power supply voltage V0 can be

V 0 = 1 +


= 1 +

Rb 
 • V EV
Ra 
α 
Rb  
 • 1 −
 • V REG
Ra  
200 


α 

=
−
•
Q
V
1
V


EV
REG 

200 



V0
Internal Rb
Internal Ra
VEV (Construct voltage supply
+ electronic volume)
Fig .5
V1.1
23/43
VSS
2006/11/1
ST8009
Part no.
Equipment Type
ST8009
Internal Power Supply
Thermal Gradient
VREG
–0.15 %/°C
2.1V
Table4
α is set to one of the 64 possible levels by the electronic
volume function depending on the data set in the 6-bit
D5
D4
0
0
0
0
0
0
Table5
D3
D2
α depending on the electronic volume register settings.
Rb/Ra is the V0 voltage regulator internal resistor ratio,
and can be set to 8 different levels through the V0
voltage regulator internal resistor ratio set command.
The Rb/Ra ratio assumes the values shown in Table 6
depending on the 3-bit data settings in the VDD voltage
0
0
0
D0
0
0
1
0
1
0
α
63
62
61
:
:
:
:
1
1
1
1
0
1
2
1
1
1
1
1
0
1
1
1
1
1
1
1
0
V0 voltage regulator internal resistance ratio register
value and (1 + Rb/Ra) ratio (Reference value)
electronic volume register. Table 5 shows the value for
0
0
0
D1
regulator internal resistor ratio register.
Table6
Register
V0 16
15
14
13
12
11
10
9
8
7
6
ST8009
D2
D1
D0
(1) –0.15 %/°C
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
5.0
5.22
5.48
5.76
6.07
6.42
6.81
7.25
Ta=25 ℃ and booster off, regulator, follower on, VOUT=15.6V, VDD=3.3V
0
1
2
3
4
5
1
V0 Voltage Regulator Internal Resistor Ratio
6
set D2, D1, and D0
7
4 7 10 13 16 19 22 25 28 31 34 37 40 43 46 49 52 55 58 61 64
Electronic Volume Register Set
V1.1
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ST8009
The LCD Voltage Generator Circuit
The V0 voltage is produced by a resistive voltage
divider within the IC, and can be produced at the V1, V2,
2. When only the voltage regulator circuit and V/F
circuit are used
V3, and V4 voltage levels required for liquid crystal
driving. Moreover, when the voltage follower changes
the impedance, it provides V1, V2, V3 and V4 to the
VDD
VDD
Externa
l power
supply
liquid crystal drive circuit.
VOUT
CAP3+
CAP4+
CAP1-
CAP5+
CAP1+
Reference Circuit Examples
CAP2-
1. When the step-up circuit, voltage regulating circuit
CAP2+
ST8009
and V/F circuit are used.
(Example with 4x setup-up)
VDD
C1
C1
C1
C1
VDD
VOUT
CAP3+
CAP4+
CAP1-
CAP5+
VOUT
C2
V0
C2
V1
C2
V2
C2
V3
C2
V4
VSS
VSS
CAP1+
CAP2-
3. When only the V/F circuit is used
CAP2+
ST8009
C2
VSS
V0
VDD
VDD
C2
V1
VOUT
C2
V2
CAP3+
CAP4+
C2
V3
CAP1-
CAP5+
C2
V4
CAP1+
VSS
CAP2CAP2+
C2
C2
C2
C2
C2
VSS
V1.1
25/43
V0
ST8009
External
power supply
V0
V1
V2
V3
V4
VSS
2006/11/1
ST8009
* 1. Because the VR terminal input impedance is high,
4. When the built-in power is not use
use short leads and shielded lines.
* 2. C1 and C2 are determined by the size of the LCD
VDD
being driven. Select a value that can stabilize the
VDD
VOUT
CAP3+
CAP4+
CAP1-
CAP5+
liquid crystal drive voltage in the Table 7.
CAP1+
CAP2CAP2+
ST8009
V0
Item
Set value
units
c1
c2
1.0 to 4.7
uF
0.1 to 4.7
uF
Table7
V1
External power sullpy
V2
V3
Following steps are the examples about how to
V4
determine the value for these capacitors:
VSS
• Turn the voltage regulator circuit and voltage follower
VSS
circuit on and supply a voltage to VOUT externally.
5. When the built-in power circuit is used to drive a
• Determine C2 by displaying an LCD pattern with a
liquid crystal panel with heavy load, it is recommended
heavy load (such as horizontal stripes), and select a
to connect an external resistor to stabilize potentials of
value for C2 that can stabilize the liquid crystal drive
V1, V2, V3 and V4 which are output from the built-in
voltages (V1 to V4). Note that all C2 capacitors must
voltage follower.
have the same capacitance value.
• Next, turn on all the power supply circuits to determine
V0
C1
R4
R4
C2
V1
V3
ST8009
V2
V4
R4
VSS
R4
VSS
R4 : 100KΩ ~ 1MΩ, it is recommended to set an
optimum resistance value for R4 according to the
quality of liquid crystal display and the drive
waveform
V1.1
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ST8009
11. INSTRUCTION TABLE
Instruction
Instruction Code
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
M
LR
PS
Software Reset
0
0
0
1
0
0
0
RST
LCD Duty selection
0
0
1
0
0
DU2
DU1
DU0
LCD Bias Set
0
0
1
1
0
B2
B1
B0
Interface control
selection
Description
Interface selection and set
Software reset, when set the register
then the ST8009 will be reset
The register can select the LCD duty
numbers
The register can select the LCD bias
Set the power mode. The register
Power Controller Set
0
1
0
1
0
B
R
F
contain three power circuits can
select (booster, regulator, follow)
Booster Frequency
Set
1
0
0
0
0
F2
F1
F0
Select internal resistor ratio (Ra/Rb)
V0 Voltage Regulator
Internal Resistor Ratio
Set the booster frequency
1
0
0
1
0
Rab2
Rab1
Rab0
1
1
E5
E4
E3
E2
E1
E0
mode
Set
Electronic Volume
Register Set
V1.1
27/43
Set the V0 output voltage electronic
volume register
2006/11/1
ST8009
12. INSTRUCTION DESCRIPTION
The ST8009 identify the data bus signals by a
Start bit
combination between SID and SCLK signals.
Software reset
Interface Control
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
M
LR
PS
Stop bit
The register can control frame direction, common,
segment, common/segment direction and serial or
Start bit
parallel (4-bits) input data Interface.
M: Frame direction control bit
Other
commands
When M=” Height”, the internal frame direction and
external frame direction are the same (normally).
When M=” Low”, the internal frame direction and
external frame direction are adverse.
LR: CS output direction control bit
Stop bit
LR=”H”
CS0
CS95
LR=”L”
CS95
CS0
LCD Duty Selection
PS: Data Interface mode select control bit
D7
D6
D5
D4
D3
D2
D1
D0
0
0
1
0
0
DU2
DU1
DU0
When PS=”Low”, the data input interface is serial
When PS=” Height”, the data input interface is
“LCD Duty Selection” register can set the duty for LCD
parallel (4-bits)
display. Detail in the following column:
Software Reset
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
1
0
0
0
RST
When RST=”1” , do software reset action.
Software reset need “Start bit” at the beginning to start
the action, and also need “Stop bit” at the end to
release the initializing state. It is different to other
DU2
DU1
DU0
COM Num.
SEG Num.
0
0
0
0
96
0
0
1
16
80
0
1
0
32
64
0
1
1
48
48
1
0
0
64
32
1
0
1
80
16
1
1
0
96
0
1
1
1
96
0
commands so can’t set continuously with other
commands.
Note: Other commands can be set continuously with
only one start bit at beginning and stop bit at end:
V1.1
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2006/11/1
ST8009
Booster Frequency Set
LCD Bias Set
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
0
0
1
1
0
B2
B1
B0
1
0
0
0
0
F2
F1
F0
This register can select the voltage bias ratio which is
This register can select one of the booster frequency in
required for the liquid crystal display. There are eight
the following column:
bias modes can be selected in ST8009.
B2
B1
B0
Bias select
0
0
0
1/4
0
0
1
1/5
0
1
0
1/6
0
1
1
1/7
1
0
0
1/8
1
0
1
1/9
1
1
0
1/10
1
1
1
1/11
F2
F1
F0
Booster Frequency
0
0
0
1K
0
0
1
2K
0
1
0
3K
0
1
1
4K
1
0
0
5K
1
0
1
6K
1
1
0
7K
1
1
1
8K
V0 Voltage Regulator Internal Resistor Ratio Set
Power Controller Set
This register can set the V0 voltage regulator internal
D7
D6
D5
D4
D3
D2
D1
D0
0
1
0
1
0
B
R
F
resistor ratio.
This register can enable or disable the power supply
D7
D6
D5
D4
D3
D2
D1
D0
1
0
0
1
0
Rab2
Rab1
Rab0
circuit in ST8009. See details in “The Power Supply
Circuit”.
B
R
F
Status
0
--
--
Booster circuit : off
1
--
-
Booster circuit : on
--
0
--
Regulator circuit : off
--
1
--
Regulator circuit : on
--
--
0
Follower circuit : off
--
--
1
Follower circuit : on
V1.1
29/43
Rab2
Rab1
Rab0
Ra/Rb Ratio
0
0
0
Small
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
Large
2006/11/1
ST8009
Electronic Volume Register Set
Initializing by internal Reset circuit
D7
D6
D5
D4
D3
D2
D1
D0
1
1
E5
E4
E3
E2
E1
E0
An internal reset circuit initializes the ST8009 after
software reset has set. Following are the initial value of
command registers after software reset:
This register can control the V0 in 64 steps of voltage
level to adjust the brightness of the liquid crystal display.
This register had better set under 0xE0. Because when
the value of this register set over 0xE0, the V0 will be
inaccuracy. The inaccurate value of V0 will exceed in
±0.1V when this register set over 0xE0. By this limit, if
we need a higher voltage for V0, we had better set the
bigger value for “V0 Voltage Regulator Internal Resistor
Ratio” register, and then adjust the value of “Electronic
Volume” register to produce the proper voltage for V0
1. Interface control selection
FR: 0
LR: 0
PS: 1
2. LCD Duty selection
The segment mode (96 segments) is selected by
default.
3. LCD Bias Set
1/4 bias is selected by default.
4. Power Controller Set
All the power circuits (booster, regulator and
terminal.
follower) will be turned off by default.
E5
E4
E3
E2
E1
E0
Ra/Rb Ratio
0
0
0
0
0
0
Small
0
0
0
0
0
1
0
0
0
0
1
0
5. Booster Frequency Set
Volume is 1 0 0 by default
6. V0 Voltage Regulator Internal Resistor Ratio Set
Volume is 1 0 0 by default
7. Electronic Volume Register Set
Volume is 1 0 0 0 0 0 by default
1
1
1
1
0
1
1
1
1
1
1
0
1
1
1
1
1
1
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ST8009
Initial Flow
Power on Flow
Software reset
Display off
Interface control selection
Power controller Set
B、F、R turn on
LCD Duty Set
EV set
LCD Bias Set
Wait 10ms
Power controller Set
Display on
EV Set
Power off Flow
Display on
Power controller Set
B、 F、 R turn off
W ait 10ms
Display off
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ST8009
13. ABSOLUTE MAXIMUM RATINGS
PARAMETER
SYMBOL
APPLICABLE PINS
RATING
UNIT
VDD
VDD
2.5~5.5
V
V1
V1
VDD +10~ VDD +0.3
V2
V2
VDD +10~ VDD +0.3
V3
V3
-0.3~ VSS +10
V
V4
V4
-0.3~ VSS +10
V
-0.3 to VDD +0.3
V
-45 to +125
°C
Supply voltage (1)
Supply voltage (2)
Input voltage
Storage temperature
D14-DI0, XCK, FR, EIO1,
VI
EIO2, XDISPOFF
TSTG
NOTE
V
1,2
NOTES:
1. TA = +25 °C
2. The maximum applicable voltage on any pin with respect to VSS (0 V).
14. RECOMMENDED OPERATING CONDITIONS
PARAMETER
SYMBOL
APPLICABLE PINS
MIN.
TYP.
MAX.
UNIT NOTE
Supply voltage (1)
VDD
VDD
+2.5
+5.5
V
Supply voltage (2)
V0
V0
+5.0
+16.0
V
Operating temperature
TOPR
-20
+85
°C
1, 2
NOTES:
1. The applicable voltage on any pin with respect to VSS (0 V).
2. Ensure that voltages are set such that V0 ≧V1 ≧V2 ≧V3 ≧V4 ≧VSS.
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ST8009
15. ELECTRICAL CHARACTERISTICS
15.1 DC Characteristics
(Segment Mode)
PARAMETER
(VSS = 0 V, VDD = +2.5 to +5.5 V, V0 = + 5.0 to +16.0 V, TOPR = -20 to +85°C)
SYMBOL
CONDITIONS
APPLICABLE PINS
MIN.
TYP. MAX. UNIT NOTE
Input "Low" voltage
VIL
DI7-DI0, XCK, FR, EIO1,
Input "High" voltage
VIH
EIO2,XDISPOFF
Output "Low" voltage
VOL
IOL = +0.4 mA
Output "High" voltage
VOH
IOH = -0.4 mA
ILIL
VI = VSS
DI7-DI0, XCK, LP, FR,
-10
µA
ILIH
VI = VDD
EIO1, EIO2,XDISPOFF
+10
µA
1.5
kΩ
Input leakage current
|∆VON|
0.2VDD
0.8VDD
V
+0.4
EIO1, EIO2
VDD-0.4
V
RON
Standby current
ISTB
VSS
5.0
µA
1
IDD1
VDD
2.0
mA
2
IDD2
VDD
7.0
mA
3
I0
V0
0.9
mA
4
Supply current (1)
(Non-selection)
Supply current (2)
(Selection)
Supply current (3)
CS0-CS95
V
Output resistance
=0.5V
V0 = 16V
V
1.0
NOTES:
1. VDD = +5.0 V, V0 = +16.0 V, VI = VSS.
2. VDD = +5.0 V, V0 = +16.0 V, fXCK = 8 MHz, no-load, El = VDD. The input data is turned over by data taking clock
(4-bit parallel input mode).
3. VDD = +5.0 V, V0 = +16.0 V, fXCK = 8MHz, fLP = 19.2 kHz, fFR = 80 Hz, no-load. The input data is turned over by
data taking clock (4-bit parallel input mode).
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ST8009
(Common Mode)
PARAMETER
(VSS = 0 V, VDD = +2.5 to +5.5 V, V0 = +5.0 to +16.0 V, TOPR = -20 to +85 °C)
SYMBOL
CONDITIONS
APPLICABL E PINS
Input "Low" voltage
VIL
DI4-DI0, XCK, FR,
Input "High" voltage
VIH
EIO1, EIO2,
XDISPOFF
Output "Low" voltage
VOL
IOL = +0.4 mA
Output "High" voltage
VOH
IOH = -0.4 mA
MIN. TYP. MAX. UNIT NOTE
0.2VDD
V
V
0.8VDD
+0.4
EIO1, EIO2
VDD-0.4
V
V
DI4-DI0, XCK, FR, P/S,
Input leakage current
ILIL
EIO1, EIO2,
-10.0
µA
+10.0
µA
100
µA
1.5
kΩ
XDISPOFF
ILIH
Input pull-down
VI = VSS
IPD
current
VI = VDD
DI4-DI0,FR,XDISPOFF
XCK, EIO1, EIO2
VI = VDD
Output resistance
RON
|∆VON|=0.5V V0 = 16V
CS0-CS95
1.0
Standby current
ISPD
VSS
5.0
µA
1
Supply current (1)
IDD
VDD
80
µA
2
Supply current (2)
I0
V0
130
µA
2
NOTES:
1. VDD = +5.0 V, V0 = +16.0 V, VI = VSS
2. VDD = +5.0 V, V0 = +16.0 V, fLP =19.2 kHz, fFR = 80 Hz, 1/96 duty operation, no-load.
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ST8009
15.2 AC Characteristics
(Segment Mode 1)
(VSS = 0 V, VDD = +2.5 to +3.0 V, V0 = + 5.0 to +16.0 V, TOPR = -20 10+85 °C)
PARAMETER
SYMBOL
CONDITIONS
MIN
Shift clock period
tWCK
tR,tF ≤ 11ns
Shift clock "H" pulse width
Shift clock "L" pulse width
UNIT
NOTE
125
ns
1
tWCKH
51
ns
tWCKL
51
ns
Data setup time
tDS
30
ns
Data hold time
tDH
40
ns
tWLPH
51
ns
Shift clock rise to latch pulse rise time
tLD
0
ns
Shift clock fall to latch pulse fall time
tSL
51
ns
Latch pulse rise to shift clock rise time
tLS
51
ns
Latch pulse fall to shift clock fall time
tLH
51
ns
Latch pulse fall to shift clock rise time
tLSW
50
ns
Enable setup time
tS
36
ns
Input signal rise time
tR
50
ns
2
Input signal fall time
tF
50
ns
2
DISPOFF removal time
tSD
100
ns
DISPOFF "L" pulse width
tWDL
1.2
µs
Latch pulse "H" pulse width
TYP.
MAX.
Output delay time (1)
tD
CL = 15 pF
78
ns
Output delay time (2)
tPD1, tPD2
CL = 15 pF
1.2
µs
Output delay time (3)
tPD3
CL = 15 pF
1.2
µs
NOTES:
1. Takes the cascade connection into consideration.
2. (tWCK - tWCKH - tWCKL)/2 is maximum in the case of high speed operation.
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ST8009
(Segment Mode 2)
(VSS = 0 V, VDD = +5.0±0.5 V, V0 = + 5.0 to +16.0 V, TOPR = -20 to +85 °C)
PARAMETER
SYMBOL
CONDITIONS
TYP.
MAX.
UNIT
NOTE
66
ns
1
Shift clock period
tWCK
Shift clock "H" pulse width
tWCKH
23
ns
Shift clock "L” pulse width
tWCKL
23
ns
Data setup time
tDS
15
ns
Data hold time
tDH
23
ns
tWLPH
30
ns
Shift clock rise to latch pulse rise time
tLD
0
ns
Shift clock fall to latch pulse fall time
tSL
50
ns
Latch pulse rise to shift clock rise time
tLS
30
ns
Latch pulse fall to shift clock fall time
tLH
30
ns
Latch pulse fall to shift clock rise time
tLSW
50
ns
Enable setup time
tS
15
ns
Input signal rise time
tR
50
ns
2
Input signal fall time
tF
50
ns
2
DISPOFF removal time
tSD
100
ns
DISPOFF "L" pulse width
tWDL
1.2
µs
Latch pulse "H" pulse width
tR,tF ≤ 10ns
MIN.
Output delay time (1)
tD
CL = 15 pF
41
ns
Output delay time (2)
tPD1, tPD2
CL = 15 pF
1.2
µs
Output delay time (3)
tPD3
CL = 15 pF
1.2
µs
NOTES:
1. Takes the cascade connection into consideration.
2. (tWCK - tWCKH - tWCKL)/2 is maximum in the case of high speed operation.
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ST8009
(Segment Mode 3)
(VSS = 0 V, VDD = +3.0 to +4.5 V, V0 = + 5.0 to +16.0 V, TOPR = -20 10+85 °C)
PARAMETER
SYMBOL
CONDITIONS
MIN.
Shift clock period
tWCK
tR,tF ≤ 10ns
Shift clock "H" pulse width
Shift clock "L” pulse width
UNIT
NOTE
82
ns
1
tWCKH
28
ns
tWCKL
28
ns
Data setup time
tDS
20
ns
Data hold time
tDH
23
ns
tWLPH
30
ns
Shift clock rise to latch pulse rise time
tLD
0
ns
Shift clock fall to latch pulse fall time
tSL
51
ns
Latch pulse rise to shift clock rise time
tLS
30
ns
Latch pulse fall to shift clock fall time
tLH
30
ns
Latch pulse fall to shift clock rise time
tLSW
50
ns
Enable setup time
tS
15
ns
Input signal rise time
tR
50
ns
2
Input signal fall time
tF
50
ns
2
DISPOFF removal time
tSD
100
ns
DISPOFF "L" pulse width
tWDL
1.2
µs
Latch pulse "H" pulse width
TYP.
MAX.
Output delay time (1)
tD
CL = 15 pF
57
ns
Output delay time (2)
tPD1, tPD2
CL = 15 pF
1.2
µs
Output delay time (3)
tPD3
CL = 15 pF
1.2
µs
NOTES: 1. Takes the cascade connection into consideration.
2. (tWCK - tWCKH - tWCKL)/2 is maximum in the case of high speed operation.
(Common Mode)
(VSS = 0 V, VDD = +2.5 to +5.5 V, V0 = + 5.0 to +16.0 V, TOPR = -20 10+85 °C)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNIT
Shift clock period
tWLP
tR, tF 20ns
250
ns
Shift clock “H” pulse width
tWLPH
VDD =5± 0.5V
15
ns
VDD =2.5~4.5V
30
Data setup time
tSU
30
ns
Data hold time
tH
50
ns
Input signal rise time
tR
50
ns
Input signal fall time
tF
50
ns
DISPOFF removal time
tSD
100
ns
DISPOFF “L” pulse width
tWDL
1.2
us
Output delay time (1)
tDL
CL=10pF
200
ns
Output delay time (2)
tPD1,tPD2
CL=10pF
1.2
us
Output delay time (3)
tPD3
CL=10pF
1.2
us
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ST8009
15.3 Timing Chart of Segment Mode
tWLPH
LP
tLD
tSL
tLH
tLS
tWCKH
tWCKL
XCK
tR
tF
tWCK
DI4 - DI0
tDS
LAST DATA
tWDL
tDH
TOP DATA
tSD
DISPOFF
FR
tPD1
LP
tPD2
DISPOFF
tPD3
Y1 - Y120
Timing Characteristics (3)
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ST8009
(Common Mode)
(VSS = 0 V, VDD = +2.5 to +5.5 V, V0 = +5.0 to +16.0 V, TOPR = -20 to +85° C)
PARAMETER
SYMBOL
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Shift clock period
tWLP
tR,tF ≤ 20ns
250
ns
Shift clock "H" pulse width
tWLPH
VDD = +5.0± 0.5V
15
ns
VDD = +2.5+ 4.5V
30
ns
Data setup time
tSU
30
ns
Data hold time
tH
50
ns
Input signal rise time
tR
50
ns
Input signal fall time
tF
50
ns
DISPOFF removal time
tSD
100
ns
DISPOFF "L" pulse width
tWDL
1.2
µs
Output delay time (1)
tDL
CL = 15 pF
200
ns
Output delay time (2)
tPD1, t PD2
CL = 15 pF
1.2
µs
Output delay time (3)
t PD3
CL = 15 pF
1.2
µs
15.4 Timing Chart of Common Mode
tWLP
LP
tR
tWLPH
tSU
tF
tH
EIO2
tDL
EIO1
tWDL
tSD
DISPOFF
FR
tPD1
LP
tPD2
DISPOFF
tPD3
Y1 - Y120
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ST8009
15.5 Application Timing Block:
Frame and Lp falling edge (or rising
Example 160X80
edge) must >10ns
15.6 Parallel vs. Serial Interface Diagram:
S
S
S
S
S
S
S
S
S15
S15
S15
S16
1
2
3
4
5
6
7
8
15
15
15
16
LP
D3
D2
D1
D0
D0
V1.1
1
5
9
1
14
14
15
15
1
5
9
2
6
1
1
14
15
15
15
2
6
1
3
7
1
1
14
15
15
15
3
7
1
4
8
1
1
14
15
15
16
4
8
1
1
2
3
4
7
8
15
15
5
6
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ST8009
16. Application Circuit
(a) When only use one ST8009 in mix mode (64X32)
(b) When use one ST8009 and two ST8011 (240X96)
240X96 DOT LCD PANEL
CS0 ~ CS95
SEG0 ~ SEG119
SEG0 ~ SEG119
D0 ~ D3
XCK
VDD
LP
Vss
SID
SCLK
FR
VDD
LP1
XDISPOFF
LP2
EIO1
XCK
4 DI0 ~ DI3
EIO2
Vss
SID
SCLK
FR
4
VDD
XDISPOFF
LP
EIO1
XCK
EIO2
DI0 ~ DI3
Vss
FR
4
VDD
XDISPOFF
LP
EIO1
XCK
EIO2
DI0 ~ DI3
Vss
FR
FLM
XDISPOFF
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ST8009
(c) When use one ST8009 and two ST8008 (160X96)
(d) When use one ST8009 and one ST8008 (112X64)
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ST8009
ST8009 Serial Specification Revision History
ST8009 Serial Specification Revision History
Version
Date
Description
0.0
2003/12/25
Preliminary version
0.1
2004/1/28
Modify registers
0.2
2004/3/11
Modify registers
0.3
2004/4/5
Add application timing block disgram
0.4
2004/5/20
Add initial flow
0.5
2004/09/08
Define timing of segment Mode. P41~P44
0.6
2005/02/14
Revise graph of ST8008,ST8011(SID, SCLK)
0.7
2005/04/19
Modify stand-by current to 5uA (max)
1.0
2005/05/12
New version update
1.1
2006/11/01
Fixing the XCS error in the fig.1
The above information is the exclusive intellectual property of Sitronix Technology Corp. and shall not be disclosed, distributed or reproduced without
permission from Sitronix.
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