ST ST8012 Dot Matrix Lcd 120 Output LCD Common/Segment driver IC Notice: Sitronix Technology Corp. reserves the right to change the contents in this document without prior notice. specification. Some parameters are subject to change. This is not a final Low-power liquid crystal display power supply circuit 1. DESCRIPTION equipped internally. The ST8012 is a 120-output segment/common driver IC suitable for driving small/medium scale dot matrix Booster circuit (with Boost ratio of 2X/3X/4X/5X/6X) Abundant command functions LCD panels, and is used in PDA or electronic dictionary. LCD bias set, electronic volume, VSS voltage The ST8012 is good as a segment driver or a common regulation internal resistor ratio and booster driver or a common/segment driver, and it can create a frequency. low power consuming, high-resolution LCD. The All Functions have initial value, user can use the ST8012 have eight modes can selected to set common default value or setting by programmable pin to set. and segment numbers by select pin. The ST8012 also have analog DC/DC converter to use. If select segment mode then except booster circuit will opened others circuit (follower and regulator circuit) will automatic closed. 2. FEATURES When don’t used the serial interface, we can select Number of LCD drive outputs: 120 one of default modes by serial interface pins please Supply voltage for LCD drive: Max +16V see Table5. Supply voltage for the logic system: +2.5 to +5.5 V Package: 154-pin COB. Low power consumption and low output impedance SEL2,SEL1,SEL0 DUTY 0 0 0 --0 0 1 1/32 0 1 0 1/48 0 1 1 1/64 1 0 0 1/80 1 0 1 1/96 1 1 0 1/112 1 1 1 1/120 BIAS Segment mode 1/6 or 1/5 1/7 or 1/5 1/9 or 1/7 1/9 or 1/7 1/10 or 1/8 1/11 or 1/9 1/11 or 1/9 (Segment mode) Displa Shift clock frequency y duty - 20 MHz (MAX.): VDD = +5.0 ± 0.5 V select - 15 MHz (MAX.): VDD = +3.0 to + 4.5 V able - 12 MHz (MAX.): VDD = +2.5 to + 3.0 V by Adopts a data bus system select 4-bit parallel / serial input modes are selectable with a pin mode (P/S) pin Automatic transfer function of an enable signal Automatic counting function which, in the chip selection mode, causes the internal clock to be stopped by automatically counting 88、72、56 、40、 24、8 or 120 bits of input data Line latch circuits are reset when XDISPOFF active (Common mode) Shift clock frequency: 4 MHz (MAX.) V1.6 1/ 47 2004/09/08 ST8012 Built-in X-bit shift register Available in a single mode Y1->YX Single mode YX->Y1 Single mode PS:X=32、48、64、80、96、112、120 The above 4 shift directions are pin-selectable Shift register circuits are reset when XDISPOFF active V1.6 2/ 47 2004/09/08 ST8012 3. PIN DESCRIPTION SYMBOL I/O COMSEG0-COMSEG119 O LCD drive output V0~V4 P Power supply for LCD drive 5 L/R I Display data shift direction selection 1 VDD P Power supply for logic system (+2.5 to +5.5 V) 1 EIO2, EIO1 I/O DI0-DI3 I Display data input at segment mode 4 XCK I Clock input for taking display data at segment mode 1 XDISPOFF I Control input for output of non-select level 1 I Latch pulse input for display data at segment mode/ LP FR XRST DESCRIPTION No of Num 120 Input/output for chip selection at segment mode and FLM input output function at com/seg mix mode or common mode Shift clock input for shift register at common mode I AC-converting signal input for LCD drive waveform I System Reset pin .When low level active. The XRST L PULSE timing min value is 200us and max value is 0.5s 2 1 1 1 This is the parallel data input/serial data input switch terminal. P/S I P/S=”H”: Parallel data input. 1 P/S=”L”: Serial data input. V1.6 VSS P CAP1- O CAP1+ O CAP2- O CAP2+ O CAP3+ O CAP4+ O CAP5+ O VOUT O XCS I Ground (0 V) 1 DC/DC voltage converter. Connect a capacitor between this terminal and the CAP2- terminal. DC/DC voltage converter. Connect a capacitor between this terminal and the CAP1- terminal. DC/DC voltage converter. Connect a capacitor between this terminal and the CAP2- terminal. DC/DC voltage converter. Connect a capacitor between this terminal and the CAP2- terminal. DC/DC voltage converter. Connect a capacitor between this terminal and the CAP1- terminal. DC/DC voltage converter. Connect a capacitor between this terminal and the CAP2- terminal. DC/DC voltage converter. Connect a capacitor between this terminal and the CAP1- terminal. DC/DC voltage converter. Connect a capacitor between this terminal and VSS. This is the command mode select pin. When XCS=”L” then write command to the LCD. See Figure1 3/ 47 1 1 1 1 1 1 1 1 1 2004/09/08 ST8012 Don’t toggle SCLK or SID from low level while XCS signal is HIGHT SID I The command data. See Figure1 1 SCLK I The serial clock input. See Figure1 1 These pin are Duty selection. SEL2,SEL1,SEL0 SEL 3, 2, 1 SEL2~SEL0 V1.6 I DUTY BIAS 0 0 0 0, 0, 0 --- Segment mode 0 0 1 0, 0, 1 1/32 1/6 or 1/5 0 1 0 0, 1, 0 1/48 1/7 or 1/5 0 1 1 0, 1, 1 1/64 1/9 or 1/7 1 0 0 1, 0, 0 1/80 1/9 or 1/7 1 0 1 1, 0, 1 1/96 1/10 or 1/8 1 1 0 1, 1, 0 1/112 1/11 or 1/9 1 1 1 1, 1, 1 1/120 1/11 or 1/9 4/47 3 2004/09/08 ST8012 4. BLOCK DIAGRAM COMSEGX .............. COMSEG 0 COM/SEG COM/SEG V0 V1 V3 V3 V4 VSS COM/SEGMENT DRIVER Voltage fallower circuit Voltage Regulator circuit XRST Voltage booster circuit Power Supply Circuit /DISPOFF COM/SEG DATA LATCH Command decorder EIO Control EIO1 EIO2 SHIFT Control XCK P/S SEL2~SEL0 DI0~DI3 V1.6 FR LP T UN OI DD CC Vout CAP1CAP1+ CAP2CAP2+ CAP3CAP4+ CAP5+ VSS SCLK SID XCS L/R LEVEL SHIFTER SEGMENT DATA LATCH SHIFT_CONTROL 3 4 DATA IN Control DIN 5/47 4 2004/09/08 ST8012 INPUT/OUTPUT CIRCUITS V DD I T o Interna l C irc u it A p p lic ab le P in s L/R , D I 3 ~ D I 0 , X D IS P O F F , L P , F R , P /S C S ,S ID ,S E L 2~ S E L0 V s s (0 V ) Input Circuit V DD To Internal Circuit I/O Control Signal Vss (0V) Vss (0V) V DD Output Signal Application Pins EIO 1 , EIO 2 Control Signal Vss (0V) Input/Output Circuit V1.6 6/47 2004/09/08 ST8012 5. FUNCTIONAL DESCRIPTION 5.1 Pin Functions (Segment mode) SYMBOL FUNCTION VDD Logic system power supply pin, connected to +2.5 to +5.5 V. VSS Ground pin, connected to 0 V. This is a multi-level power supply for the liquid crystal drive. The voltage Supply applied is determined by the liquid crystal cell, and is changed through the use of a resistive voltage divided or through changing the impedance using an op. amp. Voltage levels are determined based on VSS, and must maintain the relative magnitudes shown below. V0 ≧V1 ≧V2 ≧V3 ≧V4 ≧Vss V0 V1 V2 V3 When the power supply turns ON, the internal power supply circuits produce the V1to V4voltages shown below. The voltage settings are selected using the LCD bias set command. V4 1/120 Duty 1/112 Duty 1/96Duty 1/80Duty 1/64Duty 1/48 Duty 1/30 Duty V4 1/11*V0 ,1/9*V0 1/11*V0, 1/9*V0 1/10*V0, 1/8*V0 1/9*V0, 1/7*V0 1/9*V0, 1/7*V0 1/7*V0, 1/5*V0 1/6*V0, 1/5*V0 V3 2/11*V0,1/9*V0 2/11*V0, 2/9*V0 2/10*V0, 2/8*V0 2/9*V0, 2/7*V0 2/9*V0, 2/7*V0 2/7*V0, 2/5*V0 2/6*V0, 2/5*V0 V2 9/11*V0, 7/9*V0 9/11*V0, 7/9*V0 8/10*V0, 6/8*V0 7/9*V0, 5/7*V0 7/9*V0, 5/7*V0 5/7*V0, 3/5*V0 4/6*V0, 3/5*V0 V1 10/11*V0,8/9*V0 10/11*V0,8/9*V0 9/10*V0, 7/8*V0 8/9*V0, 6/7*V0 8/9*V0, 6/7*V0 6/7*V0, 4/5*V0 5/6*V0, 4/5*V0 Input pins for display data In 4-bit parallel input mode, input data into the 4 pins, DI3-DI0. DI3-DI0 In serial input mode, input data into the 1 pin,DI0. Connect DI3-DI1 to VSS . Refer to "RELATIONSHIP BETWEEN THE DISPLAY DATA AND LCD DRIVE OUTPUT PINS" in Functional Operations. XCK Clock input pin for taking display data * Data is read at the falling edge of the clock pulse. System Reset pin .When low level active. XRST If not used the hardware reset, this pin must pull height. The XRST L PULSE timing min value is 200us and max value is 0.5s LP Latch pulse input pin for display data Data is latched at the falling edge of the clock pulse. Input pin for selecting the reading direction of display data When set to VSS level "L", data is read sequentially from COMSEG119 to COMSEG0. L/R When set to VDD level "H", data is read sequentially from COMSEG0 to COMSEG119. Refer to "RELATIONSHIP BETWEEN THE DISPLAY DATA AND LCD DRIVE OUTPUT PINS" in Functional Operations. Control input pin for output of non-select level XDISPOFF The input signal is level-shifted from logic voltage level to LCD drive voltage level, and controls the LCD drive circuit. V1.6 7/47 2004/09/08 ST8012 When set to VSS level "L", the LCD drive output pins (COMSEG0-COMSEG119) are set to level Vss. When set to "L", the contents of the line latch are reset, but the display data are read in the data latch regardless of the condition of XDISPOFF. When the XDISPOFF function is canceled, the driver outputs non-select level (V2 or V3), then outputs the contents of the data latch at the next falling edge of the LP. At that time, if XDISPOFF removal time does not correspond to what is shown in AC characteristics, it cannot output the reading data correctly. Table of truth-values is shown in "TRUTH TABLE" in Functional Operations. AC signal input pin for LCD drive waveform The input signal is level-shifted from logic voltage level to LCD drive voltage level, and controls the LCD drive circuit. FR Normally it inputs a frame inversion signal. The LCD drive output pins' output voltage levels can be set using the line latch output signal and the FR signal. Table of truth-values is shown in "TRUTH TABLE" in Functional Operations. Interface Mode selection pin P/S When P/S is “H” then parallel data input mode. When P/S is “L” the serial data input mode, Input/output pins for chip selection. AT segment mode: When L/R input is at VSS level "L", ElO1 is set for output, and EIO2 is set for input(connect to Vss). ElO1, EIO2 When L/R input is at VDD level "H", ElO1 is set for input(connect to Vss), and EIO2 is set for output. During output, set to "H" while LP • XCK is "H" and after 120 bits of data have been read, set to "L” for one cycle (from falling edge to failing edge of XCK), after which it returns to "H". During input, the chip is selected while El is set to "L" after the LP signal is input. The chip is non-selected after 120 bits of data have been read. COMSEG0 –COMSEG119 LCD drive output pins Corresponding directly to each bit of the data latch, one level (V0, V2 ,V3,Vss) is selected and output. Table of truth values is shown in "TRUTH TABLE" in Functional Operations. CAP1- DC/DC voltage converter. Connect a capacitor between this terminal and the CAP2- terminal. CAP1+ DC/DC voltage converter. Connect a capacitor between this terminal and the CAP1- terminal. CAP2- DC/DC voltage converter. Connect a capacitor between this terminal and the CAP2- terminal. CAP2+ DC/DC voltage converter. Connect a capacitor between this terminal and the CAP2- terminal. CAP3+ DC/DC voltage converter. Connect a capacitor between this terminal and the CAP1- terminal. CAP4+ DC/DC voltage converter. Connect a capacitor between this terminal and the CAP2- terminal. CAP5+ DC/DC voltage converter. Connect a capacitor between this terminal and the CAP1- terminal. VOUT DC/DC voltage converter. Connect a capacitor between this terminal and VSS. XCS SID SCLK V1.6 This is the command mode select pin. When XCS=”L” then write command to the LCD, when not used the command mode then must fixed to Vdd . See Figure1 The command data, when not used the command mode then must fixed to Vdd. See Figure1 The serial clock input, when not used the command mode then must fixed to Vdd. See Figure1 8/47 2004/09/08 ST8012 (Common mode) SYMBOL FUNCTION VDD Logic system power supply pin, connected to +2.5 to +5.5 V. VSS Ground pin, connected to 0 V. This is a multi-level power supply for the liquid crystal drive. The voltage Supply applied is determined by the liquid crystal cell, and is changed through the use of a resistive voltage divided or through changing the impedance using an op. amp. Voltage levels are determined based on VDD, and must maintain the relative magnitudes shown below. V0 ≧V1 ≧V2 ≧V3 ≧V4 ≧Vss V0, V1 V2, V3 When the power supply turns ON, the internal power supply circuits produce the V1 to V4 voltages shown below. The voltage settings are selected using the LCD bias set command. V4 LP 1/120 Duty 1/112 Duty 1/96Duty 1/80Duty 1/64Duty 1/48 Duty 1/30 Duty V4 1/11*V0 ,1/9*V0 1/11*V0, 1/9*V0 1/10*V0, 1/8*V0 1/9*V0, 1/7*V0 1/9*V0, 1/7*V0 1/7*V0, 1/5*V0 1/6*V0, 1/5*V0 V3 2/11*V0,1/9*V0 2/11*V0, 2/9*V0 2/10*V0, 2/8*V0 2/9*V0, 2/7*V0 2/9*V0, 2/7*V0 2/7*V0, 2/5*V0 2/6*V0, 2/5*V0 V2 9/11*V0, 7/9*V0 9/11*V0, 7/9*V0 8/10*V0, 6/8*V0 7/9*V0, 5/7*V0 7/9*V0, 5/7*V0 5/7*V0, 3/5*V0 4/6*V0, 3/5*V0 V1 10/11*V0,8/9*V0 10/11*V0,8/9*V0 9/10*V0, 7/8*V0 8/9*V0, 6/7*V0 8/9*V0, 6/7*V0 6/7*V0, 4/5*V0 5/6*V0, 4/5*V0 Shift clock pulse input pin for bi-directional shift register * Data is shifted at the falling edge of the clock pulse. System Reset pin .When low level active. XRST If not used the hardware reset, this pin must pull height. The XRST L PULSE timing min value is 200us and max value is 0.5s Input pin for selecting the shift direction of bi-directional shift register Data is shifted from COMSEG119 to COMSEG0 when set to VSS level "L", and data is shifted from COMSEG0 to COMSEG119 when set to VDD level "H". L/R Refer to "RELATIONSHIP BETWEEN THE DISPLAY DATA AND LCD DRIVE OUTPUT PINS" in Functional Operations. Control input pin for output of non-select level The input signal is level-shifted from logic voltage level to LCD drive voltage level, and controls the LCD drive circuit. When set to VSS level "L", the LCD drive output pins (COMSEG0-COMSEGx) are set to level Vss. XDISPOFF When set to "L”, the contents of the shift register are reset to not reading data. When the /DISPOFF function is canceled, the driver outputs non-select level (V1 or V4), and the shift data is read at the next falling edge of the LP. At that time, if /DISPOFF removal time does not correspond to what is shown in AC characteristics, the shift data is not read correctly. Table of truth-values is shown in "TRUTH TABLE" in Functional Operations. AC signal input pin for LCD drive waveform FR The input signal is level-shifted from logic voltage level to LCD drive voltage level, and controls the LCD drive circuit. V1.6 9/47 2004/09/08 ST8012 Normally it inputs a frame inversion signal. The LCD drive output pins' output voltage levels can be set using the shift register output signal and the FR signal. Table of truth-values is shown in "TRUTH TABLE" in Functional Operations. DI3-DI0 XCK Not used Connect DI3-DI0 to VSS, not floating. Not used XCK is pulled down in common mode, so connect to VSS . LCD drive output pins COMSEG0 -COMSEG119 Corresponding directly to each bit of the shift register, one level (V0 V1, V4, or VSS) is selected and output. Table of truth-values is shown in "TRUTH TABLE" in Functional Operations. Shift data Input/output pins for shift register EIO1 is output pin when L/R is at Vss level “L”, EIO1 is input pin when L/R is at Vdd level “H” When L/R=H, EIO1 is used as input pin, it will be connect to FLM. When L/R=L, EIO1 is used as output pin, it won’t be connect to FLM. ElO1, EIO2 EIO2 is input pin when L/R is at Vss level “L”, EIO1 is output pin when L/R is at Vdd level “H” When L/R=H, EIO2 is used as output pin, it won’t be connect to FLM, When L/R=L, EIO2 is used as input pin, it will be connect to FLM Refer to “RELATIONSHIP BETWEEN THE DISPLAY DATA AND LCD DRIVE OUTPUT PINS” in Functional Operations. CAP1- DC/DC voltage converter. Connect a capacitor between this terminal and the CAP2- terminal. CAP1+ DC/DC voltage converter. Connect a capacitor between this terminal and the CAP1- terminal. CAP2- DC/DC voltage converter. Connect a capacitor between this terminal and the CAP2- terminal. CAP2+ DC/DC voltage converter. Connect a capacitor between this terminal and the CAP2- terminal. CAP3+ DC/DC voltage converter. Connect a capacitor between this terminal and the CAP1- terminal. CAP4+ DC/DC voltage converter. Connect a capacitor between this terminal and the CAP2- terminal. CAP5+ DC/DC voltage converter. Connect a capacitor between this terminal and the CAP1- terminal. VOUT DC/DC voltage converter. Connect a capacitor between this terminal and VSS. XCS SID SCLK V1.6 This is the command mode select pin. When XCS=”L” then write command to the LCD, when not used the command mode then must fixed to Vdd . See Figure1 The command data, when not used the command mode then must fixed to Vdd. See Figure1 The serial clock input, when not used the command mode then must fixed to Vdd. See Figure1 10/47 2004/09/08 ST8012 (common /segment mix mode) Input/output pins for chip selection AT common/segment mode: When L/R input is at Vss level “L”, ElO1 is set output, and EIO2 is set for input. ElO1 : segment chip enable output, as default segment is enabled internally and be non-selected after 8,24,40,56,72 or 88 bits of data have been read. Depend on select mode. ElO2 :common shift data input, no sift data output ElO1, EIO2 When L/R input is at VDD level "H", ElO1 is set for input, and EIO2 is set for output. ElO1 :common shift data, no shift data output ElO2 : segment chip enable output, as default segment is enabled internally and be non-selected after 8,24,40,56,72 or 88 bits of data have been read. Depend on select mode. During output, set to "H" while LP • XCK is "H" and after 120 bits of data have been read, set to "L” for one cycle (from falling edge to failing edge of XCK), after which it returns to "H". During input, the chip is selected while El is set to "L" after the LP signal is input. The chip is non-selected after 120 bits of data have been read. V1.6 11/47 2004/09/08 ST8012 5.2 Functional Operations TRUTH TABLE (Segment Mode) FR LATCH DATA /DISPOFF LCD DRIVE OUTPUT VOLTAGE LEVEL (COMSEG0-COMSEG119) L L H V3 L H H Vss H L H V2 H H H V0 X X L Vss LATCH DATA /DISPOFF LCD DRIVE OUTPUT VOLTAGE LEVEL (Common Mode) FR (COMSEG0-COMSEG119) L L H V4 L H H V0 H L H V1 H H H Vss X X L Vss NOTES: L : VSS (0 V), H : VDD (+2.5 to +5.5 V), X : Don't care "Don't care" should be fixed to "H" or "L", avoiding floating. There are two kinds of power supply (logic level voltage and LCD drive voltage) for the LCD driver. Supply regular voltage that is assigned by specification for each power pin. V1.6 12/47 2004/09/08 ST8012 RELATIONSHIP BETWEEN THE DISPLAY DATA AND LCD DRIVE OUTPUT PINS (Segment Mode) (A) 4-bit Parallel Input Mode L/R L H EIO1 EIO2 Output Input Input Output DATA NUMBER OF CLOCKS INPUT 30 CLOCK 29 CLOCK 28 CLOCK … 3 CLOCK 2 CLOCK 1 CLOCK DI0 COMSEG0 COMSEG4 COMSEG8 … COMSEG108 COMSEG112 COMSEG116 Dl1 COMSEG1 COMSEG5 COMSEG9 … COMSEG109 COMSEG113 COMSEG117 DI2 COMSEG2 COMSEG6 COMSEG10 … COMSEG110 COMSEG114 COMSEG118 DI3 COMSEG3 COMSEG7 COMSEG11 … COMSEG111 COMSEG115 COMSEG119 DI0 COMSEG119 COMSEG115 COMSEG111 … COMSEG11 COMSEG7 COMSEG3 Dl1 COMSEG118 COMSEG114 COMSEG110 … COMSEG10 COMSEG6 COMSEG2 DI2 COMSEG117 COMSEG113 COMSEG109 … COMSEG9 COMSEG5 COMSEG1 DI3 COMSEG116 COMSEG112 COMSEG108 … COMSEG8 COMSEG4 COMSEG0 2 CLOCK 1 CLOCK (B) Serial Input Mode L/R L EIO1 EIO2 Output Input DATA INPUT 120 CLOCK 119 CLOCK 118 CLOCK … Input Output 3 CLOCK DI0 COMSEG0 COMSEG1 Dl1 X X X X X X X DI2 X X X X X X X DI3 X X X X X X X COMSEG1 COMSEG0 DI0 H NUMBER OF CLOCKS COMSEG2 … COMSEG117 COMSEG118 COMSEG119 COMSEG119 COMSEG118 COMSEG117 … COMSEG2 Dl1 X X X X X X X DI2 X X X X X X X DI3 X X X X X X X (Common Mode) V1.6 L/R DATA TRANSFER DIRECTION EIO1 EIO2 L COMSEG119 → COMSEG0 Output Input H COMSEG0 → COMSEG119 Input Output 13/47 2004/09/08 ST8012 MIX MODE(SEGMENT/ COMMON MODE) When (SEL2,SEL1,SEL0)=(0,0,1) SELECT THE 32 COM/88 SEGMENT MODE THEN SEGMENT SIDE OF MIX MODE (a) L/R L H (b) L/R L 4-bit Parallel Input Mode EIO1 EIO2 Seg_end Com_FLM Output Input Com_FLM Seg_end Input Output DATA NUMBER OF CLOCKS INPUT 22 CLOCK 21 CLOCK 20 CLOCK … 3 CLOCK 1 CLOCK DI0 COMSEG0 COMSEG4 COMSEG8 … COMSEG76 COMSEG80 COMSEG84 Dl1 COMSEG1 COMSEG5 COMSEG9 … COMSEG77 COMSEG81 COMSEG85 DI2 COMSEG2 COMSEG6 COMSEG10 … COMSEG78 COMSEG82 COMSEG86 DI3 COMSEG3 COMSEG7 COMSEG11 … COMSEG79 COMSEG83 COMSEG87 DI0 COMSEG119 COMSEG115 COMSEG110 … COMSEG43 COMSEG39 COMSEG35 Dl1 COMSEG118 COMSEG114 COMSEG109 … COMSEG42 COMSEG38 COMSEG34 DI2 COMSEG117 COMSEG113 COMSEG108 … COMSEG41 COMSEG37 COMSEG33 DI3 COMSEG116 COMSEG112 COMSEG107 … COMSEG40 COMSEG36 COMSEG32 DATA NUMBER OF CLOCKS Serial Input Mode EIO1 EIO2 Seg_end Com_FLM Output Input INPUT 88 CLOCK Com_FLM Seg_end Input Output 87 CLOCK 86 CLOCK … 3 CLOCK 2 CLOCK 1 CLOCK COMSEG2 … COMSEG85 COMSEG86 COMSEG87 DI0 COMSEG0 COMSEG1 Dl1 X X X X X X X DI2 X X X X X X X DI3 X X X X X X X DI0 H 2 CLOCK COMSEG119 COMSEG118 COMSEG117 … COMSEG34 COMSEG33 COMSEG32 Dl1 X X X X X X X DI2 X X X X X X X DI3 X X X X X X X COMMON SIDE OF MIX MODE L/R DATA TRANSFER DIRECTION EIO1 EIO2 L COMSEG119 → COMSEG88 Seg_end output Input H COMSEG0 → COMSEG31 Input Seg_end output NOTES: L : VSS (0 V), H : VDD (+2.5 to +5.5 V), X : Don't care "Don't care" should be fixed to "H" or "L", avoiding floating. V1.6 14/47 2004/09/08 ST8012 Connection examples of plural segment drivers (120 segment) (c) When L/R = “L” Top data Last data Data flow COMSEG119 COMSEG119 COMSEG0 EIO2 COMSEG0 COMSEG119 EIO1 EIO2 EIO1 L/R COMSEG0 EIO2 EIO1 L/R L/R FR DI3-DI0 LP XCK DI3-DI0 FR LP XCK FR DI3-DI0 LP XCK XCK LP FR DI3-DI0 4 VSS (d) When L/R = “H” VDD XCK LP FR DI3-DI0 4 EIO2 EIO1 EIO2 COMSEG0 COMSEG0 COMSEG119 Last data Top data V1.6 L/R COMSEG119 Data flow DI3-DI0 EIO1 FR EIO2 LP L/R XCK COMSEG0 DI3-DI0 EIO1 FR Vss LP XCK DI3-DI0 FR LP XCK L/R 15/47 2004/09/08 ST8012 Timing chart of 4-device cascade connection of segment drivers FR LP XCK TOP DATA DI3 - DI0 n* 1 2 LAST DATA n* device A 1 2 n* 1 2 device B n* device C 1 2 n* 1 2 device D EI (device A) EO (device A) EO (device B) EO (device C) *n = 30 in 4-bit parallel input mode *n = 120 in serial input mode V1.6 16/47 2004/09/08 ST8012 Connection examples for signal common drivers (120 common) (e) L/R = ”L” First COMSEG119 FLM COMSEG0 EIO2 EIO1 FR XDISPOFF L/R XCK LP LP Vss VSS XDISPOFF FR (f) L/R = “H” FR XDISPOFF VDD Vss LP LP COMSEG0 XCK EIO1 L/R XDISPOFF FR FLM EIO2 COMSEG119 First V1.6 17/47 2004/09/08 ST8012 Connection examples for plural common/segment (mix mode) drivers The mix mode is 1/32,1/48,1/64,1/80,1/96,1/112 duty mode (g) L/R = “L” FLM VDD XCK LP FR DI3-DI0 4 DI3-DI0 FR LP XCK DI3-DI0 FR LP XCK L/R L/R Vss EIO1 EIO2 Y119 YX+1 YX Com PS L/R EIO1 EIO2 Y0 Y119 Y0 Seg COMSEG Vss Seg Data flow (h) L/R=”H” FLM VDD XCK LP FR DI3-DI0 4 DI3-DI0 Y0 YX COMSEG FR L/R EIO1 PS LP XCK DI3-DI0 FR LP XCK L/R Com EIO2 EIO2 EIO1 YX+1 Y119 Seg Y0 Y119 Seg Data flow V1.6 18/47 2004/09/08 ST8012 Connection examples for 120 com &120 seg (for 1/120 duty) (i) L/R = “L” FLM VDD XCK LP Vss FR DI3-DI0 4 DI3-DI0 FR LP XCK DI3-DI0 FR LP XCK L/R L/R Vss EIO1 EIO2 Y119 YX+1 YX Com PS (j) L/R EIO1 EIO2 Y0 Vss Y119 Y0 Com COMSEG Vss Seg Data flow L/R = “H” FLM VDD XCK LP Vss FR DI3-DI0 4 DI3-DI0 Y0 YX COMSEG FR L/R EIO1 PS LP XCK DI3-DI0 FR LP XCK L/R Com EIO2 EIO2 EIO1 YX+1 Y119 Vss Com Y0 Y119 Seg Data flow V1.6 19/47 2004/09/08 ST8012 PRECAUTIONS Precautions when connecting or disconnecting the power supply This IC has a high-voltage LCD driver, so a high current that may flow if voltage is supplied to the LCD drive power supply while the logic system power supply is floating may permanently damage it. The details are as follows, When connecting the power supply, connect the LCD drive power after connecting the logic system power. Furthermore, when disconnecting the power, disconnect the logic system power after disconnecting the LCD drive power And when connecting the logic power supply, the logic condition of this IC inside is insecure. Therefore connect the LCD drive power supply after resetting logic condition of this IC inside on /DISPOFF function. After that, cancel the /DISPOFF function after the LCD drive power supply has become stable. Furthermore, when disconnecting the power, set the LCD drive output pins to level Vss on /DISPOFF function. Then disconnect the logic system power after disconnecting the LCD drive power. When connecting the power supply, follow the recommended sequence shown here VDD VDD VSS VDD XDISPOFF VSS VDD V0 VSS V1.6 20/47 2004/09/08 ST8012 6. DESCRIPTION FUNCTIONS The MPU Interface Selecting the Interface Type With the ST8012 chips, data transfers are done through polarity to the “H” or “L” it is possible to select either an 4-bit parallel data bus (D3 to D0) or through a serial parallel data input or serial data input as shown in Table data input (SI). Through selecting the P/S terminal 1. Table 1 D0 D3~D1 H: Parallel Input D0 D3~D1 L: Serial Input SI VDD P/S Command Serial Interface With the ST8012 chips, command data transfers are Figure1. done through a serial data input. And it’s timing show in Figure1 rite command timing diagram 2 1 4 3 10 5 11 12 13 14 15 1 SCLK XCS SID D D D5 D4 D3 D2 D1 D0 D D D5 D4 D3 D2 D1 D0 ps :when don’t use the command must set XCS to height level. The Power Supply Circuits (use serial interface) The power supply circuits are low-power consumption circuits ON or OFF independently through the use of power supply circuits that generate the voltage levels the Power Control Set command. Consequently, it is required for the LCD drivers. They are Booster circuits, possible to make an external power supply and the voltage regulator circuits, and voltage follower circuits. internal power supply function somewhat in parallel. They are only enabled in master operation, when the Table 3 shows the Power Control Set Command 3-bit mode is in common mode or common/segment mode. data control function, and Table 4 shows reference The power supply circuits can turn the Booster circuits, combinations. the voltage regulator circuits, and the voltage follower Table3 Function bit D2 D1 D0 Booster circuit control bit Status “111” “000” ON OFF The Control Details of Each Bit of the Power Control Set Command V1.6 21/47 2004/09/08 ST8012 Table4 Com Use Settings / D2 Seg Only the internal power supply Com is used mode Voltage Voltage Voltage booster regulator follower 1 ON ON ON 0 OFF ON ON 1 ON ON ON 0 OFF ON ON External voltage Step-up voltage input VDD Used / Only the voltage regulator circuit and the voltage Com/Seg follower circuit are used mode Only the internal power supply is used VOUT, VDD VDD Open Used Seg Only the voltage regulator mode circuit and the voltage VOUT, VDD Open follower circuit are used Command interface unused mode (use the default value) When command interface is unused. The CS,SCLK and SID signal can be fixed as the following mode Table5 XCS SCLK SID Booster Regulator Follower H X X Default register used (All Off) L H H OFF ON ON L L H ON ON ON THE DEFAULT BIAS,CONTRAST CONTROL,Ra/Rb ratio and Boost Frequency is used when the above mode is selected. NOTE :If all of the Cs, SCLK and SID signals are set to low level. The default power control register will be used, the power control of booster, regulator and follower will always be off. PROGRAM NOTE: Do not toggle sclk or SID from low level while XCS signal is HIGHT. Entry Standby mode: Entry standby must closed the AC circuit(BOOSTER) and /XDISPOFF also go to low level. V1.6 22/47 2004/09/08 ST8012 The Step-up Voltage Circuits Using the step-up voltage circuits equipped within the or 6X step-up of the VDD – VSS voltage levels. ST8012 chips it is possible to product a 2X, 3X, 4X, 5X 6X step-up: Connect capacitor C1 between CAP1+ and CAP1–, voltage level in the negative direction at the VOUT between CAP2+ and CAP2–, between CAP1+ and terminal that is 6 times the voltage level between VDD CAP3–, between CAP2+ and CAP4–,between CAP1+ and VSS. and CAP5–, and between VDD and VOUT, to produce a 5X step-up: Connect capacitor C1 between CAP1+ and CAP1–, and VOUT, to produce a voltage level in the negative between CAP2+ and CAP2–, between CAP1+ and direction at the VOUT CAP3–, between CAP2+ and CAP4–,and between VDD voltage level between VDD and VSS. terminal that is 5 times the 4X step-up: Connect capacitor C1 between CAP1+ and CAP1–, voltage level in the negative direction at the VOUT between CAP2+ and CAP2–, between CAP1+ and terminal that is 4 times the voltage level between VDD CAP3–, and between VDD and VOUT, to produce a and VSS. 3X step-up: Connect capacitor C1 between CAP1+ and CAP1–, terminal that is 3 times the voltage difference between between CAP2+ and CAP2– and between VDD and VDD and VSS. The step-up voltage relationships are VOUT,and short between CAP3– and VOUT to produce shown in Figure2. a voltage level in the negative direction at the VOUT 2X step-up: Connect capacitor C1 between CAP1+ and CAP1–, and between VDD and VOUT, leave CAP2+ open, and short between CAP2–, CAP3– and VOUT to produce a voltage in the negative direction at the VOUT terminal that Is twice the voltage between VDD and VSS. V1.6 23/47 2004/09/08 ST8012 Figure2 VDD VDD VO T C1 C1 VO CAP3+ CAP2+ C1 CAP1C1 CAP1+ CAP1+ CAP2+ CAP2+ ST 012 CAP1C1 CAP1+ T CAP3+ ST 012 CAP1C1 VO T CAP3+ ST 012 C1 VDD C1 C1 CAP2- CAP2- CAP4+ CAP4+ CAP4+ CAP5+ CAP5+ CAP5+ 4x step-up voltage circuit VO T 4xVDD 12V OPEN 3x step-up voltage circuit VO T 3xVDD V VDD 3V 2x step-up voltage circuit VO T 2xVDD V VDD 3V VSS 0V VDD 3V VSS 0V 4x step-up voltage relations ips VSS 0V 3x step-up voltage relations ips VDD CAP2- 2x step-up voltage relations ips VDD C1 C1 VO VO T CAP3+ ST 012 CAP1C1 CAP3+ C1 ST 012 C1 T CAP1C1 CAP1+ CAP1+ CAP2+ CAP2+ C1 C1 CAP2- CAP2- C1 C1 CAP4+ Vout CAP4+ C1 CAP5+ CAP5+ 5x step-up voltage circuit x step-up voltage circuit VO VO T 5xVDD 15V VDD 3V VSS 0V 5x step-up voltage relations ips T xVDD 15V VDD 2.5V VSS 0V x step-up voltage relations ips * The VSS voltage range must be set so that the VOUT terminal voltage does not exceed the absolute maximum rated value. V1.6 24/47 2004/09/08 ST8012 The Voltage Regulator Circuit The step-up voltage generated at VOUT outputs the LCD driver voltage V0 through the voltage regulator circuit. Because the ST78012 chips have an internal high-accuracy fixed voltage power supply with a 64-level electronic volume function and internal resistors for the V0 voltage regulator, systems can be constructed without having to include high-accuracy voltage regulator circuit components.(VREG thermal gradients approximate -0.05%/°C) (A) When the V0 Voltage Regulator Internal Resistors Are Used Through the use of the V0 voltage regulator internal resistors and the electronic volume function the liquid crystal power supply voltage V0 can be controlled by commands alone (without adding any external resistors), making it possible to adjust the liquid crystal display brightness. The V0 voltage can be calculated using equation A-1 over the range where | V0 | < | VOUT|. Figure 3 V0 1+ Rb Ra VEV 1+ Rb Ra 1- ∵ V EV 1- α 200 α 200 VREG VREG V0 Internal Rb Internal Ra VEV constant voltage supply+electronic volume VSS V1.6 25/47 2004/09/08 ST8012 VREG is the IC-internal fixed voltage supply, and its voltage at Ta = 25°C is as shown in Table 6. Table6 Part no. Equipment Type ST8012 Internal Power Supply Thermal Gradient VREG –0.05 %/°C 2.1V α is set to 1 level of 64 possible levels by the electronic volume function depending on the data set in the 6-bit electronicvolume register. Table 6 shows the value for α depending on the electronic volume register settings. Rb/Ra is the V0 voltage regulator internal resistor ratio, and can be set to 8 different levels through the V0 voltage regulator internal resistor ratio set command. The Rb/Ra ratio assumes the values shown in Table 8 depending on the 3-bit data settings in the VDD voltage regulator internal resistor ratio register. Table7 D5 0 0 0 D4 0 0 0 D3 D2 D1 D0 α 0 0 0 0 0 0 0 0 1 0 1 0 1 1 1 0 1 1 1 0 1 63 62 61 : : 2 1 0 : : 1 1 1 1 1 1 1 1 1 V0 voltage regulator internal resistance ratio register value and (1 + Rb/Ra) ratio (Reference value) Table8 Register D2 D1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 ST8012 D0 0 1 0 1 0 1 0 1 (1) –0.05 %/°C 5.0 5.22 5.48 5.76 6.07 6.42 6.81 7.25 1 15 Ta=25 ℃ and booster off, regulator, follower on, out=16V, Vdd=3V 0 14 1 13 2 12 V0 11 3 UNIT :V 4 10 5 Electronic volume Resistor ratio set D2, D1, and D0 1 4 V1.5 10 13 1 1 22 25 2 31 34 3 40 43 4 26/47 4 52 55 5 1 4 2004/04/05 ST8012 The LCD Voltage Generator Circuit The V0 voltage is produced by a resistive voltage driving. Moreover, when the voltage follower changes divider within the IC, and can be produced at the V1, V2, the impedance, it provides V1, V2, V3 and V4 to the V3, and V4 voltage levels required for liquid crystal liquid crystal drive circuit. Reference Circuit Examples Figure 5 shows reference circuit examples. 1.When used all of the step-up circuit, voltage 2.When the voltage regulator circuit and V/F circuit regulating circuit and V/F circuit. alone are used (Example with 4x setup-up) Figure 4 VDD C1 C1 C1 C1 VDD VDD VDD VO T CAP3+ CAP4+ CAP1- CAP5+ Externa l power supply Vout VO T CAP3+ CAP4+ CAP1- CAP5+ CAP1+ CAP1+ CAP2- CAP2- CAP2+ CAP2+ V0 C2 V0 C2 V1 C2 V1 C2 V2 C2 V2 C2 V3 C2 V3 V4 C2 V4 C2 VSS V1.6 ST 012 ST 012 C2 VSS VSS 27/47 VSS 2004/09/08 ST8012 3.When the built-in power circuit is used to drive a output from the built-in voltage follower. Examples of liquid crystal panel heavily loaded with AC or DC, it is shared reference settings When V0 can vary recommended to connect an external resistor to between –8 and 12 V stabilize potentials of V1, V2, V3 and V4 which are V0 Item R4 R4 C2 c1 c2 V1 V3 units 1.0 to 4.7 uF 0.1 to 4.7 uF ST 012 V2 Set value C1 and C2 are determined by the size of V4 the LCD being driven R4 VSS R4 VSS Reference set value R4:100K Ω ~ 1M Ω it is R4 taking the liquid crystal display and the drive recommended to set an optimum resistance value wveform * 1. Because the VR terminal input impedance is high, use short leads and shielded lines. * 2. C1 and C2 are determined by the size of the LCD being driven. Select a value that will stabilize the liquid crystal drive voltage. Example of the Process by which to Determine the Settings: • Turn the voltage regulator circuit and voltage follower circuit ON and supply a voltage to VOUT from the outside. • Determine C2 by displaying an LCD pattern with a heavy load (such as horizontal stripes) and selecting a C2 that stabilizes the liquid crystal drive voltages (V1 to V4). Note that all C2 capacitors must have the same capacitance value. • Next turn all the power supplies ON and determine C1. V1.6 28/47 2004/09/08 ST8012 COMMANDS The ST8012 identify the data bus signals by a combination of XCS, SDI, and SCLK signals. <Example of Commands> LCD Bias Set This command selects the voltage bias ratio required for the liquid crystal display. The D3 can select the Frame direction , if select ‘0’ is normal else select ‘1’ is reverse. Select Status D7 D6 D5 0 0 0 0 0 0 D4 0 0 1/120duty 1/112duty 1/96duty 1/80duty 1/64duty 1/48duty 1/32duty 0 1/11 bias 1/11 bias 1/10 bias 1/9 bias 1/9 bias 1/7 bias 1/6 bias 1 1/9 bias 1/8 bias 1/7 bias 1/7 bias 1/5 bias 1/5 bias 0 1/11 bias 1/11 bias 1/10 bias 1/9 bias 1/9 bias 1/7 bias 1/6 bias 1 1/9 bias 1/7 bias 1/7 bias 1/5 bias 1/5 bias D3 D2 D1 D0 0 X X 1 X X 1/9 bias 1/9 bias 1/8 bias Power Controller Set This command sets the power supply circuit functions. See the function explanation in “The Power Supply Circuit,” for details Selected Mode D7 D6 D5 D4 D3 D2 D1 D0 0 0 1 0 X 0 0 0 Booster circuit: OFF 1 1 1 Booster circuit: ON V0 Voltage Regulator Internal Resistor Ratio Set This command sets the V0 voltage regulator internal resistor ratio. For details, see the function explanation is “The Voltage Regulator circuit " and table 7 . D7 D6 D5 0 1 0 D4 D3 D2 D1 D0 Rb/Ra Ratio 0 X 0 0 0 Small 0 0 1 0 1 0 ↓ ↓ 1 1 0 1 1 1 Large The Electronic Volume This command makes it possible to adjust the brightness of the liquid crystal display by controlling the LCD drive voltage V0 through the output from the voltage regulator circuits of the internal liquid crystal power supply. Electronic Volume Register Set By using this command to set six bits of data to the electronic volume register, the liquid crystal drive voltage V5 assumes one of the 64 voltage levels. When this command is input, the electronic volume mode is released after the V1.6 29/47 2004/09/08 ST8012 electronic volume register has been set. D7 D6 D5 D4 D3 D2 D1 D0 1 1 0 0 0 0 0 0 1 1 0 0 0 0 1 0 1 1 0 0 0 0 1 1 |VSS| Small ↓ ↓ 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 Large Booster Frequency Set By using this command to set three bits of data to the booster frequency, the liquid crystal drive Booster Frequency assumes one of the 8 frequencies. When this command is input, the booster frequency register has been set. D7 D6 D5 D4 D3 D2 D1 D0 0 1 1 0 X 0 0 0 0 1 1 0 X 0 0 1 0 1 1 0 X 0 1 0 0 1 1 0 X 0 1 1 0 1 1 0 X 1 0 0 0 1 1 0 X 1 0 1 0 1 1 0 X 1 1 0 0 1 1 0 X 1 1 1 Booster Frequency Small Large The default value of ST8012 When select common mode or common/segment mode the Bias、Contrast control、Ra/Rb Ratio and Booster Frequency all have the default value, if user don’t not used programmable to setting the status can used the default value. V1.6 Contrast control Ra/Rb Booster Ratio Frequency --- --- --- 1/6 32 4 5k 1/48 1/7 32 4 5k 0, 1, 1 1/64 1/9 32 4 5k 1, 0, 0 1/80 1/9 32 4 5k 1, 0, 1 1/96 1/10 32 4 5k 1, 1, 0 1/112 1/11 32 4 5k 1, 1, 1 1/120 1/11 32 4 5k SEL 3, 2, 1 DUTY BIAS 0, 0, 0 --- Segment mode 0, 0, 1 1/32 0, 1, 0 30/47 2004/09/08 ST8012 TABLE OF ST8012 COMMAND Command Command Code Function D7 D6 D5 D4 D3 D2 D1 0 0 0 0 0 X X D0 0 LCD bias set D0Sets the LCD drive voltage bias ratio.0: 1/6 bias, 1: 1/5 bias (ST8012) 1 1 Power control set 0 0 1 0 X Power control set VSS voltage regulator 0 1 0 0 X Resistor D3 select frame direction.0:normal,1:reverse Select internal power supply operating mode Select internal resistor ratio(Rb/Ra) mode internal resistor ratio set ratio Electronic volume mode set Set the V0 output voltage Electronic volume 1 1 Electronic volume value electronic volume register register set Booster Frequency Set V1.6 0 1 1 0 X 31/47 Booster Frequency Set the LCD booster frequency 2004/09/08 ST8012 7. BSOLUTE MAXIMUM RATINGS PARAMETER Supply voltage (1) Supply voltage (2) Input voltage Storage temperature SYMBOL APPLICABLE PINS RATING UNIT VDD VDD -0.3~+5.5 V V1 V1 VDD+10~ VDD-0.3 V2 V2 VDD+10~ VDD-0.3 V3 V3 -0.3~V5S+10 V V4 V4 -0.3~V5S+10 V -0.3 to VDD+0.3 V -45 to +125 °C VI D14-DI0, XCK, LP, L/R, FR, EIO1, EIO2,XDISPOFF, TSTG NOTE V 1,2 NOTES: 1. TA = +25 °C 2. The maximum applicable voltage on any pin with respect to VSS (0 V). 8. RECOMMENDED OPERATING Conditions PARAMETER SYMBOL Supply voltage (1) VDD Supply voltage (2) V0 Operating temperature TOPR V1.6 APPLICABLE PINS MIN. TYP. MAX. UNIT VDD +2.5 +5.5 V V0 +6.0 +16.0 V -20 +85 °C 32/47 NOTE 1, 2 2004/09/08 ST8012 9. ELECTRICAL CHARACTERISTICS DC Characteristics (Segment Mode) PARAMETER (VSS = 0 V, VDD = +2.5 to +3.6 V, V0 = + 6.0 to +15.0 V, TOPR = -20 to +85°C) SYMBOL CONDITIONS Input "Low" voltage Input "High" voltage Output "Low" voltage Output "High" voltage Input leakage current VIL VIH VOL VOH ILIL APPLICABLE PINS MIN. TYP. MAX. UNIT NOTE DI3-DI0, XCK, LP, L/R FR, EIO1, EIO2,XDISPOFF 0.8VDD IOL = +0.4 mA IOH = -0.4 mA VI = VSS EIO1, EIO2 0.2VDD -10 V V V V µA +10 µA 2.0 kΩ +0.4 VDD-0.4 DI3-DI0, XCK, LP, LIR, FR, EIO1, EIO2, XDISPOFF ILIH VI = VDD Output resistance RON |∆VON| V0 = 15 V =0.5V Standby current Supply current (1) (Non-selection) Supply current (2) (Selection) Supply current (3) ISTB VSS 5 µA 1 IDD1 VDD 2.0 mA 2 IDD2 VDD 7.0 mA 3 I0 V0, V0 0.9 mA 4 Y1-Y120 1.5 NOTES: 1. VDD = +3.0 V, V0 = +12.0 V 2. VDD = +3.0 V, V0 = +12.0 V, fXCK = 8 MHz, no-load, El = VDD. The input data is turned over by data taking clock (4-bit parallel input mode). 3. VDD = +3.0 V, V0 = +12.0 V, fXCK = 8 MHz, no-load, El = VSS. The input data is turned over by data taking clock (4-bit parallel input mode). 4. VDD = +3.0 V, V0 = +12.0 V, fXCK = 8MHz, fLP = 19.2 kHz, fFR = 80 Hz, no-load. The input data is turned over by data taking clock (4-bit parallel input mode). (Common Mode) (VSS = 0 V, VDD = +2.5 to +3.6 V, V0 = +6.0 to +15.0 V, TOPR = -20 to +85 °C) PARAMETER Input "Low" voltage Input "High" voltage Output "Low" voltage Output "High" voltage SYMBOL VIL VIH CONDITIONS VOL VOH IOL = +0.4 mA IOH = -0.4 mA ILIL VI = VSS ILIH VI = VDD Input leakage current Input pull-down current IPD Output resistance RON VI = VDD |∆VON| =0.5V V0 = 15 V APPLICABL E PINS MIN. TYP. MAX. UNIT NOTE DI4-DI0, XCK, LP, L/R 0.2VDD V FR, P/S, DIX, EIO1, V 0.8VDD EIO2, XDISPOFF +0.4 V EIO1, EIO2 VDD-0.4 V DI4-DI0, XCK, LP, L/R FR, P/S, DIX, EIO1, -10.0 µA EIO2, XDISPOFF DI4-DI0, LP, L/R, FR, +10.0 µA P/S, DIX, XDISPOFF XCK, EIO1, EIO2 100 µA COMSEG0COMSEG119 Standby current ISPD VSS Supply current (1) IDD VDD Supply current (2) I0 VO NOTES: 1. VDD = +3.0 V, V0 = +12.0 V, 2. VDD = +3.0 V, V0 = +12.0 V, fLP =19.2 kHz, fFR = 80 Hz, 1/240 duty operation, no-load. V1.6 33/47 1.5 2.0 kΩ 5 80 130 µA µA µA 1 2 2 2004/09/08 ST8012 AC Characteristics (Segment Mode 1) (VSS = 0 V, VDD = +2.5 to +3.6 V, V0 = + 6.0 to +15.0 V, TOPR = -20 10+85 °C) PARAMETER SYMBOL CONDITIONS MIN Shift clock period tWCK tR,tF ≤ 11ns 125 Shift clock "H" pulse width tWCKH 51 Shift clock "L" pulse width tWCKL 51 Data setup time tDS 30 Data hold time tDH 40 Latch pulse "H" pulse width tWLPH 51 Shift clock rise to latch pulse rise time tLD 0 Shift clock fall to latch pulse fall time tSL 51 Latch pulse rise to shift clock rise time tLS 51 Latch pulse fall to shift clock fall time tLH 51 Latch pulse fall to shift clock rise time tLSW 50 Enable setup time tS 36 Input signal rise time tR Input signal fall time tF DISPOFF removal time tSD 100 DISPOFF "L" pulse width tWDL 1.2 Output delay time (1) tD CL = 15 pF Output delay time (2) tPD1, t PD2 CL = 15 pF Output delay time (3) t PD3 CL = 15 pF NOTES: 1. Takes the cascade connection into consideration. 2. (tWCK - tWCKH - tWCKL)/2 is maximum in the case of high speed operation. (Segment Mode 2) MAX. 50 50 78 1.2 1.2 UNIT ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns µs ns µs µs NOTE 1 UNIT NOTE ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns µs ns µs µs 1 2 2 (VSS = 0 V, VDD = +5.0±0.5 V, V0 = + 6.0 to +15.0 V, TOPR = -20 to +85 °C) PARAMETER SYMB OL CONDITIONS MIN. Shift clock period tWCK tR,tF ≤ 10ns 66 Shift clock "H" pulse width tWCKH 23 Shift clock "L” pulse width tWCKL 23 Data setup time tDS 15 Data hold time tDH 23 Latch pulse "H" pulse width tWLPH 30 Shift clock rise to latch pulse rise time tLD 0 Shift clock fall to latch pulse fall time tSL 50 Latch pulse rise to shift clock rise time tLS 30 Latch pulse fall to shift clock fall time tLH 30 Latch pulse fall to shift clock rise time tLSW 50 Enable setup time tS 15 Input signal rise time tR Input signal fall time tF DISPOFF removal time tSD 100 DISPOFF "L" pulse width tWDL 1.2 Output delay time (1) tD CL = 15 pF Output delay time (2) tPD1, t PD2 CL = 15 pF Output delay time (3) t PD3 CL = 15 pF NOTES: 1. Takes the cascade connection into consideration. 2. (tWCK - tWCKH - tWCKL)/2 is maximum in the case of high speed operation. V1.6 TYP. 34/47 TYP. MAX. 50 50 41 1.2 1.2 2 2 2004/09/08 ST8012 (Segment Mode 3) (VSS = 0 V, VDD = +3.0 to +3.6 V, V0 = + 6.0 to +15.0 V, TOPR = -20 10+85 °C) PARAMETER SYMBOL Shift clock period tWCK Shift clock "H" pulse width tWCKH Shift clock "L” pulse width tWCKL Data setup time tDS Data hold time tDH Latch pulse "H" pulse width tWLPH Shift clock rise to latch pulse rise time tLD Shift clock fall to latch pulse fall time tSL Latch pulse rise to shift clock rise time tLS Latch pulse fall to shift clock fall time tLH Latch pulse fall to shift clock rise time Enable setup time Input signal rise time Input signal fall time DISPOFF removal time DISPOFF "L" pulse width Output delay time (1) Output delay time (2) Output delay time (3) tLSW tS tR tF tSD tWDL tD tPD1, t PD2 t PD3 CONDITIONS tR,tF ≤ 10ns MIN. 82 28 28 20 23 30 0 51 30 30 TYP. MAX. 50 15 50 50 100 1.2 CL = 15 pF CL = 15 pF CL = 15 pF 57 1.2 1.2 UNIT ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns µs ns µs µs NOTE 1 2 2 NOTES: 1. Takes the cascade connection into consideration. 2. (tWCK - tWCKH - tWCKL)/2 is maximum in the case of high speed operation. (Common Mode) (VSS = 0 V, VDD = +2.5 to +5.5 V, V0 = + 6.0 to +15.0 V, TOPR = -20 10+85 °C) SYMBOL CONDITIONS MIN Shift clock period Shift clock “H” pulse width PARAMETER tWLP tWLPH tR, tF 20ns VDD=5± 0.5V VDD=2.5~4.5V Data setup time Data hold time Input signal rise time Input signal fall time DISPOFF removal time DISPOFF “L” pulse width Output delay time (1) Output delay time (2) Output delay time (3) tSU tH tR tF tSD tWDL tDL tPD1,tPD2 tPD3 250 15 30 30 50 V1.6 TYP MAX ns ns 50 50 100 1.2 CL=10pF CL=10pF CL=10pF 35/47 UNIT 200 1.2 1.2 ns ns ns ns ns us ns us us 2004/09/08 ST8012 Timing Chart of Segment Mode tWLPH LP tLD tSL tLH tLS tWCKH tWCKL XCK tR tF tWCK DI4 - DI0 tDS LAST DATA tDH TOP DATA tWDL tSD XDISPOFF FR tPD1 LP tPD2 XDISPOFF tPD3 Y1 - Y120 Fig. 8 Timing Characteristics (3) V1.6 36/47 2004/09/08 ST8012 (Common Mode) (VSS = 0 V, VDD = +2.5 to +3.6 V, V0 = +6.0 to +15.0 V V, TOPR = -20 to +85° C) PARAMETER Shift clock period SYMBOL tWLP Shift clock "H" pulse width tWLPH Data setup time Data hold time Input signal rise time Input signal fall time DISPOFF removal time DISPOFF "L" pulse width Output delay time (1) Output delay time (2) Output delay time (3) tSU tH tR tF tSD tWDL tDL tPD1, t PD2 t PD3 CONDITIONS tR,tF ≤ 20ns VDD = +5.0± 0.5V VDD = +2.5+ 4.5V MIN. 250 15 30 30 50 TYP. MAX. 50 50 100 1.2 CL = 15 pF CL = 15 pF CL = 15 pF 200 1.2 1.2 UNIT ns ns ns ns ns ns ns ns µs ns µs µs Timing Chart of Common Mode tWLP LP tR tWLPH tSU tF tH EIO2 tDL EIO1 tWDL tSD XDISPOFF FR tPD1 LP tPD2 XDISPOFF tPD3 Y1 - Y120 V1.6 37/47 2004/09/08 ST8012 The serial interface timing tCCSS tCSH CS1 CS2 1 tSC C tSL SCLK tSH tf tr tSDS tSDH SID Item Serial Clock Period SCL “H” pulse width SCL “L” pulse width Data setup time Data hold time CS-SCL time CS-SCL time Item Serial Clock Period SCL “H” pulse width SCL “L” pulse width Data setup time Data hold time CS-SCL time CS-SCL time Item Serial Clock Period SCL “H” pulse width SCL “L” pulse width Data setup time Data hold time CS-SCL time CS-SCL time V1.6 Signal SCLK SID CS Signal SCLK SID CS Signal SCLK SID CS Symbol Condition tSCYC tSHW tSLW tSDS tSDH tCSS tCSH Symbol Condition tSCYC tSHW tSLW tSDS tSDH tCSS tCSH Symbol tSCYC tSHW tSLW tSDS tSDH tCSS tCSH 38/47 Condition Rating Min. Max. 50 — 25 — 25 — 20 — 10 — 20 — 40 — Rating Min. Max. 100 — 50 — 50 — 30 — 20 — 30 — 60 — Rating Min. Max. 200 — 80 — 80 — 60 — 30 — 40 — 100 — Units ns Units ns Units ns 2004/09/08 ST8012 10. APPLICATION CIRCUIT 8051 serial transfer mode example CLR CS CLR SCLK ;SID=D.7 MOVBIT SID,D.7 ; READ DATA FROM SID SETB SCLK CLR SCLK ;SID=D.6 MOVBIT SID,D.6 ; READ DATA FROM SID SETB SCLK CLR SCLK ;SID=D.5 MOVBIT SID,D.5 ; READ DATA FROM SID SETB SCLK CLR SCLK ;SID=D.4 MOVBIT SID,D.4 ; READ DATA FROM SID SETB SCLK CLR SCLK ;SID=D.3 MOVBIT SID,D.3 ; READ DATA FROM SID SETB SCLK CLR SCLK ;SID=D.2 MOVBIT SID,D.2 ; READ DATA FROM SID SETB SCLK CLR SCLK ;SID=D.1 MOVBIT SID,D.1 ; READ DATA FROM SID SETB SCLK CLR SCLK ;SID=D.0 MOVBIT SID,D.0 ; READ DATA FROM SID SETB SCLK CLR SCLK SETB CS RET V1.6 39/47 2004/09/08 ST8012 Application for Data Writing of segment mode When ST8012 is as a segment mode driver , you must write ‘0’ data to the part of no display, when segments are not all used . Example: the second segment have 120 segments ,but only use 100 segments then you must write 100 data that you need and right ,then you still write 20 be having ‘0’ data to fill the part of segments not used .Otherwise there will errors, when you don’t write the 20 ‘0’ data to fill the part of no display segments. A summary of ST8012 in segment mode you must write the number of segments data to fill the segments.(EX : use two ST8012 to show the 64X132, then you must write the 80X160 data to fill the segments, use three ST8012 to show 120X200 the you must write the 120X240 data to fill the segments……) EX: rite 44 Ń0ńdata The 44 segments is not use but must write 44 ‘0’ data. V1.6 40/47 2004/09/08 ST8012 Application1 Circuit for Module of VLCD No Duty Vlcd (v) 1 1/32 6,7 2 1/48 7,8 3 1/64 9,10 4 1/80 10,11 5 1/96 10,11 6 1/112 11,12 7 1/120 11,12 Note : The value of panel’s ITO resistor is 10Ω. Application Timing Block: Example 160X80 Frame and Lp falling edge (or rising edge) must >10ns Between Lp falling edge and XCK rising edge must >50ns V1.6 41/47 2004/09/08 ST8012 Parallel vs. Serial Interface Diagram S1 S2 S3 S4 S5 S6 S7 S8 S1 S1 S1 S1 1 2 3 4 5 6 7 8 15 15 15 16 LP D3 1 5 9 13 14 14 15 15 1 5 9 D2 2 6 10 14 14 15 15 15 2 6 10 D1 3 7 11 15 14 15 15 15 3 7 11 D0 4 8 12 16 14 15 15 16 4 8 12 D0 1 2 3 4 V1.5 5 6 7 42/47 8 15 15 15 16 2004/04/05 ST8012 Application2 Circuit for Module 1/120 duty, 120 commons and 120 segments V DD FR LP EIO 1 FLM V0 V1 V2 V3 V4 COMSEG0~ COMSEG11 EIO 2 XCK R 100~3.3K EIO2 V DD V SS 120 X 120 DOT LCD PANEL V0 V1 V2 V3 V4 XDISPOFF Vdd Vout Vout V DD COMSEG0~ COMSEG11 ST 012 P/S DI3~DI0 SEL 2 SEL 1 SEL 0 XDISPOFF L/R XCK FR LP 4 DI3~DI0 EIO1 P/S DI3~DI0 SEL2 SEL1 SEL0 XDISPOFF L/R XCK FR LP ST 012 V DD V SS VSS 1/80 duty, 80 commons and 160 segments VDD VDD 0 X 1 0 DOT LCD PANEL V0 V1 V2 V3 V4 COMSEG0~ COMSEG11 EIO2 R 100~3.3K EIO2 XDISPOFF Vdd V0 V1 V2 V3 V4 EIO1 VSS COMSEG0~ COMSEG11 Vout FLM VDD 4 ST 012 XCK FR LP P/S DI3~DI0 SEL2 SEL1 SEL0 XDISPOFF L/R XCK FR LP DI3~DI0 EIO1 P/S DI3~DI0 SEL2 SEL1 SEL0 XDISPOFF L/R XCK FR LP ST 012 VDD VSS V1.5 43/47 2004/04/05 ST8012 11. PAD DIAGRAM Chip size：5,840(µm) x 2,820(µm) Pad size：80 µm x 80 µm Origin： Chip center (0,0) Pin Pitch：110 ~ 110 µm Chip Thickness：19 mil (19X25.4µm=482.6µm) COMSEG111 54 55 COMSEG11 VO T CAP3P CAP1N CAP1P CAP2P CAP2N CAP4P CAP5P V0 V1 V2 V3 V4 XRST DI3 DI2 DI1 DI0 EIO1 EIO2 XCK XDISPOFF CS SID SCLK FR LP VSS SEL2 SEL1 SEL0 LR PS VDD COMSEG0 COMSEG COMSEG10 45 44 43 42 41 40 3 3 3 3 35 34 33 32 31 30 2 2 2 2 25 24 23 22 21 20 1 1 1 1 15 14 13 12 11 10 2 COMSEG110 1 ST 012 COMSEG32 132 131 COMSEG COMSEG COMSEG33 Substrate Connect to Vss. V1.6 44/47 2004/09/08 ST8012 Unit：um Pin.No V1.6 Page pin name X Y Pin.No Page pin name X Y 1 COMSEG110 2810 1300 78 COMSEG33 -2810 -1300 2 COMSEG111 2650 1300 79 COMSEG34 -2650 -1300 3 COMSEG112 2510 1300 80 COMSEG35 -2510 -1300 4 COMSEG113 2380 1300 81 COMSEG36 -2380 -1300 5 COMSEG114 2260 1300 82 COMSEG37 -2260 -1300 6 COMSEG115 2150 1300 83 COMSEG38 -2150 -1300 7 COMSEG116 2050 1300 84 COMSEG39 -2050 -1300 8 COMSEG117 1950 1300 85 COMSEG40 -1950 -1300 9 COMSEG118 1850 1300 86 COMSEG41 -1850 -1300 10 COMSEG119 1750 1300 87 COMSEG42 -1750 -1300 11 VOUT 1650 1300 88 COMSEG43 -1650 -1300 12 CAP3P 1550 1300 89 COMSEG44 -1550 -1300 13 CAP1N 1450 1300 90 COMSEG45 -1450 -1300 14 CAP1P 1350 1300 91 COMSEG46 -1350 -1300 15 CAP2P 1250 1300 92 COMSEG47 -1250 -1300 16 CAP2N 1150 1300 93 COMSEG48 -1150 -1300 17 CAP4P 1050 1300 94 COMSEG49 -1050 -1300 18 CAP5P 950 1300 95 COMSEG50 -950 -1300 19 V0 850 1300 96 COMSEG51 -850 -1300 20 V1 750 1300 97 COMSEG52 -750 -1300 21 V2 650 1300 98 COMSEG53 -650 -1300 22 V3 550 1300 99 COMSEG54 -550 -1300 23 V4 450 1300 100 COMSEG55 -450 -1300 24 XRST 350 1300 101 COMSEG56 -350 -1300 25 DI3 250 1300 102 COMSEG57 -250 -1300 26 DI2 150 1300 103 COMSEG58 -150 -1300 27 DI1 50 1300 104 COMSEG59 -50 -1300 28 DI0 -50 1300 105 COMSEG60 50 -1300 29 EIO1 -150 1300 106 COMSEG61 150 -1300 30 EIO2 -250 1300 107 COMSEG62 250 -1300 31 XCK -350 1300 108 COMSEG63 350 -1300 32 XDISPOFF -450 1300 109 COMSEG64 450 -1300 33 XCS -550 1300 110 COMSEG65 550 -1300 34 SID -650 1300 111 COMSEG66 650 -1300 35 SCLK -750 1300 112 COMSEG67 750 -1300 36 FR -850 1300 113 COMSEG68 850 -1300 37 LP -950 1300 114 COMSEG69 950 -1300 38 VSS -1050 1300 115 COMSEG70 1050 -1300 39 SEL2 -1150 1300 116 COMSEG71 1150 -1300 40 SEL1 -1250 1300 117 COMSEG72 1250 -1300 41 SEL0 -1350 1300 118 COMSEG73 1350 -1300 42 LR -1450 1300 119 COMSEG74 1450 -1300 43 PS -1550 1300 120 COMSEG75 1550 -1300 44 VDD -1650 1300 121 COMSEG76 1650 -1300 45 COMSEG0 -1750 1300 122 COMSEG77 1750 -1300 46 COMSEG1 -1850 1300 123 COMSEG78 1850 -1300 45/47 2004/09/08 ST8012 V1.6 47 COMSEG2 -1950 1300 124 COMSEG79 1950 -1300 48 COMSEG3 -2050 1300 125 COMSEG80 2050 -1300 49 COMSEG4 -2150 1300 126 COMSEG81 2150 -1300 50 COMSEG5 -2260 1300 127 COMSEG82 2260 -1300 51 COMSEG6 -2380 1300 128 COMSEG83 2380 -1300 52 COMSEG7 -2510 1300 129 COMSEG84 2510 -1300 53 COMSEG8 -2650 1300 130 COMSEG85 2650 -1300 54 COMSEG9 -2810 1300 131 COMSEG86 2810 -1300 55 COMSEG10 -2810 1160 132 COMSEG87 2810 -1160 56 COMSEG11 -2810 1030 133 COMSEG88 2810 -1030 57 COMSEG12 -2810 910 134 COMSEG89 2810 -910 58 COMSEG13 -2810 800 135 COMSEG90 2810 -800 59 COMSEG14 -2810 700 136 COMSEG91 2810 -700 60 COMSEG15 -2810 600 137 COMSEG92 2810 -600 61 COMSEG16 -2810 500 138 COMSEG93 2810 -500 62 COMSEG17 -2810 400 139 COMSEG94 2810 -400 63 COMSEG18 -2810 300 140 COMSEG95 2810 -300 64 COMSEG19 -2810 200 141 COMSEG96 2810 -200 65 COMSEG20 -2810 100 142 COMSEG97 2810 -100 66 COMSEG21 -2810 0 143 COMSEG98 2810 0 67 COMSEG22 -2810 -100 144 COMSEG99 2810 100 68 COMSEG23 -2810 -200 145 COMSEG100 2810 200 69 COMSEG24 -2810 -300 146 COMSEG101 2810 300 70 COMSEG25 -2810 -400 147 COMSEG102 2810 400 71 COMSEG26 -2810 -500 148 COMSEG103 2810 500 72 COMSEG27 -2810 -600 149 COMSEG104 2810 600 73 COMSEG28 -2810 -700 150 COMSEG105 2810 700 74 COMSEG29 -2810 -800 151 COMSEG106 2810 800 75 COMSEG30 -2810 -910 152 COMSEG107 2810 910 76 COMSEG31 -2810 -1030 153 COMSEG108 2810 1030 77 COMSEG32 -2810 -1160 154 COMSEG109 2810 1160 46/47 2004/09/08 ST8012 NOTE 2001.12/19 Modify the booster capacity 2002 1/8 Modify the serial command interface-timing block (p16) 2002 1/14 Modify the Register command code 2002 1/17 Modify the Reset Register command defined 2002 1/23 Modify the pin description defined and command interface unused mode (p17) 2002 2/22 Modify the Booster circuit diagram (p19) 2002 2/22 Modify the Mix Mode table(p10)、add the serial interface timing(p33、p34)、add pad data(p37) 2002 2/22 Modify the CS SET (p34) 2002/3/20 Modify the serial interface, when in the serial interface the d0data.and add the AC direction. 2002/4/3 Modify the pad location (P39) 2002/06/04 Modify the XREST ACTIVE (p2) 2002/06/010 Modify the Chip Size (P37) 2002/06/21 Modify common and segment mode pin description (P6~P8) 2002/07/01 Modify booster circuit (P20) 2002/07/09 Command interface unused mode (use the default value)(P18) 2002/10/14 Delete the software reset and cog package , add the regulator liner line , delete some AC application. 2002/11/22 Modify the booster frequency V1.1A 2003/03/31 Modify booster turns off command (p28) 2003/04/04 Add the XCS used math. 2003/4/17 Modify the Application circuit 2003/6/17 Add Application circuit V1.3 2003/11/12 Add Pin Pitch value V1.4 2004/04/05 Add application timing block V1.5 2004/09/08 Define timing(tLSW) of Segment Mode. P33~P35 V1.6 The above information is the exclusive intellectual property of Sitronix Technology Corp. and shall not be disclosed, distributed or reproduced without permission from Sitronix. V1.6 47/47 2004/09/08