19-2565; Rev 0; 8/02 5Gbps PC Board Equalizer Features ♦ Spans 40in (1m) of FR4 PC Board ♦ 0.18UI Deterministic Jitter Up to 40in ♦ Low Power Consumption: 185mW ♦ Equalization Reduces Intersymbol Interference ♦ Single +3.3V Supply ♦ Standby Mode ♦ Small 4mm × 4mm 16-Pin QFN Package N.C. N.C. EN TOP VIEW N.C. Pin Configuration 16 15 14 13 Applications Chassis Life Extension VCC 1 12 VCC IN+ 2 11 OUT+ IN- 3 10 OUT- GND 4 9 GND Ordering Information GND 7 8 N.C. 6 VCC 5 N.C. MAX3784 PART TEMP RANGE MAX3784UGE 0°C to +85°C PIN-PACKAGE 16 QFN QFN NOTE: THE EXPOSED PAD MUST BE SOLDERED TO SUPPLY GROUND FOR CORRECT THERMAL AND ELECTRICAL PERFORMANCE. Typical Application Circuit 1.25Gbps Rx Tx SWITCH CARD PC BOARD BACKPLANE LINE CARD T/R 1 +3.3V SWITCH 1.25Gbps Rx Tx T/R 2 T/R 1 Tx IN +3.3V T/R 2 1.25Gbps Rx Tx T/R 3 Rx Tx OUT Rx EQUALIZER T/R 3 Rx T/R 4 1.25Gbps 5Gbps MAX3784 OUT MAX3784 IN Tx EQUALIZER T/R 4 ________________________________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. 1 MAX3784 General Description The MAX3784 5Gbps equalizer provides compensation for transmission-medium losses in up to 40in of FR4. It is optimized for short run length, balanced codes such as 8b10b, as found in multiplexed 1.25Gbps Ethernet systems. The equalizer uses differential CML data inputs and outputs. A standby mode provides low power when the part is not in use. The MAX3784 is available in a 4mm × 4mm 16-pin QFN package that consumes only 185mW at +3.3V. MAX3784 5Gbps PC Board Equalizer ABSOLUTE MAXIMUM RATINGS Supply Voltage, VCC.................................................-0.5V to +6V Input Voltage............................................(-0.5V) to (VCC + 0.5V) Continuous Output Current ...............................-25mA to +25mA Continuous Power Dissipation (TA = +85°C) 16-Pin QFN (derate 25mW/°C above +85°C) ............1600mW Operating Ambient Temperature Range ................0°C to +85°C Storage Temperature Range .............................-55°C to +150°C Lead Temperature (soldering, 10s) .................................+300°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (VCC = +3V to +3.6V, TA = 0°C to +85°C. Typical values are at VCC = +3.3V and TA = +25°C, unless otherwise noted.) PARAMETER SYMBOL CONDITIONS MIN TYP EN = low Supply Power 30 EN = high Supply Noise Tolerance (Note 1) Latency From input to output MAX 185 10Hz < f < 100Hz 100 100Hz < f < 1MHz 40 1MHz < f < 2.5GHz 250 UNITS mW mVP-P 10 200 ps CML RECEIVER INPUT Input Voltage Swing VIN Measured differentially at point A in Figure 1 (Note 2) Return Loss 100MHz to 2.5GHz Input Resistance Differential 400 1000 15 80 mVP-P dB 100 120 20in 0.13 0.21 40in 0.18 0.23 Ω EQUALIZATION Residual Deterministic Jitter, 5Gbps Table 1 (Notes 2, 3, 4, 5) Residual Deterministic Jitter, 2.5Gbps Table 1 (Notes 2, 3, 4, 5) Residual Deterministic Jitter, 1.25Gbps Table 1 (Notes 2, 3, 4, 5) Random Jitter (Notes 5, 6) 20in 0.08 0.14 40in 0.13 0.28 UIP-P UIP-P 20in 0.04 0.07 40in 0.07 0.15 1.3 1.9 psRMS 600 mVP-P UIP-P CML TRANSMITTER OUTPUT (into 100Ω ±1Ω) Output Voltage Swing VO Differential swing, measured differentially at point C in Figure 1 400 Transition Time tf, tr 20% to 80% (Notes 5, 8) 30 45 60 ps Single ended 40 50 60 Ω Output Resistance 2 _______________________________________________________________________________________ 5Gbps PC Board Equalizer MAX3784 ELECTRICAL CHARACTERISTICS (continued) (VCC = +3V to +3.6V, TA = 0°C to +85°C. Typical values are at VCC = +3.3V and TA = +25°C, unless otherwise noted.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS ENABLE CONTROL PIN Input High Voltage 1.5 V Input Low Voltage 0.5 V Input High Current (Note 5) -150 +10 µA Input Low Current (Note 5) -150 +10 µA Note 1: Allowed supply noise during jitter tests. Note 2: Test pattern. This is a combination of K28.5± characters running at the full bit rate and at one-quarter the bit rate. This simulates the multiplexing of four each 1.25Gbps Ethernet data streams. Pattern (hex) 100 bits 00 FFFF F0F0 FF 0000 0F0F (quarter rate K28.5+, quarter rate K28.5-) 3EB05 (K28.5± 00 1111 1010 11 0000 0101) Note 3: Difference in deterministic jitter between reference points A and C in Figure 1. Note 4: Signal source amplitude range is 400mVP-P to 1000mVP-P, differential. Signal is applied differentially at point A as shown in Figure 1. The deterministic jitter at point B must be from media-induced loss and not from clock-source modulation. Deterministic jitter is measured at the 50% vertical level of the signal at point C. Note 5: Guaranteed by design and characterization. Note 6: Test pattern is K28.5 with 40in trace. Note 7: On-chip pullup resistor of 40kΩ typical. Negative current indicates equalizer sources current. Note 8: Using 00 0001 1111 or equivalent pattern. Measured over entire input voltage range, max and min media loss and within 2in of output pins. SIGNAL SOURCE MAX3784 EQUALIZER BACKPLANE PC BOARD A SMA CONNECTOR SMA CONNECTOR B C IN OUT 6mil LINE L ≤ 40in Figure 1. Test Conditions Table 1. PC Board Assumptions (PC board material is FR4) PARAMETER Transmission Line CONDITIONS MIN Edge-coupled stripline TYP MAX 6 mil Relative Permittivity FR4 or similar 4.4 4.5 Loss Tangent FR4 or similar 0.02 0.022 Metal Thickness 0.7mil (0.5oz copper) Impedance Differential 0.7 90 100 UNITS mil 110 Ω _______________________________________________________________________________________ 3 Typical Operating Characteristics (VCC = +3.3V, measurements done at 5Gbps, 800mVP-P board input with 100-bit pattern from Note 2 of the EC Table, TA = +25°C, unless otherwise noted.) 55mV/ div 55mV/ div 32ps/div 32ps/div DETERMINISTIC JITTER vs. LINE LENGTH 15 10 90 5 80 1.25GHz 70 60 2.5GHz 50 40 90 DETERMINISTIC JITTER (ps) 20 100 MAX3784 toc05 25 100 DETERMINISTIC JITTER (ps) MAX3784 toc04 30 DETERMINISTIC JITTER vs. AMPLITUDE (20in FR4 STRIPLINE) 5GHz 30 1 2 3 4 60 50 40 20 10 10 20 30 40 50 60 200 LINE LENGTH (in) (FR4 6mil STRIPLINE) DETERMINISTIC JITTER vs. AMPLITUDE (40in FR4 STRIPLINE) LATENCY vs. TEMPERATURE 400 50 1.25GHz 40 LATENCY (ps) 70 2.5GHz 300 200 5GHz 30 70 0 200 400 600 800 1000 INPUT AMPLITUDE (mVP-P) (FIGURE 1, POINT A) 1200 1200 ICC 60 50 40 30 10 10 0 1000 20 100 20 800 SUPPLY CURRENT vs. TEMPERATURE SUPPLY CURRENT (mA) 80 600 80 MAX3784 toc08 90 400 INPUT AMPLITUDE (mVP-P) (FIGURE 1, POINT A) 500 MAX3784 toc07 100 5GHz 1.25GHz 0 0 5 2.5GHz 30 10 FREQUENCY (GHz) 60 70 MAX3784 toc09 0 80 20 0 0 MAX3784 toc06 DIFFERENTIAL RETURN LOSS 4 MAX3784 toc03 55mV/ div 32ps/div RETURN LOSS (dB) EQUALIZER OUTPUT EYE DIAGRAM AFTER EQUALIZATION AT 5Gbps (20in, FR4, 6mil STRIPLINE) MAX3784 toc02 EQUALIZER OUTPUT EYE DIAGRAM AFTER EQUALIZATION AT 5Gbps (40in, FR4, 6mil STRIPLINE) MAX3784 toc01 EQUALIZER INPUT EYE DIAGRAM BEFORE EQUALIZATION AT 5Gbps (40in, FR4, 6mil STRIPLINE) DETERMINISTIC JITTER (ps) MAX3784 5Gbps PC Board Equalizer ISHUTDOWN 0 0 25 50 TEMPERATURE (°C) 75 100 0 25 50 TEMPERATURE (°C) _______________________________________________________________________________________ 75 100 5Gbps PC Board Equalizer PIN NAME FUNCTION 1, 7, 12 VCC 2 IN+ Positive Input, CML 3 IN- Negative Input, CML 4, 6, 9 GND Supply Ground 5, 8, 14, 15, 16 N.C. No Connection. Leave unconnected. 10 OUT- Negative Output, CML 11 OUT+ Positive Output, CML 13 EN EP Exposed Pad +3.3V Supply Voltage Enable Equalizer. A logic high or open selects normal operation. A logic low selects low-power standby mode. Connect to Ground. The exposed pad must be soldered to the circuit board ground plane for proper thermal and electrical performance. 5Gbps EQUALIZER VCC OFFSET CANCELLATION LOWPASS FILTER IN+ 100Ω MAX3784 50Ω 50Ω OUT+ EQUALIZER LIMITER OUT- INVCC 40kΩ EN Figure 2. Functional Diagram Detailed Description General Theory of Operation The MAX3784 adaptive equalizer extends the reach of transmission lines in high-frequency backplane interconnect applications. It can be used for up to 20-bit CID (coded), NRZ data operating at 5Gbps as found in 4 × 1G Ethernet (5Gbps). Internally, the MAX3784 is comprised of an equalizer control loop and limiting output driver. The equalizer reduces intersymbol interference (ISI), compensating for frequency-dependent media-induced loss. The equalization control detects the spectral contents of the input signal and provides a control voltage to the equalizer core, adapting it to different media. The equalizer operation is optimized for short-run, DC-balanced transmission codes. Standby Mode Standby saves power when the equalizer is not in use. The EN logic input must be set high or open for normal operation. Logic low at EN forces the equalizer into the standby state. CML Input and Output Buffers The input and output buffers are implemented using current-mode logic (CML). Equivalent circuits are shown in Figures 3 and 4. For details on interfacing with CML, see Maxim Application Note HFAN-1.0: Interfacing Between CML, PECL, and LVDS. The common-mode voltage of the input and output is above 2.5V. AC-coupling capacitors are required when interfacing this part with devices terminated in voltages such as 1.8V. Values of 0.10µF or greater are recommended. _______________________________________________________________________________________ 5 MAX3784 Pin Description MAX3784 5Gbps PC Board Equalizer VCC VCC 50Ω 50Ω OUT+ OUT- 50Ω 50Ω 250µA Figure 3. CML Input Equivalent Circuit Applications Information Alternate Data Rates The MAX3784 is optimized for automatic operation at 5Gbps. Equalization at other data rates, such as 1.25Gbps and 2.5Gbps, is possible. See the Typical Operating Characteristics for Deterministic Jitter vs. Line Length and Deterministic Jitter vs. Amplitude for typical performance at these data rates. 6 Figure 4. CML Output Equivalent Circuit Layout Considerations Circuit board layout and design can significantly affect the MAX3784’s performance. Use good high-frequency design techniques, including minimizing ground inductance and connections and using controlled-impedance transmission lines for the high-frequency data signals. Route signals differentially to reduce EMI susceptibility and crosstalk. Solder the exposed pad to supply ground for proper thermal and electrical operation. Place power-supply decoupling capacitors as close as possible to the VCC pins. _______________________________________________________________________________________ 5Gbps PC Board Equalizer _______________________________________________________________________________________ 7 MAX3784 Package Information (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.) MAX3784 5Gbps PC Board Equalizer Package Information (continued) (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.) Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 8 _____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 2002 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.