MAXIM MAX6851

19-2746; Rev 0; 1/03
2-Wire Interfaced, 7-, 14-, and 16-Segment Alphanumeric Vacuum-Fluorescent Display Controller
Features
♦ 400kbps I2C-Compatible Serial Interface
♦ 2.7V to 3.6V Operation
♦ Controls Up to 48 Grids of 7-Segment, 14-Segment,
or 16-Segment Alphanumeric Digits
♦ One Digit and Two Digits per Grid and Universal
Displays Supported
♦ 16-Step Digital Brightness Control
♦ Built-In ASCII 104-Character Font
Applications
Display Modules
Industrial Controllers
Retail POS Displays
White Goods
Weight and Tare
Displays
Professional Audio
Equipment
♦ 24 User-Definable Characters
♦ Up to Four Annunciators per Grid with Automatic
Blinking Control
♦ Separate Cursor Control with Automatic Blinking
♦ Filament Drive Full-Bridge Waveform Synthesis
♦ Charge-Pump Drive Output to Generate Cathode
Bias Supply
♦ Buzzer Tone Generator with Single-Ended or
Push-Pull Driver
♦ Up to Five General-Purpose Logic Outputs
♦ 11µA Low-Power Shutdown (Data Retained)
♦ 16-Pin QSOP Package
Ordering Information
PART
TEMP RANGE
MAX6851AEE
PIN-PACKAGE
-40°C to +125°C
16 QSOP
Typical Application Circuit
CHIP-ON-GLASS VFD
Bar Graph Displays
VFD SUPPLY VOLTAGE
0.1µF
Pin Configuration and Functional Diagram appear at end of
data sheet.
MICROCONTROLLER
VFCLK
MAX6851
VFDOUT
SDA
SDA
SCL
SCL
VFLOAD
VFBLANK
SPI and QSPI are trademarks of Motorola, Inc.
OSC2
MICROWIRE is a trademark of National Semiconductor Corp.
GND
OSC1
10kΩ
56pF
________________________________________________________________ Maxim Integrated Products
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
1
MAX6851
General Description
The MAX6851 compact vacuum-fluorescent display
(VFD) controller provides microprocessors with the multiplex timing for 7-segment, 14-segment, or 16-segment
alphanumeric VFD displays up to 96 characters and
controls industry-standard, shift-register, high-voltage
grid/anode VFD tube drivers. The device supports display tubes using either one or two digits per grid, as
well as universal displays. Hardware is included to simplify the generation of cathode bias and filament supplies and to provide up to five logic outputs, including a
buzzer driver. The MAX6851 provides an internal crosspoint switch to match any tube-driver, shift-register
grid/anode order, and is compatible with both chip-inglass and external tube drivers.
The MAX6851 includes an ASCII 104-character font,
multiplex scan circuitry, and static RAM that stores
digit, cursor, and annunciator data, as well as font data
for 24 user-definable characters. The display intensity
can be adjusted by an internal 16-step digital brightness control. The device also includes separate annunciator and cursor control with automatic blinking, as
well as a low-power shutdown mode.
The MAX6851 provides timing to generate the PWM
waveforms to drive the tube filament from a DC supply.
The filament drive is synchronized to the display multiplexing to eliminate beat artifacts.
For a high-speed SPI™/QSPI™/MICROWIRE™ interfaced version, refer to the MAX6850 data sheet.
MAX6851
2-Wire Interfaced, 7-, 14-, and 16-Segment Alphanumeric Vacuum-Fluorescent Display Controller
ABSOLUTE MAXIMUM RATINGS
Voltage (with respect to GND)
V+ .............................................................................-0.3V to +4V
ADO, SDA, SCL.....................................................-0.3V to +5.5V
All Other Pins................................................-0.3V to (V+ + 0.3V)
Current
V+..................................................................................200mA
GND .............................................................................-200mA
PHASE1, PHASE2, PORT0, PORT1, PUMP................±150mA
VFCLK, VFDOUT, VFLOAD, VFBLANK ......................±150mA
SDA .................................................................................15mA
Continuous Power Dissipation (TA = +70°C)
16-Pin QSOP (derate at 8.34mW/°C above +70°C).....667mW
Operating Temperature Range (TMIN, TMAX)
MAX6851AEE................................................-40°C to +125°C
Junction Temperature ......................................................+150°C
Storage Temperature Range .............................-65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
(Typical Operating Circuit, V+ = 2.7V to 3.6V, TA = TMIN to TMAX, unless otherwise noted.) (Note 1)
PARAMETER
Operating Supply Voltage
Shutdown Supply Current
SYMBOL
CONDITIONS
MIN
V+
ISHDN
2.7
Shutdown mode, all digital
inputs at V+ or GND
TA = TMIN to
TMAX
Master Clock Frequency (OSC
Internal Oscillator)
I+
fOSC
Master Clock Frequency (OSC
External Oscillator)
OSC = 4MHz
VFLOAD, VFDOUT, VFCLK,
VFBLANK, loaded 100pF
11.5
TA = TMIN to
TMAX
UNITS
3.6
V
1.3
OSC1 fitted with COSC = 56pF, OSC2 fitted
with ROSC = 10kΩ; see the Typical
Operating Circuit
Dead-Clock Protection Frequency
mA
3.0
4
2
µA
30
3.5
TA = +25°C
OSC1 overdriven with external fOSC
MAX
85
TA = +25°C
Operating Supply Current
TYP
MHz
8
200
MHz
kHz
OSC High Time
tCH
50
ns
OSC Low Time
tCL
50
ns
Fast or Slow Segment Blink Duty
Cycle
(Note 2)
49.5
50.5
%
1
µA
LOGIC INPUTS AND OUTPUTS
Input Leakage Current ADO,
SDA, SCL
IIH, IIL
Logic-High Input Voltage ADO,
SDA, SCL
VIH
Logic-Low Input Voltage ADO,
SDA, SCL
VIL
SDA Output Low Voltage
Input Capacitance
2
VOLSDA
CI
0.2
2.4
V
0.6
V
ISINK = 4mA
0.5
V
(Note 2)
10
pF
_______________________________________________________________________________________
2-Wire Interfaced, 7-, 14-, and 16-Segment Alphanumeric Vacuum-Fluorescent Display Controller
(Typical Operating Circuit, V+ = 2.7V to 3.6V, TA = TMIN to TMAX, unless otherwise noted.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
Output Rise and Fall Time
PHASE1, PHASE2, PORT0,
PORT1, PUMP, VFLOAD,
VFDOUT, VFCLK, VFBLANK
tRFT
CLOAD = 100pF
Output High-Voltage
PHASE1, PHASE2, PORT0,
PORT1, PUMP, VFLOAD,
VFDOUT, VFCLK, VFBLANK
VOH
ISOURCE = 10mA
Output Low-Voltage
PHASE1, PHASE2, PORT0,
PORT1, PUMP, VFLOAD,
VFDOUT, VFCLK, VFBLANK
VOL
ISINK = 10mA
MIN
TYP
MAX
UNITS
25
ns
V+ - 0.6
V
0.4
V
Output Short-Circuit Source
Current PHASE1, PHASE2,
PORT0, PORT1, PUMP, VFLOAD,
VFDOUT, VFCLK, VFBLANK
IOHSC
Output programmed high, output short
circuit to GND (Note 2)
62
125
mA
Output Short-Circuit Sink Current
PHASE1, PHASE2, PORT0,
PORT1, PUMP, VFLOAD,
VFDOUT, VFCLK, VFBLANK
IOLSC
Output programmed low, output short
circuit to V+ (Note 2)
72
125
mA
400
kHz
2-WIRE SERIAL INTERFACE TIMING CHARACTERISTICS (Figure 8)
Serial Clock Frequency
fSCL
Bus Free Time Between a STOP
and a START Condition
tBUF
1.3
µs
Hold Time (Repeated) START
Condition
tHD,STA
0.6
µs
Repeated START Condition Setup
Time
tSU,STA
0.6
µs
STOP Condition Setup Time
tSU,STO
0.6
Data Hold Time
tHD,DAT
Data Setup Time
tHD,DAT
µs
0.9
(Note 3)
µs
100
ns
SCL Clock Low Period
tLOW
1.3
µs
SCL Clock High Period
tHIGH
0.6
µs
_______________________________________________________________________________________
3
MAX6851
DC ELECTRICAL CHARACTERISTICS (continued)
MAX6851
2-Wire Interfaced, 7-, 14-, and 16-Segment Alphanumeric Vacuum-Fluorescent Display Controller
DC ELECTRICAL CHARACTERISTICS (continued)
(Typical Operating Circuit, V+ = 2.7V to 3.6V, TA = TMIN to TMAX, unless otherwise noted.) (Note 1)
PARAMETER
SYMBOL
TYP
MAX
UNITS
(Notes 2, 4)
20 +
0.1CB
300
ns
tF
(Notes 2, 4)
20 +
0.1CB
300
ns
Fall Time of SDA Transmitting
tF
(Notes 2, 5)
20 +
0.1CB
250
ns
Pulse Width of Spike Suppressed
tSP
(Note 6)
Capacitive Load for Each Bus
Line
CB
(Note 2)
Rise Time of Both SDA and SCL
Signals, Receiving
tR
Fall Time of Both SDA and SCL
Signals, Receiving
CONDITIONS
MIN
50
ns
400
pF
VFD INTERFACE TIMING CHARACTERISTICS (Figure 16)
VFCLK Clock Period
tVCP
(Note 2)
500
VFCLK Pulse Width High
tVCH
(Note 2)
250
ns
VFCLK Pulse Width Low
tVCL
(Note 2)
250
ns
tVCSH
(Note 2)
19
µs
VFDOUT Setup Time
tVDS
(Note 2)
50
ns
VFLOAD Pulse High
tVCSW
(Note 2)
245
ns
VFCLK Rise to VFD Load Rise
Hold Time
2050
ns
Note 1: All parameters tested at TA = +25°C. Specifications over temperature are guaranteed by design.
Note 2: Guaranteed by design.
Note 3: A master device must provide a hold time of at least 300ns for the SDA signal (referred to VIL of the SCL signal) in order to
bridge the undefined region of SCL’s falling edge.
Note 4: CB = total capacitance of one bus line in pF; tR and tF measured between 0.3V+ and 0.7V+.
Note 5: ISINK ≤ 6mA; CB = total capacitance of one bus line in pF; tR and tF measured between 0.3V+ and 0.7V+.
Note 6: Input filters on the SDA and SCL inputs suppress noise spikes less than 50ns.
4
_______________________________________________________________________________________
2-Wire Interfaced, 7-, 14-, and 16-Segment Alphanumeric Vacuum-Fluorescent Display Controller
SHUTDOWN SUPPLY CURRENT
vs. SUPPLY VOLTAGE
1.4
35
TA = +125°C
TA = -40°C
1.1
30
25
20
1.0
15
0.9
10
0.8
5
0.7
0
2.9
3.1
3.5
3.3
3.7
2.9
3.1
1.2
1.2
1.0
V+ = 3.6V
0.2
0.2
0
0
40
60
ISINK (mA)
80
100
MAX6851 toc07
1.0
0.8
V+ = 3.6V
40
60
ISINK (mA)
80
100
20
V+ = 2.7V
1.6
80
100
1.8
80
V+ = 2.7V
1.6
100
V+ = 3.3V
1.4
V+ = 3.6V
0.8
1.2
1.0
0.8
V+ = 3.6V
0.6
TA = +25°C
TA = +125°C
0.4
0.2
0
0
60
2.0
V+ = 3.3V
1.2
1.0
40
V+ - VOH vs. ISOURCE
0.2
60
ISOURCE (mA)
0
ISINK (mA)
1.8
0.4
0.2
40
TA = +125°C
0.4
0
20
0.6
TA = -40°C
20
V+ = 3.6V
1.0
0.2
1.4
1.2
0
1.2
0.6
TA = +25°C
2.0
V+ = 3.3V
8
V+ = 3.3V
V+ - VOH vs. ISOURCE
V+ = 2.7V
7
0.8
0
V+ - VOH (V)
V+ - VOH (V)
MAX6851 toc05
V+ = 3.6V
V+ - VOH vs. ISOURCE
2.0
6
V+ = 2.7V
1.6
1.4
0.6
0.4
5
1.8
V+ = 3.3V
1.0
0.4
0.4
4
OUTPUT LOW VOLTAGE vs. ISINK
0.8
TA = -40°C
0.6
0.6
3
2.0
MAX6851 toc08
0.8
V+ = 2.7V
1.6
1.4
1.4
2
FREQUENCY (MHz)
1.8
1.4
1.6
3.5
OUTPUT LOW VOLTAGE vs. ISINK
VOL (V)
VOL (V)
V+ = 3.3V
1.8
3.3
2.0
MAX6851 toc04
V+ = 2.7V
20
800
600
400
0
2.7
OUTPUT LOW VOLTAGE vs. ISINK
0
1000
V+ (V)
2.0
1.6
1800
1600
1400
1200
200
TA = -40°C
V+ (V)
1.8
2000
MAX6851 toc06
2.7
TA = +25°C
VOL (V)
1.2
V+ - VOH (V)
1.3
ISUPPLY (µA)
ISUPPLY (mA)
TA = +125°C
40
2400
2200
MAX6851 toc03
1.5
OSC1 = 0
45
MAX6851 toc09
1.6
SHUTDOWN SUPPLY CURRENT (µA)
50
MAX6851 toc01
1.7
SHUTDOWN SUPPLY CURRENT
vs. OSC FREQUENCY
MAX6851 toc02
SUPPLY CURRENT vs. SUPPLY VOLTAGE
0
0
20
40
60
ISOURCE (mA)
80
100
0
20
40
60
80
100
ISOURCE (mA)
_______________________________________________________________________________________
5
MAX6851
Typical Operating Characteristics
(Typical Application Circuit, V+ = 3.3V, TA = +25°C, unless otherwise noted.)
Typical Operating Characteristics (continued)
(Typical Application Circuit, V+ = 3.3V, TA = +25°C, unless otherwise noted.)
DEAD-CLOCK OSC FREQUENCY
vs. TEMPERATURE
fOSC vs. TEMPERATURE
3
V+ = 3.6V
2
MAX6851 toc11
V+ = 3.3V
4
0.36
0.32
0.28
FREQUENCY (MHz)
V+ = 2.7V
MAX6851 toc10
5
fOSC (MHz)
MAX6851
2-Wire Interfaced, 7-, 14-, and 16-Segment Alphanumeric Vacuum-Fluorescent Display Controller
V+ = 3.6V
0.24
0.20
0.16
V+ = 3.3V
0.12
V+ = 2.7V
0.08
1
0.04
0
0
-40 -25 -10 5 20 35 50 65 80 95 110 125
-40 -25 -10 5 20 35 50 65 80 95 110 125
TEMPERATURE (°C)
TEMPERATURE (°C)
Pin Description
6
PIN
NAME
FUNCTION
1
VFCLK
2
VFDOUT
Serial-Data Output to External Driver. Push-pull data output to external display driver.
3
VFLOAD
Serial-Load Output to External Driver. Push-pull load output to external display driver. Rising edge is
used by external display driver to load serial data into display latch.
4
VFBLANK
Display Blanking Output to External Driver. Push-pull blanking output to external display driver used for
PWM intensity control.
5
PUMP
6
PHASE1
Filament Drive PHASE1 Output and General-Purpose Output. User-configurable push-pull logic output
can also be used as a driver for external filament bridge drive.
7
PHASE2
Filament Drive PHASE2 Output and General-Purpose Output. User-configurable push-pull logic output
can also be used as a driver for external filament bridge drive.
Serial-Clock Output to External Driver. Push-pull clock output to external display driver. On VFCLK’s
falling edge, data is clocked out of VFDOUT.
Pump General-Purpose Output. User-configurable push-pull logic output.
8
V+
9
GND
Positive Supply Voltage. Bypass V+ to GND with a 0.1µF ceramic capacitor.
10
PORT0
11
SCL
Serial-Clock Input
12
SDA
Serial-Data Input I/O
13
AD0
Address Input 0. Sets device slave address. Connect to GND, V+, SCL, or SDA to give four logic
combinations. See Table 25.
14
PORT1
Ground
PORT0 General-Purpose Output. User-configurable push-pull logic output.
PORT1 General-Purpose Output. User-configurable push-pull logic output.
_______________________________________________________________________________________
2-Wire Interfaced, 7-, 14-, and 16-Segment Alphanumeric Vacuum-Fluorescent Display Controller
PIN
NAME
FUNCTION
15
OSC1
Multiplex Clock Input 1. To use the internal oscillator, connect capacitor COSC from OSC1 to GND. To
use the external clock, drive OSC1 with a 2MHz to 8MHz CMOS clock.
16
OSC2
Multiplex Clock Input 2. Connect resistor ROSC from OSC2 to GND.
GRID 1
GRID 2
GRID 3
GRID 4
GRID 5
GRID 6
GRID 7
GRID 8
GRID 9
GRID 10
GRID 11
GRID 12
GRID 13
GRID 14
GRID 15
GRID 16
Figure 1. Example of a One-Digit-per-Grid Display
Detailed Description
Overview of the MAX6851
The MAX6851 VFD controller generates the multiplex
timing for the following VFD display types:
• Multiplexed displays with one digit per grid, and up
to 48 grids (in 48/1 mode). Each grid can contain
one 7-, 14-, or 16-segment character, a decimal
place (DP) segment, a cursor segment, and four
extra annunciator segments (Figure 1).
• Multiplexed displays with two digits per grid, and up
to 48 grids (in 96/2 mode). Each grid can contain
two 7-, 14-, or 16-segment characters, two DP segments, and two cursor segments. No annunciator
segments are supported (Figure 2).
Each digit can have a 7-, 14-, or 16-segment character,
a DP segment, a cursor segment, and (for one-digitper-grid displays only) four annunciators (Figure 3).
The 7, 14, or 16 segments use on-chip fonts that map
the segments. The fonts comprise an ASCII 104-character fixed-font set, and 24 user-definable characters.
The predefined characters follow the Arial font, with the
addition of the following common symbols: £, , ¥, °, µ,
±, ↑, and ↓. The 24 user-definable characters are
uploaded by the user into on-chip RAM through the serial
interface and are lost when the device is powered down.
As well as custom 7- and 14-segment characters, the
user-definable fonts can control up to 14 custom segments, bar graph characters, or graphics.
Annunciator segments have individual, independent
control, so any combination of annunciators can be lit.
Annunciators can be off, lit, or blink either in phase or
_______________________________________________________________________________________
7
MAX6851
Pin Description (continued)
MAX6851
2-Wire Interfaced, 7-, 14-, and 16-Segment Alphanumeric Vacuum-Fluorescent Display Controller
GRID 1
GRID 2
GRID 3
GRID 4
GRID 5
GRID 6
GRID 7
GRID 8
Figure 2. Example of a Two-Digit-per-Grid Display
°C °F pH mW
4 ANNUNCIATOR SEGMENTS
14-SEGMENT CHARACTER
DECIMAL POINT (DP) SEGMENT
CURSOR SEGMENT
Figure 3. Digit Structure with 14-Segment Character,
DP Segment, Cursor Segment, and Four Annunciators
VFD TUBE DRIVER
MICROCONTROLLER
SDA
SDA
VFDOUT
VFDIN
SCL
SCL
VFCLK
VFCLK
VFLOAD
VFLOAD
VFBLANK
VFBLANK
VFD TUBE
MAX6851
GRID/
ANODE
DRIVERS
Figure 4. Connection of the MAX6851 to VFD Driver and VFD Tube
8
out of phase with the cursor. The blink-speed control is
software selectable to be one or two blinks per second
(OSC = 4MHz).
DP segments can be lit or off, but have no blink control.
A DP segment is set by the same command that writes
the digit’s 7-, 14-, or 16-segment character.
The cursor segment is controlled differently. A single
register selects one digit’s cursor from the entire display, and that can be lit either continuously or blinking.
All the other digits’ cursors are off.
The designations of DP, cursor, and annunciator are
interchangeable. For example, consider an application
requiring only one DP lit at a time, but the DP needs to
blink. The DP function does not have blink capability.
Instead, the DP segments on the display are routed
(using the output map) to the cursor function. In this
case, the DP segments are controlled using the cursor
register.
The output of the controller is a 4-wire serial stream that
interfaces to industry-standard, shift-register, high-voltage grid/anode VFD tube drivers (Figure 4). This interface uses three outputs to transfer and latch grid and
anode data into the tube drivers, and a fourth output
that enables/disables the tube driver outputs (Figure 6).
The enable/disable control is modulated by the
MAX6851 for both PWM intensity control and interdigit
_______________________________________________________________________________________
2-Wire Interfaced, 7-, 14-, and 16-Segment Alphanumeric Vacuum-Fluorescent Display Controller
f
b
f
i
g1
g
e
h
e
c
m
j
b
f
l
k
a2
h
g2
dp
d
a1
e
j
i
g1
c
MAX6851
a
a
b
g2
m
l
k
dp
c
dp
d
d1
d2
Figure 5. Segment Labeling for 7-, 14-, and 16-Segment Displays
blanking, and disables the tube driver in shutdown. The
controller multiplexes the display by enabling each grid
of the VFD in turn for 100µs (OSC = 4MHz) with the correct segment (anode) data. The data for the next grid is
transferred to the tube drivers during the display time of
the current grid.
The controller uses an internal output map to match any
tube-driver’s shift-register grid/anode order, and is
therefore compatible with all VFD internal chip-in-glass
or external tube drivers.
The MAX6851 provides five high-current output ports,
which can be configured for a variety of functions:
The PUMP output can be configured as either an 80kHz
(OSC = 4MHz) clock intended for DC-to-DC converter
use, the 4-wire serial interface’s DOUT data output, or a
general-purpose logic output.
The PHASE1 and PHASE2 outputs can be individually
configured as either 10kHz PWM outputs (OSC =
4MHz) intended for filament driving, blink status outputs, or general-purpose logic outputs.
The PORT0 and PORT1 outputs can be individually
configured as either 625Hz, 1250Hz, or 2500Hz clocks
(OSC = 4MHz) intended for buzzer driving, the 4-wire
serial interface’s DOUT data output, blink or shutdown
status outputs, or general-purpose logic outputs. Figure
5 shows segment labeling for 7-, 14-, and 16-segment
displays. Figure 6 is a block diagram of the VFD tube
driver and VFD tube.
Display Modes
The MAX6851 has two display modes (Table 1), selected by the M bit in the configuration register (Table 23).
The display modes trade the maximum allowable num-
VFD TUBE DRIVER
VFCLK
SERIAL-TO-PARALLEL SHIFT REGISTER
VFDIN
LATCHES
VFLOAD
VFBLANK
O0
O1
O2
On-2
On-1
On-0
O0
O1
O2
On-2
On-1
On-0
VFD TUBE SIMPLIFIED
Figure 6. Block Diagram of VFD Tube Driver and VFD Tube
ber of digits (96/2 mode) against the availability of
annunciator segments (48/1 mode). Table 2 is the register address map.
Initial Power-Up
On initial power-up, all control registers are reset, the
display segment and annunciator data are cleared,
intensity is set to minimum, and shutdown is enabled
(Table 3).
_______________________________________________________________________________________
9
MAX6851
2-Wire Interfaced, 7-, 14-, and 16-Segment Alphanumeric Vacuum-Fluorescent Display Controller
Table 1. Display Modes
DISPLAY
MODE
MAXIMUM NO. OF
ANNUNCIATORS
MAXIMUM NO. OF DIGITS
48 digits, each with a DP segment and a cursor
segment
96 digits, each with a DP segment and a cursor
96/2 mode
segment
MAXIMUM NO.
OF GRIDS
4 per digit
48/1 mode
DIGITS COVERED
BY EACH GRID
1 digit per grid
48 grids
None
2 digits per grid
Table 2. Register Address Map
COMMAND ADDRESS
D15
D14
D13
D12
D11
D10
D9
D8
HEX
CODE
No-Op
0
0
0
0
0
0
0
0
0x00
VFBLANK polarity
0
0
0
0
0
0
0
1
0x01
Intensity
0
0
0
0
0
0
1
0
0x02
Grids
0
0
0
0
0
0
1
1
0x03
Configuration
0
0
0
0
0
1
0
0
0x04
User-defined fonts
0
0
0
0
0
1
0
1
0x05
Output map
0
0
0
0
0
1
1
0
0x06
Display test and device ID
0
0
0
0
0
1
1
1
0x07
PUMP register
0
0
0
0
1
0
0
0
0x08
Filament duty cycle
0
0
0
0
1
0
0
1
0x09
PHASE1
0
0
0
0
1
0
1
0
0x0A
PHASE2
0
0
0
0
1
0
1
1
0x0B
PORT0
0
0
0
0
1
1
0
0
0x0C
PORT1
0
0
0
0
1
1
0
1
0x0D
REGISTER
Shift limit
0
0
0
0
1
1
1
0
0x0E
Cursor
0
0
0
0
1
1
1
1
0x0F
Factory reserved. Do not write to register.
X
0
0
1
0
0
0
0
0x10
Character Registers
The MAX6851 uses 48 character registers (48/1 mode)
(Table 4) or 96 character registers (96/2 mode) (Table
5) to store the 7-, 14-, and 16-segment characters
(Table 6). Each digit is represented by 1 byte of memory. The data in the character registers does not control
the character segments directly. Instead, the register
data is used to address a character generator, which
stores the data of the 128-character font (Table 7). The
lower 7 bits of the character data (D6 to D0) select a
character from the font table. The most significant bit
(MSB) of the register data (D7) controls the DP segment of the digit; it is set to light the DP, cleared to
leave it unlit.
10
The character registers address maps are shown in
Table 4 (48/1 mode) and Table 5 (96/2 mode).
In 48/1 mode, the character registers use a single
address range 0x20 to {0x20 + g}, where g is the value
in the grids register (Table 28). The 48/1 mode upper
address limit, when g is 0x2F, is therefore 0x4F. The
address range 0x50 to 0x7F is used for annunciator
data in 48/1 mode.
In 96/2 mode, the character registers use two address
ranges. The first row’s address range is 0x20 to
{0x20 + g}. The second row’s address range is 0x50 to
{0x50 + g}. Therefore, in 96/2 mode, the character registers are only one contiguous memory range when a 48grid display is used.
______________________________________________________________________________________
2-Wire Interfaced, 7-, 14-, and 16-Segment Alphanumeric Vacuum-Fluorescent Display Controller
REGISTER DATA
POWER-UP CONDITION
COMMAND
ADDRESS
D7
D6
D5
D4
D3
D2
D1
D0
VFBLANK polarity
VFBLANK is high to disable the
display
0x01
X
X
X
X
X
X
0
0
Intensity
1/16 (min on)
0x02
X
X
X
X
0
0
0
0
Grids
Display has 1 grid
0x03
X
X
0
0
0
0
0
0
Configuration
Shutdown enabled,
configuration unlocked
0x04
1
0
0
0
0
0
0
0
User-defined font
address pointer
Address 0x80; pointing to the
first user-defined font location
0x05
1
0
0
0
0
0
0
0
User-defined fonts
Predefined for hex fonts
Output map pointer
Address 0x80; pointing to first
entry address
0x06
0
0
Output map data
Predefined for 40-digit display
—
REGISTER
—
See Table 11 for power-up patterns.
1
0
0
0
0
0
See Table 32 for power-up patterns.
Display test
Normal operation
0x07
X
X
X
X
X
X
X
0
PUMP
General-purpose output, logic
0x08
0
0
0
0
0
0
0
0
Filament duty cycle
Minimum duty cycle
General-purpose output, logic
0x09
0
0
0
0
0
0
0
1
PHASE1
0x0A
0
0
0
0
0
0
0
0
PHASE2
General-purpose output, logic
0x0B
0
0
0
0
0
0
0
0
PORT0
General-purpose output, logic
0x0C
0
0
0
0
0
0
0
0
PORT1
General-purpose output, logic
0x0D
0
0
0
0
0
0
0
1
Shift limit
1 output bit
0x0E
X
0
0
0
0
0
0
1
Cursor
Off
0x0F
0
1
1
0
0
0
0
0
Character and
annunciator data
Clear
0x20
0
0
0
0
0
0
0
0
UP TO
—
—
—
—
—
—
—
—
0x7F
0
0
0
0
0
0
0
0
—
UP TO
Character and
annunciator data
Clear
Character Generator Font Mapping
The font comprises 104 characters in ROM, and 24
user-definable characters. The selection from the total
of 128 characters is represented by the lower 7 bits of
the 8-bit digit registers. The MSB, shown as X in the
ROM maps (Tables 7 and 8), controls the DP segment
of the digit; it is set to light the DP.
There are two font maps stored in the MAX6851. One
font map covers 14-segment displays (Table 8), and
the other suits 16-segment displays (Table 7). The F bit
in the configuration register (Table 20) selects between
the two font maps. The F bit may be set either high or
low for 7-segment displays; 7-segment displays use a
subset of the 14- or 16-segment display described in
two font maps (Figure 7).
7 SEGMENT
14/16 SEGMENTS
a
a/a1
f
b
f
g
e
MAPS TO
c
d
dp
b
g1
e
c
dp
d/d2
Figure 7. 14- and 16-Segment Fonts Map a Subset of Their 14
or 16 Segments to a 7-Segment Digit
______________________________________________________________________________________
11
MAX6851
Table 3. Initial Power-Up Register Status
MAX6851
2-Wire Interfaced, 7-, 14-, and 16-Segment Alphanumeric Vacuum-Fluorescent Display Controller
Table 4. Character and Annunciator Register Address Map in 48/1 Mode
COMMAND ADDRESS
D15
D14
D13
D12
D11
D10
D9
D8
HEX
CODE
Digit 0 character
0
0
1
0
0
0
0
0
0x20
Digit 1 character
0
0
1
0
0
0
0
1
0x21
Digit 2 character
0
0
1
0
0
0
1
0
0x22
—
—
—
—
—
—
—
—
—
Digit 45 character
0
1
0
0
1
1
0
1
0x4D
Digit 46 character
0
1
0
0
1
1
1
0
0x4E
Digit 47 character
0
1
0
0
1
1
1
1
0x4F
Digit 0 annunciators
0
1
0
1
0
0
0
0
0x50
Digit 1 annunciators
0
1
0
1
0
0
0
1
0x51
Digit 2 annunciators
0
1
0
1
0
0
1
0
0x52
—
—
—
—
—
—
—
—
—
Digit 45 annunciators
0
1
1
1
1
1
0
1
0x7D
Digit 46 annunciators
0
1
1
1
1
1
1
0
0x7E
Digit 47 annunciators
0
1
1
1
1
1
1
1
0x7F
REGISTER
UP TO
UP TO
Table 5. Character Register Address Map in 96/2 Mode
COMMAND ADDRESS
D15
D14
D13
D12
D11
D10
D9
D8
HEX
CODE
Digit 0 character, 1st row
0
0
1
0
0
0
0
0
0x20
Digit 1 character, 1st row
0
0
1
0
0
0
0
1
0x21
Digit 2 character, 1st row
0
0
1
0
0
0
1
0
0x22
0
—
—
—
—
—
—
—
—
Digit 45 character, 1st row
0
1
0
0
1
1
0
1
0x4D
Digit 46 character, 1st row
0
1
0
0
1
1
1
0
0x4E
Digit 47 character, 1st row
0
1
0
0
1
1
1
1
0x4F
Digit 0 character, 2nd row
0
1
0
1
0
0
0
0
0x50
Digit 1 character, 2nd row
0
1
0
1
0
0
0
1
0x51
Digit 2 character, 2nd row
0
1
0
1
0
0
1
0
0x52
REGISTER
UP TO
0
—
—
—
—
—
—
—
—
Digit 45 character, 2nd row
0
1
1
1
1
1
0
1
0x7D
Digit 46 character, 2nd row
0
1
1
1
1
1
1
0
0x7E
Digit 47 character, 2nd row
0
1
1
1
1
1
1
1
0x7F
UP TO
The character map follows the Arial font for 96 characters in the x0100000 through x1111111 range. The first
32 characters map the 24 user-definable positions
(RAM00 to RAM23), plus eight extra common characters in ROM.
12
User-Defined Fonts
The 24 user-definable characters are represented by
48 entries of 7-bit data, two entries per character, and
are stored in the MAX6851’s internal RAM.
______________________________________________________________________________________
2-Wire Interfaced, 7-, 14-, and 16-Segment Alphanumeric Vacuum-Fluorescent Display Controller
MODE
COMMAND ADDRESS
REGISTER DATA
D7
Writing character data to use font map
data with DP segment unlit
0x20 to 0x4F (48/1 mode)
0x20 to 0x7F (96/2 mode)
0
Writing character data to use font map
data with DP segment lit
0x20 to 0x4F (48/1 mode)
0x20 to 0x7F (96/2 mode)
1
D6
D5
D4
D3
D2
D1
D0
Bits D6 to D0 select font characters 0 to 127
The user-definable characters are preloaded on powerup with 24 fonts. These fonts are intended to be useful
for 7-segment displays, and include the hexadecimal
set for the first 16 characters, plus eight other useful
segment combinations. Table 12 shows how the 14-segment and 16-segment fonts map to 7-segment displays.
The 48 user-definable font data entries are written and
read through a single register, address 0x05. An
autoincrementing font address pointer in the MAX6851
indirectly accesses the font data. The font address
pointer can be written, setting one of 48 addresses
between 0x00 and 0x2F, but cannot be read back. The
font data is written to and read from the MAX6851 indirectly, using this font address pointer. Unused font
locations can be used as general-purpose scratch
RAM, bearing in mind that the font registers are only 7
bits wide, not 8.
Table 13 illustrates how to set the font address pointer
to a value within the acceptable range. D7 is set (1) to
denote that the user is writing the font address pointer.
If the user attempts to set the font address to one of the
out-of-range addresses by writing data in range 0xB0
to 0xFF, then address 0x00 is set instead.
The font address pointer autoincrements from address
(the last user font location) to point to address 0x00 (the
first user font location). Thus, the font address pointer
autoincrements indefinitely through font RAM.
Table 9 shows how to use the single user-defined font
register 0x05 to set the font address pointer, write font
data, and read font data. A read action always returns
font data from the font address pointer position. A write
action sets the 7-bit font address pointer if the MSB is
set, or writes 7-bit font data to the font address pointer
position if the MSB is clear.
The font address pointer autoincrements after a valid
access to the user-definable font data. Autoincrementing
allows the 48-font data entries to be written and read
back very quickly because the font pointer address
needs to be set only once. After the last data location
0x2F has been written, further font data entries are
ignored until the font address pointer is reset. If the font
address pointer is set to an out-of-range address by writing data in the 0xB0 to 0xFF range, then address 0x00 is
set instead (Table 10).
Table 11 shows the user-definable font pointer
addresses.
Table 12 shows bit/segment mapping for user-defined
fonts when applied to 7-, 14-, or 16-segment digits.
The 7 least significant bits (LSBs) of the cursor register
identify the cursor position. The MSB is clear for the
cursor to be on continuously, and set for the cursor to
be lit only during the first half of each blink period.
Cursor Register
The cursor register controls the behavior of the cursor
segments (Table 14). The MAX6851 controls 48 cursors
in 48/1 mode, and 96 cursors in 96/2 mode. The cursor
register selects one digit’s cursor to be lit either continuously or blinking. All the other digits’ cursors are off.
The valid cursor position address range is contiguous:
0 to 47 (0x00 to 0x2F) for the first row, and 48 to 95
(0x30 to 0x5F) for the 2nd row. If the cursor register is
programmed with an out-of-range value of 96 to 127
(0x60 to 0x7F), then all cursors are off.
Annunciator Registers
The annunciator registers are organized in bytes, with
each segment of each grid being represented by 2
bits. Thus, the four annunciators segments allowed for
each grid are represented by exactly 1 byte (Table 15).
Annunciators are only available in 48/1 mode. The
annunciator address map is shown in Table 4.
Configuration Register
The configuration register is used to enter and exit shutdown, lock the key VFD configuration settings, select
the blink rate, globally clear the digit and annunciator
data, reset the blink timing, and select between 48/1
and 96/2 display modes (Table 16).
______________________________________________________________________________________
13
MAX6851
Table 6. Character Registers Format
MAX6851
2-Wire Interfaced, 7-, 14-, and 16-Segment Alphanumeric Vacuum-Fluorescent Display Controller
Table 7. 16-Segment Display Font Map
MSB
LSB
x000
x001
x010
x011
x100
x101
x110
Table 8. 14-Segment Display Font Map
x111
MSB
LSB
x000
x001
0000
RAM00
RAM10
0000
RAM00
RAM10
0001
RAM01
RAM11
0001
RAM01
RAM11
0010
RAM02
RAM12
0010
RAM02
RAM12
0011
RAM03
RAM13
0011
RAM03
RAM13
0100
RAM04
RAM14
0100
RAM04
RAM14
0101
RAM05
RAM15
0101
RAM05
RAM15
0110
RAM06
RAM16
0110
RAM06
RAM16
0111
RAM07
RAM17
0111
RAM07
RAM17
1000
RAM08
1000
RAM08
1001
RAM09
1001
RAM09
1010
RAM0A
1010
RAM0A
1011
RAM0B
1011
RAM0B
1100
RAM0C
1100
RAM0C
1101
RAM0D
1101
RAM0D
1110
RAM0E
1110
RAM0E
1111
RAM0F
1111
RAM0F
14
x010
x011
x100
______________________________________________________________________________________
x101
x110
x111
2-Wire Interfaced, 7-, 14-, and 16-Segment Alphanumeric Vacuum-Fluorescent Display Controller
MAX6851
Table 9. Memory Mapping of User-Defined Font Register 0x05
COMMAND
ADDRESS
REGISTER
DATA
READ OR
WRITE
0x05
0x00–0x7F
Read
Read 7-bit user-definable font data entry from current font address. MSB of the
register data is clear. Font address pointer is incremented after the read.
0x05
0x00–0x7F
Write
Write 7-bit user-definable font data entry to current font address. Font address
pointer is incremented after the write.
0x05
0x80–0xFF
Write
Write font address pointer with the register data.
FUNCTION
Table 10. Font Pointer Address Behavior
FONT POINTER
ADDRESS
0x80 to 0xAE
0xAF
0xB0 to 0xFF
ACTION
Valid range to set the font address pointer. Pointer autoincrements after a font data read or write, while pointer
address remains in this range.
Last valid address. Further font data is ignored after a font data read or write to this pointer address.
Invalid range to set the font address pointer. Pointer is set to 0x80.
Table 11. User-Definable Font Pointer Addresses
FONT
CHARACTER
POWER-UP
DEFAULT (BIN)
POWER-UP
CHARACTER
COMMAND
ADDRESS
REGISTER
DATA
RAM00 byte 0
111 1110
7-segment 0
0x05
0x80
RAM00 byte 1
000 0000
—
0x05
0x81
RAM01 byte 0
011 0000
7-segment 1
0x05
0x82
RAM01 byte 1
000 0000
—
0x05
RAM02 byte 0
110 1101
7-segment 2
0x05
RAM02 byte 1
000 0000
—
RAM03 byte 0
111 1001
7-segment 3
RAM03 byte 1
000 0000
RAM04 byte 0
011 0011
RAM04 byte 1
000 0000
—
RAM05 byte 0
101 1011
7-segment 5
0x05
0x8A
RAM05 byte 1
000 0000
—
0x05
0x8B
RAM06 byte 0
101 1111
7-segment 6
0x05
0x8C
RAM06 byte 1
000 0000
—
0x05
RAM07 byte 0
111 0000
7-segment 7
0x05
RAM07 byte 1
000 0000
—
0x05
RAM08 byte 0
111 1111
7-segment 8
0x05
0x90
RAM08 byte 1
000 0000
—
0x05
0x91
RAM09 byte 0
111 1011
7-segment 9
0x05
0x92
RAM09 byte 1
000 0000
—
0x05
RAM10 byte 0
111 0111
7-segment A
0x05
REGISTER DATA
D7
D6
D5
D4
D3
D2
D1
D0
1
0
0
0
0
0
0
0
1
0
0
0
0
0
0
1
1
0
0
0
0
0
1
0
0x83
1
0
0
0
0
0
1
1
0x84
1
0
0
0
0
1
0
0
0x05
0x85
1
0
0
0
0
1
0
1
0x05
0x86
1
0
0
0
0
1
1
0
—
0x05
0x87
1
0
0
0
0
1
1
1
7-segment 4
0x05
0x88
1
0
0
0
1
0
0
0
0x05
0x89
1
0
0
0
1
0
0
1
1
0
0
0
1
0
1
0
1
0
0
0
1
0
1
1
1
0
0
0
1
1
0
0
0x8D
1
0
0
0
1
1
0
1
0x8E
1
0
0
0
1
1
1
0
0x8F
1
0
0
0
1
1
1
1
1
0
0
1
0
0
0
0
1
0
0
1
0
0
0
1
1
0
0
1
0
0
1
0
0x93
1
0
0
1
0
0
1
1
0x94
1
0
0
1
0
1
0
0
______________________________________________________________________________________
15
MAX6851
2-Wire Interfaced, 7-, 14-, and 16-Segment Alphanumeric Vacuum-Fluorescent Display Controller
Table 11. User-Definable Font Pointer Addresses (continued)
FONT
CHARACTER
POWER-UP
DEFAULT (BIN)
RAM10 byte 1
RAM11 byte 0
REGISTER DATA
POWER-UP
CHARACTER
COMMAND
ADDRESS
REGISTER
DATA
D7
D6
000 0000
—
0x05
0x95
1
0
0
1
0
1
0
1
001 1111
7-segment B
0x05
0x96
1
0
0
1
0
1
1
0
RAM11 byte 1
000 0000
—
0x05
0x97
1
0
0
1
0
1
1
1
RAM12 byte 0
100 1110
7-segment C
0x05
0x98
1
0
0
1
1
0
0
0
RAM12 byte 1
000 0000
—
0x05
0x99
1
0
0
1
1
0
0
1
RAM13 byte 0
011 1101
7-segment D
0x05
0x9A
1
0
0
1
1
0
1
0
RAM13 byte 1
000 0000
—
0x05
0x9B
1
0
0
1
1
0
1
1
RAM14 byte 0
100 1111
7-segment E
0x05
0x9C
1
0
0
1
1
1
0
0
RAM14 byte 1
000 0000
—
0x05
0x9D
1
0
0
1
1
1
0
1
RAM15 byte 0
100 0111
7-segment F
0x05
0x9E
1
0
0
1
1
1
1
0
RAM15 byte 1
000 0000
—
0x05
0x9F
1
0
0
1
1
1
1
1
RAM16 byte 0
000 1101
7-segment c
0x05
0xA0
1
0
1
0
0
0
0
0
RAM16 byte 1
000 0000
—
0x05
0xA1
1
0
1
0
0
0
0
1
RAM17 byte 0
001 0101
7-segment n
0x05
0xA2
1
0
1
0
0
0
1
0
RAM17 byte 1
000 0000
—
0x05
0xA3
1
0
1
0
0
0
1
1
RAM18 byte 0
111 0110
7-segment N
0x05
0xA4
1
0
1
0
0
1
0
0
RAM18 byte 1
000 0000
—
0x05
0xA5
1
0
1
0
0
1
0
1
RAM19 byte 0
001 1101
7-segment o
0x05
0xA6
1
0
1
0
0
1
1
0
RAM19 byte 1
000 0000
—
0x05
0xA7
1
0
1
0
0
1
1
1
RAM20 byte 0
000 0101
7-segment r
0x05
0xA8
1
0
1
0
1
0
0
0
RAM20 byte 1
000 0000
—
0x05
0xA9
1
0
1
0
1
0
0
1
RAM21 byte 0
100 1111
7-segment t
0x05
0xAA
1
0
1
0
1
0
1
0
D5
D4
D3
D2
D1
D0
RAM21 byte 1
000 0000
—
0x05
0xAB
1
0
1
0
1
0
1
1
RAM22 byte 0
001 1100
7-segment u
0x05
0xAC
1
0
1
0
1
1
0
0
RAM22 byte 1
000 0000
—
0x05
0xAD
1
0
1
0
1
1
0
1
RAM23 byte 0
011 1011
7-segment y
0x05
0xAE
1
0
1
0
1
1
1
0
RAM23 byte 1
000 0000
—
0x05
0xAF
1
0
1
0
1
1
1
1
Shutdown Mode (S Data Bit D0) Format
The S bit in the configuration register selects shutdown
or normal operation (Table 17). The display driver can
be programmed while in shutdown mode, and shutdown mode is overridden when in display test mode.
For normal operation, set S bit to 1.
tion of shutdown, and the square-wave clock restored
when the MAX6851 comes out of shutdown.
When the MAX6851 is in shutdown mode, the multiplex
oscillator is halted at the end of the current 100µs multiplex period (OSC = 4MHz), and the VFBLANK output is
used to disable the VFD tube driver. Data in the digit
and other control registers remain unaltered.
If the PUMP output is configured as a square-wave
clock, then the PUMP output is forced low for the dura-
When the MAX6851 comes out of shutdown, the external VFD tube driver is presumed to contain invalid data.
The VFBLANK output is used to disable the VFD tube
driver for the first multiplex cycle after exiting shutdown,
clearing any invalid data. The next multiplex cycle uses
newly sent valid data.
16
If the PHASE1 output or PHASE2 output is configured as
a filament driver, then that output is forced low for the
duration of shutdown and the filament drive waveforms
restored when the MAX6851 comes out of shutdown.
______________________________________________________________________________________
2-Wire Interfaced, 7-, 14-, and 16-Segment Alphanumeric Vacuum-Fluorescent Display Controller
MAX6851
Table 12. User-Definable Character Mapping
BIT/SEGMENT MAPPING FOR USER-DEFINABLE FONTS WHEN APPLIED TO 7-SEGMENT DIGITS
FONT BYTE
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
RAMxx byte 0
7-seg a
7-seg b
7-seg c
7-seg d
7-seg e
7-seg f
7-seg g
RAMxx byte 1
No action
No action
No action
No action
No action
No action
No action
BIT/SEGMENT MAPPING FOR USER-DEFINABLE FONTS WHEN APPLIED TO 14-SEGMENT DIGITS
FONT BYTE
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
RAMxx byte 0
7-seg a
7-seg b
7-seg c
7-seg d
7-seg e
7-seg f
7-seg g1
RAMxx byte 1
14-seg g2
14-seg h
14-seg i
14-seg j
14-seg k
14-seg l
14-seg m
BIT/SEGMENT MAPPING FOR USER-DEFINABLE FONTS WHEN APPLIED TO 16-SEGMENT DIGITS
FONT BYTE
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
RAMxx byte 0
7-seg a1
7-seg b
7-seg c
7-seg d2
7-seg e
7-seg f
7-seg g1
RAMxx byte 1
14-seg g2
14-seg h
14-seg i
14-seg j
14-seg k
14-seg l
14-seg m
Table 13. Setting a Font Character to RAM
MODE
COMMAND
ADDRESS
REGISTER DATA
D7
D6
D5
D4
D3
D2
D1
D0
Set font address to minimum (zero) with data 128 or 0x80.
(Note that this address is set as power-up default.)
0x05
1
0
0
0
0
0
0
0
Set font address to maximum (47 or 0x2F) with data 175
or 0xAF.
0x05
1
0
1
0
1
1
1
1
Set font address out of range (48 or 0x30) with data 176
or 0xB0 results in font address pointer being set to zero.
0x05
1
1
1
1
1
0
0
0
1
1
1
UP TO
0x05
UP TO
Set font address out of range (127 or 0x7F) with data 255
or 0xFF results in font address pointer being set to zero.
0x05
1
Read font address.
0x05
0
1
1
1
1
Font address; has value 0x00 to 0xAF
Table 14. Cursor Register Format
REGISTER DATA
COMMAND
ADDRESS
D7
Cursor register.
0x0F
BLINK
1st row digit 0’s cursor is lit continuously.
0x0F
0
0
0
0
0
1st row digit 0’s cursor is lit only for the first half of each
blink period.
0x0F
1
0
0
0
MODE
UP TO
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
0
0
CURSOR POSITION
0x0F
UP TO
2nd row digit 47’s cursor is lit continuously.
0x0F
0
1
0
1
1
1
1
1
2nd row digit 47’s cursor is lit only for the first half of each
blink period.
0x0F
1
1
0
1
1
1
1
1
No cursor is lit.
0x0F
X
1
1
X
X
X
X
X
______________________________________________________________________________________
17
MAX6851
2-Wire Interfaced, 7-, 14-, and 16-Segment Alphanumeric Vacuum-Fluorescent Display Controller
Table 15. Annunciator Registers Format
REGISTER DATA
ANNUNCIATOR BYTE
D7
D6
D5
D4
D3
D2
D1
D0
ANNUNCIATOR ANNUNCIATOR ANNUNCIATOR ANNUNCIATOR
A4
A3
A2
A1
BIT ALLOCATIONS
Annunciator A1 is off.
X
X
X
X
X
X
0
0
Annunciator A1 is lit only for the first half of each blink
period.
X
X
X
X
X
X
0
1
Annunciator A1 is lit only for the second half of each blink
period.
X
X
X
X
X
X
1
0
Annunciator A1 is lit continuously.
X
X
X
X
X
X
1
1
Annunciator A2 is off.
X
X
X
X
0
0
X
X
Annunciator A2 is lit only for the first half of each blink
period.
X
X
X
X
0
1
X
X
Annunciator A2 is lit only for the second half of each blink
period.
X
X
X
X
1
0
X
X
Annunciator A2 is lit continuously.
X
X
X
X
1
1
X
X
Annunciator A3 is off.
X
X
0
0
X
X
X
X
Annunciator A3 is lit only for the first half of each blink
period.
X
X
0
1
X
X
X
X
Annunciator A3 is lit only for the second half of each blink
period.
X
X
1
0
X
X
X
X
Annunciator A3 is lit continuously.
X
X
1
1
X
X
X
X
Annunciator A4 is off.
0
0
X
X
X
X
X
X
Annunciator A4 is lit only for the first half of each blink
period.
0
1
X
X
X
X
X
X
Annunciator A4 is lit only for the second half of each blink
period.
1
0
X
X
X
X
X
X
Annunciator A4 is lit continuously.
1
1
X
X
X
X
X
X
Table 16. Configuration Register Format
MODE
Configuration
register
REGISTER DATA
D7
D6
D5
D4
D3
D2
D1
D0
P
M
R
T
F
B
L
S
Table 17. Shutdown Control (S Data Bit
D0) Format
MODE
REGISTER DATA
D7
D6
D5
D4
D3
D2
D1
D0
Shutdown
P
M
R
T
F
B
L
0
Normal operation
P
M
R
T
F
B
L
1
18
Configuration Lock (L Data Bit D1) Format
The configuration lock register is a safety feature to
reduce the risk of the VFD configuration settings being
inadvertently changed due to spurious writes if software fails. When set, the shift-limit register (0x0E), grids
register (0x03), and output map data (0x06) can be
read but cannot be written. The output map data pointer itself may be written in order to allow the output map
data to be read back (Table 18).
Blink Rate Selection (B Data Bit D2) Format
The B bit in the configuration register selects the blink
rate of the cursor and annunciator segments. This is the
speed that the segments blink on and off when blinking is
selected for these segments. The frequency of the multiplex clock OSC and the setting of the B bit (Table 19)
determine the blink rate.
______________________________________________________________________________________
2-Wire Interfaced, 7-, 14-, and 16-Segment Alphanumeric Vacuum-Fluorescent Display Controller
MODE
REGISTER DATA
D7
D6
D5
D4
D3
D2
D1
D0
Unlocked
P
M
R
T
F
B
0
S
Locked
P
M
R
T
F
B
1
S
Font Selection (F Data Bit D3) Format
The F bit (Table 20) selects the internal font map
between 14-segment and 16-segment displays. If a 7segment display is used, the F bit can be either set or
cleared.
Global Blink Timing Synchronization
(T Data Bit D4) Format
Setting the T bit in multiple MAX6851s at the same time
(or in quick succession) synchronizes the blink timing
across all the devices (Table 21). The display multiplexing sequence is also reset, which can give rise to a
one-time display flicker when the register is written.
Global Clear Digit Data (R Data Bit D5) Format
When the R bit (Table 22) is set, the segment and
annunciator data are cleared.
Display Mode (M Data Bit D6) Format
The M bit (Table 23) selects the display modes (Table 1).
The display modes trade maximum allowable number of
digits (mode 96/2) against the availability of annunciator
segments (mode 48/1).
Blink Phase Readback (P Data Bit D7) Format
When the configuration register is read, the P bit
reflects the blink phase at that time (Table 24).
Serial Interface
Serial Addressing
The MAX6851 operates as a slave that sends and
receives data through an I2C-compatible 2-wire interface. The interface uses a serial data line (SDA) and a
serial clock line (SCL) to achieve bidirectional communication between master(s) and slave(s). A master (typically a microcontroller) initiates all data transfers to and
from the MAX6851, and generates the SCL clock that
synchronizes the data transfer (Figure 8).
The MAX6851 SDA line operates as both an input and
an open-drain output. A pullup resistor, typically 4.7kΩ,
is required on the SDA. The MAX6851 SCL line operates only as an input. A pullup resistor, typically 4.7kΩ,
is required on SCL if there are multiple masters on the
2-wire interface, or if the master in a single-master system has an open-drain SCL output.
Each transmission consists of a START condition
(Figure 9) sent by a master, followed by the MAX6851
7-bit slave address plus R/W bit (Figure 10), a register
address byte, 1 or more data bytes, and finally a STOP
condition (Figure 9).
Start and Stop Conditions
Both SCL and SDA remain high when the interface is
not busy. A master signals the beginning of a transmission with a START (S) condition by transitioning SDA
from high to low while SCL is high. When the master
has finished communicating with the slave, it issues a
STOP (P) condition by transitioning the SDA from low to
high while SCL is high. The bus is then free for another
transmission (Figure 9).
Bit Transfer
One data bit is transferred during each clock pulse.
The data on the SDA line must remain stable while SCL
is high (Figure 11).
Acknowledge
The acknowledge bit is a clocked 9th bit that the recipient uses to handshake receipt of each byte of data
(Figure 12). Thus, each byte transferred effectively
requires 9 bits. The master generates the 9th clock
pulse, and the recipient pulls down SDA during the
acknowledge clock pulse, such that the SDA line is stable low during the high period of the clock pulse. When
the master is transmitting to the MAX6851, the
MAX6851 generates the acknowledge bit because the
MAX6851 is the recipient. When the MAX6851 is transmitting to the master, the master generates the
acknowledge bit because the master is the recipient. In
this case, the master acknowledges all bytes received
from the MAX6853 except for the last byte required,
after which the master issues a STOP condition to signify end of transmission.
Slave Address
The MAX6851 has a 7-bit-long slave address (Figure
10). The eighth bit following the 7-bit slave address is
the R/ W bit. Set it low for a write command, high for a
read command.
The first 5 bits (MSBs) of the MAX6851 slave address
are always 11101. Slave address bits A1 and A0 correspond to the state of the address input pin AD0. This
input may be connected to GND, V+, SDA, or SCL. The
MAX6851 has four possible slave addresses and therefore a maximum of four MAX6851 devices may share
the same interface.
______________________________________________________________________________________
19
MAX6851
Table 18. Configuration Lock (L Data Bit
D1) Format
MAX6851
2-Wire Interfaced, 7-, 14-, and 16-Segment Alphanumeric Vacuum-Fluorescent Display Controller
Table 19. Blink Rate Selection (B Data Bit D2) Format
MODE
REGISTER DATA
D7
D6
D5
D4
D3
D2
D1
Slow blinking (cursor and annunciators blink on for 1s, off for 1s, for OSC = 4MHz)
P
M
R
T
F
0
L
D0
S
Fast blinking (cursor and annunciators blink on for 0.5s, off for 0.5s, for OSC = 4MHz)
P
M
R
T
F
1
L
S
D7
D6
D5
D4
D3
D2
D1
D0
14- and 7-segment fonts
P
M
R
T
0
B
L
S
16- and 7-segment fonts
P
M
R
T
1
B
L
S
D1
D0
Table 20. Font Selection (F Data Bit D3) Format
REGISTER DATA
MODE
Table 21. Global Blink Timing Synchronization (T Data Bit D4) Format
MODE
REGISTER DATA
D7
D6
D5
D4
D3
D2
Blink timing counters are unaffected.
P
M
R
0
F
B
L
S
Blink timing counters are cleared at the end of the present multiplex cycle.
P
M
R
1
F
B
L
S
D7
D6
D5
D4
D3
D2
D1
D0
Segment and annunciator data are unaffected.
P
M
0
T
F
B
L
S
Segment and annunciator data (address range 0x20 to 0x7F) are cleared during the
I2C acknowledge.
P
M
1
T
F
B
L
S
D7
D6
D5
D1
D0
Table 22. Global Clear Digit Data (R Data Bit D5) Format
MODE
REGISTER DATA
Table 23. Display Mode (M Data Bit D6) Format
MODE
DISPLAY TYPE
REGISTER DATA
D4
D3
D2
48/1
Up to 48 digits, 1 digit per grid
P
0
R
T
F
B
L
S
96/2
Up to 96 digits, 2 digits per grid
P
1
R
T
F
B
L
S
D7
D6
D5
D4
D3
D2
D1
D0
P1 blink phase
0
M
R
T
F
B
L
S
P0 blink phase
1
M
R
T
F
B
L
S
Table 24. Blink Phase Readback (P Data Bit D7) Format
MODE
20
REGISTER DATA
______________________________________________________________________________________
2-Wire Interfaced, 7-, 14-, and 16-Segment Alphanumeric Vacuum-Fluorescent Display Controller
MAX6851
SDA
tSU, STA
tSU, DAT
tLOW
tBUF
tHD, STA
tHD, DAT
tSU, STO
SCL
tHIGH
tHD, STA
tR
tF
START
CONDITION
REPEATED START
CONDITION
STOP
CONDITION
START
CONDITION
Figure 8. 2-Wire Serial Interface Timing Details
SDA
SCL
S
P
START CONDITION
STOP CONDITION
Figure 9. Start and Stop Conditions
SDA
1
START
1
0
A3
A2
A1
MSB
R/W
A0
ACK
LSB
SCL
Figure 10. Slave Address
START CONDITION
SCL
CLOCK PULSE FOR ACKNOWLEDGMENT
1
2
8
9
SDA
SDA
BY TRANSMITTER
SCL
DATA LINE STABLE, CHANGE OF DATA
DATA VALID
ALLOWED
Figure 11. Bit Transfer
SDA
BY RECEIVER
S
Figure 12. Acknowledge
______________________________________________________________________________________
21
MAX6851
2-Wire Interfaced, 7-, 14-, and 16-Segment Alphanumeric Vacuum-Fluorescent Display Controller
Message Format for Writing
A write to the MAX6851 comprises the transmission of
the MAX6851’s slave address with the R/W bit set to
zero, followed by at least 1 byte of information. The first
byte of information is the command byte, which determines which register of the MAX6851 is to be written by
the next byte, if received. If a STOP condition is detected after the command byte is received, then the
MAX6851 takes no further action (Figure 13) beyond
storing the command byte.
Any bytes received after the command byte are data
bytes. The first data byte goes into the internal register of
the MAX6851 selected by the command byte (Figure 14).
If multiple data bytes are transmitted before a STOP
condition is detected, these bytes are generally stored
in subsequent MAX6851 internal registers because the
command byte address generally autoincrements
(Table 26) (Figure 15).
Message Format for Reading
The MAX6851 is read using the MAX6851’s internally
stored command byte as address pointer, the same
way the stored command byte is used as address
pointer for a write. The pointer generally autoincrements after each data byte is read using the same rules
as for a write (Table 26). Thus, a read is initiated by first
configuring the MAX6851’s command byte by perform-
ing a write (Figure 13). The master can now read n consecutive bytes from the MAX6851, with the first data
byte being read from the register addressed by the initialized command byte (Figure 15). When performing
read-after-write verification, reset the command byte’s
address because the stored byte address generally is
autoincremented after the write (Table 26).
Operation with Multiple Masters
If the MAX6851 is operated on a 2-wire interface with
multiple masters, a master reading the MAX6851
should use a repeated start between the write, which
sets the MAX6851’s address pointer, and the read(s)
that takes the data from the location(s). This is because
it is possible for master 2 to take over the bus after
master 1 has set up the MAX6851’s address pointer but
before master 1 has read the data. If master 2 subsequently changes the MAX6851’s address pointer, then
master 1’s delayed read may be from an unexpected
location.
Command Address Autoincrementing
Address autoincrementing allows the MAX6851 to be
configured with the shortest number of transmissions
by minimizing the number of times the command byte
needs to be sent. The command address stored in the
MAX6851 generally increments after each data byte is
written or read (Table 26).
Table 25. MAX6851 Address Map
PIN CONNECTION
DEVICE ADDRESS
AD0
A6
A5
A4
A3
A2
A1
A0
GND
1
1
1
0
1
0
0
1
V+
1
1
1
0
1
0
SDA
1
1
1
0
1
1
0
SCL
1
1
1
0
1
1
1
Table 26. Command Address Autoincrement Rules
COMMAND BYTE
ADDRESS RANGE
x0000000 to x0000100
X0000101, x0000110
X0010000
x0010001 to x1111110
x1111111
22
AUTOINCREMENT BEHAVIOR
Command byte address autoincrements after byte read or written.
Command byte address remains at x0000101 or x0000110 after byte read or written, but
the font address pointer (x0000101) or output map address pointer (x0000110) autoincrements.
Factory reserved; do not write to this register.
Command byte address autoincrements after byte read or written.
Command byte address remains at x1111111 after byte read or written.
______________________________________________________________________________________
2-Wire Interfaced, 7-, 14-, and 16-Segment Alphanumeric Vacuum-Fluorescent Display Controller
D14
D13
D12
D11
D10
D9
MAX6851
D15
COMMAND BYTE IS STORED ON RECEIPT OF STOP CONDITION
D8
ACKNOWLEDGE FROM MAX6851
S
SLAVE ADDRESS
0
A
COMMAND BYTE
A
R/W
P
ACKNOWLEDGE FROM MAX6851
Figure 13. Command Byte Received
ACKNOWLEDGE FROM MAX6851
HOW CONTROL BYTE AND DATA BYTE MAP INTO
MAX6851's REGISTERS
D15
D14
D13
D12
D11
D10
D9
ACKNOWLEDGE FROM MAX6851
D8
D7
D6
D5
D4
D3
D2
D1
D0
ACKNOWLEDGE FROM MAX6851
S
SLAVE ADDRESS
0
A
COMMAND BYTE
A
DATA BYTE
A
P
A
P
1 BYTE
R/W
AUTOINCREMENT MEMORY WORD ADDRESS
Figure 14. Command and Single Data Byte Received
ACKNOWLEDGE FROM MAX6851
HOW CONTROL BYTE AND DATA BYTE MAP INTO
MAX6851's REGISTERS
D15
D14
D13
D12
D11
D10
D9
ACKNOWLEDGE FROM MAX6851
D8
D7
D6
D5
D4
D3
D2
D1
D0
ACKNOWLEDGE FROM MAX6851
S
SLAVE ADDRESS
0
A
COMMAND BYTE
R/W
A
DATA BYTE
n BYTE
AUTOINCREMENT MEMORY WORD ADDRESS
Figure 15. n Data Bytes Received
VFD Driver Serial Interface
The VFD driver interface on the MAX6851 is a serial
interface using three output pins, VFLOAD, VFCLK, and
VFDOUT (Figure 16) to drive industry-standard, shiftregister, high-voltage grid/anode VFD tube drivers
(Figures 4 and 6). The speed of VFCLK is 1MHz when
OSC is 4MHz. The maximum speed of VFCLK is 2MHz
when OSC is 8MHz. This interface is used to transfer
display data from the MAX6851 to the VFD tube driver.
The serial interface bit stream output is programmable
up to 84 bits, which are labeled DD0–DD83.
The functions of the three interface pins are as follows:
VFCLK is the serial clock output, which shifts data on
its falling edge from the MAX6851’s 84-bit output shift
register to VFLOAD.
VFDOUT is the serial data output. The data changes on
VFCLK’s falling edge, and is stable when it is sampled
by the display driver on the rising edge of VFCLK.
VFLOAD is the latch-load output. VFLOAD is high to
transfer data from the display tube driver’s shift register to
the display driver’s output latch (transparent mode), and
low to retain that data in the display driver’s output latch.
A fourth output pin, VFBLANK, provides gating control
of the tube driver. VFBLANK can be configured to be
either high or low using the VFBLANK polarity register
(Table 29) to enable the VFD tube driver. In the default
condition, VFBLANK is high to disable the VFD tube driver, which is expected to force its driver outputs low to
blank the display without altering the contents of its output latches. In the default condition, VFBLANK is low to
______________________________________________________________________________________
23
MAX6851
2-Wire Interfaced, 7-, 14-, and 16-Segment Alphanumeric Vacuum-Fluorescent Display Controller
• The VFCLK and VFDOUT outputs are used to fill the
external VFD driver’s shift register with the multiplex
data for the next grid, during the multiplex timeslot
for the current grid.
• The VFLOAD output loads the new grid-anode data
pattern at the start of its multiplex cycle.
enable its VFD tube driver outputs to follow the state of
the VFD tube driver’s output latches. The VFBLANK
output is used for PWM intensity control and to disable
the VFD tube driver in shutdown.
Multiplex Architecture
The multiplex engine transmits grid and anode control
data to the external VFD driver using the VFCLK, VFDOUT, and VFLOAD. The number of data bits M transmitted is set by the user in the shift-limit register (Table
31). Figure 17 is the VFD multiplex timing diagram.
The essential rules for multiplex action are as follows:
• The external VFD driver’s data latch contains the
data for the current grid being displayed.
• The VFBLANK input is controlled to provide the
PWM intensity control.
Grids Register
The grids register sets how many grids are multiplexed
from 1 to 48 (Table 27).
When the grids register is written, the external VFD tube
driver is presumed to contain invalid data. The
VFBLANK output is used to disable the VFD tube driver
for the first multiplex cycle after exiting shutdown, clearing any invalid data. The next multiplex cycle uses
newly sent, valid data. If the grids register is written
with an out-of-range value of 0x30 to 0xFF, then the
value 0x2F is stored instead.
VFLOAD
tVCSW
tVCL
tVCH
tVCSH
tVCP
VFCLK
tVDS
VFDOUT
DD0
M (M IS VALUE IN SHIFT-LIMIT REGISTER)
M-1
DD1
Figure 16. VFD Interface Timing Diagram
START OF NEXT
CYCLE
ONE COMPLETE MULTIPLEX CYCLE AROUND N GRIDS (OSC = 4MHz)
100µs TIMESLOT
GRID 0
100µs TIMESLOT
GRID 1
100µs TIMESLOT
GRID N-4
100µs TIMESLOT
GRID N-3
100µs TIMESLOT
GRID N-2
100µs TIMESLOT
GRID N-1
100µs TIMESLOT
GRID 0
500ns 500ns 500ns 500ns
GRID 0's 100µs MULTIPLEX TIMESLOT
VFCLK
VFDOUT
DD0
DD1 DD2
DD3
DD4 DD5 DD6 DD7
DD8 DD9 DD10
M-4
M-3
M-2 M-1
M
(M IS VALUE IN SHIFT-LIMIT REGISTER)
GRID 1's DATA, SENT DURING GRID 0's TIMESLOT
VFLOAD
Figure 17. VFD Multiplex Timing Diagram
24
______________________________________________________________________________________
2-Wire Interfaced, 7-, 14-, and 16-Segment Alphanumeric Vacuum-Fluorescent Display Controller
REGISTER DATA
COMMAND
ADDRESS
D7
D6
D5
D4
D3
D2
D1
D0
Display has 1 grid: G0 (always)
0x03
0
0
0
0
0
0
0
0
0x00
Display has 2 grids: G0 and G1
0x03
0
0
0
0
0
0
0
1
0x01
Display has 3 grids: G0 to G2
0x03
0
0
0
0
0
0
1
0
0x02
Display has 4 grids: G0 to G3
0x03
0
0
0
0
0
0
1
1
0x03
0x03
0
0
—
—
—
—
—
—
—
Display has 45 grids: G0 to G44
0x03
0
0
1
0
1
1
0
0
0x2C
Display has 46 grids: G0 to G45
0x03
0
0
1
0
1
1
0
1
0x2D
Display has 47 grids: G0 to G46
0x03
0
0
1
0
1
1
1
0
0x2E
Display has 48 grids: G0 to G47
0x03
0
0
1
0
1
1
1
1
0x2F
GRIDS
UP TO
HEX CODE
Table 28. Intensity Register Format
REGISTER DATA
DUTY CYCLE
VFBLANK BEHAVIOR
(OSC = 4MHz)
COMMAND
ADDRESS
D7
D6
D5
D4
D3
D2
D1
D0
HEX
CODE
1/16 (min on)
High for 6.25µs, low for 6.25µs, high for 87.5µs
0x02
X
X
X
X
0
0
0
0
0xX0
2/16
High for 6.25µs, low for 12.5µs, high for
81.25µs
0x02
X
X
X
X
0
0
0
1
0xX1
3/16
High for 6.25µs, low for 18.75µs, high for 75µs
0x02
X
X
X
X
0
0
1
0
0xX2
4/16
High for 6.25µs, low for 25µs, high for 68.75µs
0x02
X
X
X
X
0
0
1
1
0xX3
5/16
High for 6.25µs, low for 31.25µs, high for
62.5µs
0x02
X
X
X
X
0
1
0
0
0xX4
6/16
High for 6.25µs, low for 37.5µs, high for
56.25µs
0x02
X
X
X
X
0
1
0
1
0xX5
7/16
High for 6.25µs, low for 43.75µs, high for 50µs
0x02
X
X
X
X
0
1
1
0
0xX6
8/16
High for 6.25µs, low for 50µs, high for 43.75µs
0x02
X
X
X
X
0
1
1
1
0xX7
9/16
High for 6.25µs, low for 56.25µs, high for
37.5µs
0x02
X
X
X
X
1
0
0
0
0xX8
10/16
High for 6.25µs, low for 62.5µs, high for
31.25µs
0x02
X
X
X
X
1
0
0
1
0xX9
11/16
High for 6.25µs, low for 68.75µs, high for 25µs
0x02
X
X
X
X
1
0
1
0
0xXA
12/16
High for 6.25µs, low for 75µs, high for 18.75µs
0x02
X
X
X
X
1
0
1
1
0xXB
13/16
High for 6.25µs, low for 81.25µs, high for
12.5µs
0x02
X
X
X
X
1
1
0
0
0xXC
14/16
High for 6.25µs, low for 87.5µs, high for 6.25µs
0x02
X
X
X
X
1
1
0
1
0xXD
15/16
High for 6.25µs, low for 93.75µs
0x02
X
X
X
X
1
1
1
0
0xXE
15/16 (max on)
High for 6.25µs, low for 93.75µs
0x02
X
X
X
X
1
1
1
1
0xXF
______________________________________________________________________________________
25
MAX6851
Table 27. Grids Register Format
MAX6851
2-Wire Interfaced, 7-, 14-, and 16-Segment Alphanumeric Vacuum-Fluorescent Display Controller
START OF NEXT
CYCLE
ONE COMPLETE MULTIPLEX CYCLE AROUND N GRIDS (OSC = 4MHz)
100µs TIMESLOT
GRID 0
100µs TIMESLOT
GRID 1
100µs TIMESLOT
GRID N-4
100µs TIMESLOT
GRID N-3
100µs TIMESLOT
GRID N-2
100µs TIMESLOT
GRID N-1
100µs TIMESLOT
GRID 0
MINIMUM 6.25µs INTERDIGIT
BLANKING INTERVAL (OSC = 4MHz)
VFBLANK
GRID 0'S 100µs MULTIPLEX TIMESLOT
1/16TH
(MIN ON)
2/16TH
3/16TH
4/16TH
5/16TH
6/16TH
7/16TH
8/16TH
9/16TH
10/16TH
11/16TH
12/16TH
13/16TH
14/16TH
15/16TH
15/16TH
(MAX ON)
Figure 18. BLANK and Intensity Timing Diagram
26
______________________________________________________________________________________
2-Wire Interfaced, 7-, 14-, and 16-Segment Alphanumeric Vacuum-Fluorescent Display Controller
REGISTER DATA
COMMAND
ADDRESS
D7
D6
D5
D4
D3
D2
D1
D0
HEX
CODE
VFBLANK is high to disable the display.
0x01
X
X
X
X
X
X
0
0
0xX0
VFBLANK is low to disable the display.
0x01
X
X
X
X
X
X
1
0
0xX2
GRIDS
Table 30. Display-Test and Device ID Register Format
REGISTER DATA
COMMAND
ADDRESS
D7
D6
D5
D4
D3
D2
D1
D0
Normal operation
0x07
X
X
X
X
X
X
X
0
Display test
0x07
X
X
X
X
X
X
X
1
Read MAX6851 device ID and display test status
0x07
0
0
0
0
0
1
0
DT
MODE
Table 31. Shift-Limit Register Format
REGISTER DATA
COMMAND
ADDRESS
D7
D6
D5
D4
D3
D2
D1
D0
Minimum setting example (01)
0x0E
0
0
0
0
0
0
0
1
0x01
Maximum setting example (83 or 0x53)
0x0E
0
1
1
1
1
0
0
1
0x53
SHIFT LIMIT
Intensity Register
Digital control of display brightness is provided by pulsewidth modulation of the tube blanking time, which is controlled by the lower nibble of the intensity register (Table
28). The modulator scales the VFBLANK output in 15
steps from a minimum of 1/16 up to 15/16 of each grid’s
multiplex period. Figure 18 shows the modulator behavior
when the VFBLANK polarity register is set to 0x00 (Table
29), so VFBLANK is high to disable (blank) the display.
The minimum off-time period of a 1/16 multiplex period
(6.25µs with OSC = 4MHz) is always at the start of the
multiplex cycle. This allows time for slow display drivers
to turn off, and slow display phosphors time to decay
between grids. Thus, image ghosting is avoided. If a
display has very slow phosphor, then the allowed decay
time can be doubled by not using a 15/16 duty cycle.
VFBLANK Polarity Register
The VFBLANK polarity register sets the active level of
the VFBLANK output pin (Table 29).
No-Op Register
A write to the no-op register is ignored.
Display-Test and Device ID Register
Writing the display-test and device ID register switches
the drivers between one of two modes: normal and display test. Display-test mode turns all segments and
HEX CODE
annunciators on and sets the duty cycle to 7/16 (halfpower) (Table 30).
Reading the display-test and device ID register returns
the MAX6851 device ID 0b0000 010 that identifies the
driver type, plus the display-test status in the LSB.
Output Shift-Limit Register
The output serial interface is used to transfer display
data from the MAX6851 to the display driver. The serial
interface bit-stream output length is programmable up
to 84 bits, which are labeled DD0–DD83. Set the number of bits with the shift-limit register, address 0x0E. If
the shift-limit register is written with an out-of-range
value 0x54 to 0xFF, then the value 0x53 is stored
instead. Table 31 shows the shift-limit register.
Output Map
The output map comprises 84 words of 7-bit RAM. The
output map data should be written when the MAX6851
is configured after power-up. Table 32 shows the output map RAM codes.
The output map is an indirect addressing reference
table. It translates bit position in the output shift register
(valid range: from zero to the value in shift-limit register
0E, which has a maximum of 83) to bit function. Any
output shift-register bit position may be set to any grid
character segment, DP segment, annunciator segment,
or cursor segment.
______________________________________________________________________________________
27
MAX6851
Table 29. VFBLANK Polarity Register Format
MAX6851
2-Wire Interfaced, 7-, 14-, and 16-Segment Alphanumeric Vacuum-Fluorescent Display Controller
Table 32. Output Map RAM Codes
OUTPUT MAP RAM
CONTENT
ADDRESS RANGE
ADDRESSED FUNCTION
0 to 47
48 grids
Grid 0 to grid 47
48
7-segment a
14-segment a
16-segment a1
49
7-segment b
14-segment b
16-segment b
50
7-segment c
14-segment c
16-segment c
51
7-segment d
14-segment d
16-segment d2
52
7-segment e
14-segment e
16-segment e
53
7-segment f
14-segment f
16-segment f
54
7-segment g
14-segment g1
16-segment g1
55
No action
14-segment g2
16-segment g2
No action
14-segment h
16-segment h
16-segment I
17 character segments
56
57
Digits 0 to 47 only, 1st row
No action
14-segment I
58
No action
14-segment j
16-segment j
59
No action
14-segment k
16-segment k
60
No action
14-segment l
16-segment l
61
No action
14-segment m
16-segment m
62
No action
No action
16-segment a2
63
No action
No action
16-segment d1
64
7-segment dp
14-segment dp
16-segment dp
65
7-segment a
14-segment a
16-segment a1
66
7-segment b
14-segment b
16-segment b
67
7-segment c
14-segment c
16-segment c
68
7-segment d
14-segment d
16-segment d2
69
7-segment e
14-segment e
16-segment e
70
7-segment f
14-segment f
16-segment f
7-segment g
14-segment g1
16-segment g1
No action
14-segment g2
16-segment g2
No action
14-segment h
16-segment h
No action
14-segment I
16-segment I
No action
14-segment j
16-segment j
76
No action
14-segment k
16-segment k
77
No action
14-segment l
16-segment l
78
No action
14-segment m
16-segment m
79
No action
No action
16-segment a2
80
No action
No action
16-segment d1
81
7-segment dp
14-segment dp
16-segment dp
71
17 character segments
72
73
74
75
28
Digits 0 to 47 only, 2nd row
Only valid for 96/2 mode
(display mode select bit M = 1)
______________________________________________________________________________________
2-Wire Interfaced, 7-, 14-, and 16-Segment Alphanumeric Vacuum-Fluorescent Display Controller
MAX6851
Table 32. Output Map RAM Codes (continued)
OUTPUT MAP RAM
CONTENT
ADDRESS RANGE
ADDRESSED FUNCTION
4 annunciators
82 to 85
86
Only valid for 48/1 mode
(display mode select bit M = 0)
Cursor
Annunciator A1 to annunciator A4
Cursor segment for digits 0 to 47 on 1st row
Cursor
87
88 to 127
Only valid for 96/2 mode
(display mode select bit M = 1)
Unused
The power-up default pattern for output map RAM
maps a 40-digit, two-digits-per-grid display with DPs
and cursors (Table 33).
If the user selects an unused map RAM entry (88–127)
for an output shift-register position, then the corresponding output bit is always low (segment or grid OFF).
When selecting an invalid map RAM entry (for example,
codes 48 to 83 to select annunciators in 96/2 mode,
which does not support annunciators), the corresponding output bit is always low (segment or grid OFF).
If the map RAM entry corresponds to a nonexistent font
segment (no action in Table 33) when the digit data is
processed through the character font, then the result
again is zero (segment or grid OFF).
The output map data is indirectly accessed by an
autoincrementing output map address pointer in the
MAX6851 at address 0x06. The output map address
pointer can be written (i.e., set to an address between
0x00 and 0x53) but cannot be read back. The output
map data is written and read back through the output
map address pointer.
Table 34 shows how to set the output map address
pointer to a value within the acceptable range. Bit D7 is
set to denote that the user is writing the output map
address pointer. If the user attempts to set the output
map address to one of the out-of-range addresses by
writing data in range 0xD4 to 0xFF, then address 0x00
is set instead.
After the last data location 0x53 has been written, further output map data entries are ignored until the output map address pointer is reset.
The output map data can be written to the address set
by the output map address pointer. Bit D7 is clear to
Cursor segment for digits 0 to 47 on 2nd row
No action
denote that the user is writing actual output map data.
The output map address pointer is autoincremented
after the output map data has been written to the current location. If the user writes the output map data in
the RAM order, then the output map address pointer
need only be set once, or even not at all as the address
is set to 0x00 as power-up default (Table 35).
The output map data can be read by reading address
0x86. The 7-bit output map data at the address set by the
output map address pointer is read back, with the MSB
clear. The output map address pointer is autoincremented after the output map data has been read from the current location, in the same way as for a write (Table 36).
Filament Drive
The VFD filament is typically driven with an AC waveform, supplied by a center-tapped 50Hz or 60Hz power
transformer as part of the system power supply.
However, if the system has only DC supplies available,
the filament must be powered by a DC-to-AC or DC-toDC converter.
The MAX6851 can generate the waveforms on the
PHASE1 and PHASE2 outputs to drive the VFD filament
using a full bridge (push-pull drive). The PHASE1 and
PHASE2 outputs can be used as general-purpose outputs if the filament drive is not required. The bridge
drive transistors are external, but the waveforms are
generated by the MAX6851.
The waveform generation uses PWM to set the effective
RMS voltage across the filament, as a fraction of the
external supply voltage (Figure 19) (Table 37). The filament switching frequency is synchronized to the multiplex scan clock, eliminating beating artifacts due to
differing filament and multiplex frequencies.
______________________________________________________________________________________
29
MAX6851
2-Wire Interfaced, 7-, 14-, and 16-Segment Alphanumeric Vacuum-Fluorescent Display Controller
The PWM duty cycle is controlled by the filament dutycycle register (Table 38). The effective RMS voltage
across the filament is given by the expression:
VRMS = FilOn x (VFIL - VLO-BRIDGE - VHI-BRIDGE) / 200
or, rearranged:
Duty = 200 x VRMS / (VFIL - VLO-BRIDGE - VHI-BRIDGE)
where:
FilOn is the number to store in the filament duty-cycle
register, address 0x09.
VFIL is the supply voltage to the filament driver bridge (V).
VRMS is the specified nominal filament supply voltage (V).
V LO-BRIDGE is the voltage drop across a low-side
bridge driver (V).
100µs MULTIPLEX TIME PERIOD (OSC = 4MHz)
(E)
(C)
(A)
(D)
(B)
PHASE 1
PHASE 2
Figure 19. Filament Bridge Driver Timing Waveforms
VFIL
Q2
R2
Q4
R4
V HI-BRIDGE is the voltage drop across a high-side
bridge driver (V).
The minimum commutation time, shown at (C) in Figure
19, is set by (2/OSC)s (500ns when OSC = 4MHz) to
ensure that shoot-through currents cannot flow during
phase reversal. Otherwise, the duty cycle of the bridge
(total on-time: total time) sets the RMS voltage across
the filament. This technique provides a low-cost AC filament supply when using a regulated supply higher than
the RMS voltage rating of the filament.
Figure 20 shows the external components required for
the filament driver using a FET bridge.
PHASE1 and PHASE2 Outputs
PHASE1 and PHASE2 can be individually programmed
as one of four output types (Tables 39, 40).
When using the filament drive, first ensure that the filament duty-cycle register 0x09 is set to the correct value
before configuring the PHASE1 and PHASE2 outputs to
be filament drives. To stop the filament drive, program
either PHASE1 or PHASE2 (or both) to be logic-low general-purpose outputs. Both PHASE1 and PHASE2 outputs come out of power-on-reset in logic-low condition.
PUMP Output
The PUMP output can be programmed as one of four
output types (Table 41).
PORT0 and PORT1 Outputs
PORT0 and PORT1 can be individually programmed as
one of eight output types (Tables 42, 43). The PORT1
choices are similar to the PORT0 choices, except that
the last four items are invert logic. PORT0 output comes
out of power-on-reset in logic-low condition, whereas
PORT1 output initializes high.
30
VFD TUBE
PHASE 1
PHASE 2
Q3
Q1
GND
GND
Figure 20. Filament Bridge Driver (MOSFET)
The PORT0 and PORT1 shutdown outputs allow external hardware (for example, a DC-to-DC converter
power supply for VFD) to be disabled by the MAX6851
when the MAX6851 is shut down.
The 625Hz, 1250Hz, and 2500Hz outputs can drive a
piezo sounder either from PORT0 or PORT1 alone, or
by both ports together as bridge drive. For bridge
drive, the sounder is connected between PORT0 and
PORT1, taking advantage of the PORT1 output being
inverted with respect to PORT0. Select different frequencies for PORT0 and PORT1 to obtain a wider
range of sounds when bridge drive is used.
Multiplex Clock and Blink Timing
The OSC1 and OSC2 inputs set the multiplex and blink
timing for the display driver. Connect an external resistor from OSC2 to GND and an external capacitor COSC
from OSC1 to GND to set the frequency of the internal
RC oscillator. Alternatively, overdrive OSC1 with an
external TTL or CMOS clock. If an exact blink rate or
multiplex period is required, use an external clock
ranging between 2MHz and 8MHz to drive OSC1.
______________________________________________________________________________________
2-Wire Interfaced, 7-, 14-, and 16-Segment Alphanumeric Vacuum-Fluorescent Display Controller
fOSC = KF / (ROSC x [COSC + CSTRAY]) MHz
where:
KF = 2320
ROSC = external resistor in kΩ (allowable range 8kΩ to
80kΩ)
COSC = external capacitor in pF
CSTRAY = stray capacitance from OSC1 to GND in pF,
typically 2pF
For OSC = 4MHz, ROSC is 10kΩ and COSC is 56pF
The effective value of COSC includes not only the actual
external capacitor used, but also the stray capacitance
from OSC1 to GND. This capacitance is usually in the
1pF to 5pF range, depending on the layout used.
The allowed range of fOSC is 2MHz to 8MHz. If fOSC is
set too high, the internal oscillator can stop working. An
internal fail-safe circuit monitors the multiplex clock and
detects a slow or nonworking multiplex clock. When a
slow or nonworking multiplex clock is detected, an
internal fail-safe oscillator generates a replacement
clock of about 200kHz. This backup clock ensures that
the VFD is not damaged by the multiplex operation halting inadvertently. The scan rate for 16 grids is about
30Hz in fail-safe mode, and the display flickers. A flickering display is a good indication that there is a problem with the multiplex clock.
Power Supplies
The MAX6851 operates from a single 2.7V to 3.6V
power supply. Bypass the power supply to GND with a
0.1µF capacitor as close to the device as possible. Add
a bulk capacitor (such as a low-cost electrolytic 1µF to
22µF) if the MAX6851 is driving high current from any of
the general-purpose output ports.
______________________________________________________________________________________
31
MAX6851
The multiplex clock frequency determines the multiplex
scan rate and the blink timing. The display scan rate is
{OSC / 400 / (1 + grids register value)}. There are 400
OSC cycles per digit multiplex period. For example,
with OSC = 4MHz, each display digit is enabled for
100µs. For a 40-grid display tube (grids register value
= 39 or 0x27), the display scan rate is 250Hz.
The BLINK output is the selectable blink period clock. It
is nominally 0.5Hz or 1Hz (OSC = 4MHz). It is low during the first half of the blink period, and high during the
second half. The PORT0 and PORT1 general-purpose
outputs may be programmed to be BLINK output.
Synchronize the BLINK timing if desired by setting the
T bit in the configuration register (Table 20).
The RC oscillator uses an external resistor ROSC and
an external capacitor COSC to set the oscillator frequency. ROSC connects from OSC2 to ground. COSC
connects from OSC1 to ground. The recommended values of R OSC and C OSC set the oscillator to 4MHz,
which makes the BLINK frequencies 0.5Hz and 1 Hz:
MAX6851
2-Wire Interfaced, 7-, 14-, and 16-Segment Alphanumeric Vacuum-Fluorescent Display Controller
Table 33. Output Map RAM Initial Power-Up Status
32
OUTPUT MAP RAM
ADDRESS
POWER-UP DEFAULT
CONTENT
0 to 39
0 to 39 (in order)
40
48
7-segment a
14-segment a
16-segment a1
41
49
7-segment b
14-segment b
16-segment b
42
50
7-segment c
14-segment c
16-segment c
43
51
7-segment d
14-segment d
16-segment d2
44
52
7-segment e
14-segment e
16-segment e
45
53
7-segment f
14-segment f
16-segment f
46
54
7-segment g
14-segment g1
16-segment g1
47
55
No action
14-segment g2
16-segment g2
48
56
No action
14-segment h
16-segment h
49
57
No action
14-segment I
16-segment I
50
58
No action
14-segment j
16-segment j
51
59
No action
14-segment k
16-segment k
52
60
No action
14-segment l
16-segment l
53
61
No action
14-segment m
16-segment m
54
62
No action
No action
16-segment a2
55
63
No action
No action
16-segment d1
56
64
7-segment dp
14-segment dp
16-segment dp
57
65
7-segment a
14-segment a
16-segment a1
58
66
7-segment b
14-segment b
16-segment b
59
67
7-segment c
14-segment c
16-segment c
60
68
7-segment d
14-segment d
16-segment d2
61
69
7-segment e
14-segment e
16-segment e
62
70
7-segment f
14-segment f
16-segment f
63
71
7-segment g
14-segment g1
16-segment g1
64
72
No action
14-segment g2
16-segment g2
65
73
No action
14-segment h
16-segment h
66
74
No action
14-segment I
16-segment I
67
75
No action
14-segment j
16-segment j
68
76
No action
14-segment k
16-segment k
69
77
No action
14-segment l
16-segment l
70
78
No action
14-segment m
16-segment m
71
79
No action
No action
16-segment a2
72
80
No action
No action
16-segment d1
73
81
7-segment dp
14-segment dp
16-segment dp
74
86 (Note: Value is not 82.)
Cursor segment for digits 0 to 47, 1st row
75
87 (Note: Value is not 83.)
Cursor segment for digits 0 to 47 only, 2nd row
76 to 83
127
No action
ADDRESSED FUNCTION
Grid 0 to grid 39
______________________________________________________________________________________
2-Wire Interfaced, 7-, 14-, and 16-Segment Alphanumeric Vacuum-Fluorescent Display Controller
REGISTER DATA
COMMAND
ADDRESS
D7
D6
D5
D4
D3
D2
D1
D0
Set output map address to minimum (0x00) with data
0x80. (Note that this address is set as a power-up
default.)
0x06
1
0
0
0
0
0
0
0
Set output map address to maximum 0x53 with data
0xD3.
0x06
1
1
1
1
1
0
0
1
MODE
COMMAND
ADDRESS
D7
D6
D5
D2
D1
D0
Write output map data; output map address pointer is
autoincremented after the output map data has been
written to the current location.
0x06
0
MODE
COMMAND
ADDRESS
D7
D1
D0
Read output map data; output map address pointer is
autoincremented after the output map data has been
read from the current location.
0x06
0
MODE
Table 35. Writing Output Map Data
REGISTER DATA
D4
D3
7 bits of output map data
Table 36. Reading Output Map Data
REGISTER DATA
D6
D5
D4
D3
D2
7 bits of output map data
Table 37. Filament Bridge Driver Timing
TIMING POINT
PHASE1 BEHAVIOR
PHASE2 BEHAVIOR
EXAMPLE 1
DUTY = 1 (MIN)
EXAMPLE 2
DUTY = 100
EXAMPLE 3
DUTY = 198
(A)
Low for (199 - FilOn)
cycles
Low for (199 - FilOn)
cycles
198
99
1
(B)
Low for (FilOn) cycles
High for (FilOn) cycles
1
100
198
(C)
Low for (2) cycles
Low for (2) cycles
2
2
2
(D)
High for (FilOn) cycles
Low for (FilOn) cycles
1
100
198
(E)
Low for (199 - FilOn)
cycles
Low for (199 - FilOn)
cycles
198
99
1
Total 4MHz
cycles
(OSC = 4MHz)
400 cycles = 100µs
400 cycles = 100µs
400 cycles =
100µs
400 cycles =
100µs
400 cycles =
100µs
Table 38. Filament Duty-Cycle Register Format
REGISTER DATA
COMMAND
ADDRESS
D7
D6
D5
D4
D3
D2
D1
D0
Minimum setting example (01)
0x09
0
0
0
0
0
0
0
1
0x01
Maximum setting example (199 or 0xC7)
0x09
1
1
0
0
0
1
1
1
0xC7
FILAMENT DUTY CYCLE
HEX CODE
______________________________________________________________________________________
33
MAX6851
Table 34. Setting Output Map Address Pointer
MAX6851
2-Wire Interfaced, 7-, 14-, and 16-Segment Alphanumeric Vacuum-Fluorescent Display Controller
Table 39. PHASE1 Register Format
REGISTER DATA
COMMAND
ADDRESS
D7
D6
D5
D4
D3
D2
D1
D0
General-purpose output, logic 0.
This is the power-up condition.
0x0A
X
X
X
X
X
X
0
0
0xX0
General-purpose output, logic 1.
0x0A
X
X
X
X
X
X
0
1
0xX1
Output gives blink status:
zero if blink phase P0; 1 if blink phase P1.
0x0A
X
X
X
X
X
X
1
0
0xX2
Filament drive PHASE1 (logic 0 during
shutdown).
0x0A
X
X
X
X
X
X
1
1
0xX3
COMMAND
ADDRESS
D7
D6
D5
D4
D3
D2
D1
D0
General-purpose output, logic 0.
This is the power-up condition.
0x0B
X
X
X
X
X
X
0
0
0xX0
General-purpose output, logic 1.
0x0B
X
X
X
X
X
X
0
1
0xX1
Output gives blink status: zero if blink phase
P0; 1 if blink phase P1.
0x0B
X
X
X
X
X
X
1
0
0xX2
Filament drive PHASE2 (logic 0 during
shutdown).
0x0B
X
X
X
X
X
X
1
1
0xX3
COMMAND
ADDRESS
D7
D6
D5
D4
D3
D2
D1
D0
General-purpose output, logic 0.
This is the power-up condition.
0x08
X
X
X
X
X
X
0
0
0xX0
General-purpose output, logic 1.
0x08
X
X
X
X
X
X
0
1
0xX1
80kHz square-wave output (OSC = 4MHz)
(logic 0 during shutdown).
0x08
X
X
X
X
X
X
1
0
0xX2
80kHz square-wave output (OSC = 4MHz)
(logic 1 during shutdown).
0x08
X
X
X
X
X
X
1
1
0xX3
PHASE1 BEHAVIOR
HEX CODE
Table 40. PHASE2 Register Format
PHASE2 BEHAVIOR
REGISTER DATA
HEX CODE
Table 41. PUMP Register Format
PUMP PORT BEHAVIOR
34
REGISTER DATA
______________________________________________________________________________________
HEX CODE
2-Wire Interfaced, 7-, 14-, and 16-Segment Alphanumeric Vacuum-Fluorescent Display Controller
REGISTER DATA
COMMAND
ADDRESS
D7
D6
D5
D4
D3
D2
D1
D0
General-purpose output, logic 0.
This is the power-up condition.
0x0C
X
X
X
X
X
0
0
0
0xX0
General-purpose output, logic 1.
0x0C
X
X
X
X
X
0
0
1
0xX1
Output gives blink status: zero if blink phase
P0; 1 if blink phase P1.
0x0C
X
X
X
X
X
0
1
0
0xX2
Output gives blink status: zero if blink phase
P0; 1 for P0, zero for P1.
0x0C
X
X
X
X
X
0
1
1
0xX3
625Hz square-wave output zero in
shutdown.
0x0C
X
X
X
X
X
1
0
0
0xX4
1250Hz square-wave output zero in
shutdown.
0x0C
X
X
X
X
X
1
0
1
0xX5
2500Hz square-wave output zero in
shutdown.
0x0C
X
X
X
X
X
1
1
0
0xX6
Output gives shutdown status: zero if
shutdown mode; 1 if operating mode.
0x0C
X
X
X
X
X
1
1
1
0xX7
COMMAND
ADDRESS
D7
D6
D5
D4
D3
D2
D1
D0
General-purpose output, logic 0.
0x0D
X
X
X
X
X
0
0
0
0xX0
General-purpose output, logic 1.
This is the power-up condition.
0x0D
X
X
X
X
X
0
0
1
0xX1
Output gives blink status: zero if blink
phase P0; 1 if blink phase P1.
0x0D
X
X
X
X
X
0
1
0
0xX2
Output gives blink status: zero if blink phase
P0; 1 for P0, zero for P1.
0x0D
X
X
X
X
X
0
1
1
0xX3
Inverted 625Hz square-wave output 1 in
shutdown.
0x0D
X
X
X
X
X
1
0
0
0xX4
Inverted 1250Hz square-wave output 1 in
shutdown.
0x0D
X
X
X
X
X
1
0
1
0xX5
Inverted 2500Hz square-wave output 1 in
shutdown.
0x0D
X
X
X
X
X
1
1
0
0xX6
Output gives inverted shutdown status:
1 if shutdown mode; zero if operating mode.
0x0D
X
X
X
X
X
1
1
1
0xX7
PORT0 PORT BEHAVIOR
HEX CODE
Table 43. PORT1 Register Format
PORT1 PORT BEHAVIOR
REGISTER DATA
HEX CODE
______________________________________________________________________________________
35
MAX6851
Table 42. PORT0 Register Format
2-Wire Interfaced, 7-, 14-, and 16-Segment Alphanumeric Vacuum-Fluorescent Display Controller
MAX6851
Functional Diagram
OSC1
OSC2
CLOCK
GENERATOR
OUTPUT
MAP
RAM
CHARACTERGENERATOR
ROM
TOP VIEW
PWM
BRIGHTNESS
CONTROL
VFBLANK
OUTPUT
SHIFTER
VFDOUT
VFCLK
VFLOAD
VFCLK 1
16 OSC2
VFDOUT 2
15 OSC1
VFLOAD 3
14 PORT1
VFBLANK 4
FILAMENT
PWM
USER
OUTPUTS
Pin Configuration
PHASE 1
PHASE 2
PUMP
PORT 0
PORT 1
MAX6851
13 AD0
PUMP 5
12 SDA
PHASE1 6
11 SCL
PHASE2 7
10 PORT0
V+ 8
9
GND
QSOP
RAM
CONFIGURATION
REGISTERS
Chip Information
SCL
SDA
ADO
36
2-WIRE SERIAL INTERFACE
TRANSISTOR COUNT: 132,715
PROCESS: CMOS
______________________________________________________________________________________
2-Wire Interfaced, 7-, 14-, and 16-Segment Alphanumeric Vacuum-Fluorescent Display Controller
QSOP.EPS
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 37
© 2003 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products.
MAX6851
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)