19-2537; Rev 1; 11/02
4-Wire Interfaced, 5 ✕ 7 Matrix VacuumFluorescent Display Controller
The MAX6852 compact vacuum-fluorescent display
(VFD) controller provides microprocessors with the multiplex timing for 5 x 7 matrix VFD displays up to 96
characters and controls industry-standard, shift-register, high-voltage grid/anode VFD tube drivers. The
device supports display tubes using either one or two
digits per grid, as well as universal displays. The
MAX6852 provides an internal crosspoint switch to
match any tube-driver shift-register grid/anode order,
and is compatible with both chip-in-glass and external
tube drivers. Hardware is included to simplify the generation of cathode bias and filament supplies and to provide up to five logic outputs, including a buzzer driver.
The MAX6852 includes an ASCII 104-character font,
multiplex scan circuitry, and static RAM that stores
digit, cursor, and annunciator data, as well as font data
for 24 user-definable characters. The display intensity
can be adjusted by an internal 16-step digital brightness control. The device also includes separate annunciator and cursor control with automatic blinking, as
well as a low-power shutdown mode.
The MAX6852 provides timing to generate the PWM
waveforms to drive the tube filament from a DC supply.
The filament drive is synchronized to the display multiplexing to eliminate beat artifacts. The MAX6852 is
compatible with SPI™ and QSPI™.
For a 2-wire interfaced version, refer to the MAX6853
data sheet.
Applications
Display Modules
Bar Graph Displays
Retail POS Displays
Industrial Controllers
Features
♦ High-Speed 26MHz SPI-/QSPI-/MICROWIRE™Compatible Serial Interface
♦ 2.7V to 3.6V Operation
♦ Controls Up to 96 5 x 7 Matrix Characters
♦ One Digit and Two Digits per Grid and Universal
Displays Supported
♦ 16-Step Digital Brightness Control
♦ Built-In ASCII 104-Character Font
♦ 24 User-Definable Characters
♦ Up to Four Annunciators per Grid with Automatic
Blinking Control
♦ Separate Cursor Control with Automatic Blinking
♦ Filament Drive Full-Bridge Waveform Synthesis
♦ Buzzer Tone Generator with Single-Ended or
Push-Pull Driver
♦ Up to Five General-Purpose Logic Outputs
♦ 9µA Low-Power Shutdown (Data Retained)
♦ 16-Pin QSOP Package
Ordering Information
PART
TEMP RANGE
MAX6852AEE
PIN-PACKAGE
-40°C to +125°C
16 QSOP
Typical Application Circuit
CHIP-ON-GLASS VFD
Weight and Tare
Displays
VFD SUPPLY VOLTAGE
0.1µF
MICROCONTROLLER
VFCLK
MAX6852
VFDOUT
DOUT
DIN
SCLK
SCLK
VFLOAD
VFBLANK
Pin Configuration and Functional Diagram appear at end of
data sheet.
CS
CS
OSC2
GND
SPI and QSPI are trademarks of Motorola, Inc.
OSC1
10kΩ
56pF
MICROWIRE is a trademark of National Semiconductor Corp.
________________________________________________________________ Maxim Integrated Products
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
1
MAX6852
General Description
MAX6852
4-Wire Interfaced, 5 ✕ 7 Matrix VacuumFluorescent Display Controller
ABSOLUTE MAXIMUM RATINGS
Voltage (with respect to GND)
V+ .............................................................................-0.3V to +4V
DIN, SCLK, CS ......................................................-0.3V to +5.5V
All Other Pins................................................-0.3V to (V+ + 0.3V)
Current
V+..................................................................................200mA
GND .............................................................................-200mA
PHASE1, PHASE2, PORT0, PORT1, PUMP................±150mA
VFCLK, VFDOUT, VFLOAD, VFBLANK ......................±150mA
Continuous Power Dissipation (TA = +70°C)
16-Pin QSOP (derate at 8.34mW/°C above +70°C).....667mW
Operating Temperature Range (TMIN, TMAX)
MAX6852AEE................................................-40°C to +125°C
Junction Temperature ......................................................+150°C
Storage Temperature Range .............................-65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
(Typical operating circuit, V+ = 2.7V to 3.6V, TA = TMIN to TMAX, unless otherwise noted.) (Note 1)
PARAMETER
SYMBOL
Operating Supply Voltage
V+
Shutdown Supply Current
ISHDN
CONDITIONS
MIN
Shutdown mode, all digital
inputs at V+ or GND
TA = TMIN to
TMAX
Master Clock Frequency (OSC
Internal Oscillator)
I+
fOSC
Master Clock Frequency (OSC
External Oscillator)
OSC = 4MHz
VFLOAD, VFDOUT, VFCLK,
VFBLANK, loaded 100pF
9
TA = TMIN to
TMAX
UNITS
3.6
V
0.71
OSC1 fitted with COSC = 56pF, OSC2 fitted
with ROSC = 10kΩ; see the Typical
Operating Circuit
Dead-Clock Protection
Frequency
mA
3.0
4
2
µA
30
3.5
TA = +25°C
OSC1 overdriven with external fOSC
MAX
85
TA = +25°C
Operating Supply Current
TYP
2.7
MHz
8
200
MHz
kHz
OSC High Time
tCH
50
ns
OSC Low Time
tCL
50
ns
Fast or Slow Segment Blink Duty
Cycle
(Note 2)
49.5
50.5
%
1
µA
LOGIC INPUTS AND OUTPUTS
Input Leakage Current DIN,
SCLK, CS
IIH, IIL
Logic-High Input Voltage DIN,
SCLK, CS
VIH
Logic-Low Input Voltage DIN,
SCLK, CS
VIL
2
0.2
2.4
_______________________________________________________________________________________
V
0.6
V
4-Wire Interfaced, 5 ✕ 7 Matrix VacuumFluorescent Display Controller
(Typical operating circuit, V+ = 2.7V to 3.6V, TA = TMIN to TMAX, unless otherwise noted.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
Output Rise and Fall Time
PHASE1, PHASE2, PORT0,
PORT1, PUMP, VFLOAD,
VFDOUT, VFCLK, VFBLANK
tRFT
CLOAD = 100pF
Output High-Voltage
PHASE1, PHASE2, PORT0,
PORT1, PUMP, VFLOAD,
VFDOUT, VFCLK, VFBLANK
VOH
ISOURCE = 10mA
Output Low-Voltage
PHASE1, PHASE2, PORT0,
PORT1, PUMP, VFLOAD,
VFDOUT, VFCLK, VFBLANK
VOL
ISINK = 10mA
MIN
TYP
MAX
UNITS
25
ns
V+ - 0.6
V
0.4V
V
Output Short-Circuit Source
Current PHASE1, PHASE2,
PORT0, PORT1, PUMP, VFLOAD,
VFDOUT, VFCLK, VFBLANK
IOHSC
Output programmed high, output short
circuit to GND (Note 2)
62
125
mA
Output Short-Circuit Sink Current
PHASE1, PHASE2, PORT0,
PORT1, PUMP, VFLOAD,
VFDOUT, VFCLK, VFBLANK
IOLSC
Output programmed low, output short
circuit to V+ (Note 2)
72
125
mA
4-WIRE SERIAL INTERFACE TIMING CHARACTERISTICS (Figure 6)
SCLK Clock Period
tCP
38.4
ns
SCLK Pulse Width High
tCH
19
ns
SCLK Pulse Width Low
tCL
19
ns
CS Fall to SCLK Rise Setup Time
tCSS
9.5
ns
SCLK Rise to CS Rise Hold Time
tCSH
5
ns
DIN Setup Time
tDS
9.5
ns
DIN Hold Time
tDH
2
ns
Minimum CS Pulse High
tCSW
19
ns
DOUT Cascade Setup Time
PORT0, PORT1
tCSU
9.5
ns
PORT0 and/or PORT1 enabled as DOUT
VFD INTERFACE TIMING CHARACTERISTICS (Figure 9)
VFCLK Clock Period
tVCP
(Note 2)
250
VFCLK Pulse Width High
tVCH
(Note 2)
125
ns
VFCLK Pulse Width Low
tVCL
(Note 2)
125
ns
tVCSH
(Note 2)
19
µs
VFDOUT Setup Time
tVDS
(Note 2)
50
ns
VFLOAD Pulse High
tVCSW
(Note 2)
245
ns
VFCLK Rise to VFD Load Rise
Hold Time
1050
ns
Note 1: All parameters tested at TA = +25°C. Specifications over temperature are guaranteed by design.
Note 2: Guaranteed by design.
_______________________________________________________________________________________
3
MAX6852
DC ELECTRICAL CHARACTERISTICS (continued)
Typical Operating Characteristics
(Typical operating circuit, V+ = 3.3V, TA = +25°C, unless otherwise noted.)
SHUTDOWN SUPPLY CURRENT
vs. SUPPLY VOLTAGE
2.1
TA = +125°C
40
2.0
1200
1000
TA = +125°C
1.9
TA = -40°C
1.8
ISUPPLY (µA)
35
ISUPPLY (µA)
ISUPPLY (mA)
OSC1 = 0
45
1400
MAX6852 toc02
50
MAX6852 toc01
2.2
SHUTDOWN SUPPLY CURRENT
vs. EXTERNAL OSC FREQUENCY
30
25
20
15
1.7
MAX6852 toc03
SUPPLY CURRENT vs. SUPPLY VOLTAGE
800
600
400
TA = +25°C
10
200
5
TA = -40°C
0
1.5
3.4
3.2
0
2.7
3.6
2.9
3.1
OUTPUT LOW VOLTAGE vs. ISINK
V+ = 3.3V
1.8
1.4
1.4
1.2
1.2
1.0
V+ = 3.6V
0.2
0.2
0
0
40
60
ISINK (mA)
80
100
V+ = 3.6V
V+ = 3.6V
1.0
TA = +125°C
0.4
0.2
0
20
40
60
ISINK (mA)
80
100
0
MAX6852 toc07
V+ = 2.7V
VOL (V)
1.2
V+ = 3.6V
0.6
TA = -40°C
100
V+ = 3.3V
1.0
V+ = 3.6V
0.5
TA = +25°C
0.4
80
V+ = 2.7V
1.5
0.8
V+ = 3.6V
60
2.0
V+ = 3.3V
1.0
40
VIN - VOH vs. ISOURCE
1.8
1.6
20
ISINK (mA)
2.0
1.4
1.0
0.5
1.2
0.6
TA = +25°C
0
V+ = 3.3V
8
V+ = 3.3V
VIN - VOH vs. ISOURCE
V+ = 2.7V
7
0.8
VIN - VOH vs. ISOURCE
2.0
6
V+ = 2.7V
1.6
1.4
0.6
0.4
5
1.8
0.8
TA = -40°C
0.6
1.5
4
OUTPUT LOW VOLTAGE vs. ISINK
V+ = 3.3V
1.0
0.4
20
3
2.0
MAX6852 toc08
0.8
V+ = 2.7V
1.6
VOL (V)
VOL (V)
OUTPUT LOW VOLTAGE vs. ISINK
MAX6852 toc05
V+ = 2.7V
0
2
FREQUENCY (MHz)
2.0
MAX6852 toc04
2.0
1.6
3.5
V+ (V)
V+ (V)
1.8
3.3
MAX6852 toc06
3.1
VOL (V)
2.9
VOL (V)
2.7
MAX6852 toc09
1.6
VOL (V)
MAX6852
4-Wire Interfaced, 5 ✕ 7 Matrix VacuumFluorescent Display Controller
TA = +125°C
0.2
0
4
0
0
0
20
40
60
ISOURCE (mA)
80
100
0
20
40
60
ISOURCE (mA)
80
100
0
20
40
60
ISOURCE (mA)
_______________________________________________________________________________________
80
100
4-Wire Interfaced, 5 ✕ 7 Matrix VacuumFluorescent Display Controller
DEAD-CLOCK OSC FREQUENCY
vs. TEMPERATURE
fOSC vs. TEMPERATURE
fOSC (MHz)
1.5
V+ = 3.6V
1.0
MAX6852 toc11
V+ = 3.3V
2.0
0.18
0.16
0.14
FREQUENCY (MHz)
V+ = 2.7V
MAX6852 toc10
2.5
V+ = 3.6V
0.12
0.10
0.08
V+ = 3.3V
0.06
V+ = 2.7V
0.04
0.5
0.02
0
0
-40 -25 -10 5 20 35 50 65 80 95 110 125
-40 -25 -10 5 20 35 50 65 80 95 110 125
TEMPERATURE (°C)
TEMPERATURE (°C)
Pin Description
PIN
NAME
FUNCTION
Serial-Clock Output to External Driver. Push-pull clock output to external display driver. On VFCLK’s
falling edge, data is clocked out of VFDOUT.
1
VFCLK
2
VFDOUT
Serial-Data Output to External Driver. Push-pull data output to external display driver.
3
VFLOAD
Serial-Load Output to External Driver. Push-pull load output to external display driver. Rising edge is
used by external display driver to load serial data into display latch.
4
VFBLANK
Display Blanking Output to External Driver. Push-pull blanking output to external display driver used for
PWM intensity control.
5
PUMP
Charge-Pump Output and General-Purpose Output. User-configurable push-pull logic output can also
be used as a driver for external charge pump.
6
PHASE1
Filament Drive PHASE1 Output and General-Purpose Output. User-configurable push-pull logic output
can also be used as a driver for external filament bridge drive.
7
PHASE2
Filament Drive PHASE2 Output and General-Purpose Output. User-configurable push-pull logic output
can also be used as a driver for external filament bridge drive.
8
V+
Positive Supply Voltage. Bypass V+ to GND with a 0.1µF ceramic capacitor.
9
GND
10
PORT0
Ground
11
SCLK
12
DIN
Serial-Data Input. Data from DIN loads into the internal 16-bit shift register on SCLK’s rising edge.
13
CS
Chip-Select Input. Serial data is loaded into the shift register while CS is low. The most recent 16 bits of
data latch on CS’s rising edge.
14
PORT1
PORT0 General-Purpose Output. User-configurable push-pull logic output.
Serial-Clock Input. On SCLK’s rising edge, data shifts into the internal shift register, and data is
clocked out of DOUT. SCLK is active only while CS is low.
PORT1 General-Purpose Output. User-configurable push-pull logic output.
_______________________________________________________________________________________
5
MAX6852
Typical Operating Characteristics (continued)
(Typical operating circuit, V+ = 3.3V, TA = +25°C, unless otherwise noted.)
4-Wire Interfaced, 5 ✕ 7 Matrix VacuumFluorescent Display Controller
MAX6852
Pin Description (continued)
PIN
NAME
FUNCTION
15
OSC1
Multiplex Clock Input 1. To use the internal oscillator, connect capacitor COSC from OSC1 to GND. To
use the external clock, drive OSC1 with a 2MHz-to-8MHz CMOS clock.
16
OSC2
Multiplex Clock Input 2. Connect resistor ROSC from OSC2 to GND.
GRID 1
GRID 2
GRID 3
GRID 4
GRID 5
GRID 6
GRID 7
GRID 8
GRID 9
GRID 10
GRID 11
GRID 12
GRID 13
GRID 14
GRID 15
GRID 16
Figure 1. Example of a One-Digit-per-Grid Display
Detailed Description
Overview of the MAX6852
The MAX6852 VFD controller generates the multiplex
timing for the following VFD display types:
• Multiplexed displays with one digit per grid, and up
to 48 grids (in 48/1 mode). Each grid can contain
one 5 x 7 matrix character, a decimal place (DP)
segment, a cursor segment, and four extra annunciator segments (Figure 1).
• Multiplexed displays with two digits per grid, and up
to 48 grids (in 96/2 mode). Each grid can contain
two 5 x 7 matrix characters, two DP segments, and
two cursor segments. No annunciator segments are
supported (Figure 2).
Each digit can have a 5 x 7 matrix character, a DP segment, a cursor segment, and (for one-digit-per-grid displays only) four annunciators (Figure 3).
The 5 x 7 matrix character segments are not controlled
directly, but use on-chip fonts that map the segments.
6
The fonts comprise an ASCII 104-character fixed-font
set, and 24 user-definable characters. The predefined
characters follow the Arial font, with the addition of the
following common symbols: £, €, ¥, °, µ, ±, ↑, and ↓.
The 24 user-definable characters are uploaded by the
user into on-chip RAM through the serial interface and
are lost when the device is powered down. As well as
custom 5 x 7 characters, the user-definable fonts can
control up to 35 custom segments, bar graphs, or
graphics.
Annunciator segments have individual, independent
control, so any combination of annunciators can be lit.
Annunciators can be off, lit, or blink either in phase or
out of phase with the cursor. The blink-speed control is
software selectable to be one or two blinks per second
(OSC = 4MHz).
DP segments can be lit or off, but have no blink control.
A DP segment is set by the same command that writes
the digit’s 5 x 7 matrix character.
_______________________________________________________________________________________
4-Wire Interfaced, 5 ✕ 7 Matrix VacuumFluorescent Display Controller
GRID 2
GRID 3
GRID 4
GRID 5
GRID 6
GRID 7
MAX6852
GRID 1
GRID 8
Figure 2. Example of a Two-Digits-per-Grid Display (8 Grids, 16 Digits)
°C °F pH mW
4 ANNUNCIATOR SEGMENTS
VFD TUBE DRIVER
MICROCONTROLLER
5 x 7 MATRIX CHARACTER
WITH 35 SEGMENTS
DOUT
DIN
SCLK
SCLK
CS
DECIMAL POINT (DP) SEGMENT
CURSOR SEGMENT
CS
VFDOUT
VFDIN
VFCLK
VFCLK
VFLOAD
VFLOAD
VFBLANK
VFBLANK
VFD TUBE
MAX6852
GRID/
ANODE
DRIVERS
Figure 3. Digit Structure with 5 ✕ 7 Matrix Character, DP
Segment, Cursor Segment, Four Annunciators
Figure 4. Connection of the MAX6852 to VFD Driver and VFD Tube
The cursor segment is controlled differently. A single
register selects one digit’s cursor from the entire display, and that can be lit either continuously or blinking.
All the other digits’ cursors are off.
The designations of DP, cursor, and annunciator are
interchangeable. For example, consider an application
requiring only one DP lit at a time, but the DP needs to
blink. The DP function does not have blink capability.
Instead, the DP segments on the display are routed
(using the output map) to the cursor function. In this
case, the DP segments are controlled using the cursor
register.
The output of the controller is a 4-wire serial stream that
interfaces to industry-standard, shift-register, high-voltage grid/anode VFD tube drivers (Figure 4). This interface uses three outputs to transfer and latch grid and
anode data into the tube drivers, and a fourth output
that enables/disables the tube driver outputs (Figure 5).
The enable/disable control is modulated by the
MAX6852 for both PWM intensity control and interdigit
blanking, and disables the tube driver in shutdown. The
controller multiplexes the display by enabling each grid
of the VFD in turn for 100µs (OSC = 4MHz) with the correct segment (anode) data. The data for the next grid is
transferred to the tube drivers during the display time of
the current grid.
The controller uses an internal output map to match any
tube-driver’s shift-register grid/anode order, and is
therefore compatible with all VFD internal chip-in-glass
or external tube drivers.
The MAX6852 provides five high-current output ports,
which can be configured for a variety of functions:
The PUMP output can be configured as either an
80kHz (OSC = 4MHz) clock intended for DC-DC converter use, the 4-wire serial interface’s DOUT data output, or a general-purpose logic output.
The PHASE1 and PHASE2 outputs can be individually
configured as either 10kHz PWM outputs (OSC =
4MHz) intended for filament driving, blink status outputs, or general-purpose logic outputs.
_______________________________________________________________________________________
7
MAX6852
4-Wire Interfaced, 5 ✕ 7 Matrix VacuumFluorescent Display Controller
The PORT0 and PORT1 outputs can be individually
configured as either 625Hz, 1250Hz, or 2500Hz clocks
(OSC = 4MHz) intended for buzzer driving, the 4-wire
serial interface’s DOUT data output, blink or shutdown
status outputs, or general-purpose logic outputs.
Display Modes
The MAX6852 has two display modes (Table 1), selected by the M bit in the configuration register (Table 21).
The display modes trade the maximum allowable number of digits (96/2 mode) against the availability of
annunciator segments (48/1 mode). Table 2 is the register address map.
VFD TUBE DRIVER
VFCLK
SERIAL-TO-PARALLEL SHIFT REGISTER
VFDIN
LATCHES
VFLOAD
VFBLANK
Initial Power-Up
On initial power-up, all control registers are reset, the
display segment and annunciator data are cleared,
intensity is set to minimum, and shutdown is enabled
(Table 3).
Character Registers
The MAX6852 uses 48 character registers (48/1 mode)
(Table 4) or 96 character registers (96/2 mode) (Table
5) to store the 5 x 7 characters (Table 6). Each digit is
represented by 1 byte of memory. The data in the character registers does not control the character segments
directly. Instead, the register data is used to address a
character generator, which stores the data of the 128character font (Table 7). The lower 7 bits of the character data (D6 to D0) select a character from the font
table. The most significant bit (MSB) of the register data
(D7) controls the DP segment of the digit; it is set to
light the DP, cleared to leave it unlit.
The character registers address maps are shown in
Table 4 (48/1 mode) and Table 5 (96/2 mode).
In 48/1 mode, the character registers use a single
address range 0x20 to {0x20 + g}, where g is the value
in the grids register (Table 24). The 48/1 mode upper
address limit, when g is 0x2F, is therefore 0x4F. The
address range 0x50 to 0x7F is used for annunciator
data in 48/1 mode.
In 96/2 mode, the character registers use two address
ranges. The first row’s address range is 0x20 to
{0x20 + g}. The second row’s address range is 0x50 to
{0x50 + g}. Therefore, in 96/2 mode, the character registers are only one contiguous memory range when a 48grid display is used.
Character Generator Font Mapping
The font is a 5 x 7 matrix comprising 104 characters in
ROM, and 24 user-definable characters. The selection
from the total of 128 characters is represented by the
8
O0
O1
O2
ON
O0
O1
O2
ON
VFD TUBE SIMPLIFIED
Figure 5. Block Diagram of VFD Tube Driver and VFD Tube
lower 7 bits of the 8-bit digit registers. The MSB, shown
as x in the ROM map (Table 7), controls the DP segment of the digit; it is set to light the DP, cleared to
leave it unlit.
The character map follows the Arial font for 96 characters in the x0100000 through x1111111 range. The first
32 characters map the 24 user-definable positions
(RAM00 to RAM23), plus eight extra common characters in ROM.
User-Defined Fonts
The 24 user-definable characters are represented by
120 entries of 7-bit data, five entries per character, and
are stored in the MAX6852’s internal RAM.
The 120 user-definable font data entries are written and
read through a single register, address 0x05. An
autoincrementing font address pointer in the MAX6852
indirectly accesses the font data. The font address
pointer can be written, setting one of 120 addresses
between 0x00 and 0xF7, but cannot be read back. The
font data is written to and read from the MAX6852 indirectly, using this font address pointer. Unused font
locations can be used as general-purpose scratch
RAM, noting that the font registers are only 7 bits wide,
not 8.
_______________________________________________________________________________________
4-Wire Interfaced, 5 ✕ 7 Matrix VacuumFluorescent Display Controller
DISPLAY
MODE
48/1 mode
MAXIMUM NO. OF
ANNUNCIATORS
MAXIMUM NO. OF DIGITS
48 digits, each with a DP segment and a cursor
segment
MAXIMUM NO.
OF GRIDS
4 per digit
DIGITS COVERED
BY EACH GRID
1 digit per grid
48 grids
96/2 mode
96 digits, each with a DP segment and a cursor
segment
None
2 digits per grid
Table 2. Register Address Map
COMMAND ADDRESS
D15
D14
D13
D12
D11
D10
D9
D8
HEX
CODE
No-op
R/W
0
0
0
0
0
0
0
0x00
VFBLANK polarity
R/W
0
0
0
0
0
0
1
0x01
Intensity
R/W
0
0
0
0
0
1
0
0x02
Grids
R/W
0
0
0
0
0
1
1
0x03
Configuration
R/W
0
0
0
0
1
0
0
0x04
User-defined fonts
R/W
0
0
0
0
1
0
1
0x05
Output map
R/W
0
0
0
0
1
1
0
0x06
Display test and device ID
R/W
0
0
0
0
1
1
1
0x07
PUMP register
R/W
0
0
0
1
0
0
0
0x08
Filament duty cycle
R/W
0
0
0
1
0
0
1
0x09
PHASE1
R/W
0
0
0
1
0
1
0
0x0A
PHASE2
R/W
0
0
0
1
0
1
1
0x0B
PORT0
R/W
0
0
0
1
1
0
0
0x0C
PORT1
R/W
0
0
0
1
1
0
1
0x0D
Shift limit
R/W
0
0
0
1
1
1
0
0x0E
Cursor
R/W
0
0
0
1
1
1
1
0x0F
X
0
0
1
0
0
0
0
0x10
REGISTER
Factory reserved. Do not write to register.
Table 8 shows how to use the single user-defined font
register 0x05 to set the font address pointer, write font
data, and read font data. A read action always returns
font data from the font address pointer position. A write
action sets the 7-bit font address pointer if the MSB is
set, or writes 7-bit font data to the font address pointer
position if the MSB is clear.
The font address pointer autoincrements after a valid
access to the user-definable font data. Autoincrementing
allows the 120-font data entries to be written and read
back very quickly because the font pointer address need
only be set once. After the last data location 0xF7 has
been written, further font data entries are ignored until the
font address pointer is reset. If the font address pointer is
set to an out-of-range address by writing data in the 0xF8
to 0xFF range, then address 0x80 is set instead (Table 9).
Table 10 shows the user-definable font pointer base
addresses.
Table 11 shows an example of data (characters 0, 1,
and 2) being stored in the first three user-defined font
locations, illustrating the orientation of the data bits.
_______________________________________________________________________________________
9
MAX6852
Table 1. Display Modes
MAX6852
4-Wire Interfaced, 5 ✕ 7 Matrix VacuumFluorescent Display Controller
Table 3. Initial Power-Up Register Status
REGISTER DATA
POWER-UP CONDITION
COMMAND
ADDRESS
D7
D6
D5
D4
D3
D2
D1
D0
VFBLANK polarity
VFBLANK is high to disable the
display
0x01
X
X
X
X
X
X
0
0
Intensity
1/16 (min on)
0x02
X
X
X
X
0
0
0
0
Grids
Display has 1 grid
0x03
X
X
0
0
0
0
0
0
Configuration
Shutdown enabled,
configuration unlocked
0x04
1
0
0
0
X
0
0
0
User-defined font
address pointer
Address 0x80; pointing to the
first user-defined font location
0x05
1
0
0
0
0
0
0
0
User-defined fonts
All 24 characters blank
—
0
0
0
0
0
0
0
0
Output map pointer
Pointing to first entry address
0x06
1
0
0
0
0
0
0
0
Output map data
Predefined for 40-digit display
—
Display test
Normal operation
0x07
X
X
X
X
X
X
X
0
PUMP
General-purpose output, logic
0x08
0
0
0
0
0
0
0
0
Filament duty cycle
Minimum duty cycle
0x09
0
0
0
0
0
0
0
1
PHASE1
General-purpose output, logic
0x0A
0
0
0
0
0
0
0
0
PHASE2
General-purpose output, logic
0x0B
0
0
0
0
0
0
0
0
PORT0
General-purpose output, logic
0x0C
0
0
0
0
0
0
0
0
PORT1
General-purpose output, logic
0x0D
0
0
0
0
0
0
0
1
Shift limit
1 output bit
0x0E
X
0
0
0
0
0
0
1
Cursor
Off
0x0F
0
1
1
0
0
0
0
0
Character and
annunciator data
Clear
0x20
0
0
0
0
0
0
0
0
UP TO
—
—
—
—
—
—
—
—
0x7F
0
0
0
0
0
0
0
0
REGISTER
—
UP TO
Character and
annunciator data
Clear
See Table 30 for power-up patterns.
Table 12 shows the six sequential write commands
required to set a MAX6852’s font character RAM02 with
the data to display character 2 given in Table 7.
ter is programmed with an out-of-range value of 95 to
127 (0x60 to 0x7F), then all cursors are off.
Cursor Register
The annunciator registers are organized in bytes, with
each segment of each grid being represented by 2
bits. Thus, the four annunciators segments allowed for
each grid are represented by exactly 1 byte (Table 14).
Annunciators are only available in 48/1 mode. The
annunciator address map is shown in Table 4.
The cursor register controls the behavior of the cursor
segments (Table 13). The MAX6852 controls 48 cursors
in 48/1 mode, and 96 cursors in 96/2 mode. The cursor
register selects one digit’s cursor to be lit either continuously or blinking. All the other digits’ cursors are off.
The 7 least significant bits (LSBs) of the cursor register
identify the cursor position. The MSB is clear for the
cursor to be on continuously, and set for the cursor to
be lit only during the first half of each blink period.
The valid cursor position address range is contiguous:
0 to 47 (0x00 to 0x2F) for the 1st digit row, and 48 to 95
(0x30 to 0x5F) for the 2nd digit row. If the cursor regis10
Annunciator Registers
Configuration Register
The configuration register is used to enter and exit shutdown, lock the key VFD configuration settings, select
the blink rate, globally clear the digit and annunciator
data, reset the blink timing, and select between 48/1
and 96/2 display modes (Table 15).
______________________________________________________________________________________
4-Wire Interfaced, 5 ✕ 7 Matrix VacuumFluorescent Display Controller
MAX6852
Table 4. Character and Annunciator Register Address Map in 48/1 Mode
COMMAND ADDRESS
D15
D14
D13
D12
D11
D10
D9
D8
HEX
CODE
Digit 0 5 x 7 matrix character
R/W
0
1
0
0
0
0
0
0x20
Digit 1 5 x 7 matrix character
R/W
0
1
0
0
0
0
1
0x21
Digit 2 5 x 7 matrix character
R/W
0
1
0
0
0
1
0
0x22
REGISTER
—
—
—
—
—
—
—
—
—
Digit 45 5 x 7 matrix character
R/W
1
0
0
1
1
0
1
0x4D
Digit 46 5 x 7 matrix character
R/W
1
0
0
1
1
1
0
0x4E
Digit 47 5 x 7 matrix character
R/W
1
0
0
1
1
1
1
0x4F
Digit 0 annunciators
R/W
1
0
1
0
0
0
0
0x50
Digit 1 annunciators
R/W
1
0
1
0
0
0
1
0x51
Digit 2 annunciators
R/W
1
0
1
0
0
1
0
0x52
UP TO
—
—
—
—
—
—
—
—
—
Digit 45 annunciators
R/W
1
1
1
1
1
0
1
0x7D
Digit 46 annunciators
R/W
1
1
1
1
1
1
0
0x7E
Digit 47 annunciators
R/W
1
1
1
1
1
1
1
0x7F
UP TO
Table 5. Character Register Address Map in 96/2 Mode
COMMAND ADDRESS
D15
D14
D13
D12
D11
D10
D9
D8
HEX
CODE
Digit 0 5 x 7 matrix character, 1st row
R/W
0
1
0
0
0
0
0
0x20
Digit 1 5 x 7 matrix character, 1st row
R/W
0
1
0
0
0
0
1
0x21
Digit 2 5 x 7 matrix character, 1st row
R/W
0
1
0
0
0
1
0
0x22
—
—
—
—
—
—
—
—
—
Digit 45 5 x 7 matrix character, 1st row
R/W
1
0
0
1
1
0
1
0x4D
Digit 46 5 x 7 matrix character, 1st row
R/W
1
0
0
1
1
1
0
0x4E
Digit 47 5 x 7 matrix character, 1st row
R/W
1
0
0
1
1
1
1
0x4F
Digit 0 5 x 7 matrix character, 2nd row
R/W
1
0
1
0
0
0
0
0x50
Digit 1 5 x 7 matrix character, 2nd row
R/W
1
0
1
0
0
0
1
0x51
Digit 2 5 x 7 matrix character, 2nd row
R/W
1
0
1
0
0
1
0
0x52
—
—
—
—
—
—
—
—
—
Digit 45 5 x 7 matrix character, 2nd row
R/W
1
1
1
1
1
0
1
0x7D
Digit 46 5 x 7 matrix character, 2nd row
R/W
1
1
1
1
1
1
0
0x7E
Digit 47 5 x 7 matrix character, 2nd row
R/W
1
1
1
1
1
1
1
0x7F
REGISTER
UP TO
UP TO
______________________________________________________________________________________
11
MAX6852
4-Wire Interfaced, 5 ✕ 7 Matrix VacuumFluorescent Display Controller
Table 6. Character Registers Format
MODE
REGISTER DATA
COMMAND ADDRESS
D7
Writing character data to use font map
data with DP segment unlit
0x20 to 0x4F (48/1 mode)
0x20 to 0x7F (96/2 mode)
0
Writing character data to use font map
data with DP segment lit
0x20 to 0x4F (48/1 mode)
0x20 to 0x7F (96/2 mode)
1
D6
D5
D4
D3
D2
D1
D0
Bits D6 to D0 select font characters 0 to 127
Shutdown Mode (S Data Bit D0) Format
The S bit in the configuration register selects shutdown
or normal operation (Table 16). The display driver can
be programmed while in shutdown mode, and shutdown mode is overridden when in display test mode.
For normal operation, set S bit to 1.
When the MAX6852 is in shutdown mode, the multiplex
oscillator is halted at the end of the current 100µs multiplex period (OSC = 4MHz), and the VFBLANK output is
used to disable the VFD tube driver. Data in the digit
and other control registers remains unaltered.
If the PUMP output is configured as a square-wave
clock, then the PUMP output is forced low for the duration of shutdown, and the square-wave clock restored
when the MAX6852 comes out of shutdown.
If the PHASE1 output or PHASE2 output is configured as
a filament driver, then that output is forced low for the
duration of shutdown and the filament drive waveforms
restored when the MAX6852 comes out of shutdown.
When the MAX6852 comes out of shutdown, the external VFD tube driver is presumed to contain invalid data.
The VFBLANK output is used to disable the VFD tube
driver for the first multiplex cycle after exiting shutdown,
clearing any invalid data. The next multiplex cycle uses
newly sent valid data.
Configuration Lock (L Data Bit D1) Format
The configuration lock register is a safety feature to
reduce the risk of the VFD configuration settings being
inadvertently changed due to spurious writes if software fails. When set, the shift-limit register (0x0E), grids
register (0x03), and output map data (0x06) can be
read but cannot be written. The output map data pointer itself may be written in order to allow the output map
data to be read back (Table 17).
Blink Rate Selection (B Data Bit D2) Format
The B bit in the configuration register selects the blink
rate of the cursor and annunciator segments. This is the
speed that the segments blink on and off when blinking
12
is selected for these segments. The frequency of the
multiplex clock OSC and the setting of the B bit (Table
18) determine the blink rate.
Global Blink Timing Synchronization
(T Data Bit D4) Format
Setting the T bit in multiple MAX6852s at the same time
(or in quick succession) synchronizes the blink timing
across all the devices (Table 19). The display multiplexing sequence is also reset, which can give rise to a
one-time display flicker when the register is written.
Global Clear Digit Data (R Data Bit D5) Format
When the R bit (Table 20) is set, the segment and
annunciator data are cleared.
Display Mode (M Data Bit D6) Format
The M bit (Table 21) selects the display modes (Table 1).
The display modes trade maximum allowable number of
digits (mode 96/2) against the availability of annunciator
segments (mode 48/1).
Blink Phase Readback (P Data Bit D7) Format
When the configuration register is read, the P bit
reflects the blink phase pin at that time (Table 22).
Microcontroller 4-Wire Serial Interface
The MAX6852 communicates through an SPI-compatible 4-wire serial interface (Figure 6). The interface has
three inputs, clock (SCLK), chip select (CS), data in
(DIN), and output data out (DOUT). CS must be low to
clock data into or out of the device, and DIN must be
stable when sampled on the rising edge of SCLK.
DOUT is not a specific pin, but instead, any of the
PUMP, PORT0, or PORT1 outputs can be configured to
be DOUT. DOUT is stable on the rising edge of SCLK.
While the SPI protocol expects DOUT to be high
impedance when the MAX6852 is not being accessed,
DOUT on the MAX6852 is never high impedance. SCLK
and DIN can be used to transmit data to other peripherals. The MAX6852 ignores all activity on SCLK and DIN
except when CS is low.
______________________________________________________________________________________
4-Wire Interfaced, 5 ✕ 7 Matrix VacuumFluorescent Display Controller
Controlling the MAX6852 requires sending a 16-bit
word. The first byte, D15 through D8, is the command
address, and the second byte, D7 through D0, is the
data to be written to the command address (Table 23).
MAX6852
Control and Operation Using the 4-Wire
Interface
Table 7. Character Map
MSB
x000
x001
0000
RAM00
RAM16
0001
RAM01
RAM17
0010
RAM02
RAM18
0011
RAM03
RAM19
0100
RAM04
RAM20
0101
RAM05
RAM21
0110
RAM06
RAM22
0111
RAM07
RAM23
1000
RAM08
1001
RAM09
1010
RAM10
1011
RAM11
1100
RAM12
1101
RAM13
1110
RAM14
1111
RAM15
x010
x011
x100
x101
x110
x111
LSB
Connecting Multiple MAX6852s to the
4-Wire Bus
Daisy-chain multiple MAX6852s by connecting the
DOUT of one device to the DIN of the next, and driving
SCLK and CS lines in parallel. Data at DIN propagates
through the internal shift registers and appears at
DOUT 15.5 clock cycles later, clocked out on the rising
edge of SCLK. When sending commands to daisychained MAX6852s, all devices are accessed at the
same time. An access requires (16 x n) clock cycles,
where n is the number of MAX6852s connected together. To update just one device in a daisy-chain, send the
no-op command (0x00) to the others. Care must be
taken on power-up when daisy-chaining the serial interface in this manner. Configure each MAX6852’s PORT0
or PORT1 outputs, in turn, to act as DOUT before data
propagates through it. For this reason, PORT0 is the
preferred output to configure as DOUT because its output on power-up is low. This means that a daisychained DIN input taking data from an uninitialized
PORT0 output clocks in 16 logic zeros, which is the
safe no-op instruction.
Writing Device Registers
The MAX6852 contains a 16-bit shift register into which
DIN is clocked on the rising edge of SCLK, when CS is
low. When CS is high, transitions on SCLK have no
effect. When CS goes high, the 16 bits in the shift register are parallel loaded into a 16-bit latch. The 16 bits in
the latch are then decoded and executed.
The MAX6852 is written to using the following
sequence:
1) Take SCLK low.
2) Take CS low. This enables the internal 16-bit shift
register.
3) Clock 16 bits of data into DIN, D15 first to D0 last,
observing the setup and hold times. Bit D15 is low,
indicating a write command.
4) Take CS high (while SCLK is still high after clocking
in the last data bit).
5) Take SCLK low.
Figure 7 shows a write operation when 16 bits are
transmitted.
______________________________________________________________________________________
13
MAX6852
4-Wire Interfaced, 5 ✕ 7 Matrix VacuumFluorescent Display Controller
tCSW
CS
tCL
tCSS
tCH
tCSH
tCP
SCLK
tDS
DIN
tDH
DN
DN-1
D1
D0
tCSU
D15
DOUT
Figure 6. 4-Wire Serial Interface Timing Diagram
CS
CLK
D15
=0
DIN
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
D15 = 0
DOUT
Figure 7. 16-Bit Write Transmission to the MAX6852
If fewer or greater than 16 bits are clocked into the
MAX6852 between taking CS low and taking CS high
again, the MAX6852 stores the last 16 bits received,
including the previous transmission(s). The general
case is when n bits (where n > 16) are transmitted to
the MAX6852. The last bits comprising bits {n-15} to {n}
are retained and are parallel loaded into the 16-bit latch
as bits D15 to D0, respectively (Figure 8).
Reading Device Registers
Any register data within the MAX6852 may be read by
sending a logic high to bit D15. The sequence is:
1) Take SCLK low.
2) Take CS low. This enables the internal 16-bit shift
register.
3) Clock 16 bits of data into DIN, D15 first to D0 last,
observing the setup and hold times. Bit D15 is high,
indicating a read command, and bits D14 through
14
D8 contain the address of the register to read. Bits
D7 to D0 contain dummy data, which is discarded.
4) Take CS high. Positions D7 through D0 in the shift
register are now loaded with the data in the register
addressed by bits D15 through D8.
5) Take SCLK low.
6) Issue another read or write command (which can be
no-op), and examine the bit stream at DOUT; the
first 8 bits contain the address of the register that
was read (Note: The MSB, which was transmitted as
a 1 for a read command, may read back either as a
1 or a zero). The second 8 bits are the contents of
the register addressed by bits D14 through D8 in
Step 3.
VFD Driver Serial Interface
The VFD driver interface on the MAX6852 is a serial
interface using three output pins, VFLOAD, VFCLK, and
VFDOUT (Figure 9) to drive industry-standard, shift-reg-
______________________________________________________________________________________
4-Wire Interfaced, 5 ✕ 7 Matrix VacuumFluorescent Display Controller
MAX6852
CS
CLK
N-15
=0
DIN
DOUT
BIT
1
N-14
N-13
N-12
N-11
N-10
N-9
N-8
N-7
N-6
N-5
N-4
N-3
N-2
N-1
N
N-25
N-24
N-23
N-22
N-21
N-20
N-19
N-18
N-17
N-16
BIT
2
N-31
N-30
N-29
N-28
N-27
N-26
N-15 = 0
Figure 8. Transmission of More than 16 Bits to the MAX6852
ister, high-voltage grid/anode VFD tube drivers (Figures
3 and 4). The speed of VFCLK is 2MHz when OSC is
4MHz. The maximum speed of VFCLK is 4MHz when
OSC is 8MHz. This interface is used to transfer display
data from the MAX6852 to the VFD tube driver. The serial interface bit stream output is programmable up to
122 bits, which are labeled DD0–DD121.
The functions of the three interface pins are as follows:
VFCLK is the serial clock output, which shifts data on
its falling edge from the MAX6852’s 122-bit output shift
register to VFLOAD.
VFDOUT is the serial data output. The data changes on
VFCLK’s falling edge, and is stable when it is sampled
by the display driver on the rising edge of VFCLK.
VFLOAD is the latch-load output. VFLOAD is high to
transfer data from the display tube driver’s shift register to
the display driver’s output latch (transparent mode), and
low to retain that data in the display driver’s output latch.
A fourth output pin, VFBLANK, provides gating control
of the tube driver. VFBLANK can be configured to be
either high or low using the VBLANK polarity register
(Table 26) to enable the VFD tube driver. In the default
condition, VFBLANK is high to disable the VFD tube driver, which is expected to force its driver outputs low to
blank the display without altering the contents of its output latches. In the default condition, VFBLANK is low to
enable its VFD tube driver outputs to follow the state of
the VFD tube driver’s output latches. The VFBLANK
output is used for PWM intensity control and to disable
the VFD tube driver in shutdown.
Multiplex Architecture
The multiplex engine transmits grid and anode control
data to the external VFD driver using the VFCLK, VFDOUT, and VFLOAD. The number of data bits m transmitted is set by the user in the shift-limit register (Table
28). Figure 10 is the VFD multiplex timing diagram.
The essential rules for multiplex action are as follows:
• The external VFD driver’s data latch contains the
data for the current grid being displayed.
• The VFBLANK input is controlled to provide the
PWM intensity control.
• The VFCLK and VFDOUT outputs are used to fill the
external VFD driver’s shift register with the multiplex
data for the next grid, during the multiplex timeslot
for the current grid.
• The VFLOAD output loads the new grid-anode data
pattern at the start of its multiplex cycle.
Grids Register
The grids register sets how many grids are multiplexed
from 1 to 48 (Table 24).
When the grids register is written, the external VFD tube
driver is presumed to contain invalid data. The
VFBLANK output is used to disable the VFD tube driver
for the first multiplex cycle after exiting shutdown, clearing any invalid data. The next multiplex cycle uses
newly sent, valid data. If the grids register is written
with an out-of-range value of 0x30 to 0xFF, then the
value 0x2F is stored instead.
Intensity Register
Digital control of display brightness is provided by
pulse-width modulation of the tube blanking time, which
is controlled by the lower nibble of the intensity register
(Table 25). The modulator scales the VFBLANK output
in 15 steps from a minimum of 1/16 up to 15/16 of each
grid’s multiplex period (Figure 11). Figure 12 shows the
modulator behavior when the VFBLANK polarity register is set to 0x00 (Table 26), so VFBLANK is high to disable (blank) the display.
The minimum off-time period of a 1/16 multiplex period
(6.25µs with OSC = 4MHz) is always at the start of the
multiplex cycle. This allows time for slow display drivers
to turn off, and slow display phosphors time to decay
______________________________________________________________________________________
15
MAX6852
4-Wire Interfaced, 5 ✕ 7 Matrix VacuumFluorescent Display Controller
VFLOAD
tVCSW
tVCL
tVCH
tVCSH
tVCP
VFCLK
tVDS
VFDOUT
DD0
M (M IS VALUE IN SHIFT-LIMIT REGISTER)
M-1
DD1
Figure 9. VFD Interface Timing Diagram
START OF NEXT
CYCLE
ONE COMPLETE MULTIPLEX CYCLE AROUND N GRIDS (OSC = 4MHz)
100µs TIMESLOT
GRID 0
100µs TIMESLOT
GRID 1
100µs TIMESLOT
GRID N-4
100µs TIMESLOT
GRID N-3
100µs TIMESLOT
GRID N-2
100µs TIMESLOT
GRID N-1
100µs TIMESLOT
GRID 0
500ns 500ns 500ns 500ns
GRID 0's 100µs MULTIPLEX TIMESLOT
VFCLK
VFDOUT
DD0
DD1 DD2
DD3
DD4 DD5 DD6 DD7
DD8 DD9 DD10
M-4
M-3
M-2 M-1
M
(M IS VALUE IN SHIFT-LIMIT REGISTER)
GRID 1's DATA, SENT DURING GRID 0's TIMESLOT
VFLOAD
Figure 10. VFD Multiplex Timing Diagram
between grids. Thus, image ghosting is avoided. If a
display has very slow phosphor, then the allowed decay
time can be doubled by not using a 15/16 duty cycle.
Reading the display-test and device ID register returns
the MAX6852 device ID 0b0000 011 that identifies the
driver type, plus the display-test status in the LSB.
VFBLANK Polarity Register
Output Shift-Limit Register
The VFBLANK polarity register sets the active level of
the VFBLANK output pin (Table 26).
The output serial interface is used to transfer display
data from the MAX6852 to the display driver. The serial
interface bit-stream output length is programmable up
to 122 bits, which are labeled DD0–DD121. Set the
number of bits with the shift-limit register, address
0x0E. If the shift-limit register is written with an out-ofrange value 0x7A to 0xFF, then the value 0x79 is stored
instead. Table 28 shows the shift-limit register.
No-Op Register
A write to the no-op register is ignored.
Display-Test and Device ID Register
Writing the display-test and device ID register switches
the drivers between one of two modes: normal and display test. Display-test mode turns all segments and
annunciators on and sets the duty cycle to 7/16 (halfpower) (Table 27).
16
Output Map
The output map comprises 122 words of 7-bit RAM.
The output map data should be written when the
MAX6852 is configured after power-up. Table 29 shows
the output map RAM codes.
______________________________________________________________________________________
4-Wire Interfaced, 5 ✕ 7 Matrix VacuumFluorescent Display Controller
100µs TIMESLOT
GRID 0
100µs TIMESLOT
GRID 1
100µs TIMESLOT
GRID N-4
100µs TIMESLOT
GRID N-3
100µs TIMESLOT
GRID N-2
MAX6852
START OF NEXT
CYCLE
ONE COMPLETE MULTIPLEX CYCLE AROUND N GRIDS (OSC = 4MHz)
100µs TIMESLOT
GRID N-1
100µs TIMESLOT
GRID 0
MINIMUM 6.25µs INTERDIGIT
BLANKING INTERVAL (OSC = 4MHz)
GRID 0'S 100µs MULTIPLEX TIMESLOT
VFBLANK
1/16TH
(MIN ON)
2/16TH
3/16TH
4/16TH
5/16TH
6/16TH
7/16TH
8/16TH
9/16TH
10/16TH
11/16TH
12/16TH
13/16TH
14/16TH
15/16TH
15/16TH
(MAX ON)
Figure 11. BLANK and Intensity Timing Diagram
______________________________________________________________________________________
17
MAX6852
4-Wire Interfaced, 5 ✕ 7 Matrix VacuumFluorescent Display Controller
The output map is an indirect addressing reference
table. It translates bit position in the output shift register
(valid range: from zero to the value in shift-limit register
0x0E) to bit function. Any output shift-register bit position may be set to any grid, 5 x 7 matrix segment, DP
segment, annunciator segment, or cursor segment.
The power-up default pattern for output map RAM
maps a 40-digit, two-digits-per-grid display with DPs
and cursors (Table 30).
If the user selects an unused map RAM entry (126 or
127) for an output shift-register position, then the corresponding output bit is always low (segment or grid OFF).
When selecting an invalid map RAM entry (for example,
codes 48 to 83 to select annunciators in 96/2 mode,
which does not support annunciators), the corresponding output bit is always low (segment or grid OFF).
If the map RAM entry corresponds to a nonexistent font
segment (no action in Table 30) when the digit data is
processed through the character font, then the result
again is zero (segment or grid OFF).
The output map data is indirectly accessed by an
autoincrementing output map address pointer in the
MAX6852 at address 0x06. The output map address
pointer can be written (i.e., set to an address between
0x00 and 0x79) but cannot be read back. The output
map data is written and read back through the output
map address pointer.
Table 31 shows how to set the output map address
pointer to a value within the acceptable range. Bit D7 is
set to denote that the user is writing the output map
address pointer. If the user attempts to set the output
map address to one of the out-of-range addresses by
writing data in range 0xFA to 0xFF, then address 0x00
is set instead.
After the last data location 0xF9 has been written, further output map data entries are ignored until the output map address pointer is reset.
The output map data can be written to the address set
by the output map address pointer. Bit D7 is clear to
denote that the user is writing actual output map data.
The output map address pointer is autoincremented
after the output map data has been written to the current location. If the user writes the output map data in
the RAM order, then the output map address pointer
need only be set once, or even not at all as the address
is set to 0x00 as power-up default (Table 32).
The output map data can be read by reading address
0x86. The 7-bit output map data at the address set by
the output map address pointer is read back, with the
MSB clear. The output map address pointer is autoin18
cremented after the output map data has been read
from the current location, in the same way as for a write
(Table 33).
Filament Drive
The VFD filament is typically driven with an AC waveform, supplied by a center-tapped 50Hz or 60Hz power
transformer as part of the system power supply.
However, if the system has only DC supplies available,
the filament must be powered by a DC-AC or DC-DC
converter.
The MAX6852 can generate the waveforms on the
PHASE1 and PHASE2 outputs to drive the VFD filament
using a full bridge (push-pull drive). The PHASE1 and
PHASE2 outputs can be used as general-purpose outputs if the filament drive is not required. The bridge
drive transistors are external, but the waveforms are
generated by the MAX6852.
The waveform generation uses PWM to set the effective
RMS voltage across the filament, as a fraction of the
external supply voltage (Figure 13) (Table 34). The filament switching frequency is synchronized to the multiplex scan clock, eliminating beating artifacts due to
differing filament and multiplex frequencies.
The PWM duty cycle is controlled by the filament dutycycle register (Table 35). The effective RMS voltage
across the filament is given by the expression:
VRMS = FilOn x (VFIL - VLO-BRIDGE - VHI-BRIDGE) / 200
or, rearranged:
Duty = 200 x VRMS / (VFIL - VLO-BRIDGE - VHI-BRIDGE)
where:
FilOn is the number to store in the filament duty-cycle
register, address 0x09.
VFIL is the supply voltage to the filament driver bridge (V).
VRMS is the specified nominal filament supply voltage (V).
V LO-BRIDGE is the voltage drop across a low-side
bridge driver (V).
V HI-BRIDGE is the voltage drop across a high-side
bridge driver (V).
The minimum commutation time, shown at (C) in Figure
13, is set by (2/OSC)s (500ns when OSC = 4MHz) to
ensure that shoot-through currents cannot flow during
phase reversal. Otherwise, the duty cycle of the bridge
(total on time: total time) sets the RMS voltage across
the filament. This technique provides a low-cost AC filament supply when using a regulated supply higher than
the RMS voltage rating of the filament.
______________________________________________________________________________________
4-Wire Interfaced, 5 ✕ 7 Matrix VacuumFluorescent Display Controller
2-1
SEG 2
3-1
SEG 3
4-1
SEG 4
MAX6852
1-1
SEG 1
100µs MULTIPLEX TIME PERIOD (OSC = 4MHz)
5-1
SEG 5
(E)
(C)
(A)
(D)
(B)
1-2
SEG 6
2-2
SEG 7
3-2
SEG 8
4-2
SEG 9
5-2
SEG 10
1-3
SEG 11
2-3
SEG 12
3-3
SEG 13
4-3
SEG 14
5-3
SEG 15
1-4
SEG 16
2-4
SEG 17
3-4
SEG 18
4-4
SEG 19
5-4
SEG 20
1-5
SEG 21
2-5
SEG 22
3-5
SEG 23
4-5
SEG 24
5-5
SEG 25
PHASE 1
PHASE 2
Figure 13. Filament Bridge Driver Timing Waveforms
VFIL
Q2
R2
1-6
SEG 26
2-6
SEG 27
3-6
SEG 28
4-6
SEG 29
5-6
SEG 30
1-7
SEG 31
2-7
SEG 32
3-7
SEG 33
4-7
SEG 34
5-7
SEG 35
CURSOR
Q4
R4
VFD TUBE
PHASE 1
PHASE 2
Q3
Q1
Figure 12. Relationship Between Segment Output and VFD
Tube 5 ✕ 7 Matrix Dots
GND
GND
Figure 14. Filament Bridge Driver (MOSFET)
Figure 14 shows the external components required for
the filament driver using a FET bridge.
PHASE1 and PHASE2 Outputs
PHASE1 and PHASE2 can be individually programmed
as one of four output types (Tables 36, 37).
When using the filament drive, first ensure that the filament duty-cycle register 0x09 is set to the correct value
before configuring the PHASE1 and PHASE2 outputs to
be filament drives. To stop the filament drive, program
either PHASE1 or PHASE2 (or both) to be logic-low general-purpose outputs. Both PHASE1 and PHASE2 outputs come out of power-on-reset in logic-low condition.
PUMP Output
The PUMP output can be programmed as one of four
output types (Table 38).
PORT0 and PORT1 Outputs
PORT0 and PORT1 can be individually programmed as
one of eight output types (Tables 39, 40). The PORT1
choices are similar to the PORT0 choices, except that
the last four items are invert logic. PORT0 output comes
out of power-on-reset in logic-low condition, whereas
PORT1 output initializes high.
The PORT0 and PORT1 shutdown outputs allow external hardware (for example, a DC-DC converter power
supply for VFD) to be disabled by the MAX6852 when
the MAX6852 is shut down.
The 625Hz, 1250Hz, and 2500Hz outputs can drive a
piezo sounder either from PORT0 or PORT1 alone, or
by both ports together as bridge drive. For bridge
drive, the sounder is connected between PORT0 and
PORT1, taking advantage of the PORT1 output being
inverted with respect to PORT0. Select different frequencies for PORT0 and PORT1 to obtain a wider
range of sounds when bridge drive is used.
Multiplex Clock and Blink Timing
The OSC1 and OSC2 inputs set the multiplex and blink
timing for the display driver. Connect an external resistor from OSC2 to GND and an external capacitor COSC
from OSC1 to GND to set the frequency of the internal
RC oscillator. Alternatively, overdrive OSC1 with an
external TTL or CMOS clock. If an exact blink rate or
multiplex period is required, use an external clock
ranging between 2MHz and 8MHz to drive OSC1.
______________________________________________________________________________________
19
MAX6852
4-Wire Interfaced, 5 ✕ 7 Matrix VacuumFluorescent Display Controller
The multiplex clock frequency determines the multiplex
scan rate and the blink timing. The display scan rate is
{OSC / 400 / (1 + grids register value)}. There are 400
OSC cycles per digit multiplex period. For example,
with OSC = 4MHz, each display digit is enabled for
100µs. For a 40-grid display tube (grids register value
= 39 or 0x27), the display scan rate is 250Hz.
The BLINK output is the selectable blink period clock. It
is nominally 0.5Hz or 1Hz (OSC = 4MHz). It is low during the first half of the blink period, and high during the
second half. The PORT0 and PORT1 general-purpose
outputs may be programmed to be BLINK output.
Synchronize the BLINK timing if desired by setting the
T bit in the configuration register (Table 19).
The RC oscillator uses an external resistor ROSC and
an external capacitor COSC to set the oscillator frequency. ROSC connects from OSC2 to ground. COSC
connects from OSC1 to ground. The recommended values of R OSC and C OSC set the oscillator to 4MHz,
which makes the BLINK frequencies 0.5Hz and 1 Hz:
fOSC = KF / (ROSC x [COSC + CSTRAY]) MHz
where:
KF = 2320
ROSC = external resistor in kΩ (allowable range 8kΩ to
80kΩ)
The effective value of COSC includes not only the actual
external capacitor used, but also the stray capacitance
from OSC1 to GND. This capacitance is usually in the
1pF-to-5pF range, depending on the layout used.
The allowed range of fOSC is 2MHz to 8MHz. If fOSC is
set too high, the internal oscillator can stop working. An
internal fail-safe circuit monitors the multiplex clock and
detects a slow or nonworking multiplex clock. When a
slow or nonworking multiplex clock is detected, an
internal fail-safe oscillator generates a replacement
clock of about 200kHz. This backup clock ensures that
the VFD is not damaged by the multiplex operation halting inadvertently. The scan rate for 16 digits is about
15Hz in fail-safe mode, and the display flickers. A flickering display is a good indication that there is a problem with the multiplex clock.
Power Supplies
The MAX6852 operates from a single 2.7V to 3.6V
power supply. Bypass the power supply to GND with a
0.1µF capacitor as close to the device as possible. Add
a bulk capacitor (such as a low-cost electrolytic 1µF to
22µF) if the MAX6852 is driving high current from any of
the general-purpose output ports.
COSC = external capacitor in pF
CSTRAY = stray capacitance from OSC1 to GND in pF,
typically 2pF
For OSC = 4MHz, ROSC is 10kΩ and COSC is 56pF.
Table 8. Memory Mapping of User-Defined Font Register 0x05
COMMAND
ADDRESS
REGISTER
DATA
READ OR
WRITE
0x85
0x00–0x7F
Read
Read 7-bit user-definable font data entry from current font address. MSB of the
register data is clear. Font address pointer is incremented after the read.
0x05
0x00–0x7F
Write
Write 7-bit user-definable font data entry to current font address. Font address
pointer is incremented after the write.
0x05
0x80–0xFF
Write
Write font address pointer with the register data.
FUNCTION
Table 9. Font Pointer Address Behavior
FONT POINTER
ADDRESS
0x80 to 0xF6
0xF7
0xF8 to 0xFF
20
ACTION
Valid range to set the font address pointer. Pointer autoincrements after a font data read or write, while pointer
address remains in this range.
Further font data is ignored after a font data read or write to this pointer address.
Invalid range to set the font address pointer. Pointer is set to 0x80.
______________________________________________________________________________________
4-Wire Interfaced, 5 ✕ 7 Matrix VacuumFluorescent Display Controller
FONT
CHARACTER
COMMAND
ADDRESS
REGISTER DATA
RAM00
0x05
RAM01
REGISTER DATA
0x80
D7
1
D6
0
D5
0
D4
0
D3
0
D2
0
D1
0
D0
0
0x05
0x85
1
0
0
0
0
1
0
1
RAM02
0x05
0x8A
1
0
0
0
1
0
1
0
RAM03
0x05
0x8F
1
0
0
0
1
1
1
1
RAM04
0x05
0x94
1
0
0
1
0
1
0
0
RAM05
0x05
0x99
1
0
0
1
1
0
0
1
RAM06
0x05
0x9E
1
0
0
1
1
1
1
0
RAM07
0x05
0xA3
1
0
1
0
0
0
1
1
RAM08
0x05
0xA8
1
0
1
0
1
0
0
0
RAM09
0x05
0xAD
1
0
1
0
1
1
0
1
RAM10
0x05
0xB2
1
0
1
1
0
0
1
0
RAM11
0x05
0xB7
1
0
1
1
0
1
1
1
RAM12
0x05
0xBC
1
0
1
1
1
1
0
0
RAM13
0x05
0xC1
1
1
0
0
0
0
0
1
RAM14
0x05
0xC6
1
1
0
0
0
1
1
0
RAM15
0x05
0xCB
1
1
0
0
1
0
1
1
RAM16
0x05
0xD0
1
1
0
1
0
0
0
0
RAM17
0x05
0xD5
1
1
0
1
0
1
0
1
RAM18
0x05
0xDA
1
1
0
1
1
0
1
0
RAM19
0x05
0xDF
1
1
0
1
1
1
1
1
RAM20
0x05
0xE4
1
1
1
0
0
1
0
0
RAM21
0x05
0xE9
1
1
1
0
1
0
0
1
RAM22
0x05
0xEE
1
1
1
0
1
1
1
0
RAM23
0x05
0xF3
1
1
1
1
0
0
1
1
______________________________________________________________________________________
21
MAX6852
Table 10. User-Definable Font Pointer Base Address
MAX6852
4-Wire Interfaced, 5 ✕ 7 Matrix VacuumFluorescent Display Controller
Table 11. User-Definable Character Storage Example
REGISTER DATA
FONT
CHARACTER
FONT ADDRESS
POINTER
COMMAND
ADDRESS
D7
D6
D5
D4
D3
D2
D1
D0
RAM00
0x00
0x05
0
0
1
1
1
1
1
0
RAM00
0x01
0x05
0
1
0
1
0
0
0
1
RAM00
0x02
0x05
0
1
0
0
1
0
0
1
RAM00
0x03
0x05
0
1
0
0
0
1
0
1
RAM00
0x04
0x05
0
0
1
1
1
1
1
0
RAM01
0x05
0x05
0
0
0
0
0
0
0
0
RAM01
0x06
0x05
0
1
0
0
0
0
1
0
RAM01
0x07
0x05
0
1
1
1
1
1
1
1
RAM01
0x08
0x05
0
1
0
0
0
0
0
0
RAM01
0x09
0x05
0
0
0
0
0
0
0
0
RAM02
0x0A
0x05
0
1
0
0
0
0
1
0
RAM02
0x0B
0x05
0
1
1
0
0
0
0
1
RAM02
0x0C
0x05
0
1
0
1
0
0
0
1
RAM02
0x0D
0x05
0
1
0
0
1
0
0
1
RAM02
0x0E
0x05
0
1
0
0
0
1
1
0
Table 12. Setting a Font Character to RAM Example
COMMAND
ADDRESS
REGISTER
DATA
0x05
0x8A
Set font address pointer to the base address of font character RAM02.
0x05
0x42
1st 7 bits of data: 1000010 goes to font address 0x8A; pointer then autoincrements to address 0x8B.
0x05
0x61
2nd 7 bits of data: 1100001 goes to font address 0x8B; pointer then autoincrements to address 0x8C.
0x05
0x51
3rd 7 bits of data: 1010001 goes to font address 0x8C; pointer then autoincrements to address 0x8D.
0x05
0x49
4th 7 bits of data: 1001001 goes to font address 0x8D; pointer then autoincrements to address 0x8E.
0x05
0x46
5th 7 bits of data: 1000110 goes to font address 0x8E; pointer then autoincrements to address 0x8F.
ACTION BEING PERFORMED
Table 13. Cursor Register Format
REGISTER DATA
COMMAND
ADDRESS
D7
Cursor register.
0x0F
BLINK
Digit 1's cursor is lit continuously.
0x0F
Digit 1's cursor is lit only for the first half of each blink
period.
0x0F
MODE
UP TO
D6
D5
D4
D3
0
0
0
0
0
1
0
0
0
D2
D1
D0
0
0
0
0
0
0
0
CURSOR POSITION
0x0F
UP TO
Digit 96's cursor is lit continuously.
0x0F
0
1
0
1
1
1
1
1
Digit 96's cursor is lit only for the first half of each blink
period.
0x0F
1
1
0
1
1
1
1
1
No cursor is lit.
0x0F
X
1
1
X
X
X
X
X
22
______________________________________________________________________________________
4-Wire Interfaced, 5 ✕ 7 Matrix VacuumFluorescent Display Controller
REGISTER DATA
ANNUNCIATOR BYTE
D7
D6
D5
D4
D3
D2
D1
D0
ANNUNCIATOR ANNUNCIATOR ANNUNCIATOR ANNUNCIATOR
A1
A4
A3
A2
BIT ALLOCATIONS
Annunciator A1 is off.
X
X
X
X
X
X
0
0
Annunciator A1 is lit only for the first half of each blink
period.
X
X
X
X
X
X
0
1
Annunciator A1 is lit only for the second half of each blink
period.
X
X
X
X
X
X
1
0
Annunciator A1 is lit continuously.
X
X
X
X
X
X
1
1
Annunciator A2 is off.
X
X
X
X
0
0
X
X
Annunciator A2 is lit only for the first half of each blink
period.
X
X
X
X
0
1
X
X
Annunciator A2 is lit only for the second half of each blink
period.
X
X
X
X
1
0
X
X
Annunciator A2 is lit continuously.
X
X
X
X
1
1
X
X
Annunciator A3 is off.
X
X
0
0
X
X
X
X
Annunciator A3 is lit only for the first half of each blink
period.
X
X
0
1
X
X
X
X
Annunciator A3 is lit only for the second half of each blink
period.
X
X
1
0
X
X
X
X
Annunciator A3 is lit continuously.
X
X
1
1
X
X
X
X
Annunciator A4 is off.
0
0
X
X
X
X
X
X
Annunciator A4 is lit only for the first half of each blink
period.
0
1
X
X
X
X
X
X
Annunciator A4 is lit only for the second half of each blink
period.
1
0
X
X
X
X
X
X
Annunciator A4 is lit continuously.
1
1
X
X
X
X
X
X
Table 15. Configuration Register Format
MODE
Configuration
register
REGISTER DATA
D7
D6
D5
D4
D3
D2
D1
Table 17. Configuration Lock
(L Data Bit D1) Format
D0
MODE
P
M
R
T
X
B
L
REGISTER DATA
D7
D6
D5
D4
D3
D2
D1
D0
Unlocked
P
M
R
T
X
B
0
S
Locked
P
M
R
T
X
B
1
S
S
Table 16. Shutdown Control
(S Data Bit D0) Format
MODE
REGISTER DATA
D7
D6
D5
D4
D3
D2
D1
D0
Shutdown
P
M
R
T
X
B
L
0
Normal operation
P
M
R
T
X
B
L
1
______________________________________________________________________________________
23
MAX6852
Table 14. Annunciator Registers Format
MAX6852
4-Wire Interfaced, 5 ✕ 7 Matrix VacuumFluorescent Display Controller
Table 18. Blink Rate Selection (B Data Bit D2) Format
REGISTER DATA
MODE
D7
D6
D5
D4
D3
D2
D1
D0
Slow blinking (cursor and annunciators blink on for 1s, off for 1s, for OSC = 4MHz)
P
M
R
T
X
0
L
S
Fast blinking (cursor and annunciators blink on for 0.5s, off for 0.5s, for OSC = 4MHz)
P
M
R
T
X
1
L
S
Table 19. Global Blink Timing Synchronization (T Data Bit D4) Format
REGISTER DATA
MODE
D7
D6
D5
D4
D3
D2
D1
D0
Blink timing counters are unaffected.
P
M
R
0
X
B
L
S
Blink timing counters are cleared on the rising edge of CS.
P
M
R
1
X
B
L
S
D7
D6
D5
D4
D3
D2
D1
D0
Segment and annunciator data are unaffected.
P
M
0
T
X
B
L
S
Segment and annunciator data (address range 0x20 to 0x7F) are cleared on the rising
edge of CS.
P
M
1
T
X
B
L
S
Table 20. Global Clear Digit Data (R Data Bit D5) Format
REGISTER DATA
MODE
Table 21. Display Mode (M Data Bit D6) Format
MODE
DISPLAY TYPE
48/1
96/2
REGISTER DATA
D7
D6
D5
D4
D3
D2
D1
D0
Up to 48 digits, 1 digit per grid
P
0
R
T
X
B
L
S
Up to 96 digits, 2 digits per grid
P
1
R
T
X
B
L
S
Table 22. Blink Phase Readback (P Data Bit D7) Format
REGISTER DATA
MODE
D7
D6
D5
D4
D3
D2
D1
D0
P1 blink phase
0
M
R
T
X
B
L
S
P0 blink phase
1
M
R
T
X
B
L
S
Table 23. Serial-Data Format (16 Bits)
D15
R/W
24
D14
D13
D12
D11
D10
COMMAND ADDRESS
D9
D8
D7
MSB
D6
D5
D4
D3
D2
REGISTER DATA
______________________________________________________________________________________
D1
D0
LSB
4-Wire Interfaced, 5 ✕ 7 Matrix VacuumFluorescent Display Controller
REGISTER DATA
COMMAND
ADDRESS
D7
D6
D5
D4
D3
D2
D1
D0
Display has 1 grid: G0
0x03
0
0
0
0
0
0
0
0
0x00
Display has 2 grids: G0 and G1
0x03
0
0
0
0
0
0
0
1
0x01
Display has 3 grids: G0 to G2
0x03
0
0
0
0
0
0
1
0
0x02
Display has 4 grids: G0 to G3
0x03
0
0
0
0
0
0
1
1
0x03
0x03
0
0
—
—
—
—
—
—
—
Display has 45 grids: G0 to G44
0x03
0
0
1
0
1
1
0
0
0x2C
Display has 46 grids: G0 to G45
0x03
0
0
1
0
1
1
0
1
0x2D
Display has 47 grids: G0 to G46
0x03
0
0
1
0
1
1
1
0
0x2E
Display has 48 grids: G0 to G47
0x03
0
0
1
0
1
1
1
1
0x2F
GRIDS
UP TO
HEX CODE
Table 25. Intensity Register Format
DUTY CYCLE
1/16 (min on)
REGISTER DATA
VFBLANK BEHAVIOR
(OSC = 4MHz)
COMMAND
ADDRESS
D7
D6
D5
D4
D3
D2
D1
D0
HEX
CODE
High for 6.25µs, low for 6.25µs, high for 87.5µs
0x02
X
X
X
X
0
0
0
0
0xX0
2/16
High for 6.25µs, low for 12.5µs, high for
81.25µs
0x02
X
X
X
X
0
0
0
1
0xX1
3/16
High for 6.25µs, low for 18.75µs, high for 75µs
0x02
X
X
X
X
0
0
1
0
0xX2
4/16
High for 6.25µs, low for 25µs, high for 68.75µs
0x02
X
X
X
X
0
0
1
1
0xX3
5/16
High for 6.25µs, low for 31.25µs, high for
62.5µs
0x02
X
X
X
X
0
1
0
0
0xX4
6/16
High for 6.25µs, low for 37.5µs, high for
56.25µs
0x02
X
X
X
X
0
1
0
1
0xX5
7/16
High for 6.25µs, low for 43.75µs, high for 50µs
0x02
X
X
X
X
0
1
1
0
0xX6
8/16
High for 6.25µs, low for 50µs, high for 43.75µs
0x02
X
X
X
X
0
1
1
1
0xX7
9/16
High for 6.25µs, low for 56.25µs, high for
37.5µs
0x02
X
X
X
X
1
0
0
0
0xX8
10/16
High for 6.25µs, low for 62.5µs, high for
31.25µs
0x02
X
X
X
X
1
0
0
1
0xX9
11/16
High for 6.25µs, low for 68.75µs, high for 25µs
0x02
X
X
X
X
1
0
1
0
0xXA
12/16
High for 6.25µs, low for 75µs, high for 18.75µs
0x02
X
X
X
X
1
0
1
1
0xXB
13/16
High for 6.25µs, low for 81.25µs, high for
12.5µs
0x02
X
X
X
X
1
1
0
0
0xXC
14/16
High for 6.25µs, low for 87.5µs, high for 6.25µs
0x02
X
X
X
X
1
1
0
1
0xXD
15/16
High for 6.25µs, low for 93.75µs
0x02
X
X
X
X
1
1
1
0
0xXE
15/16 (max on)
High for 6.25µs, low for 93.75µs
0x02
X
X
X
X
1
1
1
1
0xXF
______________________________________________________________________________________
25
MAX6852
Table 24. Grids Register Format
MAX6852
4-Wire Interfaced, 5 ✕ 7 Matrix VacuumFluorescent Display Controller
Table 26. VFBLANK Polarity Register Format
REGISTER DATA
COMMAND
ADDRESS
D7
D6
D5
D4
D3
D2
D1
D0
HEX
CODE
VFBLANK is high to disable the display.
0x01
X
X
X
X
X
X
0
0
0xX0
VFBLANK is low to disable the display.
0x01
X
X
X
X
X
X
1
0
0xX2
GRIDS
Table 27. Display-Test and Device ID Register Format
REGISTER DATA
COMMAND
ADDRESS
D7
D6
D5
D4
D3
D2
D1
D0
Normal operation
0x07
X
X
X
X
X
X
X
0
Display test
0x07
X
X
X
X
X
X
X
1
Read MAX6852 device ID and display test status
0x87
0
0
0
0
0
1
1
DT
MODE
Table 28. Shift-Limit Register Format
REGISTER DATA
COMMAND
ADDRESS
D7
D6
D5
D4
D3
D2
D1
D0
Minimum setting example (01)
0x0E
0
0
0
0
0
0
0
1
0x01
Maximum setting example (121 or 0x79)
0x0E
0
1
1
1
1
0
0
1
0x79
SHIFT LIMIT
26
______________________________________________________________________________________
HEX CODE
4-Wire Interfaced, 5 ✕ 7 Matrix VacuumFluorescent Display Controller
MAX6852
Table 29. Output Map RAM Codes
OUTPUT MAP RAM CODE
(DECIMAL)
APPLICATION
0 to 47
48 grids
48, 49, 50, 51, 52
53, 54, 55, 56, 57
68, 69, 70, 71, 72
73, 74, 75, 76, 77
78, 79, 80, 81, 82
Grids G0 to G47
5 x 7 matrix character segments 1-1, 2-1, 3-1, 4-1, 5-1
5 x 7 matrix character segments
58, 59, 60, 61, 62
63, 64, 65, 66, 67
FUNCTION MAPPED BY OUTPUT MAP RAM CODE
5 x 7 matrix character segments 1-2, 2-2, 3-2, 4-2, 5-2
5 x 7 matrix character segments 1-3, 2-3, 3-3, 4-3, 5-3
Digits 0 to 47 only
Use character registers
0x20 to 0x4F
(Figure 12)
83
5 x 7 matrix character segments 1-4, 2-4, 3-4, 4-4, 5-4
5 x 7 matrix character segments 1-5, 2-5, 3-5, 4-5, 5-5
5 x 7 matrix character segments 1-6, 2-6, 3-6, 4-6, 5-6
5 x 7 matrix character segments 1-7, 2-7, 3-7, 4-7, 5-7
5 x 7 matrix character segment DP
5 x 7 matrix character segments
Digits 48 to 95 only
84, 85, 86, 87, 88
89, 90, 91, 92, 93
5 x 7 matrix character segments 1-1, 2-1, 3-1, 4-1, 5-1
Use character registers 0x50 to 0x7F
(Figure 12)
Only valid for 96/2 mode
(display mode select bit M = 1)
—
5 x 7 matrix character segments 1-2, 2-2, 3-2, 4-2, 5-2
94, 95, 96, 97, 98
5 x 7 matrix character segments 1-3, 2-3, 3-3, 4-3, 5-3
99, 100, 101,102, 103
5 x 7 matrix character segments 1-4, 2-4, 3-4, 4-4, 5-4
104, 105, 106, 107, 108
—
109, 110, 111, 112, 113
5 x 7 matrix character segments 1-6, 2-6, 3-6, 4-6, 5-6
114, 115, 116, 117, 118
119
5 x 7 matrix character segments 1-5, 2-5, 3-5, 4-5, 5-5
5 x 7 matrix character segments 1-7, 2-7, 3-7, 4-7, 5-7
—
5 x 7 matrix character segment DP
4 annunciators
120 to 123
124
Only valid for 48/1 mode
(display mode select bit M = 0)
Cursor
Annunciator A1 to annunciator A4
Cursor segment for digits 0 to 47 only
Cursor
125
126, 127
Only valid for 96/2 mode
(display mode select bit M = 1)
Unused
Cursor segment for digits 48 to 95 only
No action
______________________________________________________________________________________
27
MAX6852
4-Wire Interfaced, 5 ✕ 7 Matrix VacuumFluorescent Display Controller
Table 30. Output Map RAM Initial Power-Up Status
OUTPUT MAP RAM
ADDRESS
OUTPUT MAP RAM CODE ON
POWER-UP (DECIMAL)
0x00 to 0x27
0–39
0x28, 0x29, 0x2A, 0x2B, 0x2C
FUNCTION MAPPED BY OUTPUT MAP RAM CODE
Grids 0–39
48, 49, 50, 51, 52
5 x 7 matrix character segments 1-1, 2-1, 3-1, 4-1, 5-1
0x2D, 0x2E, 0x2F, 0x30, 0x31
53, 54, 55, 56, 57
5 x 7 matrix character segments 1-2, 2-2, 3-2, 4-2, 5-2
0x32, 0x33, 0x34, 0x35, 0x36
58, 59, 60, 61, 62
5 x 7 matrix character segments 1-3, 2-3, 3-3, 4-3, 5-3
0x37, 0x38, 0x39, 0x3A, 0x3B
63, 64, 65, 66, 67
5 x 7 matrix character segments 1-4, 2-4, 3-4, 4-4, 5-4
0x3C, 0x3D, 0x3E, 0x3F, 0x40
68, 69, 70, 71, 72
5 x 7 matrix character segments 1-5, 2-5, 3-5, 4-5, 5-5
0x41, 0x42, 0x43, 0x44, 0x45
73, 74, 75, 76, 77
5 x 7 matrix character segments 1-6, 2-6, 3-6, 4-6, 5-6
0x46, 0x47, 0x48, 0x49, 0x4A
78, 79, 80, 81, 82
5 x 7 matrix character segments 1-7, 2-7, 3-7, 4-7, 5-7
0x4B
83
5 x 7 matrix character segment DP
0x4C, 0x4D, 0x4E, 0x4F, 0x50
84, 85, 86, 87, 88
5 x 7 matrix character segments 1-1, 2-1, 3-1, 4-1, 5-1
0x51, 0x52, 0x53, 0x54, 0x55
89, 90, 91, 92, 93
5 x 7 matrix character segments 1-2, 2-2, 3-2, 4-2, 5-2
0x56, 0x57, 0x58, 0x59, 0x5A
94, 95, 96, 97, 98
5 x 7 matrix character segments 1-3, 2-3, 3-3, 4-3, 5-3
0x5B, 0x5C, 0x5D, 0x5E, 0x5F
99, 100, 101,102, 103
5 x 7 matrix character segments 1-4, 2-4, 3-4, 4-4, 5-4
0x60, 0x61, 0x62, 0x63, 0x64
104, 105, 106, 107, 108
5 x 7 matrix character segments 1-5, 2-5, 3-5, 4-5, 5-5
0x65, 0x66, 0x67, 0x68, 0x69
109, 110, 111, 112, 113
5 x 7 matrix character segments 1-6, 2-6, 3-6, 4-6, 5-6
0x6A, 0x6B, 0x6C, 0x6D, 0x6E
114, 115, 116, 117, 118
5 x 7 matrix character segments 1-7, 2-7, 3-7, 4-7, 5-7
0x6F
119
5 x 7 matrix character segment DP
0x70
124
Cursor segment for digits 0 to 47 1st row
0x71
125
Cursor segment for digits 0 to 47 2nd row
0x72 to 0x79
127
No action
Table 31. Setting Output Map Address Pointer
REGISTER DATA
COMMAND
ADDRESS
D7
D6
D5
D4
D3
D2
D1
D0
Set output map address to minimum (0x00) with data
0x80. (Note that this address is set as a power-up
default.)
0x06
1
0
0
0
0
0
0
0
Set output map address to maximum 0x79 with data
0xF9.
0x06
1
1
1
1
1
0
0
1
COMMAND
ADDRESS
D7
D6
D5
D2
D1
D0
0x06
0
MODE
Table 32. Writing Output Map Data
MODE
Write output map data; output map address pointer is
autoincremented after the output map data has been
written to the current location.
28
REGISTER DATA
D4
D3
7 bits of output map data
______________________________________________________________________________________
4-Wire Interfaced, 5 ✕ 7 Matrix VacuumFluorescent Display Controller
MODE
REGISTER DATA
COMMAND
ADDRESS
D7
0x86
0
Read output map data; output map address pointer is
autoincremented after the output map data has been
read from the current location.
D6
D5
D4
D3
D2
D1
D0
7 bits of output map data
Table 34. Filament Bridge Driver Timing
TIMING POINT
PHASE1 BEHAVIOR
PHASE2 BEHAVIOR
EXAMPLE 1
DUTY = 1 (MIN)
EXAMPLE 2
DUTY = 100
EXAMPLE 3
DUTY = 198
(A)
Low for (199 - FilOn)
cycles
Low for (199 - FilOn)
cycles
198
99
1
198
(B)
Low for (FilOn) cycles
High for (FilOn) cycles
1
100
(C)
Low for (2) cycles
Low for (2) cycles
2
2
2
(D)
High for (FilOn) cycles
Low for (FilOn) cycles
1
100
198
(E)
Low for (199 - FilOn)
cycles
Low for (199 - FilOn)
cycles
198
99
1
Total 4MHz
cycles
(OSC = 4MHz)
400 cycles = 100µs
400 cycles = 100µs
400 cycles =
100µs
400 cycles =
100µs
400 cycles =
100µs
Table 35. Filament Duty-Cycle Register Format
REGISTER DATA
COMMAND
ADDRESS
D7
D6
D5
D4
D3
D2
D1
D0
Minimum setting example (01)
0x09
0
0
0
0
0
0
0
1
0x01
Maximum setting example (199 or 0xC7)
0x09
1
1
0
0
0
1
1
1
0xC7
FILAMENT DUTY CYCLE
HEX CODE
Table 36. PHASE1 Register Format
REGISTER DATA
COMMAND
ADDRESS
D7
D6
D5
D4
D3
D2
D1
D0
General-purpose output, logic 0.
This is the power-up condition.
0x0A
X
X
X
X
X
X
0
0
0xX0
General-purpose output, logic 1.
0x0A
X
X
X
X
X
X
0
1
0xX1
Output gives blink status:
0 if blink phase P0; 1 if blink phase P1.
0x0A
X
X
X
X
X
X
1
0
0xX2
Filament drive PHASE1 (logic 0 during
shutdown).
0x0A
X
X
X
X
X
X
1
1
0xX3
PHASE1 BEHAVIOR
HEX CODE
______________________________________________________________________________________
29
MAX6852
Table 33. Reading Output Map Data
MAX6852
4-Wire Interfaced, 5 ✕ 7 Matrix VacuumFluorescent Display Controller
Table 37. PHASE2 Register Format
REGISTER DATA
COMMAND
ADDRESS
D7
D6
D5
D4
D3
D2
D1
D0
General-purpose output, logic 0.
This is the power-up condition.
0x0B
X
X
X
X
X
X
0
0
0xX0
General-purpose output, logic 1.
0x0B
X
X
X
X
X
X
0
1
0xX1
Output gives blink status: 0 if blink phase P0;
1 if blink phase P1.
0x0B
X
X
X
X
X
X
1
0
0xX2
Filament drive PHASE2 (logic 0 during
shutdown).
0x0B
X
X
X
X
X
X
1
1
0xX3
COMMAND
ADDRESS
D7
D6
D5
D4
D3
D2
D1
D0
General-purpose output, logic 0.
This is the power-up condition.
0x08
X
X
X
X
X
X
0
0
0xX0
General-purpose output, logic 1.
0x08
X
X
X
X
X
X
0
1
0xX1
80kHz square-wave output (OSC = 4MHz)
(logic 0 during shutdown).
0x08
X
X
X
X
X
X
1
0
0xX2
DOUT output.
0x08
X
X
X
X
X
X
1
1
0xX3
PHASE2 BEHAVIOR
HEX CODE
Table 38. PUMP Register Format
PUMP PORT BEHAVIOR
REGISTER DATA
HEX CODE
Table 39. PORT0 Register Format
REGISTER DATA
COMMAND
ADDRESS
D7
D6
D5
D4
D3
D2
D1
D0
General-purpose output, logic 0.
This is the power-up condition.
0x0C
X
X
X
X
X
0
0
0
0xX0
General-purpose output, logic 1.
0x0C
X
X
X
X
X
0
0
1
0xX1
Output gives blink status: 0 if blink phase P0;
1 if blink phase P1.
0x0C
X
X
X
X
X
0
1
0
0xX2
DOUT output.
0x0C
X
X
X
X
X
0
1
1
0xX3
625Hz square-wave output zero in
shutdown.
0x0C
X
X
X
X
X
1
0
0
0xX4
1250Hz square-wave output zero in
shutdown.
0x0C
X
X
X
X
X
1
0
1
0xX5
2500Hz square-wave output zero in
shutdown.
0x0C
X
X
X
X
X
1
1
0
0xX6
Output gives shutdown status: 0 if
shutdown mode; 1 if operating mode.
0x0C
X
X
X
X
X
1
1
1
0xX7
PORT0 PORT BEHAVIOR
30
______________________________________________________________________________________
HEX CODE
4-Wire Interfaced, 5 ✕ 7 Matrix VacuumFluorescent Display Controller
REGISTER DATA
COMMAND
ADDRESS
D7
D6
D5
D4
D3
D2
D1
D0
General-purpose output, logic 0.
0x0D
X
X
X
X
X
0
0
0
0xX0
General-purpose output, logic 1.
This is the power-up condition.
0x0D
X
X
X
X
X
0
0
1
0xX1
Output gives blink status: 0 if blink phase
P0; 1 if blink phase P1.
0x0D
X
X
X
X
X
0
1
0
0xX2
DOUT output.
0x0D
X
X
X
X
X
0
1
1
0xX3
Inverted 625Hz square-wave output 1 in
shutdown.
0x0D
X
X
X
X
X
1
0
0
0xX4
Inverted 1250Hz square-wave output 1 in
shutdown.
0x0D
X
X
X
X
X
1
0
1
0xX5
Inverted 2500Hz square-wave output 1 in
shutdown.
0x0D
X
X
X
X
X
1
1
0
0xX6
Output gives inverted shutdown status:
1 if shutdown mode; 0 if operating mode.
0x0D
X
X
X
X
X
1
1
1
0xX7
PORT1 PORT BEHAVIOR
Functional Diagram
HEX CODE
Pin Configuration
TOP VIEW
OSC1
OSC2
CLOCK
GENERATOR
OUTPUT
MAP
RAM
CHARACTERGENERATOR
ROM
RAM
CLK
CS
DIN
DOUT
PWM
BRIGHTNESS
CONTROL
VFBLANK
OUTPUT
SHIFTER
VFDOUT
VFCLK
VFLOAD
16 OSC2
VFDOUT 2
15 OSC1
VFLOAD 3
14 PORT1
VFBLANK 4
MAX6852
PUMP 5
FILAMENT
PWM
USER
OUTPUTS
VFCLK 1
PHASE 1
PHASE 2
PUMP
PORT 0
PORT 1
13 CS
12 DIN
PHASE1 6
11 SCLK
PHASE2 7
10 PORT0
V+ 8
9
GND
QSOP
CONFIGURATION
REGISTERS
Chip Information
4-WIRE SERIAL INTERFACE
TRANSISTOR COUNT: 197,738
PROCESS: CMOS
______________________________________________________________________________________
31
MAX6852
Table 40. PORT1 Register Format
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
QSOP.EPS
MAX6852
4-Wire Interfaced, 5 ✕ 7 Matrix VacuumFluorescent Display Controller
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
32 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2002 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products.