Revised January 2004 74F283 4-Bit Binary Full Adder with Fast Carry General Description The 74F283 high-speed 4-bit binary full adder with internal carry lookahead accepts two 4-bit binary words (A0–A3, B0–B3) and a Carry input (C0). It generates the binary Sum outputs (S0–S3) and the Carry output (C4) from the most significant bit. The 74F283 will operate with either active HIGH or active LOW operands (positive or negative logic). Ordering Code: Order Number Package Number Package Description 74F283SC M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow 74F283PC N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Logic Symbols Connection Diagram IEEE/IEC Unit Loading/Fan Out Pin Names © 2004 Fairchild Semiconductor Corporation DS009513 Description U.L. Input IIH/IIL HIGH/LOW Output IOH/IOL 20 µA/−1.2 mA A0–A3 A Operand Inputs 1.0/2.0 B0–B3 B Operand Inputs 1.0/2.0 20 µA/−1.2 mA C0 Carry Input 1.0/1.0 20 µA/−0.6 mA S0–S3 Sum Outputs 50/33.3 −1 mA/20 mA C4 Carry Output 50/33.3 −1 mA/20 mA www.fairchildsemi.com 74F283 4-Bit Binary Full Adder with Fast Carry April 1988 74F283 Functional Description However, other means can be used to effectively insert a carry into, or bring a carry out from, an intermediate stage. Figure 2 shows how to make a 3-bit adder. Tying the operand inputs of the fourth adder (A3, B3) LOW makes S3 dependent only on, and equal to, the carry from the third adder. Using somewhat the same principle, Figure 3 shows a way of dividing the 74F283 into a 2-bit and a 1-bit adder. The third stage adder (A2, B2, S2) is used merely as a means of getting a carry (C10) signal into the fourth stage (via A2 and B2) and bringing out the carry from the second stage on S2. Note that as long as A2 and B2 are the same, whether HIGH or LOW, they do not influence S2. Similarly, when A2 and B2 are the same the carry into the third stage does not influence the carry out of the third stage. Figure 4 shows a method of implementing a 5-input encoder, where the inputs are equally weighted. The outputs S0, S1 and S2 present a binary number equal to the number of inputs I1– I5 that are true. Figure 5 shows one method of implementing a 5-input majority gate. When three or more of the inputs I1–I5 are true, the output M5 is true. The 74F283 adds two 4-bit binary words (A plus B) plus the incoming Carry (C0). The binary sum appears on the Sum (S0–S3) and outgoing carry (C4) outputs. The binary weight of the various inputs and outputs is indicated by the subscript numbers, representing powers of two. 20 (A0 + B0 + C0) + 21 (A1 + B1) + 22 (A2 + B2) + 23 (A3 + B3) = S0 + 2S1 + 4S2 + 8S3 + 16C4 Where (+) = plus Interchanging inputs of equal weight does not affect the operation. Thus C0, A0, B0 can be arbitrarily assigned to pins 5, 6 and 7 for DIPS, and 7, 8 and 9 for chip carrier packages. Due to the symmetry of the binary add function, the 74F283 can be used either with all inputs and outputs active HIGH (positive logic) or with all inputs and outputs active LOW (negative logic). See Figure 1. Note that if C0 is not used it must be tied LOW for active HIGH logic or tied HIGH for active LOW logic. Due to pin limitations, the intermediate carries of the 74F283 are not brought out for use as inputs or outputs. C0 A0 A1 A2 A3 B0 B1 B2 B3 S0 S1 S2 S3 C4 Logic Levels L L H L H H L L H H H L L H Active HIGH 0 0 1 0 1 1 0 0 1 1 1 0 0 1 Active LOW 1 1 0 1 0 0 1 1 0 0 0 1 1 0 Active HIGH: 0 + 10 + 9 = 3 + 16 Active LOW: 1 + 5 + 6 = 12 + 0 FIGURE 1. Active HIGH versus Active LOW Interpretation FIGURE 2. 3-Bit Adder FIGURE 3. 2-Bit and 1-Bit Adders FIGURE 4. 5-Input Encoder FIGURE 5. 5-Input Majority Gate www.fairchildsemi.com 2 74F283 Logic Diagram Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. 3 www.fairchildsemi.com 74F283 Absolute Maximum Ratings(Note 1) Recommended Operating Conditions Storage Temperature −65°C to +150°C Ambient Temperature under Bias −55°C to +125°C Free Air Ambient Temperature Junction Temperature under Bias −55°C to +150°C Supply Voltage 0°C to +70°C +4.5V to +5.5V −0.5V to +7.0V VCC Pin Potential to Ground Pin Input Voltage (Note 2) −0.5V to +7.0V Input Current (Note 2) −30 mA to +5.0 mA Voltage Applied to Output in HIGH State (with VCC = 0V) Standard Output −0.5V to VCC 3-STATE Output −0.5V to +5.5V Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Current Applied to Output in LOW State (Max) Note 2: Either voltage limit or current limit is sufficient to protect inputs. twice the rated IOL (mA) ESD Last Passing Voltage (Min) 4000V DC Electrical Characteristics Symbol Parameter Min Typ Max VCC Units VIH Input HIGH Voltage VIL Input LOW Voltage 0.8 V VCD Input Clamp Diode Voltage −1.2 V Min V Min VOH Output HIGH Voltage VOL Output LOW Voltage IIH Input HIGH 2.0 10% VCC 2.5 5% VCC 2.7 V 10% VCC Current IBVI Input HIGH Current Breakdown Test ICEX Output HIGH Leakage Current VID Input Leakage IOD Output Leakage IIL V Min IOL = 20 mA µA Max VIN = 2.7V 7.0 µA Max VIN = 7.0V 50 µA Max VOUT = VCC V 0.0 µA 0.0 mA Max −150 mA Max VOUT = 0V −0.6 Input LOW Current −1.2 −60 IOH = −1 mA IOH = −1 mA 5.0 3.75 Circuit Current Recognized as a LOW Signal IIN = −18 mA 0.5 4.75 Test Conditions Recognized as a HIGH Signal IID = 1.9 µA All Other Pins Grounded VIOD = 150 mV All Other Pins Grounded VIN = 0.5V (CO) VIN = 0.5V (An, Bn) IOS Output Short-Circuit Current ICCH Power Supply Current 36 55 mA Max VO = HIGH ICCL Power Supply Current 36 55 mA Max VO = LOW AC Electrical Characteristics Symbol Parameter TA = +25°C TA = −55°C to +125°C TA = 0°C to +70°C VCC = +5.0V VCC = 5.0V VCC = 5.0V CL = 50 pF CL = 50 pF CL = 50 pF Min Typ Max Min Max Min Max tPLH Propagation Delay 3.5 7.0 9.5 3.5 14.0 3.5 11.0 tPHL C0 to Sn 3.0 7.0 9.5 3.0 14.0 3.0 11.0 tPLH Propagation Delay 3.0 7.0 9.5 3.0 17.0 3.0 13.0 tPHL An or Bn to Sn 3.0 7.0 9.5 3.0 14.0 3.0 11.5 tPLH Propagation Delay 3.0 5.7 7.5 3.0 10.5 3.0 8.5 tPHL C0 to C4 3.0 5.4 7.0 2.5 10.0 3.0 8.0 tPLH Propagation Delay 3.0 5.7 7.5 3.0 10.5 3.0 8.5 tPHL An or Bn to C4 2.5 5.3 7.0 2.5 10.0 2.5 8.0 www.fairchildsemi.com 4 Units ns ns ns ns 74F283 Physical Dimensions inches (millimeters) unless otherwise noted 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow Package Number M16A 5 www.fairchildsemi.com 74F283 4-Bit Binary Full Adder with Fast Carry Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Package Number N16E Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. 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