4 Channel 500MSPS DDS with 10-bit DACs AD9959 Preliminary Technical Data FEATURES Software/Hardware controlled power-down Dual supply operation (1.8 V DDS core / 3.3 V serial I/O) Built-in synchronization for multiple devices Selectable REF_CLK multipier(PLL) 4x to 20x (bypassable) Selectable REF_CLK crystal operation 56 pin LFCSP package Four synchronized DDS channels @500 MSPS Independent frequency / phase / amplitude control between all channels Matched latencies for Freq, Phase, and Amplitude changes Excellent channel to channel isolation Frequency sweeping capability Up to 16 levels of modulation (pin selectable) Individually programmable DAC full scale currents Four integrated 10-bit D/A converters(DACs) 32-bit frequency tuning resolution 14-bit phase offset resolution 10-bit output amplitude scaling resolution Serial I/O Port(SPI) with enhanced data throughput APPLICATIONS Agile L.O. frequency synthesis Phased array radar / sonar Instrumentation Synchronized clocking RF source for AOTF FUNCTIONAL BLOCK DIAGRAM DDS CORE FREQUENCY ACCUMULATOR 32 Σ Σ Σ 32 15 COS(X) 10 × 10 × 10 × 10 × 10 DAC 10 DAC 10 DAC 10 DAC IOUT IOUT DDS CORE FREQUENCY ACCUMULATOR 32 Σ Σ Σ 32 15 COS(X) DDS CORE FREQUENCY ACCUMULATOR 32 Σ Σ Σ 32 15 COS(X) IOUT IOUT IOUT IOUT DDS CORE FREQUENCY ACCUMULATOR 32 Σ 32 RAMP RATE DFTW 32 8 FTW SYNC_IN SYNC_OUT I/O_UPDATE Σ Σ PHASE OFFSET 32 15 COS(X) 14 DIGITAL MULTIPLIER 10 SCALABLE DAC REF CURRENT Timing & Control Logic OSC / REF_CLK DAC_RSET MASTER_RESET CONTROL REGISTERS REF CLOCK MULTIPLIER (PLL) 4x to 20x OSC / REF_CLK IOUT PWR_DWN_CTL SYSTEM CLK ÷4 SYNC_CLK IOUT M U X CHANNEL REGISTERS PROFILE REGISTERS BUFFER / XTAL OSCILLATOR 1.8V 1.8V AVDD DVDD SCLK CS I/O Port Buffer SDIO_0 SDIO_1 SDIO_2 SDIO_3 3.3V P P P P S S S S 0 1 2 3 CLK_MODE_SEL DVDD_IO Figure 1 AD9959 Block Diagram Rev. PrB Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.326.8703 © 2004 Analog Devices, Inc. All rights reserved. AD9959 Preliminary Technical Data AD9959—SPECIFICATIONS Table 1. Unless otherwise noted, AVDD, DVDD = 1.8 V ± 5%, DVDD_I/O = 3.3 V ± 5%, RSET = 1.96 kΩ, External Reference Clock Frequency = 500 MSPS (REF_CLK multiplier bypassed) Parameter Min Typ Max Units REF_CLK inputs must be AC coupled due to internal biasing REF CLOCK INPUT CHARACTERISTICS Frequency Range REF_CLK Multiplier bypassed REF_CLK Multiplier enabled at 4x(min) REF_CLK Multiplier enabled at 20x(max) Internal VCO range w/ REF_CLK multiplier enabled Crystal REF_CLK source mode Input Power Sensitivity Input voltage level Input Capacitance Input Impedance Duty Cycle w/ REF_CLK Multiplier bypassed Duty Cycle w/ REF_CLK Multiplier enabled CLK Mode Select logic 1 Voltage CLK Mode Select logic 0 Voltage 0 25 5 100 20 -15 500 125 25 500 30 3 400 3 1500 50 35 1.25 65 0.6 MHz MHz MHz MHz MHz dBm mV pF ohms % % V V DAC OUTPUT CHARACTERISTICS Resolution Full Scale Ouput Current Gain Error Output Offset Differential Nonlinearity Integral Nonlinearity Output Capactiance Voltage Compliance Range Channel to Channel Isolation Channel to Channel amplitude matching error External 50 ohm termination Not a 3.3V digital input Not a 3.3V digital input Must be referenced to AVDD 10 10 -10 10 0.6 0.5 1 -0.5 -1 5 AVDD– 0.50 AVDD + 0.50 60 2 Bits mA %FS uA LSB LSB pF V dB % Wideband SFDR defined as DC to Nyquist WIDEBAND SFDR 1-20 MHz Analog Out 20-60 MHz Analog Out 60-100 MHz Analog Out 100-150 MHz Analog Out 150-200 MHz Analog Out Test Conditions/Comments -65 -62 -59 -56 -54 dBc dBc dBc dBc dBc 1.1 MHz Analog Out (+/- 10kHz) 1.1 MHz Analog Out (+/- 50kHz) 1.1 MHz Analog Out (+/- 250kHz) 1.1 MHz Analog Out (+/- 1MHz) -90 -88 -86 -85 dBc dBc dBc dBc 15.1 MHz Analog Out (+/- 10kHz) 15.1 MHz Analog Out (+/- 50kHz) 15.1 MHz Analog Out (+/- 250kHz) 15.1 MHz Analog Out (+/- 1MHz) -90 -87 -85 -83 dBc dBc dBc dBc 40.1 MHz Analog Out (+/- 10kHz) 40.1 MHz Analog Out (+/- 50kHz) 40.1 MHz Analog Out (+/- 250kHz) 40.1 MHz Analog Out (+/- 1MHz) -90 -87 -84 -82 dBc dBc dBc dBc NARROWBAND SFDR Rev. PrB | Page 2 of 9 Preliminary Technical Data AD9959 Min Parameter Typ Max Units 75.1 MHz Analog Out (+/- 10kHz) 75.1 MHz Analog Out (+/- 50kHz) 75.1 MHz Analog Out (+/- 250kHz) 75.1 MHz Analog Out (+/- 1MHz) -87 -85 -83 -82 dBc dBc dBc dBc 100.1 MHz Analog Out (+/- 10kHz) 100.1 MHz Analog Out (+/- 50kHz) 100.1 MHz Analog Out (+/- 250kHz) 100.1 MHz Analog Out (+/- 1MHz) -87 -85 -83 -81 dBc dBc dBc dBc 200.1 MHz Analog Out (+/- 10kHz) 200.1 MHz Analog Out (+/- 50kHz) 200.1 MHz Analog Out (+/- 250kHz) 200.1 MHz Analog Out (+/- 1MHz) -87 -85 -83 -81 dBc dBc dBc dBc TBD TBD TBD TBD dBc/ Hz dBc/ Hz dBc/ Hz dBc/ Hz TBD TBD TBD TBD dBc/ Hz dBc/ Hz dBc/ Hz dBc/ Hz TBD TBD TBD TBD dBc/ Hz dBc/ Hz dBc/ Hz dBc/ Hz TBD TBD TBD TBD dBc/ Hz dBc/ Hz dBc/ Hz dBc/ Hz TBD TBD TBD TBD dBc/ Hz dBc/ Hz dBc/ Hz dBc/ Hz @1kHz offset TBD dBc/ Hz @10kHz offset TBD dBc/ Hz @100kHz offset TBD dBc/ Hz @1MHz offset TBD dBc/ Hz Maximum Frequency 200 MHz Minimum Clock Pulsewidth Low (tPWL) TBD ns Minimum Clock Pulsewidth High (tPWH) TBD ns PHASE NOISE CHARACTERISTICS Residual Phase Noise @15.1 MHz(Aout) @1kHz offset @10kHz offset @100kHz offset @1MHz offset Residual Phase Noise @ 75.1 MHz(Aout) @1kHz offset @10kHz offset @100kHz offset @1MHz offset Residual Phase Noise @ 200.1 MHz(Aout) @1kHz offset @10kHz offset @100kHz offset @1MHz offset Residual Phase Noise @ 15.1 MHz(Aout) w/ REF CLK multiplier enabled 4x @1kHz offset @10kHz offset @100kHz offset @1MHz offset Residual Phase Noise @ 75.1 MHz(Aout) w/ REF CLK multiplier enabled 4x @1kHz offset @10kHz offset @100kHz offset @1MHz offset Residual Phase Noise @ 200.1 MHz(Aout) w/ REF CLK multiplier enabled 4x SERIAL PORT TIMING CHARACTERISTICS Rev. PrB | Page 3 of 9 Test Conditions/Comments AD9959 Preliminary Technical Data Maximum Clock Rise/Fall Time TBD ns Minimum Data Setup Time (tDS) TBD ns Minimum Data Hold Time TBD ns TBD Sync CLK 1 Sync CLK Minimum setup time (IO_Update to Sync_CLK) TBD ns Rising edge to rising edge Minimum hold time (IO_Update to Sync_CLK) 0 ns Rising edge to rising edge Minimum setup time (Profile inputs to Sync_CLK) TBD ns Minimum hold time (Profile inputs to Sync_CLK) 0 ns MISC TIMING CHARACTERISTICS Master_Reset minimum Pulsewidth I/O_Update minimum Pulsewidth Matched pipe line of Freq, Phase, Amplitude TBD Sys Clks Pipeline delays for Freq, Phase, Amp changes are programmable to match one another. matched Frequency word to DAC output TBD Sys Clks unmatched Phase Offset word to DAC output TBD Sys Clks unmatched Amplitude word to DAC output TBD Sys Clks unmatched DATA LATENCY (PIPE LINE DELAY) CMOS LOGIC INPUTS VIH 2.2 V VIL Logic 1 Current Logic 0 Current 3 0.6 V 12 uA -12 Input Capacitance uA 2 pF CMOS LOGIC OUTPUTS (1 mA Load) VOH 2.8 V VOL 0.4 V POWER SUPPLY Total Power Dissipation- all channels ON, single-tone mode TBD Maximum Power Dissipation- all channels, freq accumulator output multiplier ON Iavdd – All Channels ON, Single tone mode TBD TBD mA Iavdd – All Ch(s) ON, Freq accum, and output multiplier ON TBD mA Idvdd – All Ch(s) ON, Single tone mode TBD mA Idvdd – All Ch(s) ON, Freq accum, and output multiplier ON TBD mA Idvdd_I/O TBD mA Power down Mode TBD mA Rev. PrB | Page 4 of 9 mW Preliminary Technical Data AD9959 ABSOLUTE MAXIMUM RATINGS Table 2. Parameter Maximum Junction Temperature DVDD_I/O (Pin 49) AVDD, DVDD Digital Input Voltage (DVDD_I/O = 3.3 V) Digital Output Current Storage Temperature Operating Temperature Lead Temperature (10 sec Soldering) Rating 150°C 4V 2V –0.7 V to +4V 5 mA –65°C to +150°C –40°C to +105°C 300°C θJA 21°C/W θJC 2°C/W Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. CMOS DIGITAL INPUTS OSC / REF_CLK INPUTS DAC OUPUTS AVDD DVDD_I/O= 3.3V Iout Iout 1.5 k INPUT z z 1.5 k REF_CLK REF_CLK OUTPUT AVDD AVOID OVERDRIVING DIGITAL INPUTS. FORWARD BIASING DIODES MAY COUPLE DIGITAL NOISE ON POWER PINS. TERMINATE OUTPUTS INTO AVDD. DO NOT EXCEED OUTPUT VOLTAGE COMPLIANCE. AVDD AMP OSC REF_CLK INPUTS ARE INTERNALLY BIASED AND NEED TO BE AC-COUPLED. OSC INPUTS ARE DC COUPLED Figure 1 Equivalent input and output circuits Rev. PrB | Page 5 of 9 OSC AD9959 Preliminary Technical Data PRODUCT OVERVIEW The AD9959 consists of four independently programmable DDS channels. The AD9959 features independent frequency, phase, and amplitude control of each channel; this allows for the correction of imbalances due to analog processing such as filtering, amplification, or PCB layout related mismatches. The AD9959 supports frequency sweeping for radar and instrumentation applications. Since all four channels share a common system clock, they are inherently synchronized. If more than four channels are required, synchronizing multiple AD9959s is a simple task. Each DDS acts as a high resolution frequency divider with the REF_ CLK as the input and the DAC providing the output. The REF_CLK input source is common to all DDS channels, and can be driven directly, or used in combination with an integrated REF_CLK multiplier (using a PLL) up to a maximum of 500 MSPS. The REF_ CLK multiplication factor is programmable from 4 to 20, in integer steps. The REF_CLK input features an oscillator which supports either a crystal as a source, or may be bypassed. The crystal frequency must be between 20MHz and 30MHz. The crystal can be used with or without the REF_CLK multiplier. The AD9959 uses advanced DDS technology which provides low power dissipation with high performance. The device incorporates four integrated high speed 10-bit DACs with excellent wideband and narrowband SFDR. Each DDS has a 32bit frequency tuning word, 14-bits of phase offset, and a 10-bit output scale multiplier. The DAC outputs are supply referenced and must be terminated into AVDD by a resistor, or an AVDD center-tapped transformer. Each DAC has it own programmable reference to enable a different full scale current for each channel. The AD9959 operates over the industrial temperature range of -40C to +85 The AD9959 comes in a space-saving 56-lead LFCSP package. The DDS core (AVDD and DVDD pins) must be powered by a 1.8V supply. The digital I/O interface (SPI) operates at 3.3V and requires that the pin labeled “DVDD_I/O” (pin 49) be connected to 3.3V. Rev. PrB | Page 6 of 9 Preliminary Technical Data AD9959 SCLK CS I/O_UPDATE 49 48 47 46 P3 DVDD_I/O 50 43 SDIO_0 51 DVDD SDIO_1 52 DGND SDIO_2 53 44 SDIO_3 54 45 DVDD SYNC_CLK 55 DGND 56 PIN CONFIGURATION SYNC_IN 1 42 SYNC_OUT 2 41 MASTER_RESET 3 PWR_DWN_CTL 4 AVDD 5 AGND 6 AVDD P2 P1 40 P0 AD9959 39 AVDD 38 AGND 56-LD LFCSP 37 AVDD 7 36 CH1_IOUT CH2_IOUT 8 35 CH1_IOUT CH2 _IOUT 9 34 AGND AGND 10 33 AVDD AVDD 11 32 AGND 19 20 21 22 23 24 25 26 27 28 AVDD OSC / REF_CLK OSC / REF_CLK CLK_MODE_SEL AGND AVDD LOOP_FILTER AGND AGND AVDD 18 DAC_RSET AGND 17 14 16 CH3_IOUT TOP VIEW (Not to Scale) AGND 13 15 12 AVDD AGND CH3_IOUT Notes : 1) The exposed EPAD on bottom side of package is an electrical connection and must be soldered to ground. 2) Pin 49 is DVDD_IO and is tied to 3.3V. Rev. PrB | Page 7 of 9 31 AVDD 30 CH0_IOUT 29 CH0_IOUT AD9959 Preliminary Technical Data Table 3. Pin Function Descriptions Pin No. 1 2 3 Mnemonic SYNC_IN SYNC_OUT I/O I O I Description Used to synchronize multiple AD9959s. Connect to the SYNC_OUT pin of the master AD9959. Used to synchronize multiple AD9959s. Connect to the SYNC_IN pin of the slave AD9959. Active high reset pin. Asserting the RESET pin forces the AD9959’s internal registers to their default state, as described in the serial I/O port register map section in this document. MASTER_RESET PWR_DWN_CTL AVDD I I External Power-Down Control. Analog Power Supply Pins (1.8V). AGND I Analog Ground Pins. I I O Digital Power Supply Pins (1.8 V). Digital Power Ground Pins. True DAC Output. Terminate into AVDD. O Complementary DAC Output. Terminate into AVDD. O True DAC Output. Terminate into AVDD. O Complementary DAC Output. Terminate into AVDD. 17 DVDD DGND CH2_IOUT _________ CH2_IOUT CH3_IOUT _________ CH3_IOUT DAC_RSET I 22 OSC / REF_CLK I 23 OSC / REF_CLK I 24 CLK_MODE_SEL I 27 LOOP_FILTER I Establishes the reference current for all DACs. A 1.962 kΩ resistor (nominal) is connected from pin 17 to AGND. Complementary Reference Clock/Oscillator Input. When the REF_CLK is operated in singleended mode, this pin should be decoupled to AVDD or AGND with a 0.1 µF capacitor. Reference Clock/Oscillator Input. When the REF_CLK is operated in single-ended mode, this is the input. Control Pin for the Oscillator Section. When high (1.8V), the oscillator section is enabled to accept a crystal as the REFCLK source. When low, the oscillator section is bypassed. CAUTION: Do not drive this pin beyond 1.8V. Connect to the external zero compensation network of the PLL loop filter for the REFCLK multiplier. For a 20x multiplier value the network should be a 1.2kΩ resistor in series with a 1.2 nF capacitor tied to AVDD. 4 5,7,11,15,19,21, 26,31,33,37,39 6,10,12,16,18,20, 25,28,32,34,38 45, 55 44, 56 8 9 13 14 36 40, 41, 42, 43 _________ CH0_IOUT CH0_IOUT _________ CH1_IOUT CH1_IOUT PS0, PS1, PS2, PS3 46 47 48 I/O_UPDATE CS SCLK 49 50, 51 52, 53 54 DVDD_I/O SDIO_0, SDIO_1 SDIO_2, SDIO_3 SYNC_CLK 29 30 35 O Complementary DAC Output. Terminate into AVDD. O True DAC Output. Terminate into AVDD. O Complementary DAC Output. Terminate into AVDD. O I True DAC Output. Terminate into AVDD. These Pins are synchronous to the SYNC_CLK (pin 54). Any change in Profile inputs transfers the contents of the internal buffer memory to the I/O active registers (same as an external I/O _UPDATE). A rising edge detected on this pin transfers data from serial port buffer to active registers. Active low chip select allowing multiple devices to share a common I/O bus (SPI). Serial data clock for I/O operations. Data bits are written on rising edge of SCLK and read on the falling edge of SCLK. 3.3 V Digital Power Supply for SPI port and I/O (excluding CLK_MODE_SEL). These data pins have multiple functions. Data I/O pins for the serial I/O port operation. They are also used as data pins in modulation modes. I I I I I/O O I/O_UPDATE and Profile signals should meet the set-up and hold requirements with respect to this signal in order to guarantee a fixed pipeline delay of data to DAC outputs. Rev. PrB | Page 8 of 9 AD9959 PR05246-0-11/04(PrB) Preliminary Technical Data ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. PrB | Page 9 of 9