a MicroConverter ®, Small Package 12-Bit ADC with Embedded FLASH MCU ADuC814 FEATURES Analog I/O 6-Channel 247 kSPS ADC 12-Bit Resolution ADC High Speed Data Capture Mode Programmable Reference via On-Chip DAC for Low Level Inputs ADC Performance Down to VREF of 0.1 V Dual-Voltage Output DACs 12-Bit Resolution, 15 s Settling Time Memory 8 KBytes On-Chip Flash/EE Program Memory 640 Bytes On-Chip Flash/EE Data Memory Flash/EE, 100-Year Retention, 100 K Cycles Endurance Three Levels of Flash/EE Program Memory Security In-Circuit Serial Download (No External Hardware Required) 256 Bytes On-Chip Data RAM 8051 Based Core 8051 Compatible Instruction Set 32 kHz External Crystal On-Chip Programmable PLL (16.78 MHz Max) Three 16-Bit Timer/Counters 11 Programmable I/O Lines 11 Interrupt Sources, Two Priority Levels Power Specified for 3 V and 5 V Operation Normal: 3 mA @ 3 V (Core CLK = 2.1 MHz) Power-Down: 15 A at 3 V (32 kHz Running) On-Chip Peripherals Power-On Reset Circuit (No Need for External POR Device) Temperature Monitor (ⴞ1.5ⴗC) Precision Voltage Reference Time Interval Counter (Wake-Up/RTC Timer) UART Serial I/O SPI®/I2C ® Compatible Serial I/O Watchdog Timer (WDT) and Power Supply Monitor (PSM) Package and Temperature Range 28-Lead TSSOP 4.4 mm ⴛ 9.7 mm Body Package Fully Specified for –40ⴗC to +125ⴗC Operation APPLICATIONS Optical Networking—Laser Power Control Base Station Systems—Power Amplifier Bias Control Precision Instruments and Smart Sensors Battery-Powered Systems and General Precision System Monitors REV. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. FUNCTIONAL BLOCK DIAGRAM ADuC814 AIN0 AIN MUX T/H 12-BIT ADC ADC CONTROL LOGIC DAC CONTROL LOGIC AIN5 DAC0 BUF DAC0 DAC1 BUF DAC1 TEMP MONITOR INTERNAL BAND GAP VREF VREF CREF BUF POWERON RESET PROG. CLOCK DIVIDER OSC AND PLL 8051-BASED MCU WITH ADDITIONAL PERIPHERALS 8 KBYTES FLASH/EE PROGRAM MEMORY 640 BYTES FLASH/EE DATA MEMORY 256 BYTES USER RAM 3 ⴛ 16-BIT TIMER/COUNTERS 1 ⴛ WAKE-UP/RTC TIMER ON-CHIP MONITORS POWER SUPPLY MONITOR WATCHDOG TIMER 10 ⴛ DIGITAL I/O PINS UART AND SPI SERIAL I/O XTAL1 XTAL2 GENERAL DESCRIPTION The ADuC814 is a fully integrated 247 kSPS 12-bit data acquisition system incorporating a high performance multichannel ADC, an 8-bit MCU, and program/data Flash/EE memory on a single chip. This low power device operates from a 32 kHz crystal with an on-chip PLL generating a high frequency clock of 16.78 MHz. This clock is in turn routed through a programmable clock divider from which the MCU core clock operating frequency is generated. The microcontroller core is an 8052 and is therefore 8051instruction-set compatible. 8 Kbytes of nonvolatile Flash/EE program memory are provided on-chip. 640 bytes of nonvolatile Flash/EE data memory and 256 bytes of RAM are also integrated on-chip. The ADuC814 also incorporates additional analog functionality with dual 12-bit DACs, a power supply monitor, and a band gap reference. On-chip factory firmware supports in-circuit serial download and debug modes (via UART), as well as the single-pin emulation mode via the DLOAD pin. The ADuC814 is supported by a QuickStart™ development system. This is a full featured low cost system, consisting of PC-based (Windows® compatible) hardware and software development tools. The part operates from a single 3 V or 5 V supply over the extended temperature range –40⬚C to +125⬚C. When operating from 3 V supplies, the power dissipation for the part is below 10 mW. The ADuC814 is housed in a 28-lead TSSOP package. MicroConverter is a registered trademark of Analog Devices, Inc. SPI is a registered trademark of Motorola Inc. I2C is a registered trademark of Phillips Corporation. QuickStart is a trademark of Analog Devices, Inc. Windows is a registered trademark of Microsoft Corporation. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 2002 1 (AV = DV = 2.7 V to 3.3 V or 4.5 V to 5.5 V. V ADuC814–SPECIFICATIONS XTAL1/XTAL2 = 32.768 kHz Crystal. All specifications T to T , unless otherwise noted.) DD MIN Parameter DD REF = 2.5 V Internal Reference. MAX VDD = 5 V VDD = 3 V Unit 12 ±2 ±1 ±4 ±2 ± 2.5 ±5 12 ±2 ±1 ±4 ±2 ± 2.5 ±5 Bits LSB max LSB typ LSB max LSB typ LSB typ LSB typ ±5 ±1 ±5 ±1 ±5 ±1 ±5 ±1 LSB max LSB typ LSB max LSB typ Test Conditions ADC CHANNEL SPECIFICATIONS A GRADE DC ACCURACY2, 3 Resolution Integral Nonlinearity Differential Nonlinearity Integral Nonlinearity Differential Nonlinearity CALIBRATED ENDPOINT ERRORS4, 5 Offset Error Offset Error Match Gain Error Gain Error Match fSAMPLE = 147 kHz DYNAMIC PERFORMANCE Signal-to-Noise Ratio (SNR)6 Total Harmonic Distortion (THD) Peak Harmonic or Spurious Noise Channel-to-Channel Crosstalk7 2.5 V Internal Reference 2.5 V Internal Reference 1 V External Reference 1 V External Reference fIN = 10 kHz Sine Wave fSAMPLE = 147 kHz 62.5 –65 –65 –80 62.5 –65 –65 –80 dB typ dB typ dB typ dB typ 12 ±1 ± 0.3 ± 0.9 ± 0.25 ± 1.5 +1.5/–0.9 1 12 ±1 ± 0.3 ± 0.9 ± 0.25 ± 1.5 +1.5/–0.9 1 Bits LSB max LSB typ LSB max LSB typ LSB max LSB max LSB typ ±2 ±1 ±2 ±1 ±3 ±1 ±3 ±1 LSB max LSB typ LSB max LSB typ B GRADE DC ACCURACY2, 3 Resolution Integral Nonlinearity Differential Nonlinearity Integral Nonlinearity13 Differential Nonlinearity13 Code Distribution CALIBRATED ENDPOINT ERRORS4, 5 Offset Error Offset Error Match Gain Error Gain Error Match fSAMPLE = 147 kHz DYNAMIC PERFORMANCE Signal-to-Noise Ratio (SNR)6 Total Harmonic Distortion (THD) Peak Harmonic or Spurious Noise Channel-to-Channel Crosstalk7 2.5 V Internal Reference 2.5 V Internal Reference 1 V External Reference 1 V External Reference ADC Input Is a DC Voltage fIN = 10 kHz Sine Wave fSAMPLE = 147 kHz 71 –85 –85 –80 71 –85 –85 –80 dB typ dB typ dB typ dB typ ANALOG INPUT Input Voltage Ranges Leakage Current Input Capacitance 0 to VREF ±1 32 0 to VREF ±1 32 V µA max pF typ TEMPERATURE MONITOR8 Voltage Output at 25°C Voltage TC Accuracy Accuracy 650 –2 ±3 ± 1.5 650 –2 ±3 ± 1.5 mV typ mV/°C typ °C typ °C typ –2– Internal 2.5 V VREF External 2.5 V VREF REV. 0 ADuC814 Parameter VDD = 5 V VDD = 3 V Unit DAC CHANNEL SPECIFICATIONS DC ACCURACY9 Resolution Relative Accuracy Differential Nonlinearity10 Test Conditions DAC Load to AGND RL = 10 kΩ, CL = 100 pF 12 ±3 –1 ± 1/2 ± 50 ±1 ±1 0.5 12 ±3 –1 ± 1/2 ± 50 ±1 ±1 0.5 Bits LSB typ LSB max LSB typ mV max % max % typ % typ ANALOG OUTPUTS Voltage Range_0 Voltage Range_1 Output Impedance ISINK 0 to VREF 0 to VDD 0.5 50 0 to VREF 0 to VDD 0.5 50 V V Ω typ µA typ DAC VREF = 2.5 V DAC VREF = VDD DAC AC SPECIFICATIONS Voltage Output Settling Time 15 15 µs typ 10 10 nVs typ Full-Scale Settling Time to within 1/2 LSB of Final Value 1 LSB Change at Major Carry 2.5 ± 2.5 2.5 ± 2.5 V % max 47 ± 100 80 57 ± 100 80 dB typ ppm/ºC typ ms typ 0.1 VDD 20 10 0.1 VDD 20 10 V min V max kΩ typ µA max 2.63 2.93 3.08 4.63 2.63 2.93 3.08 4.63 V V V V ± 3.5 ± 3.5 % max 0 2000 0 2000 ms min ms max 0.8 2.0 0.4 2.0 V max V min Offset Error Gain Error Gain Error Mismatch Digital-to-Analog Glitch Energy REFERENCE INPUT/OUTPUT REFERENCE OUTPUT11 Output Voltage (VREF) Accuracy Power Supply Rejection Reference Temperature Coefficient Internal VREF Power-On Time EXTERNAL REFERENCE INPUT12 Voltage Range (VREF)13 Input Impedance Input Leakage POWER SUPPLY MONITOR (PSM) VDD Trip Point Selection Range VDD Power Supply Trip Point Accuracy WATCHDOG TIMER (WDT)13 Time-Out Period LOGIC INPUTS13 All Inputs Except SCLOCK, RESET, and XTAL1 VINL, Input Low Voltage VINH, Input High Voltage REV. 0 –3– Guaranteed Monotonic VREF Range VREF Range AVDD Range Of Full Scale on DAC1 Of VREF Measured at the CREF Pin Internal Band Gap Deselected via ADCCON2.6 Four Trip Points Selectable in this Range Programmed via TP1-0 in PSMCON Nine Time-Out Periods Selectable in this Range Programmed via PRE3-0 in WDCON ADuC814 SPECIFICATIONS (continued) Parameter VDD = 5 V VDD = 3 V Unit Test Conditions 1.3 3.0 0.8 1.4 0.3 0.85 0.95 2.5 0.4 1.1 0.3 0.85 V min V max V min V max V min V max ± 10 –10 –40 ± 10 ± 10 20 105 ± 10 ±1 –180 –660 –360 –20 –75 –38 ± 10 –3 –15 ± 10 ± 10 10 35 ± 10 ±1 –70 –200 –100 –5 –25 –12 µA max µA min µA max µA max µA max µA min µA max µA max µA typ µA min µA max µA typ µA min µA max µA typ VIN = 0 V or VDD VIN = 0 V, Internal Pull-Up VIN = 0 V, Internal Pull-Up VIN = VDD VIN = 0 V VIN = 5 V, 3 V Internal Pull-Down VIN = 5 V, 3 V Internal Pull-Down VIN = 5 V, 3 V INPUT CAPACITANCE 5 5 pF typ All Digital Inputs CRYSTAL OSCILLATOR (XTAL1 AND XTAL2) Logic Inputs, XTAL1 Only VINL, Input Low Voltage VINH, Input High Voltage XTAL1 Input Capacitance XTAL2 Output Capacitance 0.8 3.5 18 18 0.4 2.5 18 18 V typ V typ pF typ pF typ 2.4 2.4 V min ISOURCE = 1.6 mA 0.4 0.4 0.4 0.4 0.4 0.4 0.4 0.4 V max V max V max V max ISINK = 10 mA, TMAX = 85°C ISINK = 8 mA, TMAX = 125°C ISINK = 4 mA ISINK = 1.6 mA 131.1 16.78 131.1 16.78 kHz MHz Clock Rate Generated via On-Chip PLL, Programmable via CD2-0 in PLLCON 500 100 500 100 ms typ s typ 13 SCLOCK and RESET Only (Schmitt-Triggered Inputs) VT+ VT– VT+ – VT– INPUT CURRENTS P1.2–P1.7, DLOAD SCLOCK14 RESET P1.0, P1.1, Port 3 (includes MISO, MOSI/SDATA, and SS) DIGITAL OUTPUTS Output High Voltage (VOH) Output Low Voltage (VOL) P1.0 and P1.1 P1.0 and P1.1 SCLOCK, MISO, MOSI All Other Outputs MCU CORE CLOCK MCU Clock Rate START-UP TIME At Power-On From Idle Mode From Power-Down Mode Oscillator Running Wake-Up with INT0 Interrupt Wake-Up with SPI/I2C Interrupt Wake-Up with TIC Interrupt Wake-Up with External RESET VIN = 2 V, VDD = 5 V, 3 V VIN = 450 mV, VDD = 5 V, 3 V OSC_PD Bit = 0 in PLLCON SFR 100 100 100 3 100 100 100 3 –4– s typ s typ s typ ms typ REV. 0 ADuC814 Parameter VDD = 5 V VDD = 3 V Unit START-UP TIME (continued) Oscillator Powered Down15 Wake-Up with SPI/I2C Interrupt Wake-Up with TIC Interrupt Wake-Up with External RESET After External RESET in Normal Mode After WDT Reset in Normal Mode 150 150 150 3 3 400 400 400 3 3 ms typ ms typ ms typ ms typ ms typ FLASH/EE MEMORY RELIABILITY CHARACTERISTICS16 Endurance17 Data Retention18 100,000 100 100,000 100 cycles min years min 2.7 3.3 V min V max V min V max AVDD/DVDD = 3 V Nominal Core CLK = 2.097 MHz (CD Bits in PLLCON = 3) OSC_PD Bit = 1 in PLLCON POWER REQUIREMENTS19, 20 Power Supply Voltages AVDD/DVDD – AGND 4.5 5.5 Power Supply Currents – Normal Mode DVDD Current13 AVDD Current13 DVDD Current AVDD Current DVDD Current13 AVDD Current Power Supply Currents – Idle Mode DVDD Current13 AVDD Current13 DVDD Current13 AVDD Current13 DVDD Current13 AVDD Current13 Power Supply Currents – Power-Down Mode 5 2.5 mA max 4 1.7 20 16 1.7 3.5 2.8 1.7 2 1.7 10 8 1.7 1.5 1.2 1.7 mA typ mA max mA max mA typ mA max mA max mA typ mA max 1.7 1.2 mA max 1.5 0.15 6 4 0.15 1.25 1.1 0.15 1 0.15 3 2.5 0.15 1 0.7 0.15 mA typ mA max mA max mA typ mA max mA max mA typ mA max DVDD Current13 AVDD Current DVDD Current AVDD Current Typical Additional Power Supply Currents PSM Peripheral ADC DAC REV. 0 Test Conditions 20 14 1 15 10 1 40 1 20 1 µA max µA typ µA typ µA max µA typ µA typ µA typ mA typ µA typ 50 1.5 150 –5– Controlled via WDCON AVDD/DVDD = 5 V Nominal Core CLK = 16.78 MHz (max) (CD Bits in PLLCON = 0) Core CLK = 131.2 kHz (min) (CD Bits in PLLCON = 7) Core CLK = 2.097 MHz (CD Bits in PLLCON = 3) Core CLK = 16.78 MHz (max) (CD Bits in PLLCON = 0) Core CLK = 131 kHz (min) (CD Bits in PLLCON = 7) Core CLK = 2.097 MHz or 16.78 MHz (CD Bits in PLLCON = 3 or 0) Oscillator ON Oscillator OFF Core CLK = 2.097 MHz, (CD Bits in PLLCON = 3) AVDD = DVDD = 5 V ADuC814 SPECIFICATIONS (continued) NOTES 1 Temperature range –40ºC to +125ºC. 2 ADC linearity is guaranteed when operating in nonpipelined mode, i.e., ADC conversion followed sequentially by a read of the ADC result. ADC linearity is also guaranteed during normal MicroConverter core operation. 3 ADC LSB size = V REF/2^12, i.e., for 2.5 V, 1 LSB = 610 µV and for External V REF = 1 V, 1 LSB = 244 µV. 4 Offset and gain error and offset and gain error match are measured after factory calibration. 5 Based on external ADC system components, the user may need to execute a system calibration to remove additional external channel errors and achieve these specifications. 6 SNR calculation includes distortion and noise components. 7 Channel-to-channel crosstalk is measured on adjacent channels. 8 The temperature monitor will give a measure of the die temperature directly; air temperature can be inferred from this result. 9 DAC linearity is calculated using: Reduced Code Range of 48 to 4095, 0 to V REF Range. Reduced Code Range of 48 to 3950, 0 to V DD Range. DAC output load = 10 kΩ and 100 pF. 10 DAC differential nonlinearity specified on 0 to V REF and 0 to VDD ranges. 11 Power-up time for the internal reference will be determined by the value of the decoupling capacitor chosen for both the VREF and CREF pins. 12 When using an external reference device, the internal band gap reference input can be bypassed by setting the ADCCON1.6 bit. In this mode, the VREF and CREF pins need to be shorted together for correct operation. 13 These numbers are not production tested but are guaranteed by design and/or characterization data on production release. 14 Pins configured in I 2C compatible mode or SPI mode; pins configured as digital inputs during this test. 15 These typical specifications assume no loading on the XTAL2 pin. Any additional loading on the XTAL2 pin will increase the power-on times. 16 Flash/EE memory reliability characteristics apply to both the Flash/EE program memory and the Flash/EE data memory. 17 Endurance is qualified to 100 Kcycles as per JEDEC STD. 22 method A117 and measured at –40ºC, +25ºC, and +125ºC; typical endurance at +25ºC is 700 Kcycles. 18 Retention lifetime equivalent at junction temperature (Tj) = 55ºC as per JEDEC STD. 22 method A117. Retention lifetime based on an activation energy of 0.6e V will derate with junction temperature. 19 Power supply current consumption is measured in normal, idle, and power-down modes under the following conditions: Normal Mode: Reset and all digital I/O pins = open circuit, core clk changed via CD Bits in PLLCON, and core executing internal software loop. Idle Mode: Reset and all digital I/O pins = open circuit, core clk changed via CD Bits in PLLCON, PCON.0 = 1, and core execution suspended in idle mode. Power-Down Mode: Reset and all other digital I/O pins = open circuit, core clk changed via CD Bits in PLLCON, PCON.1 = 1, core execution suspended in Power-Down Mode, and OSC turned ON or OFF via OSC_PD Bit (PLLCON.7) in PLLCON SFR. 20 DVDD power supply current will increase typically by 3 mA (3 V operation) and 10 mA (5 V operation) during a Flash/EE memory program or erase cycle. Specifications subject to change without notice. Purchase of licensed I 2C components of Analog Devices or one of its sublicensed associated companies conveys a license for the purchaser under the Phillips I2C Patent Rights to use the ADuC814 in an I 2C system, provided that the system conforms to the I 2C standard specifications as defined by Phillips. –6– REV. 0 ADuC814 TIMING SPECIFICATIONS1, 2, 3 (AVDD = 2.7 V to 3.6 V or 4.75 V to 5.25 V, DVDD = 2.7 V to 3.6 V or 4.75 V to 5.25 V; all specifications TMIN to TMAX, unless otherwise noted.) 32.768 kHz External Crystal Min Typ Max Parameter CLOCK INPUT (External Clock Driven XTAL1) XTAL1 Period tCK XTAL1 Width Low tCKL XTAL1 Width High tCKH tCKR XTAL1 Rise Time XTAL1 Fall Time tCKF ADuC814 Core Clock Frequency4 1/tCORE tCORE ADuC814 Core Clock Period5 tCYC ADuC814 Machine Cycle Time6 30.52 15.16 15.16 20 20 0.131 16.78 0.476 5.7 0.72 91.55 Unit Figure µs µs µs ns ns MHz µs µs 1 1 1 1 1 NOTES 1 AC inputs during testing are driven at DV DD – 0.5 V for a Logic 1 and 0.45 V for a Logic 0. Timing measurements are made at V IH min for a Logic 1, and V IL max for a Logic 0, as shown in Figure 2. 2 For timing purposes, a port pin is no longer floating when a 100 mV change from the load voltage occurs. A port pin begins to float when a 100 mV change from the loaded VOH/VOL level occurs, as shown in Figure 2. 3 CLOAD for all outputs = 80 pF, unless otherwise noted. 4 ADuC814 internal PLL locks onto a multiple 512 times the external crystal frequency of 32.768 kHz to provide a stable 16.777216 MHz internal clock for the system. The core can operate at this frequency or at a binary submultiple called Core_CLK, selected via the PLLCON SFR. 5 This number is measured at the default Core_CLK operating frequency of 2.09 MHz. 6 ADuC814 machine cycle time is nominally defined as 12/Core_CLK. tCKR tCKH tCKL tCKF tCK Figure 1. XTAL1 Input DVDD – 0.5V 0.2DV DD + 0.9V TEST POINTS 0.2DV DD – 0.1V VLOAD – 0.1V VLOAD VLOAD + 0.1V 0.45V TIMING REFERENCE POINTS Figure 2. Timing Waveform Characteristics REV. 0 –7– VLOAD – 0.1V VLOAD VLOAD + 0.1V ADuC814 TIMING SPECIFICATIONS (continued) Parameter 16.78 MHz Core_CLK Min Typ Max UART TIMING (Shift Register Mode) Serial Port Clock Cycle Time tXLXL tQVXH Output Data Setup to Clock Input Data Setup to Clock tDVXH Input Data Hold after Clock tXHDX tXHQX Output Data Hold after Clock 463 252 0 22 Min Variable Core_CLK Typ Max 715 12tCORE 10tCORE – 133 2tCORE + 133 0 2tCORE – 117 Unit Figure µs ns ns ns ns 3 3 3 3 3 tXLXL TXD (OUTPUT CLOCK) 67 01 SET RI OR SET TI tQVXH tXHQX RXD (OUTPUT DATA) BIT 6 MSB BIT 1 tDVXH RXD (INPUT DATA) MSB tXHDX BIT 1 BIT 6 LSB Figure 3. UART Timing in Shift Register Mode –8– REV. 0 ADuC814 Parameter Min SPI MASTER MODE TIMING (CPHA = 1) SCLOCK Low Pulsewidth* tSL SCLOCK High Pulsewidth* tSH Data Output Valid after SCLOCK Edge tDAV tDSU Data Input Setup Time before SCLOCK Edge Data Input Hold Time after SCLOCK Edge tDHD Data Output Fall Time tDF tDR Data Output Rise Time SCLOCK Rise Time tSR tSF SCLOCK Fall Time Typ Max 630 630 50 100 100 10 10 10 10 25 25 25 25 *Characterized Unit Figure ns ns ns ns ns ns ns ns ns 4 4 4 4 4 4 4 4 4 under the following conditions: a. Core clock divider Bits CD2, CD1, and CD0 in PLLCON SFR set to 0, 1, and 1, respectively, i.e., core clock frequency = 2.09 MHz. b. SPI bit rate selection Bits SPR1 and SPR0 in SPICON SFR set to 0 and 0, respectively. SCLOCK (CPOL = 0) tSH tSL tSR SCLOCK (CPOL = 1) tDAV tDF tSF tDR MOSI BITS 6–1 MSB MISO BITS 6–1 MSB IN tDSU tDHD Figure 4. SPI Master Mode Timing (CPHA = 1) REV. 0 –9– LSB LSB IN ADuC814 TIMING SPECIFICATIONS (continued) Parameter Min SPI MASTER MODE TIMING (CPHA = 0) tSL SCLOCK Low Pulsewidth* SCLOCK High Pulsewidth* tSH tDAV Data Output Valid after SCLOCK Edge Data Output Setup before SCLOCK Edge tDOSU Data Input Setup Time before SCLOCK Edge tDSU tDHD Data Input Hold Time after SCLOCK Edge Data Output Fall Time tDF Data Output Rise Time tDR tSR SCLOCK Rise Time tSF SCLOCK Fall Time Typ Max 630 630 50 150 100 100 10 10 10 10 25 25 25 25 Unit Figure ns ns ns ns ns ns ns ns ns ns 5 5 5 5 5 5 5 5 5 5 *Characterized under the following conditions: a. Core clock divider Bits CD2, CD1, and CD0 in PLLCON SFR set to 0, 1, and 1, respectively, i.e., core clock frequency = 2.09 MHz. b. SPI bit rate selection Bits SPR1 and SPR0 in SPICON SFR set to 0 and 0, respectively. SCLOCK (CPOL = 0) tSH tSL tSR SCLOCK (CPOL = 1) tSF tDAV tDF tDOSU MOSI MISO MSB MSB IN tDSU tDR BITS 6–1 BITS 6–1 LSB LSB IN tDHD Figure 5. SPI Master Mode Timing (CPHA = 0) –10– REV. 0 ADuC814 Parameter Min SPI SLAVE MODE TIMING (CPHA = 1) SS to SCLOCK Edge tSS SCLOCK Low Pulsewidth tSL tSH SCLOCK High Pulsewidth Data Output Valid after SCLOCK Edge tDAV Data Input Setup Time before SCLOCK Edge tDSU tDHD Data Input Hold Time after SCLOCK Edge Data Output Fall Time tDF Data Output Rise Time tDR tSR SCLOCK Rise Time SCLOCK Fall Time tSF tSFS SS High after SCLOCK Edge Typ Max 0 330 330 50 100 100 10 10 10 10 25 25 25 25 0 SS tSFS tSS SCLOCK (CPOL = 0) tDF tSL tSH tSR tSF SCLOCK (CPOL = 1) tDAV tDF MISO MOSI BITS 6–1 MSB BITS 6–1 MSB IN tDSU tDR tDHD Figure 6. SPI Slave Mode Timing (CPHA = 1) REV. 0 –11– LSB LSB IN Unit Figure ns ns ns ns ns ns ns ns ns ns ns 6 6 6 6 6 6 6 6 6 6 6 ADuC814 Parameter Min SPI SLAVE MODE TIMING (CPHA = 0) SS to SCLOCK Edge tSS SCLOCK Low Pulsewidth tSL SCLOCK High Pulsewidth tSH tDAV Data Output Valid after SCLOCK Edge Data Input Setup Time before SCLOCK Edge tDSU Data Input Hold Time after SCLOCK Edge tDHD tDF Data Output Fall Time Data Output Rise Time tDR SCLOCK Rise Time tSR tSF SCLOCK Fall Time SS to SCLOCK Edge tSSR Data Output Valid after SS Edge tDOSS tSFS SS High after SCLOCK Edge Typ Max 0 330 330 50 100 100 10 10 10 10 25 25 25 25 50 20 0 Unit Figure ns ns ns ns ns ns ns ns ns ns ns ns ns 7 7 7 7 7 7 7 7 7 7 7 7 7 SS tSFS tSS SCLOCK (CPOL = 0) tSH tSL tSF tSR SCLOCK (CPOL = 1) tDAV tDOSS tDF MSB MISO MOSI MSB IN tDSU tDR BITS 6–1 BITS 6–1 LSB LSB IN tDHD Figure 7. SPI Slave Mode Timing (CPHA = 0) –12– REV. 0 ADuC814 ABSOLUTE MAXIMUM RATINGS 1 PIN CONFIGURATION 28-Lead TSSOP (TA = 25°C, unless otherwise noted.) AVDD to AGND . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V DVDD to AGND . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V AVDD to DVDD . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V AGND to DGND2 . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V Analog Input Voltage to AGND3 . . . . –0.3 V to AVDD + 0.3 V Reference Input Voltage to AGND . . –0.3 V to AVDD + 0.3 V Analog Input Current (Indefinite) . . . . . . . . . . . . . . . . . 30 mA Reference Input Current (Indefinite) . . . . . . . . . . . . . . . 30 mA Digital Input Voltage to DGND . . . . –0.3 V to DVDD + 0.3 V Digital Output Voltage to DGND . . . –0.3 V to DVDD + 0.3 V Operating Temperature Range . . . . . . . . . . . –40°C to +85°C Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . 97.9°C/W Lead Temperature, Soldering Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . . 215°C Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C DGND 1 28 DVDD DLOAD 2 27 XTAL2 P3.0/RXD 3 26 XTAL1 P3.1/TXD 4 25 SCLOCK P3.2/INT0 5 24 P3.7/MOSI P3.3/INT1 6 P3.4/T0/CONVST 7 P1.0/T2 8 ADuC814 TOP VIEW (Not to Scale) P1.1/T2EX 9 23 P3.6/MISO 22 P3.5/T1/SS/EXTCLK 21 P1.7/ADC5/DAC1 20 P1.6/ADC4/DAC0 RESET 10 19 P1.5/ADC3 P1.2/ADC0 11 18 P1.4/ADC2 P1.3/ADC1 12 17 CREF AVDD 13 16 VREF AGND 14 15 AGND NOTES 1 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 AGND and DGND are shorted internally on the ADuC814. 3 Applies to P1.2 to P1.7 pins operating in analog or digital input modes. ORDERING GUIDE Model Temperature Range Package Description Package Option ADuC814ARU ADuC814BRU –40°C to +125°C –40°C to +125°C Thin Shrink Small Outline Package Thin Shrink Small Outline Package RU-28 RU-28 QuickStart Development System Model Description EVAL-ADuC814QS Development System for the ADuC814 MicroConverter Contains: • Evaluation Board • Serial Port Cable • Windows Serial Downloader (WSD) • Windows Debugger (DeBug) • Windows ADuC814 Simulator (ADSIM) • Windows ADC Analysis Software Program (WASP) • 8051 Assembler (Metalink) • Example Code • Documentation CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADuC814 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. REV. 0 –13– WARNING! ESD SENSITIVE DEVICE ADuC814 PIN FUNCTION DESCRIPTIONS Pin No. Mnemonic Type* Function 1 2 DGND DLOAD S I 3-7 P3.0–P3.4 I/O 3 P3.0/RXD I/O 4 P3.1/TXD I/O 5 P3.2/INT0 I/O 6 P3.3/INT1 I/O 7 8-9 P3.4/T0/CONVST I/O P1.0–P1.1 I/O 8 P1.0/T2 I/O 9 10 P1.1/T2EX RESET I/O I 11-12 P1.2–P1.3 I 11 12 13 14, 15 P1.2/ADC0 P1.3/ADC1 AVDD AGND I I S G Digital Ground. Ground reference point for the digital circuitry. Enables Debug/Serial Download Mode when pulled high through a resistor on power-on or RESET. In this mode, DLOAD may also be used as an external emulation I/O pin, and therefore, the voltage level at this pin must not be changed during this mode of operation since it may cause an emulation interrupt that will halt code execution. User code is executed when this pin is pulled low on power-on or RESET. P3.0–P3.4 are bidirectional port pins with internal pull-up resistors. Port 3 pins that have 1s written to them are pulled high by the internal pull-up resistors, and in that state, can be used as inputs. As inputs, Port 3 pins being pulled externally low will source current because of the internal pull-up resistors. When driving a 0-to-1 output transition, a strong pull-up is active during S1 of the instruction cycle. Port 3 pins also have various secondary functions that are described below. Receiver Data Input (Asynchronous) or Data Input/Output (Synchronous) in Serial (UART) Mode Transmitter Data Output (Asynchronous) or Clock Output (Synchronous) in Serial (UART) Mode Interrupt 0 programmable edge or level triggered interrupt input, that can be programmed to one of two priority levels. This pin can also be used as a gate control input to Timer 0. Interrupt 1 programmable edge or level triggered interrupt input, that can be programmed to one of two priority levels. This pin can also be used as a gate control input to Timer 1. Timer/Counter 0 Input and External Trigger Input for ADC Conversion Start P1.0–P1.1 are bidirectional port pins with internal pull-up resistors. Port 1 pins that have 1s written to them are pulled high by the internal pull-up resistors, and in that state, can be used as inputs. As inputs, Port 1 pins being pulled externally low will source current because of the internal pull-up resistors. When driving a 0-to-1 output transition, a strong pull-up is active during S1 of the instruction cycle. Port 1 pins also have various secondary functions that are described below. Timer 2 Digital Input. Input to Timer/Counter 2. When enabled, Counter 2 is incremented in response to a 1 to 0 transition of the T2 input. Digital Input. Capture/reload trigger for Counter 2. Reset Input. A high level on this pin while the oscillator is running resets the device. There is an internal weak pull-down and a Schmitt trigger input stage on this pin. These pins have no digital output drivers, i.e., they can only function as digital inputs, for which 0 must be written to the Port Bit. These port pins also have the following analog functionality. ADC Input Channel 0, Selected via ADCCON2 SFR ADC Input Channel 1, Selected via ADCCON2 SFR Analog Positive Supply Voltage, 3 V or 5 V Analog Ground. Ground reference point for the analog circuitry. –14– REV. 0 ADuC814 Pin No. Mnemonic Type* Function 16 VREF I/O 17 18-21 CREF P1.4–P1.7 I I 18 19 20 P1.4/ADC2 I P1.5/ADC3 I P1.6/ADC4/DAC0 I/O 21 P1.7/ADC5/DAC1 I/O 22-24 P3.5–P3.7 I/O 22 P3.5/T1 I/O 22 P3.5/SS/EXTCLK I/O 23 24 25 26 27 28 P3.6/MISO P3.7/MOSI SCLOCK XTAL1 XTAL2 DVDD I/O I/O I/O I O S Reference Input/Output. This pin is connected to the internal reference through a switch and is the reference source for the analog-to-digital converter. The nominal internal reference voltage is 2.5 V, which appears at the pin. This pin can be used to connect an external reference to the analog-to-digital converter by setting ADCCON1.6 to 1.0. Connect 0.1 µF between this pin and AGND. Decoupling input for on-chip reference. Connect 0.1 µF between this pin and AGND. These pins have no digital output drivers, i.e., they can only function as digital inputs, for which 0 must be written to the Port Bit. These port pins also have the following analog functionality. ADC Input Channel 2, Selected via ADCCON2 SFR ADC Input Channel 2, Selected via ADCCON2 SFR ADC Input Channel 4, Selected via ADCCON2 SFR. The voltage DAC Channel 0 can also be configured to appear on P1.6 ADC Input Channel 5, Selected via ADCCON2 SFR. The voltage DAC Channel 1 can also be configured to appear on P1.7 P3.5–P3.7 are bidirectional port pins with internal pull-up resistors. Port 3 pins that have 1s written to them are pulled high by the internal pull-up resistors, and in that state, can be used as inputs. As inputs, Port 3 pins being pulled externally low will source current because of the internal pull-up resistors. When driving a 0-to-1 output transition, a strong pull-up is active during S1 of the instruction cycle. Port 3 pins also have various secondary functions that are described below. Timer/Counter 1 Input. P3.5–P3.7 pins also have SPI interface functions. To enable these functions, Bit 0 of the CFG814 SFR must be set to 1. This pin also functions as the slave select input for the SPI interface when the device is operated in Slave Mode. P3.5 can also function as an input for an external clock. This clock effectively bypasses the PLL. This function is enabled by setting Bit 1 of the CFG814 SFR. SPI Master Input/Slave Output Data Input/Output Pin SPI Master Output/Slave Input Data Input/Output Pin Serial Clock Pin for SPI Serial Interface Clock Input to the Crystal Oscillator Inverter Output from the Crystal Oscillator Inverter Analog Positive Supply Voltage, 3 V or 5 V *I = Input, O = Output, I/O = Input and Output, and S = Supply. NOTES 1. SET implies a Logic 1 state and CLEARED implies a Logic 0 state, unless otherwise stated. 2. SET and CLEARED also imply that the bit is set or automatically cleared by the ADuC814 hardware, unless otherwise stated. 3. User software should not write 1s to Reserved or Unimplemented Bits as they may be used in future products. REV. 0 –15– ADuC814 OUTLINE DIMENSIONS 28-Lead TSSOP Package (RU-28) Dimensions shown in millimeters and (inches) 28 C02748–0–5/02(0) 9.80 (0.386) 9.60 (0.378) 15 4.50 (0.177) 4.30 (0.169) 6.50 (0.256) 6.25 (0.246) 1 14 PIN 1 0.15 (0.006) 0.05 (0.002) SEATING PLANE 1.10 (0.0433) MAX 0.65 (0.0256) BSC 0.30 (0.0118) 0.19 (0.0075) 0.20 (0.0079) 0.090 (0.0035) 8ⴗ 0ⴗ 0.70 (0.028) 0.50 (0.020) PRINTED IN U.S.A. CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN –16– REV. 0