19-4822; Rev 0; 7/09 TION KIT EVALUA BLE IL AVA A TMDS Digital Video Equalizer for HDMI/DVI Cables Features The MAX3815A cable equalizer automatically provides compensation for DVI™ and HDMI™ v1.3 cables. It extends the usable cable distance up to 40 meters (1.65Gbps) and 35 meters (2.25Gbps). The MAX3815A is designed to equalize signals encoded in the transitionminimized differential signaling (TMDS®) format. S Guaranteed Performance to 2.25Gbps (HDMI 1.3), The MAX3815A features four CML-differential inputs and outputs (three data and one clock). It provides a loss-ofsignal (LOS) output that indicates loss-of-clock signal. The outputs include a disable function. Upon LOS, the chip is powered down. For direct chip-to-chip communication, the output drivers can be switched to one-half the DVI output specification to conserve power and reduce EMI. The output drive current can also be increased to allow the use of back termination resistors for improved signal integrity. Equalization can be automatic or set to manual control for specific in-cable applications. S Extends 1.65Gbps TMDS Interface Length The MAX3815A is available in a 7mm x 7mm, 48-pin TQFP-EP package and operates over a 0°C to +70°C temperature range. Improved Jitter Performance at Low Source Amplitude, and Enhanced Output Driver S Extends 2.25Gbps TMDS Interface Length 0 to 35 Meters Over HDMI Cable, 24 AWG 0 to 22 Meters Over HDMI Cable, 28 AWG 0 to 40 Meters Over HDMI Cable, 24 AWG 0 to 28 Meters Over HDMI Cable, 28 AWG S Compatible with HDTV Resolutions 720p, 1080i, 1080p, and 1080p with 36-Bit Color S Compatible with Computer Resolutions VGA, SVGA, XGA, SXGA, UXGA, and WUXGA S Fully Automatic Equalization, No System Control Required S 3.3V Power Supply S Power Dissipation of 0.6W (typ) S 7mm x 7mm, 48-Pin TQFP Lead-Free Package Applications Front-Projector HDMI/DVI Inputs Ordering Information PART High-Definition Televisions and Displays MAX3815ACCM+ HDMI/DVI-D Cable-Extender Modules and Active Cable Assemblies TEMP RANGE PIN-PACKAGE 0NC to +70NC 48 TQFP-EP* +Denotes a lead(Pb)-free/RoHS compliant package. *EP = Exposed pad. LCD Computer Monitors Pin Configuration appears at end of data sheet. HDMI 1.3 Deep Color Systems Typical Operating Circuits HDMI OR DVI EXTENDER BOX VIDEO SOURCE UP TO 35m OF HDMI OR DVI CABLE MAX3815A EQUALIZER STANDARD LENGTH DVI-D OR HDMI CABLE HDTV MAX3816A DDC EXTENDER Typical Operating Circuits continued at end of data sheet. DVI is a trademark of Digital Display Working Group. HDMI is a trademark of HDMI Licensing, LLC. TMDS is a registered trademark of Silicon Image Inc. ________________________________________________________________ Maxim Integrated Products 1 For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. MAX3815A General Description MAX3815A TMDS Digital Video Equalizer for HDMI/DVI Cables ABSOLUTE MAXIMUM RATINGS Supply Voltage Range, VCC.................................-0.5V to +4.0V Voltage Range at Output CML Pins......................-0.5V to +4.0V Voltage Range at Input CML Pins, RES, VCC_T, and GND_T............................................. -0.5V to (VCC + 0.7V) Voltage Between Input CML Complementary Pair............ ±3.3V Voltage Between Output CML Complementary Pair......... ±1.4V Continuous Power Dissipation (TA = +70°C) 48-Pin TQFP (derate 36.2mW/°C above +70°C).........2896mW Operating Junction Temperature Range.......... -55°C to +150°C Storage Temperature Range............................. -55°C to +150°C Die Attach Temperature...................................................+400°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (VCC = +3.0V to +3.5V, TA = 0°C to +70°C. Typical Values are at VCC = +3.3V, external terminations = 50Ω ±1%, MAX3815A in automatic equalization mode (EQCONTROL = GND), TMDS rate = 250Mbps to 2.25Gbps, TA = +25°C, unless otherwise noted.) PARAMETER TYP MAX Clock present (CLKLOS = HIGH) 210 270 Clock and data absent (CLKLOS = LOW) DC to 500kHz 12 200 Residual Output Jitter (Cables Only) 0.25Gbps to 1.65Gbps (Notes 1, 2, and 3) 1dB skin-effect loss at 825MHz 0.05 24dB skin-effect loss at 825MHz 0.13 Residual Output Jitter (Cables Only) 1.65Gbps to 2.25Gbps (Notes 1, 2, and 3) 1dB skin-effect loss at 825MHz 0.1 24dB skin-effect loss at 825MHz 0.14 Power-Supply Current SYMBOL ICC Supply-Noise Tolerance CONDITIONS MIN UNITS mA mVP-P EQUALIZER PERFORMANCE UI CID Tolerance 0.21 0.28 20 UI Bits CONTROL AND STATUS Differential peak-to-peak at EQ input with max 225MHz clock (see the Typical Operating Characteristics for more information) CLKLOS Assert Level 50 mVP-P CML INPUTS (CABLE SIDE) Differential Input-Voltage Swing VID Common-Mode Input Voltage VCM Input Resistance RIN At cable input 800 1000 VCC 0.4 Single-ended 1200 mVP-P VCC + 0.1 V W 45 50 55 800 1000 1200 CML OUTPUTS (ASIC SIDE) Differential Output-Voltage Swing VOD 50W load, each side to VCC OUTLEVEL = HIGH OUTLEVEL = LOW 500 mVP-P With back termination as shown in Figure 4, OUTLEVEL = OPEN 910 Output-Voltage High Single-ended, OUTLEVEL = HIGH VCC Output-Voltage Low Single-ended, OUTLEVEL = HIGH VCC 600 VCC 400 mV Output Voltage During Clock Absence (CLKLOS = LOW) Single-ended VCC 10 VCC + 10 mV 2 _______________________________________________________________________________________ mV TMDS Digital Video Equalizer for HDMI/DVI Cables (VCC = +3.5V to +3.5V, TA = 0°C to +70°C. Typical Values are at VCC = +3.3V, external terminations = 50Ω ±1%, MAX3815A in automatic equalization mode (EQCONTROL = GND), TMDS rate = 250Mbps to 2.25Gbps, TA = +25°C, unless otherwise noted.) PARAMETER SYMBOL CONDITIONS Common-Mode Output Voltage 50W load, each side to VCC, OUTLEVEL = HIGH Rise/Fall Time (Note 1) 20% to 80% MIN 80 TYP MAX UNITS VCC 0.25 V 160 ps LVTTL CONTROL AND STATUS INTERFACE LVTTL Input High Voltage VIH LVTTL Input Low Voltage VIL 2.0 V 0.8 V LVTTL Input High Current VIH(MIN) < VIN < VCC ±50 µA LVTTL Input Low Current GND < VIN < VIL(MAX) -100 µA Open-Collector Output High Voltage RLOAD ≥ 10kW to VCC Open-Collector Output Low Voltage RLOAD ≥ 2kW to VCC 2.4 V Open-Collector Output Sink Current OUTLEVEL Input Open-State Current Tolerance ±5 0.4 V 5 mA µA Note 1: AC specifications are guaranteed by design and characterization. Note 2: Cable input swing is 800mV to 1200mV differential peak-to-peak. Residual output jitter is defined as peak-to-peak jitter, both deterministic plus random, as measured using an oscilloscope histogram with 5000 hits. Source jitter subtracted. Note 3: Test pattern is a 27 - 1 PRBS + 20 ones + 27 - 1 PRBS (inverted) + 20 zeros. Typical Operating Characteristics (Typical values are at VCC = +3.3V, TA = +25°C, data pattern = 27 - 1 PRBS + 20 ones + 27 - 1 PRBS (inverted) + 20 zeros, equalizer in automatic mode, cable launch amplitude 1VP-P differential, unless otherwise noted.) SUPPLY CURRENT vs. AMBIENT TEMPERATURE -5 -10 220 210 200 GAIN (dB) SUPPLY CURRENT (mA) 230 TMDS SOURCE DC-COUPLED TO MAX3815A INPUT (NOMINAL AMPLITUDE) 190 MAX3815A toc02 OUTLEVEL = OPEN, EQCONTROL = VCC, CLOCK SIGNAL ACTIVE 240 INPUT RETURN LOSS vs. FREQUENCY 0 MAX3815A toc02 250 -15 -20 -25 180 -30 170 -35 TMDS SOURCE AC-COUPLED TO MAX3815A 160 -40 150 0 10 20 30 40 50 AMBIENT TEMPERATURE (°C) 60 70 0 500 1000 1500 2000 2500 3000 FREQUENCY (MHz) _______________________________________________________________________________________ 3 MAX3815A ELECTRICAL CHARACTERISTICS Typical Operating Characteristics (continued) (Typical values are at VCC = +3.3V, TA = +25°C, data pattern = 27 - 1 PRBS + 20 ones + 27 - 1 PRBS (inverted) + 20 zeros, equalizer in automatic mode, cable launch amplitude 1VP-P differential, unless otherwise noted.) EQUALIZER INPUT AFTER 100ft OF 26 AWG CABLE (TOP) EQUALIZER OUTPUT (BOTTOM) EQUALIZER INPUT EYE AFTER 100ft OF 26 AWG CABLE (TOP) EQUALIZER OUTPUT (BOTTOM) MAX3815A toc03 MAX3815A toc04 DATA RATE = 2.25Gbps 30dB CABLE SKIN-EFFECT LOSS AT 1.11GHz DATA RATE = 2.25Gbps 30dB CABLE SKIN-EFFECT LOSS AT 1.11GHz 20mV/div 350mV/div 500mV/div 100ps/div EQUALIZER INPUT EYE AFTER 150ft OF 26 AWG CABLE (TOP) EQUALIZER OUTPUT (BOTTOM) TOTAL JITTER vs. DATA RATE (50m HDMI CABLE) MAX3815A toc05 MAX3815A toc06 200 DATA RATE = 742.5Mbps 24dB CABLE SKIN-EFFECT LOSS AT 370MHz DVIGear SHR™ HDMI CABLE (22 AWG) 180 TOTAL JITTER (psP-P) 160 350mV/div 0.4 PEAK-TO-PEAK JITTER IN PICOSECONDS 140 120 0.3 100 80 0.2 60 40 0.1 PEAK-TO-PEAK JITTER IN UNIT INTERVALS 20 0 250 300ps/div 750 1250 1750 DATA RATE (Mbps) NOISE AMPLITUDE: 200mVP-P DATA THROUGH 50m DVIGear SHR HDMI CABLE, 22 AWG 170 160 MAX3815A toc07 TOTAL JITTER vs. POWER-SUPPLY NOISE FREQUENCY (DATA RATE = 2.25Gbps) 180 150 140 130 120 110 100 1 10 100 1000 0.5 10,000 FREQUENCY (kHz) SHR is a trademark of DVIGear, Inc. 4 _______________________________________________________________________________________ 0 2250 TOTAL JITTER (UIP-P) 5ns/div TOTAL JITTER (psP-P) MAX3815A TMDS Digital Video Equalizer for HDMI/DVI Cables TMDS Digital Video Equalizer for HDMI/DVI Cables 2.25Gbps 0.5 130 MAX3815A toc08 1.485Mbps 0.4 0.3 742.5Mbps 0.2 50m OF DVIGear SHR HDMI CABLE WITH 35dB LOSS AT 1.11GHz 120 TOTAL JITTER (psP-P) DETERMINISTIC JITTER (UIP-P) 0.6 NO EQ WITH MAX3815A EQ 0.1 MAX3815A toc09 TOTAL JITTER vs. SIGNAL AMPLITUDE INPUT TO CABLE (DATA RATE 2.25Gbps) TOTAL JITTER vs. CABLE LENGTH (CARLISLE INTERCONNECT TECHNOLOGIES TWIN-AX 28 AWG) 110 100 90 80 70 60 0 0 10 20 30 40 50 CABLE LENGTH (m) 0.4 0.6 0.8 1.0 1.2 1.4 1.6 DIFFERENTIAL AMPLITUDE (VP-P) MAX3815A toc10 -0.3 180 160 140 120 EQCONTROL VOLTAGE -0.4 100 80 -0.5 60 -0.6 40 RESIDUAL JITTER AT 2.25Gbps -0.7 DIFFERENTIAL CLOCK AMPLITUDE (mVP-P) EQCONTROL VOLTAGE (V) -0.2 350 200 CABLE IS CARLISLE INTERCONNECT TECHNOLOGIES TWIN-AX 28 AWG WITH APPROXIMATELY 1.35dB OF LOSS PER METER AT 1.11GHz RESIDUAL JITTER (psP-P) 0 -0.1 LOSS-OF-CLOCK ASSERT THRESHOLD vs. CABLE LENGTH 20 -0.8 10 20 250 225MHz CLOCK FREQUENCY 200 150 25MHz CLOCK FREQUENCY 100 50 0 0 0 CLOCK AMPLITUDE IS AT INPUT OF CABLE CABLE IS CARLISLE INTERCONNECT TECHNOLOGIES TWIN-AX, 28 AWG 300 MAX3815A toc11 EQCONTROL VOLTAGE (RELATIVE TO VCC) vs. CABLE LENGTH (MANUAL EQ CONTROL) 0 30 6 CABLE LENGTH (m) 12 18 24 30 36 CABLE LENGTH (m) EQUALIZER OUTPUT EYE AFTER 50m OF 22 AWG HDMI CABLE (DATA RATE = 2.25Gbps) MAX3815A toc12 DVIGear SHR HDMI CABLE 200mV/div 100ps/div _______________________________________________________________________________________ 5 MAX3815A Typical Operating Characteristics (continued) (Typical values are at VCC = +3.3V, TA = +25°C, data pattern = 27 - 1 PRBS + 20 ones + 27 - 1 PRBS (inverted) + 20 zeros, equalizer in automatic mode, cable launch amplitude 1VP-P differential, unless otherwise noted.) MAX3815A TMDS Digital Video Equalizer for HDMI/DVI Cables Pin Description PIN NAME 1, 4, 5, 8, 9, 12, 13, 16, 38 FUNCTION VCC 2 RX0_IN- Negative Data Input, CML 3 RX0_IN+ Positive Data Input, CML 6 RX1_IN- Negative Data Input, CML 7 RX1_IN+ Positive Data Input, CML 10 RX2_IN- Negative Data Input, CML 11 RX2_IN+ Positive Data Input, CML 14 RXC_IN+ Positive Clock Input, CML 15 RXC_IN- Negative Clock Input, CML 17 EQCONTROL 18 CLKLOS 19 N.C. Not Connected. This pin is not internally connected. 20, 23, 24, 25, 28, 29, 32, 33, 36, 37 GND Ground Supply Voltage. All pins must be connected to VCC. Equalizer Control. This pin allows the user to control the equalization level of the MAX3815A. Connect the pin to GND for automatic operation. Set the voltage to VCC/2 for minimum equalization, or set the voltage between VCC - 1V to VCC for manual equalization. See the Applications Information section for more information. Loss-of-Clock Signal Output, LVTTL Open Collector. This pin asserts low upon loss of the input TMDS clock from the cable. Connect pin to VCC through a 4.7kω resistor. 21 RXC_OUT- Negative Clock Output, CML 22 RXC_OUT+ Positive Clock Output, CML 26 RX2_OUT+ Positive Data Output, CML 27 RX2_OUT- Negative Data Output, CML 30 RX1_OUT+ Positive Data Output, CML 31 RX1_OUT- Negative Data Output, CML 34 RX0_OUT+ Positive Data Output, CML 35 RX0_OUT- Negative Data Output, CML 39 OUTLEVEL Output-Level Control Input • HIGH: Standard swing (1000mVP-P) differential • OPEN: Standard swing (900mVP-P differential) with external 267ω back termination resistor (see Figure 4) • LOW: One-half standard swing (500mVP-P differential) 40 OUTON Output-Enable Control Input, LVTTL. This input enables the CML outputs when forced low and sets a differential logic zero when forced high. 41, 43, 44 VCC_T Reserved. Must be connected to VCC for normal operation. 42 GND_T Reserved. Must be connected to GND for normal operation. 45–48 RES — EP Reserved. Must be left open for normal operation. Exposed Pad. The exposed pad must be soldered to the circuit-board ground for proper thermal and electrical operation. 6 _______________________________________________________________________________________ TMDS Digital Video Equalizer for HDMI/DVI Cables RX1_IN+/- RX2_IN+/- TERMINATED 3.3V CML TERMINATED 3.3V CML TERMINATED 3.3V CML INPUT BUFFER ADAPTIVE EQ LIMITING AMPLIFIER DRIVER RX0_OUT+/- INPUT BUFFER ADAPTIVE EQ LIMITING AMPLIFIER DRIVER RX1_OUT+/- INPUT BUFFER ADAPTIVE EQ LIMITING AMPLIFIER DRIVER RX2_OUT+/- EQCONTROL RXC_IN+/- TERMINATED 3.3V CML CLOCK LOS DETECTOR CLKLOS LIMITING AMPLIFIER INPUT BUFFER DRIVER RXC_OUT+/- OUTON MAX3815A OUTLEVEL Figure 1. Functional Diagram Detailed Description The MAX3815A TMDS equalizer accepts differential CML input data at rates of 250Mbps up to 2.25Gbps (individual channel data rate). It automatically adjusts to skin-effect losses in copper cable. It consists of four CML input buffers, a loss-of-clock signal detector, three independent adaptive equalizers, four limiting amplifiers, and four output buffers (Figure 1). CML Input Buffers and Output Drivers The input buffers and the output drivers are implemented using current-mode logic (CML) (see Figures 4 and 5). The output drivers are open-collector and can be turned off with the OUTON pin. The OUTLEVEL pin sets the output drive current to one of three levels; see the Applications Information and Pin Description sections for more information. For details on interfacing with CML, refer to Application Note 291: HFAN-01.0: Introduction to LVDS, PECL, and CML. Loss-of-Clock Signal Detector The loss-of-clock signal detector indicates a loss-ofclock signal at the CLKLOS pin. This is an open-collector output that must be connected to VCC through a 4.7kω external pullup. This resistor is required whether or not the LOS output is used. Adaptive Equalizer The three data channels each contain an independent adaptive equalizer. Each channel analyzes the incoming signal and determines the amount of equalization to apply. Limiting Amplifier The limiting amplifier amplifies the signal from the adaptive equalizer and truncates the top and bottom of the waveform to provide a clean high- and low-level signal to the output drivers. _______________________________________________________________________________________ 7 MAX3815A RX0_IN+/- MAX3815A TMDS Digital Video Equalizer for HDMI/DVI Cables D0 D0 D1 D1 D2 D2 MAX3815A CLK CLK MAX3815A D3 D3 D4 D4 D5 D5 Figure 2. Connection Scheme for MAX3815A in Dual Link Application VCC MAX3815A VCC 4.7kΩ Typical shielded twisted pair (STP), unshielded twisted pair (UTP), and twin-ax cables exhibit skin-effect losses, which attenuate the high-frequency spectrum of a TMDS signal, eventually causing data errors or even closing the signal eye altogether given a long enough cable. The MAX3815A recovers the data and opens the signal eye through compensating equalization. The basic TMDS interface is composed of four differential serial links: three links carry serial data up to 2.25Gbps each, and the fourth is a one-tenth-rate (0.1x) clock that operates up to 225MHz. TMDS, as with analog nVGA links, must handle a variety of resolutions and screen update rates. The actual range of digital serial rates is roughly 250Mbps to 2.25Gbps. For applications requiring ultra-high resolutions (e.g., QXGA), a “dual-link” DVI interface is used and is composed of six data links plus the clock, requiring two MAX3815A ICs with the clock going to both ICs. See Figure 2. The MAX3815A can be used to extend any TMDS interface as used under the following trademarked names: DVI (digital visual interface), DFP™ (digital flat-panel), PanelLink, ADC™ (Apple display connector), and HDMI (high-definition multimedia interface). CLKLOS TO CHIP POWERCONTROL CIRCUITRY Applications Information Loss-of-Clock Signal (CLKLOS) Output Figure 3. Simplified CLKLOS Output Circuit Schematic +3.3V MAX3815A RX_OUT+ 50Ω 267Ω RX_OUT- HDM/DVI RECEIVER 50Ω A loss-of-clock signal is indicated by the CLKLOS output. A low level on CLKLOS indicates that the signal power on the RXC_IN pins has dropped below a threshold. When there is sufficient input voltage to the channel (typically greater than 100mVP-P differential), CLKLOS is high. The CLKLOS output is suitable for indicating problems with the transmission link caused by, for example, a broken cable, a defective driver, or a lost connection to the equalizer. Note that the loss-of-clock circuitry is sensitive to a DC or AC voltage between the RXC_IN pins. A DC or AC voltage greater than Q30mV (typical) is sensed as an active clock signal. 12.5mA Figure 4. Back Termination Circuit DFP is a trademark of Video Electronics Standards Association (VESA). ADC is a trademark of Apple Computer, Inc. 8 _______________________________________________________________________________________ TMDS Digital Video Equalizer for HDMI/DVI Cables MAX3815A VCC The CLKLOS is an open-collector output that requires a resistive pullup to VCC for operation. The pullup resistor range is 1kω to 10kω (see Figure 3). 50Ω Output Level Control (OUTLEVEL) Input RX_IN+/- The OUTLEVEL pin is a three-state input that allows the user to select between three output settings. Forcing this pin high results in the standard output signal level with no back terminations; leaving the pin open results in a standard output swing with 267ω differential back termination resistors. Forcing this pin low results in one-half standard output signal level. Figure 5. Simplified Input Circuit Schematic Using Back Termination Using back termination resistance improves signal integrity through absorption of reflections. It also shifts the single-ended output voltage high (VH) and low (VL). Table 1 shows the output voltages when using the MAX3815A in each of its three output configurations. MAX3815A TRANSIENT SUPRESSOR CLAMP RX_OUT+ Equalizer Control (EQCONTROL) Input The EQCONTROL pin allows the user to control the equalization in one of two ways: forcing the pin to ground sets the equalizer in automatic equalization mode, and forcing a voltage between VCC - 1V to VCC allows manual control of the equalization level. Set to VCC for maximum boost (long cable). Set to VCC - 1V for minimum boost (short cable). RX_OUT- PWRDWN 0 1 10mA OUTLEVEL = HIGH 12.5mA OUTLEVEL = OPEN 5mA OUTLEVEL = LOW Figure 6. Simplified Output Circuit Schematic Table 1. Output Settings and Swings OUTLEVEL BACK TERMINATION DIFFERENTIAL SWING (mVP-P) SINGLE-ENDED HIGH (VH) SINGLE-ENDED LOW (VL) High Open 1000 VCC VCC - 500mV Open 267I 910 VCC - 85mV VCC - 540mV Low Open 500 VCC VCC - 250mV _______________________________________________________________________________________ 9 MAX3815A Interface Models The loss-of-clock circuitry powers down the part whenever there is an absence of a clock signal. This mutes the output and reduces power consumption to 83mW whenever the input signal is removed. During powerdown, the MAX3815A’s TMDS output pins go to a highimpedance state. •T he data and clock inputs should be wired directly between the cable connector and IC without stubs. TYPICAL MAX3815A CABLE REACH (DATA RATE = 2.25Gbps) •P lace supply filter capacitors close to the MAX3815A inputs to provide a low inductance path for supply return currents. 60 50 CABLE LENGTH (m) MAX3815A TMDS Digital Video Equalizer for HDMI/DVI Cables • Input and output data channel designations are only a guide. Polarity assignments can be swapped and channel paths can be interchanged. TYPICAL LIMIT OF CABLE WITH EQ AT 2.25Gbps 40 •A n uninterrupted ground plane should be positioned beneath the high-speed I/Os. 30 TYPICAL LIMIT OF CABLE WITHOUT EQ AT 2.25Gbps 20 •G round-path vias should be placed close to the input/ output connectors to allow a low inductance return current path. 10 0 28 26 24 22 WIRE GAUGE (AWG) Figure 7. Cable Reach Output On (OUTON) Input The OUTON pin is an LVTTL input. Force the pin low to enable the outputs. Force the pin high to set a differential zero on the outputs, irrespective of the signal at the inputs. Cable Selection TMDS performance is heavily dependent on cable quality. Deterministic jitter (DJ) can be caused by differential-tocommon-mode conversion (or vice versa) within a twisted pair (STP or UTP), usually a result of cable twist or dielectric imbalance. Refer to Application Note 3353: HFAN-04.5.4: ‘Jitter Happens’ when a Twisted Pair is Unbalanced and Application Note 4218: Unbalanced Twisted Pairs Can Give You the Jitters! for more information. Layout Considerations The data and clock inputs are the most critical paths for the MAX3815A and great care should be taken to minimize discontinuities on these transmission lines between the connector and the IC. Here are some suggestions for maximizing the performance of the MAX3815A: •M aintain 100Ω differential transmission line impedance into and out of the MAX3815A. •U se good high-frequency layout techniques and multilayer boards with an uninterrupted ground plane to minimize EMI and crosstalk. Refer to Application Note 3854: MAX3815: Interfacing to the MAX3815 DVI/HDMI Cable Equalizer and the EV kit data sheet, MAX3815AEVKIT-HDMI. Exposed-Pad Package The exposed pad on the 48-pin TQFP-EP provides a very low thermal resistance path for heat removal from the IC. The pad is also electrical ground on the MAX3815A and must be soldered to the circuit board ground for proper thermal and electrical performance. Refer to Maxim Application Note 862: HFAN-08.1: Thermal Considerations of QFN and Other Exposed-Paddle Packages for additional information. Chip Information PROCESS: SiGe BiPOLAR Package Information For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. PACKAGE TYPE PACKAGE CODE DOCUMENT NO. 48 TQFP-EP C48E+8 21-0065 10 ������������������������������������������������������������������������������������� TMDS Digital Video Equalizer for HDMI/DVI Cables VIDEO PROJECTOR RGB/HV ADC/SYNC VGA INPUT DVI-D INPUT SELECT LAPTOP TMDS DESERIALIZER MAX3815A EQUALIZER IMAGE SCALER AND PROCESSOR PANEL INTERFACE TIMING AND DRIVERS LCD, DLP, OR LCOS DVI-D CABLE UP TO 35m OR 120ft (24 AWG STP) GND VCC OUTON OUTLEVEL VCC_T GND_T VCC_T RES RES RES RES TOP VIEW VCC_T Pin Configuration 48 47 46 45 44 43 42 41 40 39 38 37 VCC 1 + 36 GND RX0_IN- 2 35 RX0_OUT- RX0_IN+ 3 34 RX0_OUT+ VCC 4 33 GND VCC 5 32 GND MAX3815A RX1_IN- 6 31 RX1_OUT- RX1_IN+ 7 30 RX1_OUT+ VCC 8 29 GND VCC 9 28 GND RX2_IN- 10 27 RX2_OUT*EP RX2_IN+ 11 26 RX2_OUT+ VCC 12 25 GND *EXPOSED PAD. GND GND RXC_OUT+ RXC_OUT- N.C. GND CLKLOS EQCONTROL VCC RXC_IN- RXC_IN+ VCC 13 14 15 16 17 18 19 20 21 22 23 24 TQFP Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 2009 Maxim Integrated Products 11 Maxim is a registered trademark of Maxim Integrated Products, Inc. MAX3815A Typical Operating Circuits (continued)