Preliminary RT9644/A ACPI Regulator/Controller for Dual Channel DDR Memory Systems General Description Features The RT9644/A is a complete ACPI compliant power solution for DDR and DDR2 memory system with up to 4 DIMMs dual channel systems. This RT9644 includes one synchronous buck controller for DDR/DDR2 VDDQ, one DDR/DDR2 bus terminator VTT (equal to VDDQ/2) regulator with source and sinking ability, three LDO controllers for V GMCH (cascode), and GMCH/CPU terminat ion VTT_GMCH/CPU. The RT9644A includes one synchronous buck controller for DDR/DDR2 VDDQ, one PWM controller for VGMCH (with external MOSFET driver), one DDR/DDR2 bus terminator VTT (equal to VDDQ/2) regulator with source and sinking ability, and two LDO controllers for VTT_GMCH/CPU and VDAC. l These parts also provide a reference buffer for DDR/DDR2 input reference voltage generator. When during S0 state, the VIDPGD indicates the GMCH_CPU VTT within spec and operational. The synchronous buck DC-DC PWM is implemented by two N-MOSFETs as upper and lower MOSFETs with voltage mode control. The linear controllers are implemented with one N-MOSFET with suitable capacitance. Each output is monitored by under voltage protection (RT9644 except VGMCHH and RT9644A except VDAC). V DDQ PW M controller and DDR/DDR2 bus terminator regulator have over voltage protection. Moreover, the VDDQ PWM controller has the over current protection by external resister adjustment. Thermal shut down is integrated. All the internal voltage reference is fixed at 0.8V, and users can adjust the resistance divider for desired voltage output. l l l l l l l l Applications l l l l l l Motherboard, Desktop Servers : Single/Dual channel DDR/DDR2 ACPI compliant Graphic Card : GPU and memory supply IA Equipments Telecomm Equipments DSP, ASIC or embedded processor and IO supplies High Power DC-DC Regulators DS9644/A-01 August 2007 l l l l RT9644 Includes Three LDO Controllers, One LDO Regulator and One PWM Controller }One DDR/DDR2 VDDQ with Synchronous Buck PWM }One DDR/DDR2 Bus Terminator VTT Regulator Source/Sink 3A }Two Cascode LDO Controllers for GMCH Core }One LDO Controller for GMCH/CPU Bus Terminator VTT_GMCH/CPU RT9644A Includes Two LDO Controllers, One LDO Regulator and Two PWM Controllers }One DDR/DDR2 VDDQ with Synchronous Buck PWM }One VGMCH with External Richtek MOSFET Driver }One DDR/DDR2 Bus Terminator VTT Regulator Source/Sink 3A }One LDO Controller for VDAC } One LDO Controller for GMCH/CPU Bus Terminator VTT_GMCH/CPU Operating with 5V and 12V Supply Voltage ACPI Compliant Sleep Mode Control Drive All Low Cost N-MOSFETs Voltage Mode PWM Control }250kHz Fixed Frequency Oscillator (RT9644A : Two PWM controllers with phase shift 90o) }Simple Voltage Mode Loop Control }Fast Transient Response }Over Current Protection Fully Adjustable Output Voltage Down to Compatible with DDR2 Integrated DDR/DDR2 Reference Buffer Integrated VIDPGD to Indicated V TT_GMCH/CPU Operational All Regulator Outputs Monitored by Under Voltage Protection DDR/DDR2 VDDQ and Bus Terminator VTT Also Integrated Over Voltage Protection Integrated Thermal Shut Down RoHS Compliant and 100% Lead (Pb)-Free www.richtek.com 1 RT9644/A Preliminary Ordering Information Note : RT9644/A Package Type QV : VQFN-28L 6x6 (V-Type) Operating Temperature Range P : Pb Free with Commercial Standard G : Green (Halogen Free with Commercial Standard) Two PWM Controller One PWM Controller RichTek Pb-free and Green products are : }RoHS compliant and compatible with the current requirements of IPC/JEDEC J-STD-020. }Suitable for use in SnPb or Pb-free soldering processes. }100% matte tin (Sn) plating. Pin Configurations LGATE GND UGATE BOOT PHASE S5# OCSET LGATE GND UGATE BOOT PHASE S5# OCSET (TOP VIEW) 28 27 26 25 24 23 22 28 27 26 25 24 23 22 DRIVE4 S3# 2 20 REFADJ4 P12V 3 19 GND 4 18 20 FB3 DRIVE3 P12V 3 19 PWM4 FB3 GND 4 18 FB4 17 FB4 DDR_VTT 5 17 COMP4 16 COMP DDR_VTT 6 16 COMP 15 FB VDDQ 7 15 FB GND 8 9 10 11 12 13 14 8 9 10 11 VREF_IN VDDQ DDR_VTTSNS DRIVE2 FB2 29 VIDPGD 29 2 VREF_OUT 7 S3# FB2 6 VDDQ DRIVE3 DRIVE2 DDR_VTT 21 DDR_VTTSNS 5 1 VDDQ DDR_VTT GND 5VSBY RT9644 12 13 14 VREF_IN 21 VIDPGD 1 VREF_OUT 5VSBY RT9644A VQFN-28L 6x6 www.richtek.com 2 DS9644/A-01 August 2007 RT9644/A Preliminary Typical Application Circuit 1 5VSBY 3 P12V BOOT 5VSBY OCSET 25 5VDL 22 P12V RT9644 V DDQ 21 Q3 DRIVE4 UGATE Q4 18 V GMCH PHASE 24 19 DRIVE3 20 LGATE REFADJ4 GND FB3 COMP Q5 10 DRIVE2 FB 28 V DDQ Q2 4, 27, Exposed Pad (29) 16 15 V DDQ 11 FB2 V TT_GMCH/CPU Q1 L1 17 FB4 V GMCHH 26 DDR_VTT 5, 6 DDR_VTTSNS 9 DDR_VTT V DDQ 7, 8 V DDQ VREF_OUT 13 VDDQ VREF_IN 14 23 S5# 12 VIDPGD 2 S3# VIDPGD SLP_S3# 5VSBY V CC V GMCH SLP_S5# P12V 3 P12V 5VSBY 1 V REF BOOT Q3 OCSET Richtek 19 PWM4 MOSFET RT9644A Driver Q4 UGATE 25 5VDL 22 26 Q1 L1 17 18 PHASE 24 COMP4 FB4 V GMCH Q5 V TT_GMCH/CPU 10 LGATE V DDQ Q2 4, 27, GND Exposed Pad (29) DRIVE2 11 FB2 COMP FB V CC Q6 28 21 DRIVE3 VDAC 20 FB3 V DDQ 7, 8 VDDQ 16 15 V DDQ DDR_VTT 5, 6 DDR_VTTSNS 9 DDR_VTT V DDQ VIDPGD SLP_S3# DS9644/A-01 August 2007 12 VIDPGD 2 S3# VREF_OUT 13 VREF_IN S5# V REF 14 23 SLP_S5# www.richtek.com 3 RT9644/A Preliminary Functional Pin Description Pin No. RT9644 RT9644A Pin Name Pin Function 1 1 5VSBY 5VSBY is the main internal power supply. The part works at normal operation mode (Icc_S0) and stand_by mode Icc_S5 (<1mA). The 5VSBY should be locally bypassed using a 0.1µF capacitor. 2 2 S3# This pin accepts the SLP_S3# sleep state signal. The internal LDO controller and DDR/DDR2 bus terminator VTT_DDR regulator are powered by the P12V. P12V is 3 3 P12V typically connected to the +12V rail of an ATX power supply. The P12V is not necessary in S3, S4, and S5 states. The GND terminals provide the return path for the chip. 4, 27, 4, 27, Large ground currents flow through the Exposed pad of the GND Exposed Pad (29) Exposed Pad (29) QFN package. The exposed pad must be soldered to a large PCB and connected to GND for maximum power dissipation. These two DDR_VTT pins (Pin 5 and 6) should be 5, 6 5, 6 DDR_VTT connected externally together. The pins are the output of DDR/DDR2 bus terminator that active in S0 and S1 states. These two VDDQ pins (Pin 7 and 8) should be connected externally together to the regulated VDDQ output. The pins 7, 8 7, 8 VDDQ are the power rail of DDT_VTT regulator. Large ground currents flow through these VDDQ pins. DDR_VTTSNS is used as the feedback for control of the DDR/DDR2 bus terminator VTT_DDR regulator. Connect 9 9 DDR_VTTSNS this pin to the DDR_VTT outputs (Pin 5 and 6) physical desired portion. This pin provides the gate voltage for the V TT_GMCH/CPU 10 10 DRIVE2 linear regulator. Connect this pin to the gate of an external N-MOSFET transistor. Connect the output of the V TT_GMCH/CPU linear regulator to this pin through a properly sized resistor divider. The voltage 11 11 FB2 at this pin is regulated to 0.8V. This pin is also monitored for under-voltage events. The VIDPGD pin is an open-drain logic output that changes to logic low if the VTT_GMCH/CPU linear regulator is out of 12 12 VIDPGD regulation in S0/S1/S2 state. It should be externally pulled high when VTT_GMCH/CPU is under regulated in S0, S1 and S2 states. VREF_OUT is a buffered version of DDR_VTT and also acts as the reference voltage for the DDR_VTT linear regulator. It is recommended that a typical capacitance of 0.1 µF is 13 13 VREF_OUT connected between V DDQ and VREF_OUT and also between VREF_OUT and ground for proper operation. Larger then 0.3µF capacitance is not recommended. To be continued www.richtek.com 4 DS9644/A-01 August 2007 RT9644/A Preliminary Pin No. RT9644 14 Pin Name 14 VREF_IN 15 15 FB 16 16 COMP 17 Pin Function RT9644A 18 FB4 A capacitor, CSS, connected between VREF_IN and ground is required. This capacitor and the parallel combination of the Upper and Lower Divider Impedance (RU//RL), sets the time constant for the start up ramp when transitioning from S3/S4/S5 to S0/S1/S2. The soft start capacitance will determine the V TT_DDR soft start ramp by the above RC time constant. CSS > (CVTT x VDDQ) / [10 x 2 x 1A x (RU//RL)] FB is the error amplifier negative input that needs proper resistance divider connected to V DDQ. The VDDQ synchronous DC-DC buck is simple voltage control mode. It needs a typical Type 2 compensation network from COMP to FB (or Type 3). The reference voltage of the error amplifier is 0.8V m onitored by under and over voltage protection. The COMP is the output to the voltage loop error amplifier. Loop compensation is achieved by connecting an AC network across COMP and FB. In RT9644, the FB4 pin connects the output of the upper V GMCH (VGMCHH) linear regulator to this pin. The voltage at this pin is regulated via the REFADJ4 pin (Pin 20). Generally, the FB4 is connected to V GMCHH, and REFADJ4 = VGMCH. The VGMCHH LDO controller will set the positive input to (VDDQ+REFADJ4)/2 as reference voltage. Then we can have the VGMCHH equal to (VDDQ +VGMCH)/2. nd In RT9644A, the FB4 is the 2 synchronous DC-DC buck converter error amplifier feedback. There should be the suitable AC compensation RC network. The compensation may be Type 2 even Type 3. The feedback voltage is monitored by the under voltage protection. 18 20 FB3 In RT9644, the FB3 pin connects the output of the lower V GMCH (VGMCH) linear regulator to this pin through a properly sized resistor divider. The voltage at this pin is regulated to 0.8V. This pin is monitored for under-voltage protection. In RT9644A, the pin connects the output of the V DAC linear regulator with proper resister divider. 19 21 DRIVE3 20 -- REFADJ4 21 -- DRIVE4 In RT9644, the DRIVE3 pin provides the gate voltage for the lower V GMCH linear regulator pass transistor. Connect this pin to the gate terminal of an external N-MOSFET transistor. In RT9644A, the DRIVE3 pin provides the gate voltage for the V DAC linear regulator pass transistor. Connect this pin to the gate terminal of an external N- MOSFET transistor. This REFADJ4 pin controls the V GMCHH LDO controller reference voltage. To ENSURE that both upper and lower pass transistors dissipate the same power, connecting this REFADJ4 pin to the V GMCH output rail. The DRIVE4 pin provides the gate voltage for the upper V GMCH (VGMCHH) linear regulator. Connect this pin to the gate terminal of an external N-MOSFET transistor. To be continued DS9644/A-01 August 2007 www.richtek.com 5 RT9644/A Pin No. Preliminary Pin Name RT9644 RT9644A -- 17 COMP4 -- 19 PWM4 Pin Function nd 22 22 OCSET The COMP4 pin provides the compensation AC network for the 2 synchronous DC-DC buck PWM controller. nd The PWM4 pin is the output of the 2 synchronous DC-DC buck converter used for VGMCH. The PWM4 should be connected to suitable RICHTEK MOSFET driver to drive 2 N-MOSFETs. VDDQ synchronous DC-DC buck converter has over current protection via the ROCSET to decide the over current criteria. Connect a resistor (R OCSET) from this pin to the drain of the upper N-MOSFET. There is an internal 20 µA current sink (I OCSET) from the OCSET pin. We can define the OC trip point via ROCSET, IOCSET, and the upper N-MOSFET on-resistance (R DS(ON)) as following equation : IPEAK = (IOCSET x ROCSET) / RDS(ON) 23 23 S5# 24 24 PHASE 25 25 BOOT 26 28 www.richtek.com 6 26 28 This pin accepts the SLP_S5# sleep state signal. For the VDDQ synchronous DC-DC buck converter, connect the PHASE pin to the upper N-MOSFET's source. This pin is used to monitor the voltage drop across the upper N-MOSFET for over-current protection. The PHASE pin is the return path rail for the upper MOSFET deriver (UGATE). For the VDDQ synchronous DC-DC buck converter, the BOOT pin provides as power supply to the upper N-MOSFET driver. A bootstrap circuit is used to create a voltage suitable to drive a logic-level N-MOSFET. UGATE For the V DDQ synchronous DC-DC buck converter, connect the UGATE pin to the upper N-MOSFET's gate. This pin provides the PWM-controlled gate drive for the upper N-MOSFET. This pin is also monitored by the adaptive shootthrough protection circuitry to determine when the upper N- MOSFET has turned off. Do not insert any circuitry between this pin and the gate of the upper N-MOSFET, as it may interfere with the internal adaptive shoot-through protection circuitry and render it ineffective. LGATE For the VDDQ synchronous DC-DC buck converter, Connect the LGATE pin to the lower N-MOSFET's gate. This pin provides the PWM-controlled gate drive for the lower N-MOSFET. This pin is also monitored by the adaptive shootthrough protection circuitry to determine when the lower N- MOSFET has turned off. Do not insert any circuitry between this pin and the gate of the lower N-MOSFET, as it may interfere with the internal adaptive shoot-through protection circuitry and render it ineffective. DS9644/A-01 August 2007 RT9644/A Preliminary Function Block Diagram RT9644 FB VDDQ RT9644 + + - DRIVE4 BOOT + + - UV COMP + - UGATE PHASE RAMP@ 250kHz 5VSBY FB4 REFADJ4 LGATE + FB3 + - OC OV 20uA + DRIVE3 + - + FB2 + DRIVE2 OCSET DDR_VTT VDDQ Digital & Peripheral Control VIDPGD + + VREF_IN Fault + + - Thermal shut_down shut_down S3# S5# P12V 5VSBY VREE_OUT DDR_VTTSNS GND RT9644A COMP4 FB4 FB RT9644A + + - PWM4 + - + UV DRIVE3 + - + 5VSBY OV + - OC OCSET 20uA + - + Digital & Peripheral Control DDR_VTT VDDQ VIDPGD + + VREF_IN Fault shut_down GND DS9644/A-01 August 2007 PHASE RAMP@ 250kHz + + UGATE LGATE + FB2 DRIVE2 BOOT + RAMP@ 250kHz shift 90 FB3 COMP + Thermal shut_down S3# + - S5# P12V 5VSBY VREE_OUT DDR_VTTSNS www.richtek.com 7 RT9644/A Preliminary Absolute Maximum Ratings l l l l l l l l l l l l (Note 1) Supply Voltage, 5VSBY ------------------------------------------------------------------------------- 7V Supply Voltage, P12V --------------------------------------------------------------------------------- 16V BOOT, VBOOT − VPHASE -------------------------------------------------------------------------------- 7V UGATE Voltage ------------------------------------------------------------------------------------------ VPHASE − 0.3V to VBOOT + 0.3V LGATE Voltage ------------------------------------------------------------------------------------------ GND − 0.3V to 5VSBY + 0.3V Input, Output or I/O Voltage -------------------------------------------------------------------------- GND − 0.3V to 7V Power Dissipation, PD @ TA = 25°C VQFN-28L 6x6 ------------------------------------------------------------------------------------------- 2.857W Package Thermal Resistance (Note 4) VQFN-28L 6x6, θJA ------------------------------------------------------------------------------------- 35°C/W Junction Temperature ---------------------------------------------------------------------------------- 150°C Lead Temperature (Soldering, 10 sec.) ------------------------------------------------------------- 260°C Storage Temperature Range -------------------------------------------------------------------------- −40°C to 150°C ESD Susceptibility (Note 2) HBM (Human Body Mode) ---------------------------------------------------------------------------- 2kV MM (Machine Mode) ----------------------------------------------------------------------------------- 200V Recommended Operating Conditions l l l l (Note 3) Supply Voltage, 5VSBY ------------------------------------------------------------------------------- 5V ± 5% Supply Voltage, P12V --------------------------------------------------------------------------------- 12V ± 10% Junction Temperature Range ------------------------------------------------------------------------- −40°C to 125°C Ambient Temperature Range ------------------------------------------------------------------------- −40°C to 85°C Electrical Characteristics (5VSBY = 5V, P12V = 12V, TA = 25°C, unless otherwise specification) Min Typ Max Units 5.5 7 8 mA -- 700 850 µA Rising 5VSBY POR Threshold 4 -- 4.35 V Falling 5VSBY POR Threshold 3.6 -- 3.95 V Rising P12V POR Threshold 10 -- 10.5 V Falling P12V POR Threshold 8.8 -- 9.75 V 220 250 280 kHz -- 1.5 -- V 6.5 8.2 9.5 ms Parameter Symbol Test Condition 5VSBY Supply Current ICC_S0 S3# & S5# High, UGATE/LGATE Open ICC_S5 S5# Low, S3# Don’t Care UGATE/LGATE Open Nominal Supply Current Power-On Reset Oscillator and Soft-Start PWM Frequency f OSC Ramp Amplitude △VOSC Soft-Start Interval tSS To be continued www.richtek.com 8 DS9644/A-01 August 2007 RT9644/A Preliminary Min Typ Max Units Reference Voltage V REF -- 0.8 -- V System Accuracy -2 - 2 % DC Gain Guaranteed By Design -- 80 -- dB Gain-Bandwidth Product GBWP 15 -- -- MHz Slew Rate SR -- 6 -- V/µs Low Level Input Threshold -- -- 0.75 V High Level Input Threshold 2.2 -- -- V UGATE and LGATE Source IGATE -- -0.8 -- A UGATE and LGATE Sink IGATE -- 0.8 -- A Parameter Symbol Test Condition Reference Voltage VDDQ PWM Controller Error Amplifier Control I/O (S3# and S5#) PWM Controller Gate Drivers V TT Regulator Upper Divider Impedance RU RU -- 2.5 -- kΩ Lower Divider Impedance RL RL -- 2.5 -- kΩ -- -- 2 mA -3 -- 3 A DC GAIN Guaranteed By Design -- 80 -- dB Gain Bandwidth Product GBWP 12 -- -- MHz Slew Rate SR -- 6 -- V/µs VREF_OUT Buffer Source Current IVREF_OUT Maximum VTT Load Current IVTT_MAX Periodic load applied with 30% duty cycle and 10ms period Linear Regulators DRIVEn High Output Voltage DRIVEn unloaded 9.75 10 -- V DRIVEn Low Output Voltage DRIVEn unloaded -- 0.16 0.4 V DRIVEn High Output Source Current -- 1.2 -- mA DRIVEn Low Output Sink Current -- 1.2 -- mA VIDPGOOD V TT_GMCH/CPU Rising Threshold S0 0.725 0.74 -- V V TT_GMCH/CPU Falling Threshold S0 -- 0.7 0.715 V 18 20 22 µA −3.3 -- 3.3 A Protection OCSET Current Source IOCS ET DDR_VTT Current Limit VDDQ OV Level S0/S3 By Design VFB/VREF S0/S3 -- 115 -- % VDDQ UV Level VFB/VREF S0/S3 -- 75 -- % DDR_VTT OV Level VTT/V VREF_IN S0 -- 115 -- % To be continued DS9644/A-01 August 2007 www.richtek.com 9 RT9644/A Parameter Preliminary Symbol Test Condition Min Typ Max Units DDR_VTT UV Level VTT/V VREF_IN S0 -- 85 -- % V GMCH UV Level VFB4/VREF S0 -- 75 -- % V TT_GMCH/CPU UV Level VFB2/VREF S0 -- 75 -- % Thermal Shutdown Limit TSD By Design -- 140 -- °C Note 1. Stresses listed as the above "Absolute Maximum Ratings" may cause permanent damage to the device. These are for stress ratings. Functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may remain possibility to affect device reliability. Note 2. Devices are ESD sensitive. Handling precaution is highly recommended. Note 3. The device is not guaranteed to function outside its operating conditions. Note 4. θJA is measured in the natural convection at T A = 25°C on a low effective thermal conductivity test board of JEDEC 51-3 thermal measurement standard. www.richtek.com 10 DS9644/A-01 August 2007 RT9644/A Preliminary Application Information S5# Overview S3# The RT9644/A provides complete control, drive, protection and ACPI compliance for a regulator powering DDR memory systems and the GMCH core and GMCH/CPU termination rails. It is primarily designed for computer applications powered from an ATX power supply. P12V VDDQ VGMCH VTT_GMCH/CPU A 250kHz Synchronous Buck Regulator with a precision 0.8V reference provides the proper Core voltage to the system memory of the computer. An internal LDO regulator with the ability to both sink and source current and an externally available buffered reference that tracks the VDDQ output by 50% provides the VTT termination voltage. In RT9644, a two-stage LDO controller provides the GMCH core voltage. A third LDO controller is included for the regulation of the GMCH/CPU termination voltage. In RT9644A, a second 250kHz PWM Buck regulator, which requires an external MOSFET driver, provides the GMCH core voltage. This PWM regulator is 90° out of phase with the PWM regulator used for the Memory core. Two additional LDO controllers are included, one for the regulation of the GMCH/CPU termination rail and the second for the DAC. ACPI State Transitions ACPI compliance is realized through the S3# and S5# sleep signals and through monitoring of the 12V ATX bus. Figure 1 and Figure 2 shows how the RT9644 and RT9644A individual regulators are controlled during all state transitions. S5# S3# P12V V DAC DDR_VTT TSS VIDPGD >3TSS t0t1 t2t3t4t5t6 t7 t8t9 t10 t12 t14 t11 t13 t15 Figure 2. Timing diagram for RT9644A S5 to S0 Transition At the onset of a mechanical start, time t0 in Figure 1, the RT9644 receives its bias voltage from the 5V Standby bus (5VSBY). Once the 5VSBY rail has exceeded the POR threshold, the RT9644 will remain in an internal S5 state until both the S3# and S5# signal have transitioned high and the 12V POR threshold has been exceeded by the +12V rail from the ATX, which occurs at time t1. Once all of these conditions are met, the PWM error amplifier will first be reset by internally shorting the COMP pin to the FB pin. This reset lasts for 3-4 soft-start cycles, Then digital soft-start sequence will begin. Each regulator is enabled and soft-started according to a preset sequence. At time t2 the VDDQ rail and the upper VGMCH LDO rail of RT9644 are digitally soft-started. The digital sof t-start f or the PW M regulator is accomplished by clamping the error amplifier reference input to a level proportional to the internal digital soft-start voltage. As the soft-start voltage slews up, the PWM comparator generates PHASE pulses of increasing width that charge the output capacitor(s). VDDQ VGMCHH VGMCH VTT_GMCH/CPU DDR_VTT TSS VIDPGD >3TSS t0t1 t2t3t4t5t6 t7 t8t9 t10 t12 t14 t11 t13 t15 This method provides a rapid and controlled rising output voltage. The linear regulators, with the exception of the internal DDR_VTT LDO, are soft-started in a similar manner. The error amplifier reference is clamped to the internal digital soft-start voltage. As the soft-start voltage ramps up, the respective DRIVE pin voltages increase, thus enhancing the N-MOSFETs and charging the output Figure 1. Timing diagram for RT9644 DS9644/A-01 August 2007 www.richtek.com 11 RT9644/A Preliminary capacitors in a controlled manner. S3 to S0 Transition At time t3, the VDDQ and upper VGMCH LDO output rails are in regulation and the lower VGMCH LDO is soft-started. At time t4, the VGMCH rail is in regulation and the VTT_GMCH/ CPU linear regulator is soft-started. At time t5, the VTT_GMCH/CPU rail is in regulation DDR_VTT internal regulator is soft-started. When S3# transits from LOW to HIGH with S5# held HIGH and after the 12V rail exceeds POR, the RT9644/A will initiate the soft-start sequence. This sequence is very similar to the mechanical start soft-start sequencing. The transition from S3 to S0 is represented in Figure 1 and Figure 2 between times t8 and t14. The DDR_VTT LDO soft-starts in a manner unlike the other regulators. When the DDR_VTT regulator is disabled, the reference is internally shorted to the DDR_VTT output. This allows the termination voltage to float during the S3 sleep state. When the RT9644 enables the DDR_VTT regulator or enters S0 state from a sleep state, this short is released and the internal divide down resistors which set the DDR_VTT voltage to 50% of DDR_VTT will provide a controlled voltage rise on the capacitor that is tied to the VREF_IN pin. At time t8, the S3# signal transits to HIGH. This enables the ATX, which brings up the 12V rail. At time t9, the 12V rail has exceeded the POR threshold and the RT9644 enters a reset mode that lasts for 3 soft-start cycles. At time t10, the 3 soft-start cycle reset is ended and the individual regulators are enabled and soft-started in the same sequence as the mechanical cold start sequence, with the exception that the VDDQ regulator is already enabled and in regulation. The voltage on this capacitor is the reference for the DDR_VTT regulator and the output will track it as it settles to 50% of the VDDQ voltage. The combination of the internal resistors and the VREF_IN capacitor will determine the rise time of the DDR_VTT regulator (see the Functional Pin Description section for proper sizing of the VREF_IN capacitor). At time t6, a full soft-start cycle has passed from the time that the DDR_VTT regulator was enabled. At this time the VIDPGD comparator is enabled. Once enabled if the VTT_GMCH/CPU output is within regulation, the VIDPGD pin will be forced to a high impedance state. S0 to S3 Transition When S3# goes LOW with S5# still HIGH, the RT9644/A will disable all the regulators except for the VDDQ regulator, which is continually supplied by the 5VDUAL rail. VIDPGD will also transition LOW. When VTT is disabled, the internal reference for the VTT regulator is internally shorted to the VTT rail. This allows the VTT rail to float. S0 to S5 Transition When the system transits from active state to shutdown (S0 to S5) state, the RT9644/A IC disables all regulators and forces the VIDPGD pin LOW. This transition is represented on Figure 1 and Figure 2 at time t15. Fault Protection The RT9644/A monitors the VDDQ regulator for under voltage,over-voltage and over-current protection. The internal DDR_VTT LDO regulator is monitored for undervoltageand over-voltage protection. All other regulators are monitored for under-voltage protection. An over-voltage protection on either the VDDQ or DDR_VTT regulator and thermal Shutdown protection will cause an immediate shutdown of all regulators. This can only be cleared by toggling the S5# signal such that the system enters the S5 sleep state and then transitions back to the active, S0, state. If a regulator experiences any other fault condition (an under-voltage or an over-current on VDDQ), all of regulator will be disabled and an internal fault counter will be incremented by 1. When floating, the voltage on the VTT rail will depend on the leakage characteristics of the memory and MCH I/O At every fault occurrence, the internal fault counter is incremented by 1 and an internal Fault Reset Counter is pins. It is important to note that the VTT rail may not bleed down to 0V. Figure 1 shows how the individual regulators cleared to zero. The Fault Reset Counter will Count 9 x Tss period. If the Fault Reset Counter reaches 9 x Tss are affected by the S3 state at time t7. www.richtek.com 12 DS9644/A-01 August 2007 RT9644/A Preliminary period and no other fault occurs, then the Fault Counter is cleared to 0. If a fault occurs prior to the Fault Reset Counter reaching 9 x Tss period, then the Fault Reset Counter is set back to zero. The break frequency FLC and FESR are expressed as Equation (1) and (2) respectively. 1 (1) FP_LC = 2π LCOUT The RT9644/A will immediately shut down when the Fault Counter reaches a count of 4. When attempting to restart a faulted regulator, the RT9644/A will follow the preset start up sequencing. If a regulator is already in regulation, then it will not be affected by the start up sequencing. FZ_ESR = VDDQ Overcurrent Protection The OCP function monitors output current by using upper MOSFET RDS(ON). The OCP function cycles soft-start function in a hiccup mode. Over-current triggering level can be arbitrarily set by adjusting ROCSET. An Internal 20µA current sink makes a voltage drop across ROCSET from VIN. When VPHASE is lower than VOCSET , OCP function initializes soft-start cycles. The OCP funcion will be triggered as inductor current reach : I × R OCSET IL(MAX) = OCSET R DS(ON) 1 2π × ESR × COUT (2) The compensation network consists of the error amplifier EA and the impedance networks ZIN and ZFB. The goal of the compensation network is to provide a closed loop transfer function with the highest DC gain, the highest 0dB crossing frequency (FC) and adequate phase margin. Typically, FC in range 1/5 to 1/10 of switching frequency is adequate. The higher FC is, the faster dynamic response is. A phase margin in the range of 45° C to 60° C is desirable. The equations below relate the compensation network poles, zeros and gain to the components (R1, R2, R3, C1, C2, and C3) in Figure 4. FZ1 = 1 2π × R2 × C1 (3) FZ2 = 1 2π × (R1 + R3) × C3 (4) To prevent OC form tripping in normal operation, ROCSET must be carefully chosen with : FP1 = 1 2π × R2 × C1× C2 C1 + C2 (5) 1. Maximum RDS(ON) at highest junction temperature FP2 = 1 2π × R3 × C3 (6) 2. MInimum IOCSET from specification table 3. IL(MAX) > IOUT(MAX) + ∆ IL /2 VIN ∆IL = inductor ripple current Feedback Compensation Figure 3 highlights the voltage-mode control loop for a synchronous buck converter. Figure 4 shows the corresponding Bode plot. The output voltage (VOUT ) is regulated to the reference voltage. The error amplifier EA output (COMP) is compared with the oscillator (OSC) sawtooth wave to provide a pulse-width modulated (PWM) wave with an amplitude of VIN at the PHASE node. The PWM wave is smoothed by the output filter (L and COUT ). OSC Driver PWM Comparator ∆VOSC Driver DS9644/A-01 August 2007 VOUT PHASE COUT ESR ZFB VE/A EA + ZIN REF Z FB C2 C1 The modulator transfer function is the small-signal transfer function of VOUT /COMP. This function is dominated by a DC gain and the output filter (L and COUT ), with a double pole break frequency at FP_LC and a zero at FZ_ESR. The DC gain of the modulator is simply the input voltage (VIN) divided by the peak-to-peak oscillator voltage %VOSC. L + ZIN C3 R2 VOUT R3 R1 COMP FB EA + REF Figure 3 www.richtek.com 13 RT9644/A 100 Preliminary FZ1 FZ2 FP1 Generally, an inductor that limits the ripple current between 20% and 50% of output current is appropriate. Make sure that the output inductor could handle the maximum output current and would not saturate over the operation temperature range. FP2 80 Gain (dB) 60 Open Loop Error AMP Gain 40 20 20LOG (R1/R2) 0 Compensation Gain Modulator Gain -20 Output Capacitor Selection 20LOG (VIN/∆VOSC) Closed Loop Gain -40 FLC -60 10 100 1K FESR 10K 100K 1M The output capacitors determine the output ripple voltage (%VOUT ) and the initial voltage drop after a high slew rate load transient. The selection of output capacitor depends on the output ripple requirement. The output ripple voltage is described as Equation (8). 10M Frequency (Hz) ∆VOUT = ∆IL × ESR + 1 × 8 f2 VOUT OSC Figure 4 Feedback Loop Design Procedure Use these guidelines for locating the poles and zeros of the compensation network: 1. Pick Gain (R2/R1) for desired 0dB crossing frequency (FC). 2. Place 1st zero FZ1 below modulator double pole FLC (~75% FLC). 3. Place 2nd zero FZ2 at modulator double pole FLC. 4. Place 1st pole FP1 at the ESR zero FZ_ESR 5. Place 2nd pole FP2 at half the switching frequency. 6. Check gain against error amplifier’ s open-loop gain. 7. Pick RFB for desired output voltage. 8. Estimate phase margin and repeat if necessary. Component Selection Components should be appropriately selected to ensure stable operation, fast transient response, high efficiency, minimum BOM cost and maximum reliability. × L × COUT (1 − D) (8) For electrolytic capacitor application, typically 90 to 95% of the output voltage ripple is contributed by the ESR of output capacitors. Paralleling lower ESR ceramic capacitor with the bulk capacitors could dramatically reduce the equivalent ESR and consequently the ripple voltage. Input Capacitor Selection Use mixed types of input bypass capacitors to control the input voltage ripple and switching voltage spike across the MOSFETs. The buck converter draws pulsewise current from the input capacitor during the on time of upper MOSFET. The RMS value of ripple current flowing through the input capacitor is described as : IIN(RMS) = IOUT × D × (1 − D) (9) The input bulk capacitor must be cable of handling this ripple current. Sometime, for higher efficiency the low ESR capacitor is necessarily. Appropriate high frequency ceramic capacitors physically near the MOSFETs effectively reduce the switching voltage spikes. MOSFET Selection of PWM Buck Converter Output Inductor Selection The selection of output inductor is based on the considerations of efficiency, output power and operating frequency. For a synchronous buck converter, the ripple current of inductor (%IL) can be calculated as follows : ∆IL = (VIN − VOUT ) × www.richtek.com 14 VOUT VIN × fOSC × L The sel ection of MOSF ETs i s based upon the considerations of RDS(ON), gate driving requirements, and thermal management requirements. The power loss of upper MOSFET consists of conduction loss and switching loss and is expressed as : (7) DS9644/A-01 August 2007 Preliminary PUPPER = PCOND_UPPER + PSW_UPPER (10) = I2 OUT × RDS(ON) × D + 1 IOUT 2 × VIN × (TRISE + TFALL ) × fOSC where TRISE and TFALL are rising and falling time of VDS of upper MOSFET respectively. RDS(ON) and QG should be simultaneously considered to minimize power loss of upper MOSFET. The power loss of lower MOSFET consists of conduction loss, reverse recovery loss of body diode, and conduction loss of body diode and is expressed as : PLOWER = PCOND_LOWER + PRR + PDIODE (11) = I2 OUT × RDS(ON) × (1 - D) + QRR × VIN × fOSC + 1 IOUT × VF × TDIODE × fOSC 2 where TDIODE is the conducting time of lower body diode. Special control scheme is adopted to minimize body diode conducting time. As a result, the RDS(ON) loss dominates the power loss of lower MOSFET. Use MOSFET with adequate RDS(ON) to minimize power loss and satisfy thermal requirements. RT9644/A inductor, and output capacitor should be as close to each other as possible. This can reduce the radiation of EMI due to the high frequency current loop. If the output capacitors are placed in parallel to reduce the ESR of capacitor, equal sharing ripple current should be considered. Place the input capacitor directly to the drain of high-side MOSFET. The MOSFETs of linear regulator should have wide pad to dissipate the heat. In multilayer PCB, use one layer as power ground and have a separate control signal ground as the reference of the all signal. To avoid the signal ground is effect by noise and have best load regulation, it should be connected to the ground terminal of output. Furthermore, follows below guide lines can get better performance of IC : (1). The IC needs a bypassing ceramic capacitor as a R-C filter to isolate the pulse current from power stage and supply to IC, so the ceramic capacitor should be placed adjacent to the IC. (2). Place the high frequency ceramic decoupling close to the power MOSFETs. (3). The feedback part should be placed as close to IC as possible and keep away from the inductor and all noise sources. MOSFET Selection of LDO The main criteria for selection of the LDO pass transistor is package selection for efficient removal of heat. Select a package and heatsink that maintains the junction temperature below the rating with a maximum expected ambient temperature. The power dissipated in the linear regulator is: PD = IOUT(MAX) x (VIN - VOUT ) where IOUT(MAX) is the maximum output current and VOUT is the nominal output voltage of LDO Layout Consideration (4). The components of bootstraps should be closed to each other and close to MOSFETs. (5).The PCB trace from Ug and Lg of controller to MOSFETs should be as short as possible and can carry 1A peak current. (6). Place all of the components as close to IC as possible. (7).VTT LDO must dissipate heat generated,the pin29 should be connected to the internal ground plane through four vias. Below PCB gerber files are our test board for your reference : Layout is very important in high frequency switching converter design. If designed improperly, the PCB could radiate excessive noise and contribute to the converter instability. First, place the PWM power stage components. Mount all the power components and connections in the top layer with wide copper areas. The MOSFETs of Buck, DS9644/A-01 August 2007 www.richtek.com 15 RT9644/A Preliminary Figure 5. Top Layer for RT9644 Figure 6. Bottom Layer for RT9644 Figure 7. Top Layer for RT9644A Figure 8. Bottom Layer for RT9644A www.richtek.com 16 DS9644/A-01 August 2007 RT9644/A Preliminary Outline Dimension D D2 SEE DETAIL A 1 E E2 L e b 1 1 2 2 A A1 A3 DETAIL A Pin #1 ID and Tie Bar Mark Options Note : The configuration of the Pin #1 identifier is optional, but must be located within the zone indicated. Symbol Dimensions In Millimeters Dimensions In Inches Min Max Min Max A 0.800 1.000 0.031 0.039 A1 0.000 0.050 0.000 0.002 A3 0.175 0.250 0.007 0.010 b 0.230 0.350 0.009 0.014 D 5.900 6.100 0.232 0.240 D2 3.500 4.100 0.138 0.161 E 5.900 6.100 0.232 0.240 E2 3.500 4.100 0.138 0.161 e L 0.650 0.500 0.026 0.700 0.020 0.028 V-Type 28L QFN 6x6 Package Richtek Technology Corporation Richtek Technology Corporation Headquarter Taipei Office (Marketing) 5F, No. 20, Taiyuen Street, Chupei City 8F, No. 137, Lane 235, Paochiao Road, Hsintien City Hsinchu, Taiwan, R.O.C. Taipei County, Taiwan, R.O.C. Tel: (8863)5526789 Fax: (8863)5526611 Tel: (8862)89191466 Fax: (8862)89191465 Email: [email protected] DS9644/A-01 August 2007 www.richtek.com 17