Addendum DS1, 2002-07-31 C161U Embedded C166 with USB, USART and SSC SAF C161U-LF, Version 1.3 Please, replace the erroneous description in the C161U Data Sheet, 2001-04-19, by the following correct text: 1 Fast External Interrupts Page 127, second paragraph: The pins of Port 2 (P2.1...P2.0) can individually be programmed to this fast interrupt mode, where also the trigger transition (rising, falling or both) can be selected. The External Interrupt Control register EXICON controls this feature for all 2 pins. EXICON (F1C0H / E0H) 15 14 13 12 ESFR 11 10 9 8 Reset Value: 0000H 7 6 5 4 3 2 1 0 00 00 00 00 00 00 EXI1ES EXI0ES rw rw rw rw rw rw rw rw Bit EXIxES Function External Interrupt x Edge Selection Field (x = 1:0) 0 0 Fast external interrupts disabled: standard mode 0 1 Interrupt on positive edge (rising) 1 0 Interrupt on negative edge (falling) 1 1 Interrupt on any edge (rising or falling) Revision History: Previous Version: Major Changes: Addendum 1/6 2002-07-31 C161U SAF C161U-LF External Interrupt Source Control 2 External Interrupt Source Control Page 128. EXISEL register is defined as follows: EXISEL (F1DAH / EDH) 15 14 13 12 ESFR-b 11 10 9 8 7 Reset Value: 0000H 6 5 4 3 2 1 0 EXI7SS 00 EXI5SS EXI4SS EXI3SS EXI2SS 00 00 rw rw rw rw rw rw rw rw Bit Function EXI0SS 00 01 10 11 Must be set to ’00’. Not allowed. Not allowed. Not allowed. EXI1SS 00 01 10 11 Must be set to ’00’. Not allowed. Not allowed. Not allowed. EXI2SS 00 01 10 11 Not applicable. Input from source ASC_RxD @ P3.11. Not allowed. Not allowed. EXI3SS 00 01 10 11 Not applicable. Input from source SSC_RxD @ P3.9. Not allowed. Not allowed. EXI4SS 00 01 10 11 Not applicable. Input from source SSC_SCLK @ P3.13. Not allowed. Not allowed. EXI5SS 00 01 10 11 Not applicable. Input from source USB_suspend interrupt. Not allowed. Not allowed. Addendum 2/6 2002-07-31 C161U SAF C161U-LF Interrupt Subnode Control Bit Function EXI6SS 00 01 10 11 Must be set to ’00’. Not allowed. Not allowed. Not allowed. EXI7SS 00 01 10 11 Not applicable. Input from source RTC_INT. Not allowed. Not allowed. 3 Interrupt Subnode Control Page 130. The ISNC register is defined as follows: ISNC (F1DEH / EFH) 15 14 13 12 ESFR-b 11 10 9 8 7 Reset Value: 0000H 6 5 4 3 2 1 0 PLL IE PLL IR RTC T14 IE RTC T14 IR Bit Function T14IR T14 Overflow Interrupt Request Flag ‘0’ No request pending ‘1’ This source has raised an interrupt request T14IE T14 Overflow Interrupt Enable Control Bit ‘0’ Interrupt request is disabled ‘1’ Interrupt request is enabled PLLIR PLL Interrupt Request Flag (OWD Interrupt) ‘0’ No request pending ‘1’ This source has raised an interrupt request PLLIE PLL Interrupt Enable Control Bit ‘0’ Interrupt request is disabled ‘1’ Interrupt request is enabled Note: See Data Sheet, Chapter 3.3 for Clock Generation Concept. Addendum 3/6 2002-07-31 C161U SAF C161U-LF System Startup Configuration 4 System Startup Configuration Page 369. Table 91 C161U’s Supported Modes and Related Reset Configurations P0L.5: P0L.2 (SMOD) P0L.1 (ADP) Selected Mode xxxx 0 Adapt Mode 1111 1 Normal Mode 0001 1 Internal Boot-ROM Read-Out Not applicable 1011 1 Bootstrap-Loader Mode 1101 1 Selftest Not applicable 5 Interrupt System Structure Page 109. Note: 1. The X-Bus interrupts xb(0), xb(1) and xb(2), known from other C16x device’s, are connected to the main interrupt node of the respective X-Bus peripheral: UTXRINT (xb(0) and irq(22)), EPECINT (xb(1) and irq(40)) and IOMIOINT (xb(2) and irq(42)). 2. Each entry of the interrupt vector table provides space for two word instructions or one doubleword instruction. The respective vector location results from multiplying the trap number by 4 (4 bytes per entry). 3. One interrupt control register is provided for each interrupt node. All IC registers of the C161U can be found in the SFR list. 4. ISNC register controls the interrupt xb(3). See Data Sheet, Chapter 7.8.3 for further description. Addendum 4/6 2002-07-31 C161U SAF C161U-LF Defining the RTC Time Base 6 Defining the RTC Time Base Page 296. Correct values are indicated blue. Table 67 RTC Interrupt Periods Oscillator Frequency Divider Factor RTC Input Frequency 32 kHz 1 32 kHz 1 MHz 32 31.25 kHz 4 MHz 32 5 MHz Prescaler Factor RTC_T14INT Period Minimum Maximum 31.25 µs 2.048 s 8 256.0 µs 16.77 s 125 kHz 8 64.0 µs 4.194 s 32 156.25 kHz 8 51.2 µs 3.355 s 8 MHz 32 250 kHz 8 32.0 µs 2.097 s 10 MHz 32 312.5 kHz 8 25.6 µs 1.678 s 12 MHz 32 375 kHz 8 21.3 µs 1.398 s 16 MHz 32 500 kHz 8 16.0 µs 1.049 s 20 MHz 32 625 kHz 8 12.8 µs 0.839 s 24 MHz 32 750 kHz 8 10.67 µs 0.699 s 25 MHz 32 781.25 kHz 8 10.24 µs 0.671 s 32 MHz 32 1 MHz 8 8.0 µs 0.524 s 50 MHz 32 1.56 MHz 8 5.12 µs 0.336 s : Table 68 RTC Reload Values RTC Input Frequency T14REL Base T14REL Base T14REL Base 32 kHz 8300H 1.000 s F380H 100.0 ms FFE0H 1.000 ms 31.25 kHz F0BEH 0.999 s FE79H 100.1 ms FFFCH 1.024 ms 125 kHz C2F7H 1.000 s F9E5H 100.0 ms FFF0H 1.024 ms 156.25 kHz B3B5H 0.999 s F85FH 99.9 ms FFECH 1.024 ms 250 kHz 85EEH 1.000 s F3CBH 100.0 ms FFE1H 0.992 ms 312.5 kHz 6769H 1.000 s F0BEH 99.9 ms FFD9H 0.998 ms 375 kHz 48E5H 1.000 s EDB0H 100.0 ms FFD1H 1.003 ms 500 kHz 0BDCH 1.000 s E796H 100.0 ms FFC1H 1.008 ms Addendum Reload Value A Reload Value B 5/6 Reload Value C 2002-07-31 C161U SAF C161U-LF Defining the RTC Time Base Table 68 RTC Input Frequency RTC Reload Values (cont’d) Reload Value A T14REL Base Reload Value B Reload Value C T14REL Base T14REL Base 625 kHz E17BH 100.0 ms FFB2H 0.998 ms 750 kHz DB61H 100.0 ms FFA2H 1.003 ms 781.25 kHz D9DAH 100.0 ms FF9EH 1.004 ms 1 MHz CF2CH 100.0 ms FF83H 1.000 ms 1.56 MHz B3B5H 99.9 ms FF3DH 0.998 ms Addendum 6/6 2002-07-31