ZARLINK ZL50114

ZL50110/11/12/14
128, 256, 512 and 1024 Channel CESoP
Processors
Data Sheet
Features
April 2008
Ordering Information
General
•
Circuit Emulation Services over Packet (CESoP)
transport for MPLS, IP and Ethernet networks
•
On chip timing & synchronization recovery across
a packet network
•
Grooming capability for Nx64 Kbps trunking
ZL50110GAG
552 PBGA
Trays, Bake
ZL50111GAG
552 PBGA
Trays, Bake
ZL50112GAG
552 PBGA
Trays, Bake
ZL50114GAG
552 PBGA
Trays, Bake
ZL50110GAG2 552 PBGA** Trays, Bake
ZL50111GAG2 552 PBGA** Trays, Bake
ZL50112GAG2 552 PBGA** Trays, Bake
ZL50114GAG2 552 PBGA** Trays, Bake
**Pb Fee Tin Silver/Copper
•
Supports ITU-T Recommendation Y.1413 and
Y.1453
•
Supports IETF RFC4553 and RFC5086
•
Supports MEF8 and MFA 8.0.0
•
Structured, synchronous CESoP with clock
recovery
•
Unstructured, asynchronous CESoP, with integral
per stream clock recovery
•
Direct connection to LIUs, framers, backplanes
•
Dual reference Stratum 4 and 4E DPLL for
synchronous operation
Network Interfaces
•
Up to 3 x 100 Mbps MII Fast Ethernet or Dual
Redundant 1000 Mbps GMII/TBI Ethernet
Interfaces
System Interfaces
•
Up to 1024 bi-directional 64 Kbps channels
TDM
In te rfa c e
(L IU , F ra m e r, B a c kp la n e )
P e r P o rt D C O fo r
C lo c k R e c o v e ry
•
On-chip packet memory for self-contained
operation, with buffer depths of over 16 ms
•
Up to 8 Mbytes of off-chip packet memory,
supporting buffer depths of over 128 ms
M u lti-P ro to c o l
P acket
P ro c e s s in g
E n g in e
PW , RTP, UDP,
IP v4 , IP v6 , M P L S ,
E C ID , V L A N , U s e r
D e fin e d , O th e rs
T rip le
P acket
In te rfa c e
MAC
(M II, G M II, T B I)
O n C h ip P a c k e t M e m o ry
Clocks
(J itte r B u ffe r C o m p e n s a tio n fo r 1 6 -1 2 8 m s o f P a c k e t D e la y V a ria tio n )
D u a l R e fe re n ce
S tra tu m 3 D P L L
H o st P ro ce ss o r
In te rfa ce
E x te rn a l M e m o ry
In te rfa c e (o p tio n a l)
3 2 -b it M o to ro la c o m p a tib le
D M A fo r s ig n a lin g p a c k e ts
Z B T -S R A M
(0 - 8 M b y te s )
Figure 1 - ZL50111 High Level Overview
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Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 2003-2008, Zarlink Semiconductor Inc. All Rights Reserved.
TBI Gigabit Ethernet
H.110, H-MVIP, ST-BUS backplanes
Flexible 32 bit host CPU interface (Motorola
PowerQUICC™ compatible)
or
•
•
Dual Redudnat 1000 Mbps GMII/
Up to 32 T1/E1, 8 J2, or 2 T3/E3 ports
H.110, H-MVIP, ST-BUS backplanes
•
Triple 100 Mbps MII Fast Ethernet
TDM Interfaces
32 T1/E1, 8 J2, 2 T3/E3 ports
Drypack
Drypack
Drypack
Drypack
Drypack
Drypack
Drypack
Drypack
-40°C to +85°C
Circuit Emulation Services
Backplane
&
&
&
&
&
&
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ZL50110/11/12/14
Data Sheet
Packet Processing Functions
•
Flexible, multi-protocol packet encapsulation including support for IPv4, IPv6, RTP, MPLS, L2TPv3, ITU-T
Y.1413, RFC4553, RFC5086 and user programmable
•
Packet re-sequencing to allow lost packet detection
•
Four classes of service with programmable priority mechanisms (WFQ and SP) using egress queues
•
Flexible classification of incoming packets at layers 2, 3, 4 and 5
•
Supports up to 128 separate CESoP connections across the Packet Switched Network
Applications
•
Circuit Emulation Services over Packet Networks
•
Leased Line support over packet networks
•
Multi-Tenant Unit access concentration
•
TDM over Cable
•
Fibre To The Premises G/E-PON
•
Layer 2 VPN services
•
Customer-premise and Provider Edge Routers and Switches
•
Packet switched backplane applications
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Zarlink Semiconductor Inc.
ZL50110/11/12/14
Data Sheet
Description
The ZL50110/11/12/14 family of CESoP processors are highly functional TDM to Packet bridging devices. The
ZL50110/11/12/14 provides both structured and unstructured circuit emulation services over packet (CESoP) for up
to 32 T1, 32 E1 and 8 J2 streams across a packet network based on MPLS, IP or Ethernet. The ZL50111 also
supports unstructured T3 and E3 streams.
The circuit emulation features in the ZL50110/11/12/14 family supports the ITU Recommendations Y.1413 and
Y.1453, as well as the CESoP standards from the Metro Ethernet Forum (MEF) and MPLS and Frame Relay
Alliance. The ZL50110/11/14 also supports IETF RFC4553 and RFC5086.
The ZL50110/11/12/14 provides up to triple 100 Mbps MII ports or dual redundant 1000 Mbps GMII/TBI ports.
The ZL50110/11/12/14 incorporates a range of powerful clock recovery mechanisms for each TDM stream, allowing
the frequency of the source clock to be faithfully generated at the destination, enabling greater system performance
and quality. Timing is carried using RTP or similar protocols, and both adaptive and differential clock recovery
schemes are included, allowing the customer to choose the correct scheme for the application. An externally
supplied clock may also be used to drive the TDM interface of the ZL50110/11/12/14.
The ZL50110/11/12/14 incur very low latency for the data flow, thereby increasing QoS when carrying voice
services across the Packet Switched Network. Voice, when carried using CESoP, which typically has latencies of
less than 10 ms, does not require expensive processing such as compression and echo cancellation.
The ZL50110/11/12/14 is capable of assembling user-defined packets of TDM traffic from the TDM interface and
transmitting them out the packet interfaces using a variety of protocols. The ZL50110/11/12/14 supports a range of
different packet switched networks, including Ethernet VLANs, IP and MPLS.
The ZL50110/11/12/14 can support up to 4 protocol stacks at the same time, provided that each protocol stack can
be uniquely identified by a mask & match approach.
Packets received from the packet interfaces are parsed to determine the egress destination, and are appropriately
queued to the TDM interface, they can also be forwarded to the host interface, or back toward the packet interface.
Packets queued to the TDM interface can be re-ordered based on sequence number, and lost packets filled in to
maintain timing integrity.
The ZL50110/11/12/14 family includes sufficient on-chip memory that external memory is not required in most
applications. This reduces system costs and simplifies the design. For applications that do require more memory
(e.g., high stream count or high latency), the device supports up to 8 Mbytes of SSRAM.
A comprehensive evaluation system is available upon request from your local Zarlink representative or distributor.
This system includes the CESoP processor, various TDM interfaces and a fully featured evaluation software GUI
that runs on a Windows PC.
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Zarlink Semiconductor Inc.
ZL50110/11/12/14
Data Sheet
Device Line Up
There are four products within the ZL50110/11/12/14 family, with capacity as shown in the following table:
Device
TDM Interfaces
Ethernet Packet I/F
Notes
ZL50114
4 T1, 4 E1, or 1 J2 streams or
4 MVIP/ST-BUS streams at 2.048 Mbps or
1 H.110/H-MVIP/ST-BUS streams at
8.192 Mbps
Dual 100 Mbps MII or
Dual Redundant 1000 Mbps GMII/TBI
Note 1
ZL50110
8 T1, 8 E1 or 2 J2 streams or
8 MVIP/ST-BUS streams at 2.048 Mbps or
2 H.110/H-MVIP/ST-BUS streams at
8.192 Mbps
Dual 100 Mbps MII or
Dual Redundant 1000 Mbps GMII/TBI
Note 1
ZL50112
16 T1, 16 E1, 4 J2 streams or
16 MVIP/ST-BUS streams at 2.048 Mbps or
4 H.110/H-MVIP/ST-BUS streams at
8.192 Mbps
Triple 100 Mbps MII or
Dual Redundant 1000 Mbps GMII/TBI
or Single 100 Mbps MII and Single
1000 Mbps GMII/TBI
Note 1
ZL50111
32 T1, 32 E1, 8 J2, 2 T3, 2 E3 streams or
32 MVIP/ST-BUS streams at 2.048 Mbps or
8 H.110/H-MVIP/ST-BUS streams at
8.192 Mbps
Triple 100 Mbps MII or
Dual Redundant 1000 Mbps GMII/TBI
or Single 100 Mbps MII and Single
1000 Mbps GMII/TBI
Note 1
Table 1 - Capacity of Devices in the ZL50110/11/14 Family
Note 1: T1/E1/J2 is for unstructured mode, and the H-MVIP/H.110/ST-BUS is for structured mode.
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Zarlink Semiconductor Inc.
ZL50110/11/12/14
Data Sheet
Table of Contents
1.0 Changes Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.0 Physical Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.0 External Interface Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.1 TDM Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.1.1 ZL50111 Variant TDM Stream Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.1.2 ZL50112 Variant TDM Stream Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.1.3 ZL50110 Variant TDM Stream Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.1.4 ZL50114 Variant TDM Stream Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.1.5 TDM Signals Common to ZL50110, ZL50111, ZL50112 and ZL50114 . . . . . . . . . . . . . . . . . . . . . . 30
3.2 PAC Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
3.3 Packet Interfaces. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
3.4 External Memory Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
3.5 CPU Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
3.6 System Function Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
3.7 Test Facilities. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
3.7.1 Administration, Control and Test Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
3.7.2 JTAG Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
3.8 Miscellaneous Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
3.9 Power and Ground Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
3.10 ZL50111, ZL50112, ZL50110 and ZA50114 Internal Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
3.11 ZL50112 Internal Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
3.12 ZL50112 Auxiliary Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
4.0 Typical Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
4.1 Leased Line Provision . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
4.2 Metropolitan Area Network Aggregation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
4.3 Digital Loop Carrier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
4.4 Remote Concentrator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
4.5 Cell Site Backhaul . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
4.6 Equipment Architecture Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
5.0 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
5.1 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
5.2 Data and Control Flows . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
5.3 TDM Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
5.3.1 TDM Interface Block. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
5.3.2 Structured TDM Port Data Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
5.3.3 TDM Clock Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
5.3.3.1 Synchronous TDM Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
5.3.3.2 Asynchronous TDM Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
5.4 Payload Assembly . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
5.4.1 Structured Payload Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
5.4.1.1 Structured Payload Order. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
5.4.2 Unstructured Payload Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
5.5 Protocol Engine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
5.6 Packet Transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
5.7 Packet Reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
5.8 TDM Formatter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
6.0 Clock Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
6.1 Differential Clock Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
6.2 Adaptive Clock Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
6.3 SYSTEM_CLK Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
7.0 System Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
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Zarlink Semiconductor Inc.
ZL50110/11/12/14
Data Sheet
Table of Contents
7.1 Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
7.2 Loopback Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
7.3 Host Packet Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
7.4 Loss of Service (LOS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
7.5 External Memory Requirement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
7.6 GIGABIT Ethernet - Recommended Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
7.6.1 Central Ethernet Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
7.6.2 Redundant Ethernet Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
7.7 Power Up sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
7.8 JTAG Interface and Board Level Test Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
7.9 External Component Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
7.9.1 Host Processor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
7.9.2 Other components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
7.10 Miscellaneous Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
7.11 Test Modes Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
7.11.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
7.11.1.1 System Normal Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
7.11.1.2 System Tri-State Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
7.11.2 Test Mode Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
7.11.3 System Normal Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
7.11.4 System Tri-state Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
8.0 DPLL Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
8.1 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
8.1.1 Locking Mode (normal operation) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
8.1.2 Holdover Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
8.1.3 Freerun Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
8.1.4 Powerdown Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
8.2 Reference Monitor Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
8.3 Locking Mode Reference Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
8.4 Locking Range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
8.5 Locking Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
8.6 Lock Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
8.7 Jitter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
8.7.1 Acceptance of Input Wander . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
8.7.2 Intrinsic Jitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
8.7.3 Jitter Tolerance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
8.7.4 Jitter Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
8.8 Maximum Time Interval Error (MTIE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
9.0 Memory Map and Register Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
10.0 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
11.0 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
11.1 TDM Interface Timing - ST-BUS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
11.1.1 ST-BUS Slave Clock Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
11.1.2 ST-BUS Master Clock Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
11.2 TDM Interface Timing - H.110 Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
11.3 TDM Interface Timing - H-MVIP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
11.4 TDM LIU Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
11.5 PAC Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
11.6 Packet Interface Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
11.6.1 MII Transmit Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
11.6.2 MII Receive Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
11.6.3 GMII Transmit Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
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11.6.4 GMII Receive Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
11.6.5 TBI Interface Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
11.6.6 Management Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
11.7 External Memory Interface Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
11.8 CPU Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
11.9 System Function Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
11.10 JTAG Interface Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
12.0 Power Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
13.0 Design and Layout Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
13.1 High Speed Clock & Data Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
13.1.1 External Memory Interface - special considerations during layout. . . . . . . . . . . . . . . . . . . . . . . . 104
13.1.2 GMAC Interface - special considerations during layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
13.1.3 TDM Interface - special considerations during layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
13.1.4 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
13.2 CPU TA Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
13.3 Mx_LINKUP_LED Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
14.0 Reference Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
14.1 External Standards/Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
14.2 Zarlink Standards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
15.0 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
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Figure 1 - ZL50111 High Level Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Figure 2 - ZL50111 Package View and Ball Positions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 3 - ZL50112 Package View and Ball Positions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 4 - ZL50110 Package View and Ball Positions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 5 - ZL50114 Package View and Ball Positions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 6 - Leased Line Services Over a Circuit Emulation Link. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Figure 7 - Metropolitan Area Network Aggregation using CESoP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Figure 8 - Digital Loop Carrier using CESoP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Figure 9 - Remote Concentrator using CESoP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Figure 10 - Cell Site Backhaul using CESoP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Figure 11 - Equipment example using CESoP. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Figure 12 - ZL50110/11/12/14 Family Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Figure 13 - ZL50110/11/12/14 Data and Control Flows . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Figure 14 - Synchronous TDM Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Figure 15 - ZL50110/11/12/14 Packet Format - Structured Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Figure 16 - Channel Order for Packet Formation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Figure 17 - ZL50110/11/12/14 Packet Format - Unstructured Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Figure 18 - Differential Clock Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Figure 19 - Adaptive Clock Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Figure 20 - External Memory Requirement for ZL50111 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Figure 21 - External Memory Requirement for ZL50110 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Figure 22 - Gigabit Ethernet Connection - Central Ethernet Switch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Figure 23 - Gigabit Ethernet Connection - Redundant Ethernet Switch. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Figure 24 - Powering Up the ZL50110/11/12/14 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Figure 25 - Jitter Transfer Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Figure 26 - Jitter Transfer Function - Detail . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Figure 27 - TDM ST-BUS Slave Mode Timing at 8.192 Mbps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Figure 28 - TDM ST-BUS Slave Mode Timing at 2.048 Mbps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Figure 29 - TDM Bus Master Mode Timing at 8.192 Mbps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Figure 30 - TDM Bus Master Mode Timing at 2.048 Mbps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Figure 31 - H.110 Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Figure 32 - TDM - H-MVIP Timing Diagram for 16 MHz Clock (8.192 Mbps) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Figure 33 - TDM-LIU Structured Transmission/Reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Figure 34 - MII Transmit Timing Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Figure 35 - MII Receive Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Figure 36 - GMII Transmit Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Figure 37 - GMII Receive Timing Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Figure 38 - TBI Transmit Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Figure 39 - TBI Receive Timing Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Figure 40 - Management Interface Timing for Ethernet Port - Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Figure 41 - Management Interface Timing for Ethernet Port - Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Figure 42 - External RAM Read and Write Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Figure 43 - CPU Read - MPC8260 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Figure 44 - CPU Write - MPC8260. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Figure 45 - CPU DMA Read - MPC8260 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Figure 46 - CPU DMA Write - MPC8260 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Figure 47 - JTAG Signal Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Figure 48 - JTAG Clock and Reset Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
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Figure 49 - ZL50110/11/12/14 Power Consumption Plot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Figure 50 - CPU_TA Board Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Figure 51 - Mx_LINKUP_LED Stuffing Option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
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List of Tables
Table 1 - Capacity of Devices in the ZL50110/11/14 Family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Table 2 - TDM Interface ZL50111 Stream Pin Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 3 - TDM Interface ZL50112 Stream Pin Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 4 - TDM Interface ZL50110 Stream Pin Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 5 - TDM Interface ZL50114 Stream Pin Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 6 - TDM Interface Common Pin Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 7 - PAC Interface Package Ball Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 8 - Packet Interface Signal Mapping - MII to GMII/TBI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 9 - MII Management Interface Package Ball Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 10 - MII Port 0 Interface Package Ball Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 11 - MII Port 1 Interface Package Ball Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Table 12 - MII Port 2 Interface Package Ball Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Table 13 - MII Port 3 Interface Package Ball Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Table 14 - External Memory Interface Package Ball Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Table 15 - CPU Interface Package Ball Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Table 16 - System Function Interface Package Ball Definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Table 17 - Administration/Control Interface Package Ball Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Table 18 - JTAG Interface Package Ball Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Table 19 - Miscellaneous Inputs Package Ball Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Table 20 - Power and Ground Package Ball Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Table 21 - No Connection Ball Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Table 22 - No Connection Ball Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Table 23 - Auxiliary clock Ball Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Table 24 - Standard Device Flows . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Table 25 - TDM Services Offered by the ZL50110/11/12/14 Family. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Table 26 - Some of the TDM Port Formats Accepted by the ZL50110/11/12/14 Family . . . . . . . . . . . . . . . . . . . . 59
Table 27 - DMA Maximum Bandwidths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Table 28 - Test Mode Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Table 29 - DPLL Input Reference Frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Table 30 - TDM ST-BUS Master Timing Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Table 31 - TDM H.110 Timing Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Table 32 - TDM H-MVIP Timing Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Table 33 - TDM - LIU Structured Transmission/Reception. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Table 34 - PAC Timing Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Table 35 - MII Transmit Timing - 100 Mbps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Table 36 - MII Receive Timing - 100 Mbps. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Table 37 - GMII Transmit Timing - 1000 Mbps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Table 38 - GMII Receive Timing - 1000 Mbps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Table 39 - TBI Timing - 1000 Mbps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Table 40 - MAC Management Timing Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Table 41 - External Memory Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Table 42 - CPU Timing Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Table 43 - System Clock Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Table 44 - JTAG Interface Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Table 45 - Mx_LINKUP_LED Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Table 46 - Mx_LINKUP_LED Stuffing Option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
10
Zarlink Semiconductor Inc.
ZL50110/11/12/14
1.0
Data Sheet
Changes Summary
The following table captures the changes from the April 2007 issue.
Page
Several
Item
Change
Include ZL50112 device
Add description for ZL50112
1, 2 and 3
Standard
Updated IETF RFC number and standards in general
1, 58, 74,
75 and 77
Stratum 3 DPLL
Updated the description for Stratum 3 DPLL
1, 4, 23, 51
and 58
STS-1 stream
Remove STS-1 stream
13
Section 2.0
Combine the packaged descriptions for all devices
32
Section 3.3
Include more detailed description for the packet interface
48
Section 3.7.2
ZL50112 and ZL50111 share the same JTAG ID
55
Section 4.6
Change the title of the section
56
Section 5.0
Add a note about jumbo packets
58
Section 5.3
Include a paragraph to clarify the support for structure and
unstructure modes at the same time
60
Section 5.4
Include more detailed description for the Payload Assembly
62
Section 5.4.2
Add a note at the end of the section
63
Section 5.8
Include more detailed description for the TDM formatter
64
Section 6.0
Include more detailed description for Clock Recovery
64
Section 6.1
Include more detailed description for Differential Clock
Recovery
65
Section 6.2
Updated the description of Adaptive Clock Recovery
72
Section 7.9
Added sub sections
86
Table 32
TDM_HDS Input Setup and TDM_HDS Input Hold, Max. time
corrected.
93
Section 11.6.5
Updated TXD[9:0] output delay
94
Section 11.6.6
UpdatedSection 11.6.6 Management Interface Timing
(M_MDIO hold time and Figure 40)
97
Figure 43 and Figure 44
CPU_TS_ALE and CPU_TA. Added mode details in Figure 43
and Figure 44
Added the CPU_TA assertion time.
The following table captures the changes from the February 2006 issue.
Page
95
Item
Table 41, Table 41 - External
Memory Timing
Change
Added Minimum Values
11
Zarlink Semiconductor Inc.
ZL50110/11/12/14
Data Sheet
The following table captures the changes from the April 2005 issue.
Page
Item
Change
Clarified ZL50111 supports 3 MII ports, ZL50110/4 support 2 MII
ports.
47, 48
66
Section 3.6 and Section 3.7.2
Added external pull-up/pull-down resistor recommendations for
SYSTEM_RST, SYSTEM_DEBUG, JTAG_TRST, JTAG_TCK.
Section 6.3
Added Section 6.3 SYSTEM_CLK Considerations.
The following table captures the changes from the January 2005 issue.
Page
Item
Change
Clarified data sheet to indicate ZL50110/11/12/14 supports
clock recovery in both synchronous and asynchronous modes
of operation.
98
Figure 45
Inverted polarity of CPU_DREQ0 and CPU_DREQ1 to conform
with default MPC8260. Polarity of CPU_DREQ and
CPU_SDACK remains programmable through API.
98
Figure 46
Inverted polarity of CPU_DREQ0 and CPU_DREQ1 to conform
with default MPC8260. Polarity of CPU_DREQ and
CPU_SDACK remains programmable through API.
The following table captures the changes from the October 2004 issue.
Page
48
Item
Section 3.7.1
Change
Added 5 kohm pulldown recommendation to GPIO signals.
The following table captures the changes from the September 2004 issue.
Page
12, 16, 19
Item
Change
Fig. 2 and Ball Signal
Assignment Table
Corrected Mx_LINKUP_LED pin assignment.
73
DC Electrical Characteristics
Table and Output Levels Table
Changed Electrical Characteristics to differentiate between
3.3 V and 5 V tolerant signals.
98
Section 13.3
New section added; Mx_LINKUP_LED Outputs.
12
Zarlink Semiconductor Inc.
ZL50110/11/12/14
2.0
Physical Specification
The ZL50110/11/12/14 is packaged in a PBGA device.
Features:
•
Body Size:
35 mm x 35 mm (typ)
•
Ball Count:
552
•
Ball Pitch:
1.27 mm (typ)
•
Ball Matrix:
26 x 26
•
Ball Diameter:
0.75 mm (typ)
•
Total Package Thickness:
2.33 mm (typ)
13
Zarlink Semiconductor Inc.
Data Sheet
ZL50110/11/12/14
Data Sheet
ZL50111 Package view from TOP side. Note that ball A1 is non-chamfered corner.
1 2
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
AA
AB
AC
AD
AE
AF
GND
3 4 5 6
7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
TDM_STo[ TDM_CLK TDM_STo[ TDM_STo[ TDM_STi[ TDM_STo[ TDM_STi[ TDM_CLK TDM_CLKiTDM_CLKi TDM_CLK
1]
o[3]
4]
5]
6]
7]
7]
o[10]
[10]
[11]
o[13]
GND
TDM_STo[ TDM_STo[ TDM_CLK TDM_STo[ TDM_CLK TDM_STi[ TDM_CLKi TDM_STi[ TDM_STo[ TDM_STi[ TDM_CLK TDM_CLK
13]
14]
o[15]
16]
o[18]
18]
[20]
20]
21]
21]
o[24]
o[25]
GND
TDM_FRM TDM_STo[ TDM_STi[ TDM_CLKi TDM_STi[ TDM_CLK TDM_STo[ TDM_CLK TDM_CLKi TDM_STo[ TDM_STi[ TDM_CLKi TDM_STo[ TDM_STi[ TDM_CLKi TDM_STi[ TDM_STi[ TDM_CLKi TDM_CLK TDM_STo[ TDM_STo[ TDM_CLK TDM_STo[ TDM_CLK TDM_STi[ TDM_CLK
o_REF
0]
2]
[3]
4]
o[6]
6]
o[8]
[9]
10]
10]
[12]
12]
13]
[15]
15]
17]
[18]
o[20]
19]
22]
o[23]
24]
o[26]
24]
o[27]
TDM_CLKiTDM_FRMTDM_CLKi TDM_CLK TDM_STi[ TDM_CLK TDM_CLKi TDM_CLKi TDM_CLK TDM_STo[ TDM_STi[ TDM_STi[ TDM_CLKi TDM_CLK TDM_CLK TDM_STi[ TDM_CLK TDM_STi[ TDM_CLK TDM_CLKiTDM_CLKi TDM_STi[ TDM_STo[ TDM_CLKi TDM_STi[ TDM_STi[
P
i_REF
_REF
o[1]
3]
o[2]
[6]
[7]
o[9]
9]
9]
11]
[13]
o[14]
o[16]
16]
o[17]
19]
o[21]
[21]
[24]
22]
26]
[27]
27]
28]
RAM_DAT RAM_DAT TDM_CLKi RAM_DAT TDM_STi[ TDM_CLKi TDM_STo[ TDM_STi[ TDM_CLKi TDM_CLK TDM_STi[ TDM_CLK TDM_STi[ TDM_STi[ TDM_CLKi TDM_CLK TDM_STo[ TDM_STo[ TDM_CLK TDM_STo[ TDM_STo[ TDM_CLKi TDM_CLK TDM_CLKi TDM_STi[ TDM_STi[
A[3]
A[1]
S
A[0]
0]
[1]
3]
5]
[5]
o[7]
8]
o[11]
12]
14]
[16]
o[19]
18]
20]
o[22]
27]
25]
[26]
o[28]
[29]
29]
31]
RAM_DAT RAM_DAT RAM_DAT RAM_DAT RAM_DAT TDM_CLK TDM_CLKi TDM_CLK TDM_STi[ TDM_CLKi TDM_STo[ TDM_CLKi TDM_CLK TDM_STo[ TDM_CLKi TDM_CLKi TDM_STo[ TDM_STi[ TDM_CLKi TDM_STi[ TDM_CLKi
A[10]
A[9]
A[5]
A[4]
A[2]
o_REF
[0]
o[4]
1]
[4]
8]
[8]
o[12]
15]
[17]
[19]
23]
23]
[25]
26]
[28]
RAM_DAT RAM_DAT RAM_DAT RAM_DAT RAM_DAT
A[15]
A[13]
A[12]
A[6]
A[7]
GND
VDD_COR TDM_STo[ TDM_CLK TDM_CLKi TDM_CLK VDD_COR TDM_STo[ TDM_CLKiVDD_COR TDM_STo[ TDM_CLKi TDM_STi[ TDM_CLKi VDD_COR
E
2]
o[0]
[2]
o[5]
E
11]
[14]
E
17]
[22]
25]
[23]
E
GND
GND
TDM_CLK TDM_CLKi TDM_STi[ TDM_STo[
o[30]
[30]
30]
29]
TDM_CLKi TDM_CLK TDM_STo[ TDM_CLK M1_LINKU
[31]
o[29]
28]
o[31]
P_LED
RAM_DAT RAM_DAT RAM_DAT RAM_DAT RAM_DAT RAM_DAT
A[21]
A[18]
A[16]
A[14]
A[11]
A[8]
TDM_STo[ TDM_STo[ M2_LINKUM3_LINKU M1_GIGA M_MDIO
31]
30]
P_LED
P_LED BIT_LED
RAM_DAT RAM_DAT RAM_DAT RAM_DAT RAM_DAT VDD_COR
A[25]
A[24]
A[23]
A[19]
A[17]
E
VDD_COR M0_GIGA M_MDC
E
BIT_LED
RAM_DAT RAM_DAT RAM_DAT RAM_DAT RAM_DAT RAM_DAT
A[29]
A[28]
A[27]
A[26]
A[22]
A[20]
VDD_IO
RAM_PAR RAM_PAR RAM_DAT RAM_DAT
ITY[1]
ITY[0]
A[31]
A[30]
VDD_COR
E
VDD_IO
RAM_PAR RAM_PAR RAM_PAR RAM_PAR RAM_PAR RAM_PAR
ITY[7]
ITY[6]
ITY[5]
ITY[4]
ITY[3]
ITY[2]
VDD_IO
GND
GND
GND
GND
GND
RAM_ADD RAM_ADD RAM_ADD RAM_ADD RAM_ADD RAM_ADD
R[5]
R[4]
R[2]
R[3]
R[0]
R[1]
VDD_IO
GND
GND
GND
GND
VDD_COR
E
VDD_IO
GND
GND
GND
RAM_ADD RAM_ADD RAM_ADD RAM_ADD RAM_ADD
R[9]
R[10]
R[11]
R[13]
R[16]
GND
VDD_IO
GND
GND
RAM_ADD RAM_ADD RAM_ADD RAM_ADD IC_GND
R[12]
R[14]
R[15]
R[19]
IC
VDD_IO
GND
A1VDD
VDD_IO
GND
GND
RAM_ADD RAM_ADD RAM_ADD
R[6]
R[7]
R[8]
RAM_ADD RAM_ADD RAM_BW IC_GND
R[17]
R[18]
_B
GND
GND
GND
PLL_PRI RAM_BW RAM_BW RAM_RW SYSTEM_ SYSTEM_
_A
_C
DEBUG
CLK
VDD_IO
PLL_SEC RAM_BW RAM_BW SYSTEM_ GPIO[2] VDD_COR
_D
_F
RST
E
VDD_IO
VDD_IO
VDD_IO
VDD_IO
VDD_IO
VDD_IO
VDD_IO
M3_RXDV M3_RXD[3M3_RXD[2M3_RXD[1 M3_RXD[0 M3_COL
]
]
]
]
VDD_IO
VDD_COR
E
GND
VDD_IO
M1_RXER M1_TXCL M1_CRS M3_TXD[0 M3_TXD[1 M3_TXD[2
K
]
]
]
GND
GND
VDD_IO
VDD_COR M1_REFC M1_RXCL M1_RXD[5 M1_RXD[7 M1_RXDV
E
LK
K
]
]
GND
GND
GND
VDD_IO
M1_GTX_
CLK
GND
GND
GND
GND
VDD_IO
M1_TXD[2 M1_TXD[6 M1_TXEN
]
]
GND
GND
GND
GND
GND
VDD_IO
M1_TXD[0 M1_TXD[3 M1_TXD[5 M1_TXD[7 M1_COL M1_RXD[1
]
]
]
]
]
GND
GND
GND
GND
GND
VDD_IO
VDD_COR M1_TXD[1 M1_TXD[4
E
]
]
VDD_IO
M0_GTX_ M0_RXD[2M0_RXD[5 M0_TXCL M0_CRS M1_RBC0
CLK
]
]
K
VDD_IO
M0_TXD[7 M0_TXER M0_TXEN M0_RXD[4 M0_RXDV M0_RXER
]
]
VDD_IO
VDD_IO
VDD_IO
VDD_IO
VDD_IO
VDD_IO
VDD_IO
VDD_IO
VDD_IO
VDD_IO
M3_CRS M3_TXCL M3_RXER
K
VDD_IO
GND
GND
M3_TXD[3 M3_TXEN M3_TXER M3_RXCL
]
K
M1_TXER M1_RXD[2 M1_RXD[3
]
]
GND
GND
GND
M1_RXD[4 M1_RXD[6
]
]
M1_RBC1 M1_RXD[0
]
RAM_BW RAM_BW GPIO[0]
_E
_G
GPIO[3]
GPIO[9] RAM_DAT
A[33]
M0_TXD[2 M0_TXD[5 M0_TXD[6 M0_RXD[6 M0_RXD[7 M0_RXD[3
]
]
]
]
]
]
RAM_BW GPIO[4]
_H
GPIO[6]
GPIO[10] RAM_DAT VDD_COR
A[32]
E
VDD_COR M0_TXD[1 M0_TXD[4 M0_RBC0 M0_COL M0_RXD[1
E
]
]
]
GPIO[8]
GPIO[15] RAM_DAT
A[39]
GPIO[1]
GPIO[7]
GND
RAM_DAT RAM_DAT VDD_COR JTAG_TM CPU_ADD CPU_ADD VDD_COR VDD_COR CPU_DAT CPU_DAT CPU_DAT VDD_COR M2_RXCL M2_RXDV
A[45]
A[52]
E
S
R[2]
R[12]
E
E
A[8]
A[15]
A[23]
E
K
GPIO[5]
GPIO[11] GPIO[14] RAM_DAT RAM_DAT RAM_DAT RAM_DAT RAM_DAT TEST_MO
A[38]
A[43]
A[44]
A[51]
A[60]
DE[1]
GND
GND
M0_TXD[0 M0_TXD[3 M0_REFC M0_RBC1 M0_RXD[0
]
]
LK
]
CPU_ADD CPU_ADD CPU_ADD CPU_TA CPU_DAT CPU_DAT CPU_DAT CPU_DAT CPU_DAT M2_TXER M2_RXD[1 M0_RXCL M0_LINKUM2_ACTIV M1_ACTIV M3_ACTIV
R[6]
R[14]
R[23]
A[1]
A[7]
A[12]
A[22]
A[30]
]
K
P_LED
E_LED
E_LED
E_LED
GPIO[12] GPIO[13] RAM_DAT RAM_DAT RAM_DAT RAM_DAT RAM_DAT TEST_MO JTAG_TD CPU_ADD CPU_ADD CPU_ADD CPU_ADD CPU_CLK CPU_DRE
A[37]
A[42]
A[46]
A[49]
A[59]
DE[0]
O
R[4]
R[9]
R[16]
R[22]
Q0
IC
CPU_DAT CPU_DAT CPU_DAT CPU_DAT M2_TXD[1 M2_TXEN M2_RXD[2 M2_RXER M2_CRS M0_ACTIV
A[10]
A[16]
A[21]
A[27]
]
]
E_LED
RAM_DAT RAM_DAT RAM_DAT RAM_DAT RAM_DAT RAM_DAT RAM_DAT JTAG_TC IC-GND CPU_ADD CPU_ADD CPU_ADD CPU_ADD CPU_WE CPU_SDA CPU_IRE CPU_DAT CPU_DAT CPU_DAT CPU_DAT CPU_DAT CPU_DAT M2_TXD[2 M2_RXD[0 M2_RXD[3 M2_TXCL
A[34]
A[36]
A[41]
A[47]
A[53]
A[58]
A[63]
K
R[7]
R[11]
R[17]
CK2
Q1
A[3]
A[6]
A[14]
A[20]
A[24]
A[29]
]
]
]
K
R[21]
RAM_DAT RAM_DAT RAM_DAT RAM_DAT RAM_DAT RAM_DAT JTAG_TR IC_GND CPU_ADD CPU_ADD CPU_ADD CPU_ADD CPU_ADD CPU_OE CPU_TS_ CPU_DRE
A[35]
A[40]
A[48]
A[54]
A[57]
A[62]
ST
R[3]
R[8]
R[13]
R[18]
R[20]
ALE
Q1
GND
RAM_DAT RAM_DAT RAM_DAT RAM_DAT TEST_MO JTAG_TDI IC_GND CPU_ADD CPU_ADD CPU_ADD CPU_ADD
A[50]
A[55]
A[56]
A[61]
DE[2]
R[5]
R[10]
R[15]
R[19]
1 2
3 4 5 6
GND
IC
CPU_DAT CPU_DAT CPU_DAT CPU_DAT CPU_DAT CPU_DAT M2_TXD[0 M2_TXD[3 M2_COL
A[4]
A[9]
A[13]
A[18]
A[25]
A[28]
]
]
CPU_CS CPU_SDA IC_VDD_I CPU_IRE CPU_DAT CPU_DAT CPU_DAT CPU_DAT CPU_DAT CPU_DAT CPU_DAT CPU_DAT
CK1
O
Q0
A[0]
A[5]
A[2]
A[11]
A[17]
A[19]
A[26]
A[31]
GND
7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
Figure 2 - ZL50111 Package View and Ball Positions
14
Zarlink Semiconductor Inc.
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
AA
AB
AC
AD
AE
AF
ZL50110/11/12/14
Data Sheet
ZL50112 Package view from TOP side. Note that ball A1 is non-chamfered corner.
1 2
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
AA
AB
AC
AD
AE
AF
GND
3 4 5 6
7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
TDM_STo[ TDM_CLK TDM_STo[ TDM_STo[ TDM_STi[ TDM_STo[ TDM_STi[ TDM_CLK TDM_CLKiTDM_CLKi TDM_CLK
1]
o[3]
4]
5]
6]
7]
7]
o[10]
[10]
[11]
o[13]
GND
TDM_STo[ TDM_STo[ TDM_CLK
13]
14]
o[15]
N/C
AUX1_CL
Ko[0]
N/C
N/C
N/C
N/C
N/C
N/C
N/C
GND
TDM_FRM TDM_STo[ TDM_STi[ TDM_CLKi TDM_STi[ TDM_CLK TDM_STo[ TDM_CLK TDM_CLKi TDM_STo[ TDM_STi[ TDM_CLKi TDM_STo[ TDM_STi[ TDM_CLKi TDM_STi[
o_REF
0]
2]
[3]
4]
o[6]
6]
o[8]
[9]
10]
10]
[12]
12]
13]
[15]
15]
N/C
AUX1_CL
Ki[0]
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
AUX2_CL
Ko[1]
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
RAM_DAT RAM_DAT TDM_CLKi RAM_DAT TDM_STi[ TDM_CLKi TDM_STo[ TDM_STi[ TDM_CLKi TDM_CLK TDM_STi[ TDM_CLK TDM_STi[ TDM_STi[ AUX2_CL AUX1_CL
A[3]
A[1]
S
A[0]
0]
[1]
3]
5]
[5]
o[7]
8]
o[11]
12]
14]
Ki[0]
Ko[1]
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
RAM_DAT RAM_DAT RAM_DAT RAM_DAT RAM_DAT TDM_CLK TDM_CLKi TDM_CLK TDM_STi[ TDM_CLKi TDM_STo[ TDM_CLKi TDM_CLK TDM_STo[ AUX2_CL AUX1_CL
A[10]
A[9]
A[5]
A[4]
A[2]
o_REF
[0]
o[4]
1]
[4]
8]
[8]
o[12]
15]
Ki[1]
Ki[1]
N/C
N/C
N/C
N/C
N/C
GND
N/C
N/C
N/C
IC
RAM_DAT RAM_DAT RAM_DAT RAM_DAT RAM_DAT
A[15]
A[13]
A[12]
A[6]
A[7]
N/C
N/C
N/C
VDD_COR
E
GND
N/C
N/C
N/C
IC
M1_LINKU
P_LED
IC
IC
M2_LINKU
P_LED
N/C
TDM_CLKiTDM_FRMTDM_CLKi TDM_CLK TDM_STi[ TDM_CLK TDM_CLKi TDM_CLKi TDM_CLK TDM_STo[ TDM_STi[ TDM_STi[ TDM_CLKi TDM_CLK AUX2_CL
P
i_REF
_REF
o[1]
3]
o[2]
[6]
[7]
o[9]
9]
9]
11]
[13]
o[14]
Ko[0]
GND
VDD_COR TDM_STo[ TDM_CLK TDM_CLKi TDM_CLK VDD_COR TDM_STo[ TDM_CLKiVDD_COR
E
2]
o[0]
[2]
o[5]
E
11]
[14]
E
N/C
N/C
RAM_DAT RAM_DAT RAM_DAT RAM_DAT RAM_DAT RAM_DAT
A[21]
A[18]
A[16]
A[14]
A[11]
A[8]
RAM_DAT RAM_DAT RAM_DAT RAM_DAT RAM_DAT VDD_COR
A[25]
A[24]
A[23]
A[19]
A[17]
E
VDD_COR M0_GIGA M_MDC
E
BIT_LED
RAM_DAT RAM_DAT RAM_DAT RAM_DAT RAM_DAT RAM_DAT
A[29]
A[28]
A[27]
A[26]
A[22]
A[20]
VDD_IO
RAM_PAR RAM_PAR RAM_DAT RAM_DAT
ITY[1]
ITY[0]
A[31]
A[30]
VDD_COR
E
VDD_IO
RAM_PAR RAM_PAR RAM_PAR RAM_PAR RAM_PAR RAM_PAR
ITY[7]
ITY[6]
ITY[5]
ITY[4]
ITY[3]
ITY[2]
VDD_IO
GND
GND
GND
GND
GND
RAM_ADD RAM_ADD RAM_ADD RAM_ADD RAM_ADD RAM_ADD
R[5]
R[4]
R[2]
R[3]
R[0]
R[1]
VDD_IO
GND
GND
GND
GND
VDD_COR
E
VDD_IO
GND
GND
GND
RAM_ADD RAM_ADD RAM_ADD RAM_ADD RAM_ADD
R[9]
R[10]
R[11]
R[13]
R[16]
GND
VDD_IO
GND
GND
RAM_ADD RAM_ADD RAM_ADD RAM_ADD IC_GND
R[12]
R[14]
R[15]
R[19]
IC
VDD_IO
GND
A1VDD
VDD_IO
GND
GND
RAM_ADD RAM_ADD RAM_ADD
R[6]
R[7]
R[8]
RAM_ADD RAM_ADD RAM_BW IC_GND
R[17]
R[18]
_B
GND
GND
GND
PLL_PRI RAM_BW RAM_BW RAM_RW SYSTEM_ SYSTEM_
_A
_C
DEBUG
CLK
VDD_IO
PLL_SEC RAM_BW RAM_BW SYSTEM_ GPIO[2] VDD_COR
_D
_F
RST
E
VDD_IO
VDD_IO
VDD_IO
VDD_IO
VDD_IO
VDD_IO
N/C
N/C
N/C
N/C
VDD_IO
VDD_COR
E
GND
N/C
N/C
N/C
N/C
GND
VDD_IO
M1_RXER M1_TXCL M1_CRS
K
N/C
N/C
N/C
GND
GND
VDD_IO
VDD_COR M1_REFC M1_RXCL M1_RXD[5 M1_RXD[7 M1_RXDV
E
LK
K
]
]
GND
GND
GND
VDD_IO
M1_GTX_
CLK
GND
GND
GND
GND
VDD_IO
M1_TXD[2 M1_TXD[6 M1_TXEN
]
]
GND
GND
GND
GND
GND
VDD_IO
M1_TXD[0 M1_TXD[3 M1_TXD[5 M1_TXD[7 M1_COL M1_RXD[1
]
]
]
]
]
GND
GND
GND
GND
GND
VDD_IO
VDD_COR M1_TXD[1 M1_TXD[4
E
]
]
VDD_IO
M0_GTX_ M0_RXD[2M0_RXD[5 M0_TXCL M0_CRS M1_RBC0
CLK
]
]
K
VDD_IO
M0_TXD[7 M0_TXER M0_TXEN M0_RXD[4 M0_RXDV M0_RXER
]
]
VDD_IO
VDD_IO
VDD_IO
VDD_IO
N/C
N/C
VDD_IO
VDD_IO
N/C
N/C
VDD_IO
VDD_IO
N/C
VDD_IO
VDD_IO
VDD_IO
M1_GIGA M_MDIO
BIT_LED
VDD_IO
GND
M1_TXER M1_RXD[2 M1_RXD[3
]
]
GND
GND
GND
M1_RXD[4 M1_RXD[6
]
]
M1_RBC1 M1_RXD[0
]
RAM_BW RAM_BW GPIO[0]
_E
_G
GPIO[3]
GPIO[9] RAM_DAT
A[33]
M0_TXD[2 M0_TXD[5 M0_TXD[6 M0_RXD[6 M0_RXD[7 M0_RXD[3
]
]
]
]
]
]
RAM_BW GPIO[4]
_H
GPIO[6]
GPIO[10] RAM_DAT VDD_COR
A[32]
E
VDD_COR M0_TXD[1 M0_TXD[4 M0_RBC0 M0_COL M0_RXD[1
E
]
]
]
GPIO[8]
GPIO[15] RAM_DAT
A[39]
GPIO[1]
GPIO[7]
GND
RAM_DAT RAM_DAT VDD_COR JTAG_TM CPU_ADD CPU_ADD VDD_COR VDD_COR CPU_DAT CPU_DAT CPU_DAT VDD_COR M2_RXCL M2_RXDV
A[45]
A[52]
E
S
R[2]
R[12]
E
E
A[8]
A[15]
A[23]
E
K
GPIO[5]
GPIO[11] GPIO[14] RAM_DAT RAM_DAT RAM_DAT RAM_DAT RAM_DAT TEST_MO
A[38]
A[43]
A[44]
A[51]
A[60]
DE[1]
GND
GND
M0_TXD[0 M0_TXD[3 M0_REFC M0_RBC1 M0_RXD[0
]
]
LK
]
CPU_ADD CPU_ADD CPU_ADD CPU_TA CPU_DAT CPU_DAT CPU_DAT CPU_DAT CPU_DAT M2_TXER M2_RXD[1 M0_RXCL M0_LINKUM2_ACTIV M1_ACTIV
R[6]
R[14]
R[23]
A[1]
A[7]
A[12]
A[22]
A[30]
]
K
P_LED
E_LED
E_LED
GPIO[12] GPIO[13] RAM_DAT RAM_DAT RAM_DAT RAM_DAT RAM_DAT TEST_MO JTAG_TD CPU_ADD CPU_ADD CPU_ADD CPU_ADD CPU_CLK CPU_DRE
A[37]
A[42]
A[46]
A[49]
A[59]
DE[0]
O
R[4]
R[9]
R[16]
R[22]
Q0
IC
N/C
CPU_DAT CPU_DAT CPU_DAT CPU_DAT M2_TXD[1 M2_TXEN M2_RXD[2 M2_RXER M2_CRS M0_ACTIV
A[10]
A[16]
A[21]
A[27]
]
]
E_LED
RAM_DAT RAM_DAT RAM_DAT RAM_DAT RAM_DAT RAM_DAT RAM_DAT JTAG_TC IC-GND CPU_ADD CPU_ADD CPU_ADD CPU_ADD CPU_WE CPU_SDA CPU_IRE CPU_DAT CPU_DAT CPU_DAT CPU_DAT CPU_DAT CPU_DAT M2_TXD[2 M2_RXD[0 M2_RXD[3 M2_TXCL
A[34]
A[36]
A[41]
A[47]
A[53]
A[58]
A[63]
K
R[7]
R[11]
R[17]
CK2
Q1
A[3]
A[6]
A[14]
A[20]
A[24]
A[29]
]
]
]
K
R[21]
RAM_DAT RAM_DAT RAM_DAT RAM_DAT RAM_DAT RAM_DAT JTAG_TR IC_GND CPU_ADD CPU_ADD CPU_ADD CPU_ADD CPU_ADD CPU_OE CPU_TS_ CPU_DRE
A[35]
A[40]
A[48]
A[54]
A[57]
A[62]
ST
R[3]
R[8]
R[13]
R[18]
R[20]
ALE
Q1
GND
RAM_DAT RAM_DAT RAM_DAT RAM_DAT TEST_MO JTAG_TDI IC_GND CPU_ADD CPU_ADD CPU_ADD CPU_ADD
A[50]
A[55]
A[56]
A[61]
DE[2]
R[5]
R[10]
R[15]
R[19]
1 2
3 4 5 6
GND
IC
CPU_DAT CPU_DAT CPU_DAT CPU_DAT CPU_DAT CPU_DAT M2_TXD[0 M2_TXD[3 M2_COL
A[4]
A[9]
A[13]
A[18]
A[25]
A[28]
]
]
CPU_CS CPU_SDA IC_VDD_I CPU_IRE CPU_DAT CPU_DAT CPU_DAT CPU_DAT CPU_DAT CPU_DAT CPU_DAT CPU_DAT
CK1
O
Q0
A[0]
A[5]
A[2]
A[11]
A[17]
A[19]
A[26]
A[31]
GND
7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
Figure 3 - ZL50112 Package View and Ball Positions
15
Zarlink Semiconductor Inc.
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
AA
AB
AC
AD
AE
AF
ZL50110/11/12/14
Data Sheet
ZL50110 Package view from TOP side. Note that ball A1 is non-chamfered corner.
1 2
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
AA
AB
AC
AD
AE
AF
GND
3 4 5 6
7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
TDM_STo TDM_CL TDM_STo TDM_STo TDM_STi[ TDM_STo TDM_STi[
[1]
Ko[3]
[4]
[5]
6]
[7]
7]
N/C
N/C
N/C
N/C
GND
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
GND
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
RAM_DA RAM_DA TDM_CL RAM_DA TDM_STi[ TDM_CL TDM_STo TDM_STi[ TDM_CL TDM_CL
TA[3]
TA[1]
KiS
TA[0]
0]
Ki[1]
[3]
5]
Ki[5]
Ko[7]
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
RAM_DA RAM_DA RAM_DA RAM_DA RAM_DA TDM_CL TDM_CL TDM_CL TDM_STi[ TDM_CL
TA[10]
TA[9]
TA[5]
TA[4]
TA[2]
Ko_REF
Ki[0]
Ko[4]
1]
Ki[4]
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
GND
N/C
N/C
N/C
N/C
N/C
N/C
VDD_CO
RE
N/C
N/C
N/C
N/C
VDD_CO
RE
GND
N/C
N/C
N/C
N/C
N/C
N/C
N/C
TDM_FR TDM_STo TDM_STi[ TDM_CL TDM_STi[ TDM_CL TDM_STo
Mo_REF
[0]
2]
Ki[3]
4]
Ko[6]
[6]
N/C
TDM_CL TDM_FR TDM_CL TDM_CL TDM_STi[ TDM_CL TDM_CL TDM_CL
KiP
Mi_REF Ki_REF
Ko[1]
3]
Ko[2]
Ki[6]
Ki[7]
RAM_DA RAM_DA RAM_DA RAM_DA RAM_DA
TA[15]
TA[13]
TA[12]
TA[6]
TA[7]
GND
VDD_CO TDM_STo TDM_CL TDM_CL TDM_CL VDD_CO
RE
[2]
Ko[0]
Ki[2]
Ko[5]
RE
RAM_DA RAM_DA RAM_DA RAM_DA RAM_DA RAM_DA
TA[21]
TA[18]
TA[16]
TA[14]
TA[11]
TA[8]
RAM_DA RAM_DA RAM_DA RAM_DA RAM_DA VDD_CO
TA[25]
TA[24]
TA[23]
TA[19]
TA[17]
RE
VDD_CO M0_GIGA M_MDC
RE
BIT_LED
RAM_DA RAM_DA RAM_DA RAM_DA RAM_DA RAM_DA
TA[29]
TA[28]
TA[27]
TA[26]
TA[22]
TA[20]
VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO
RAM_PA RAM_PA RAM_DA RAM_DA
RITY[1] RITY[0]
TA[31]
TA[30]
VDD_CO
RE
VDD_IO
RAM_PA RAM_PA RAM_PA RAM_PA RAM_PA RAM_PA
RITY[7] RITY[6] RITY[5] RITY[4] RITY[3] RITY[2]
VDD_IO
GND
GND
GND
GND
GND
RAM_AD RAM_AD RAM_AD RAM_AD RAM_AD RAM_AD
DR[5]
DR[4]
DR[2]
DR[3]
DR[0]
DR[1]
VDD_IO
GND
GND
GND
GND
VDD_CO
RE
VDD_IO
GND
GND
GND
RAM_AD RAM_AD RAM_AD RAM_AD RAM_AD
DR[9]
DR[10]
DR[11]
DR[13]
DR[16]
GND
VDD_IO
GND
GND
RAM_AD RAM_AD RAM_AD RAM_AD IC_GND
DR[12]
DR[14]
DR[15]
DR[19]
IC
VDD_IO
GND
A1VDD
VDD_IO
GND
GND
RAM_AD RAM_AD RAM_AD
DR[6]
DR[7]
DR[8]
RAM_AD RAM_AD RAM_BW IC_GND
DR[17]
DR[18]
_B
GND
GND
GND
M1_LINK M0_LINK M1_GIGA M_MDIO
UP_LED UP_LED BIT_LED
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
VDD_IO
VDD_CO
RE
GND
N/C
N/C
N/C
N/C
GND
VDD_IO
M1_RXE M1_TXCL M1_CRS
R
K
N/C
N/C
N/C
GND
GND
VDD_IO
VDD_CO M1_REF M1_RXCL M1_RXD[ M1_RXD[ M1_RXD
RE
CLK
K
5]
7]
V
GND
GND
GND
VDD_IO
M1_GTX_
CLK
GND
GND
GND
GND
VDD_IO
M1_TXD[ M1_TXD[ M1_TXEN
2]
6]
GND
GND
GND
GND
GND
VDD_IO
M1_TXD[ M1_TXD[ M1_TXD[ M1_TXD[ M1_COL M1_RXD[
0]
3]
5]
7]
1]
GND
GND
GND
GND
GND
VDD_IO
VDD_CO M1_TXD[ M1_TXD[
RE
1]
4]
GND
M1_TXER M1_RXD[ M1_RXD[
2]
3]
GND
GND
GND
M1_RXD[ M1_RXD[
4]
6]
M1_RBC1 M1_RXD[
0]
PLL_PRI RAM_BW RAM_BW RAM_RW SYSTEM SYSTEM
_A
_C
_DEBUG _CLK
VDD_IO
VDD_IO
M0_GTX_ M0_RXD[ M0_RXD[ M0_TXCL M0_CRS M1_RBC0
CLK
2]
5]
K
PLL_SEC RAM_BW RAM_BW SYSTEM GPIO[2] VDD_CO
_D
_F
_RST
RE
VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO
M0_TXD[ M0_TXERM0_TXEN M0_RXD[ M0_RXD M0_RXE
7]
4]
V
R
RAM_BW RAM_BW GPIO[0]
_E
_G
RAM_BW GPIO[4]
_H
GPIO[1]
GPIO[7]
GPIO[3]
GPIO[9] RAM_DA
TA[33]
M0_TXD[ M0_TXD[ M0_TXD[ M0_RXD[ M0_RXD[ M0_RXD[
2]
5]
6]
6]
7]
3]
GPIO[6] GPIO[10] RAM_DA VDD_CO
TA[32]
RE
VDD_CO M0_TXD[ M0_TXD[ M0_RBC0 M0_COL M0_RXD[
RE
1]
4]
1]
GPIO[8] GPIO[15] RAM_DA
TA[39]
GND
RAM_DA RAM_DA VDD_CO JTAG_TM CPU_AD CPU_AD VDD_CO VDD_CO CPU_DAT CPU_DAT CPU_DAT VDD_CO
TA[45]
TA[52]
RE
S
DR[2]
DR[12]
RE
RE
A[8]
A[15]
A[23]
RE
GPIO[5] GPIO[11] GPIO[14] RAM_DA RAM_DA RAM_DA RAM_DA RAM_DA TEST_M
TA[38]
TA[43]
TA[44]
TA[51]
TA[60]
ODE[1]
GND
N/C
CPU_AD CPU_AD CPU_AD CPU_TA CPU_DAT CPU_DAT CPU_DAT CPU_DAT CPU_DAT
DR[6]
DR[14]
DR[23]
A[1]
A[7]
A[12]
A[22]
A[30]
GPIO[12] GPIO[13] RAM_DA RAM_DA RAM_DA RAM_DA RAM_DA TEST_M JTAG_TD CPU_AD CPU_AD CPU_AD CPU_AD CPU_CLK CPU_DR
TA[37]
TA[42]
TA[46]
TA[49]
TA[59]
ODE[0]
O
DR[4]
DR[9]
DR[16]
DR[22]
EQ0
IC
N/C
GND
M0_TXD[ M0_TXD[ M0_REF M0_RBC1 M0_RXD[
0]
3]
CLK
0]
N/C
N/C
M0_RXCL
K
N/C
N/C
M1_ACTI
VE_LED
N/C
N/C
N/C
N/C
N/C
N/C
M0_ACTI
VE_LED
N/C
N/C
N/C
N/C
N/C
N/C
N/C
CPU_DAT CPU_DAT CPU_DAT CPU_DAT
A[10]
A[16]
A[21]
A[27]
RAM_DA RAM_DA RAM_DA RAM_DA RAM_DA RAM_DA RAM_DA JTAG_TC IC_GND CPU_AD CPU_AD CPU_AD CPU_AD CPU_WE CPU_SD CPU_IRE CPU_DAT CPU_DAT CPU_DAT CPU_DAT CPU_DAT CPU_DAT
TA[34]
TA[36]
TA[41]
TA[47]
TA[53]
TA[58]
TA[63]
K
DR[7]
DR[11]
DR[17]
ACK2
Q1
A[3]
A[6]
A[14]
A[20]
A[24]
A[29]
DR[21]
RAM_DA RAM_DA RAM_DA RAM_DA RAM_DA RAM_DA JTAG_TR IC_GND CPU_AD CPU_AD CPU_AD CPU_AD CPU_AD CPU_OE CPU_TS_ CPU_DR
TA[35]
TA[40]
TA[48]
TA[54]
TA[57]
TA[62]
ST
DR[3]
DR[8]
DR[13]
DR[18]
DR[20]
ALE
EQ1
GND
RAM_DA RAM_DA RAM_DA RAM_DA TEST_M JTAG_TDI IC_GND CPU_AD CPU_AD CPU_AD CPU_AD
TA[50]
TA[55]
TA[56]
TA[61]
ODE[2]
DR[5]
DR[10]
DR[15]
DR[19]
1 2
3 4 5 6
GND
IC
CPU_DAT CPU_DAT CPU_DAT CPU_DAT CPU_DAT CPU_DAT
A[4]
A[9]
A[13]
A[18]
A[25]
A[28]
CPU_CS CPU_SD IC_VDD_I CPU_IRE CPU_DAT CPU_DAT CPU_DAT CPU_DAT CPU_DAT CPU_DAT CPU_DAT CPU_DAT
ACK1
O
Q0
A[0]
A[5]
A[2]
A[11]
A[17]
A[19]
A[26]
A[31]
GND
7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
Figure 4 - ZL50110 Package View and Ball Positions
16
Zarlink Semiconductor Inc.
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
AA
AB
AC
AD
AE
AF
ZL50110/11/12/14
Data Sheet
ZL50114 Package view from TOP side. Note that ball A1 is non-chamfered corner.
1 2
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
AA
AB
AC
AD
AE
AF
GND
3 4 5 6
TDM_STo TDM_CL
[1]
Ko[3]
N/C
7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
GND
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
GND
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
RAM_DA RAM_DA TDM_CL RAM_DA TDM_STi[ TDM_CL TDM_STo
TA[3]
TA[1]
KiS
TA[0]
0]
Ki[1]
[3]
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
RAM_DA RAM_DA RAM_DA RAM_DA RAM_DA TDM_CL TDM_CL
TA[10]
TA[9]
TA[5]
TA[4]
TA[2]
Ko_REF
Ki[0]
N/C
TDM_STi[
1]
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
GND
N/C
N/C
N/C
N/C
N/C
VDD_CO
RE
N/C
N/C
VDD_CO
RE
N/C
N/C
N/C
N/C
VDD_CO
RE
GND
N/C
N/C
N/C
N/C
N/C
N/C
N/C
TDM_FR TDM_STo TDM_STi[ TDM_CL
Mo_REF
[0]
2]
Ki[3]
TDM_CL TDM_FR TDM_CL TDM_CL TDM_STi[ TDM_CL
KiP
Mi_REF Ki_REF
Ko[1]
3]
Ko[2]
RAM_DA RAM_DA RAM_DA RAM_DA RAM_DA
TA[15]
TA[13]
TA[12]
TA[6]
TA[7]
GND
VDD_CO TDM_STo TDM_CL TDM_CL
RE
[2]
Ko[0]
Ki[2]
RAM_DA RAM_DA RAM_DA RAM_DA RAM_DA RAM_DA
TA[21]
TA[18]
TA[16]
TA[14]
TA[11]
TA[8]
RAM_DA RAM_DA RAM_DA RAM_DA RAM_DA VDD_CO
TA[25]
TA[24]
TA[23]
TA[19]
TA[17]
RE
VDD_CO M0_GIGA M_MDC
RE
BIT_LED
RAM_DA RAM_DA RAM_DA RAM_DA RAM_DA RAM_DA
TA[29]
TA[28]
TA[27]
TA[26]
TA[22]
TA[20]
VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO
RAM_PA RAM_PA RAM_DA RAM_DA
RITY[1] RITY[0]
TA[31]
TA[30]
VDD_CO
RE
VDD_IO
RAM_PA RAM_PA RAM_PA RAM_PA RAM_PA RAM_PA
RITY[7] RITY[6] RITY[5] RITY[4] RITY[3] RITY[2]
VDD_IO
GND
GND
GND
GND
GND
RAM_AD RAM_AD RAM_AD RAM_AD RAM_AD RAM_AD
DR[5]
DR[4]
DR[2]
DR[3]
DR[0]
DR[1]
VDD_IO
GND
GND
GND
GND
VDD_CO
RE
VDD_IO
GND
GND
GND
RAM_AD RAM_AD RAM_AD RAM_AD RAM_AD
DR[9]
DR[10]
DR[11]
DR[13]
DR[16]
GND
VDD_IO
GND
GND
RAM_AD RAM_AD RAM_AD RAM_AD IC_GND
DR[12]
DR[14]
DR[15]
DR[19]
IC
VDD_IO
GND
A1VDD
VDD_IO
GND
GND
RAM_AD RAM_AD RAM_AD
DR[6]
DR[7]
DR[8]
RAM_AD RAM_AD RAM_BW IC_GND
DR[17]
DR[18]
_B
GND
GND
GND
M1_LINK M0_LINK M1_GIGA M_MDIO
UP_LED UP_LED BIT_LED
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
VDD_IO
VDD_CO
RE
GND
N/C
N/C
N/C
N/C
GND
VDD_IO
M1_RXE M1_TXCL M1_CRS
R
K
N/C
N/C
N/C
GND
GND
VDD_IO
VDD_CO M1_REF M1_RXCL M1_RXD[ M1_RXD[ M1_RXD
RE
CLK
K
5]
7]
V
GND
GND
GND
VDD_IO
M1_GTX_
CLK
GND
GND
GND
GND
VDD_IO
M1_TXD[ M1_TXD[ M1_TXEN
2]
6]
GND
GND
GND
GND
GND
VDD_IO
M1_TXD[ M1_TXD[ M1_TXD[ M1_TXD[ M1_COL M1_RXD[
0]
3]
5]
7]
1]
GND
GND
GND
GND
GND
VDD_IO
VDD_CO M1_TXD[ M1_TXD[
RE
1]
4]
GND
M1_TXER M1_RXD[ M1_RXD[
2]
3]
GND
GND
GND
M1_RXD[ M1_RXD[
4]
6]
M1_RBC1 M1_RXD[
0]
PLL_PRI RAM_BW RAM_BW RAM_RW SYSTEM SYSTEM
_A
_C
_DEBUG _CLK
VDD_IO
VDD_IO
M0_GTX_ M0_RXD[ M0_RXD[ M0_TXCL M0_CRS M1_RBC0
CLK
2]
5]
K
PLL_SEC RAM_BW RAM_BW SYSTEM GPIO[2] VDD_CO
_D
_F
_RST
RE
VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO
M0_TXD[ M0_TXERM0_TXEN M0_RXD[ M0_RXD M0_RXE
7]
4]
V
R
RAM_BW RAM_BW GPIO[0]
_E
_G
RAM_BW GPIO[4]
_H
GPIO[1]
GPIO[7]
GPIO[3]
GPIO[9] RAM_DA
TA[33]
M0_TXD[ M0_TXD[ M0_TXD[ M0_RXD[ M0_RXD[ M0_RXD[
2]
5]
6]
6]
7]
3]
GPIO[6] GPIO[10] RAM_DA VDD_CO
TA[32]
RE
VDD_CO M0_TXD[ M0_TXD[ M0_RBC0 M0_COL M0_RXD[
RE
1]
4]
1]
GPIO[8] GPIO[15] RAM_DA
TA[39]
GND
RAM_DA RAM_DA VDD_CO JTAG_TM CPU_AD CPU_AD VDD_CO VDD_CO CPU_DAT CPU_DAT CPU_DAT VDD_CO
TA[45]
TA[52]
RE
S
DR[2]
DR[12]
RE
RE
A[8]
A[15]
A[23]
RE
GPIO[5] GPIO[11] GPIO[14] RAM_DA RAM_DA RAM_DA RAM_DA RAM_DA TEST_M
TA[38]
TA[43]
TA[44]
TA[51]
TA[60]
ODE[1]
GND
N/C
CPU_AD CPU_AD CPU_AD CPU_TA CPU_DAT CPU_DAT CPU_DAT CPU_DAT CPU_DAT
DR[6]
DR[14]
DR[23]
A[1]
A[7]
A[12]
A[22]
A[30]
GPIO[12] GPIO[13] RAM_DA RAM_DA RAM_DA RAM_DA RAM_DA TEST_M JTAG_TD CPU_AD CPU_AD CPU_AD CPU_AD CPU_CLK CPU_DR
TA[37]
TA[42]
TA[46]
TA[49]
TA[59]
ODE[0]
O
DR[4]
DR[9]
DR[16]
DR[22]
EQ0
IC
N/C
GND
M0_TXD[ M0_TXD[ M0_REF M0_RBC1 M0_RXD[
0]
3]
CLK
0]
N/C
N/C
M0_RXCL
K
N/C
N/C
M1_ACTI
VE_LED
N/C
N/C
N/C
N/C
N/C
N/C
M0_ACTI
VE_LED
N/C
N/C
N/C
N/C
N/C
N/C
N/C
CPU_DAT CPU_DAT CPU_DAT CPU_DAT
A[10]
A[16]
A[21]
A[27]
RAM_DA RAM_DA RAM_DA RAM_DA RAM_DA RAM_DA RAM_DA JTAG_TC IC_GND CPU_AD CPU_AD CPU_AD CPU_AD CPU_WE CPU_SD CPU_IRE CPU_DAT CPU_DAT CPU_DAT CPU_DAT CPU_DAT CPU_DAT
TA[34]
TA[36]
TA[41]
TA[47]
TA[53]
TA[58]
TA[63]
K
DR[7]
DR[11]
DR[17]
ACK2
Q1
A[3]
A[6]
A[14]
A[20]
A[24]
A[29]
DR[21]
RAM_DA RAM_DA RAM_DA RAM_DA RAM_DA RAM_DA JTAG_TR IC_GND CPU_AD CPU_AD CPU_AD CPU_AD CPU_AD CPU_OE CPU_TS_ CPU_DR
TA[35]
TA[40]
TA[48]
TA[54]
TA[57]
TA[62]
ST
DR[3]
DR[8]
DR[13]
DR[18]
DR[20]
ALE
EQ1
GND
RAM_DA RAM_DA RAM_DA RAM_DA TEST_M JTAG_TDI IC_GND CPU_AD CPU_AD CPU_AD CPU_AD
TA[50]
TA[55]
TA[56]
TA[61]
ODE[2]
DR[5]
DR[10]
DR[15]
DR[19]
1 2
3 4 5 6
GND
IC
CPU_DAT CPU_DAT CPU_DAT CPU_DAT CPU_DAT CPU_DAT
A[4]
A[9]
A[13]
A[18]
A[25]
A[28]
CPU_CS CPU_SD IC_VDD_I CPU_IRE CPU_DAT CPU_DAT CPU_DAT CPU_DAT CPU_DAT CPU_DAT CPU_DAT CPU_DAT
ACK1
O
Q0
A[0]
A[5]
A[2]
A[11]
A[17]
A[19]
A[26]
A[31]
GND
7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
Figure 5 - ZL50114 Package View and Ball Positions
17
Zarlink Semiconductor Inc.
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
AA
AB
AC
AD
AE
AF
ZL50110/11/12/14
Ball Signal Assignment
Ball
Number
A1
A2
A3
A4
‡
A5
‡
A6‡
A7‡
A8
‡
A9†
A10†
A11†
A12†
A13
†
A14
A15†
†
A16
A17*
A18†*
*
A19
A20*
A21*
A22*
A23*
A24*
A25*
A26
B1
B2
B3
B4
B5
‡
B6‡
B7‡
B8†
B9†
B10†
B11†
Signal Name
Data Sheet
Ball
Number
Signal Name
Ball
Number
Signal Name
B12†
TDM_CLKi[12]
C24*
TDM_CLKi[27]
*
TDM_STi[27]
†
GND
B13
TDM_STo[12]
C25
TDM_STo[1]
B14†
TDM_STi[13]
C26*
TDM_STi[28]
TDM_CLKo[3]
B15†
TDM_CLKi[15]
D1
RAM_DATA[3]
TDM_STo[4]
†
B16
TDM_STi[15]
D2
RAM_DATA[1]
TDM_STo[5]
B17*
TDM_STi[17]
D3
TDM_CLKiS
TDM_STi[6]
B18†*
TDM_CLKi[18]
D4
RAM_DATA[0]
*
TDM_STo[7]
B19
TDM_CLKo[20]
D5
TDM_STi[0]
TDM_STi[7]
B20*
TDM_STo[19]
D6
TDM_CLKi[1]
TDM_CLKo[10]
B21*
TDM_STo[22]
D7
TDM_STo[3]
‡
TDM_STi[5]
*
TDM_CLKi[10]
B22
TDM_CLKi[11]
B23*
*
TDM_CLKo[13]
B24
GND
B25*
TDM_STo[13]
B26*
TDM_STo[14]
TDM_CLKo[15]
TDM_STo[16]
TDM_CLKo[18]
C1
C2
C3
C4
TDM_CLKo[23]
D8
TDM_STo[24]
D9‡
‡
TDM_CLKi[5]
TDM_CLKo[26]
D10
TDM_STi[24]
D11†
TDM_CLKo[7]
TDM_STi[8]
TDM_CLKo[27]
D12†
TDM_CLKo[11]
TDM_CLKiP
D13
†
TDM_STi[12]
TDM_FRMi_REF
D14†
TDM_STi[14]
TDM_CLKi_REF
D15†*
TDM_CLKi[16]
†
TDM_CLKo[19]
TDM_CLKo[1]
D16
TDM_STo[18]
TDM_STo[20]
TDM_STi[18]
C5
TDM_STi[3]
D17*
TDM_CLKi[20]
C6
TDM_CLKo[2]
D18*
TDM_CLKi[6]
D19
*
TDM_CLKi[7]
D20*
TDM_STo[27]
TDM_CLKo[9]
D21*
TDM_STo[25]
TDM_STo[9]
D22
*
TDM_CLKi[26]
TDM_STi[9]
D23*
TDM_CLKo[28]
TDM_STi[11]
D24*
TDM_CLKi[29]
‡
TDM_STi[20]
C7
TDM_STo[21]
C8‡
TDM_STi[21]
C9†
†
TDM_CLKo[24]
C10
TDM_CLKo[25]
C11†
GND
C12†
†
TDM_CLKo[22]
*
TDM_STi[29]
TDM_FRMo_REF
C13
TDM_CLKi[13]
D25
TDM_STo[0]
C14†
TDM_CLKo[14]
D26*
TDM_STi[31]
TDM_STi[2]
C15*
TDM_CLKo[16]
E1
RAM_DATA[10]
TDM_STi[16]
E2
RAM_DATA[9]
TDM_CLKo[17]
E3
RAM_DATA[5]
RAM_DATA[4]
*
TDM_CLKi[3]
C16
TDM_STi[4]
C17*
TDM_CLKo[6]
C18*
TDM_STi[19]
E4
TDM_STo[6]
C19
*
TDM_CLKo[21]
E5
RAM_DATA[2]
TDM_CLKo[8]
C20*
TDM_CLKi[21]
E6
TDM_CLKo_REF
TDM_CLKi[9]
C21*
TDM_CLKi[24]
E7
TDM_CLKi[0]
‡
TDM_CLKo[4]
TDM_STo[10]
C22
*
TDM_STi[22]
E8
TDM_STi[10]
C23*
TDM_STo[26]
E9
18
Zarlink Semiconductor Inc.
TDM_STi[1]
ZL50110/11/12/14
Data Sheet
Ball
Number
Signal Name
Ball
Number
Signal Name
Ball
Number
Signal Name
E10‡
TDM_CLKi[4]
F22*
TDM_CLKi[31]
J12
VDD_IO
TDM_STo[8]
F23
*
TDM_CLKo[29]
J13
VDD_IO
TDM_CLKi[8]
F24*
TDM_STo[28]
J14
VDD_IO
TDM_CLKo[12]
F25*
TDM_CLKo[31]
J15
VDD_IO
M1_LINKUP_LED
J16
VDD_IO
†
E11
E12†
E13†
†
†
E14
TDM_STo[15]
F26
E15*
TDM_CLKi[17]
G1
RAM_DATA[21]
J17
VDD_IO
E16*
TDM_CLKi[19]
G2
RAM_DATA[18]
J18
VDD_IO
*
M3_RXDV
*
E17
TDM_STo[23]
G3
RAM_DATA[16]
J21
E18*
TDM_STi[23]
G4
RAM_DATA[14]
J22*
M3_RXD[3]
E19*
TDM_CLKi[25]
G5
RAM_DATA[11]
J23*
M3_RXD[2]
RAM_DATA[8]
J24
*
M3_RXD[1]
TDM_STo[31]
J25*
M3_RXD[0]
*
*
E20
E21*
TDM_STi[26]
G6
TDM_CLKi[28]
G21*
*
GND
G22
TDM_STo[30]
J26
*
E23
TDM_CLKo[30]
G23
M1/2_LINKUP_LED
K1
RAM_PARITY[1]
E24*
E22
M3_COL
TDM_CLKi[30]
G24
M0/3_LINKUP_LED
K2
RAM_PARITY[0]
*
E25
TDM_STi[30]
G25
M1_GIGABIT_LED
K3
RAM_DATA[31]
E26†*
TDM_STo[29]
G26
M_MDIO
K4
RAM_DATA[30]
F1
RAM_DATA[15]
H1
RAM_DATA[25]
K5
GND
F2
RAM_DATA[13]
H2
RAM_DATA[24]
K6
VDD_CORE
F3
RAM_DATA[12]
H3
RAM_DATA[23]
K9
VDD_IO
F4
RAM_DATA[6]
H4
RAM_DATA[19]
K18
VDD_IO
F5
RAM_DATA[7]
H5
RAM_DATA[17]
K21
VDD_CORE
F6
GND
H6
VDD_CORE
K22
GND
VDD_CORE
K23*
M3_TXD[3]
M0_GIGABIT_LED
*
K24
M3_TXEN
M_MDC
K25*
M3_TXER
M3_RXCLK
F7
VDD_CORE
F8
TDM_STo[2]
H21
H22
TDM_CLKo[0]
H23
TDM_CLKi[2]
H24*
M3_CRS
K26*
TDM_CLKo[5]
H25
*
M3_TXCLK
L1
RAM_PARITY[7]
F12
VDD_CORE
H26*
M3_RXER
L2
RAM_PARITY[6]
F13†
TDM_STo[11]
J1
RAM_DATA[29]
L3
RAM_PARITY[5]
TDM_CLKi[14]
J2
RAM_DATA[28]
L4
RAM_PARITY[4]
F9
F10
F11
‡
F14
†
VDD_CORE
J3
RAM_DATA[27]
L5
RAM_PARITY[3]
F16*
F15
TDM_STo[17]
J4
RAM_DATA[26]
L6
RAM_PARITY[2]
*
TDM_CLKi[22]
J5
RAM_DATA[22]
L9
VDD_IO
F18*
TDM_STi[25]
J6
RAM_DATA[20]
L11
GND
F19*
TDM_CLKi[23]
J9
VDD_IO
L12
GND
F20
VDD_CORE
J10
VDD_IO
L13
GND
F21
GND
J11
VDD_IO
L14
GND
F17
19
Zarlink Semiconductor Inc.
ZL50110/11/12/14
Data Sheet
Ball
Number
Signal Name
Ball
Number
Signal Name
Ball
Number
Signal Name
L15
GND
N13
GND
R11
GND
L16
GND
N14
GND
R12
GND
L18
VDD_IO
N15
GND
R13
GND
L21
M1_RXER
N16
GND
R14
GND
L22
M1_TXCLK
N18
VDD_IO
R15
GND
L23
M1_CRS
N21
M1_GTX_CLK
R16
GND
L24*
M3_TXD[0]
N22
GND
R18
VDD_IO
*
M3_TXD[1]
N23
M1_TXER
R21
M1_TXD[0]
L26*
M3_TXD[2]
N24
M1_RXD[2]
R22
M1_TXD[3]
M1
RAM_ADDR[5]
N25
M1_RXD[3]
R23
M1_TXD[5]
M2
RAM_ADDR[4]
N26
GND
R24
M1_TXD[7]
M3
RAM_ADDR[2]
P1
RAM_ADDR[9]
R25
M1_COL
M4
RAM_ADDR[3]
P2
RAM_ADDR[10]
R26
M1_RXD[1]
M5
RAM_ADDR[0]
P3
RAM_ADDR[11]
T1
RAM_ADDR[17]
M6
RAM_ADDR[1]
P4
RAM_ADDR[13]
T2
RAM_ADDR[18]
M9
VDD_IO
P5
RAM_ADDR[16]
T3
RAM_BW_B
M11
GND
P6
GND
T4
IC_GND
M12
GND
P9
VDD_IO
T5
GND
M13
GND
P11
GND
T6
A1VDD
M14
GND
P12
GND
T9
VDD_IO
M15
GND
P13
GND
T11
GND
M16
GND
P14
GND
T12
GND
M18
VDD_IO
P15
GND
T13
GND
M21
VDD_CORE
P16
GND
T14
GND
M22
M1_REFCLK
P18
VDD_IO
T15
GND
M23
M1_RXCLK
P21
M1_TXD[2]
T16
GND
M24
M1_RXD[5]
P22
M1_TXD[6]
T18
VDD_IO
M25
M1_RXD[7]
P23
M1_TXEN
T21
VDD_CORE
M26
M1_RXDV
P24
GND
T22
M1_TXD[1]
N1
GND
P25
M1_RXD[4]
T23
M1_TXD[4]
N2
RAM_ADDR[6]
P26
M1_RXD[6]
T24
GND
N3
RAM_ADDR[7]
R1
RAM_ADDR[12]
T25
M1_RBC1
N4
RAM_ADDR[8]
R2
RAM_ADDR[14]
T26
M1_RXD[0]
N5
GND
R3
RAM_ADDR[15]
U1
PLL_PRI
N6
VDD_CORE
R4
RAM_ADDR[19]
U2
RAM_BW_A
N9
VDD_IO
R5
IC_GND
U3
RAM_BW_C
N11
GND
R6
IC
U4
RAM_RW
N12
GND
R9
VDD_IO
U5
SYSTEM_DEBUG
L25
20
Zarlink Semiconductor Inc.
ZL50110/11/12/14
Data Sheet
Ball
Number
Signal Name
Ball
Number
Signal Name
Ball
Number
Signal Name
U6
SYSTEM_CLK
W22
M0_TXD[5]
AA22
M0_TXD[0]
U9
VDD_IO
W23
M0_TXD[6]
AA23
M0_TXD[3]
U18
VDD_IO
W24
M0_RXD[6]
AA24
M0_REFCLK
U21
M0_GTX_CLK
W25
M0_RXD[7]
AA25
M0_RBC1
U22
M0_RXD[2]
W26
M0_RXD[3]
AA26
M0_RXD[0]
U23
M0_RXD[5]
Y1
RAM_BW_H
AB1
GPIO[5]
U24
M0_TXCLK
Y2
GPIO[4]
AB2
GPIO[11]
U25
M0_CRS
Y3
GPIO[6]
AB3
GPIO[14]
U26
M1_RBC0
Y4
GPIO[10]
AB4
RAM_DATA[38]
V1
PLL_SEC
Y5
RAM_DATA[32]
AB5
RAM_DATA[43]
V2
RAM_BW_D
Y6
VDD_CORE
AB6
RAM_DATA[44]
V3
RAM_BW_F
Y21
VDD_CORE
AB7
RAM_DATA[51]
V4
SYSTEM_RST
Y22
M0_TXD[1]
AB8
RAM_DATA[60]
V5
GPIO[2]
Y23
M0_TXD[4]
AB9
TEST_MODE[1]
V6
VDD_CORE
Y24
M0_RBC0
AB10
GND
V9
VDD_IO
Y25
M0_COL
AB11
CPU_ADDR[6]
V10
VDD_IO
Y26
M0_RXD[1]
AB12
CPU_ADDR[14]
V11
VDD_IO
AA1
GPIO[1]
AB13
CPU_ADDR[23]
V12
VDD_IO
AA2
GPIO[7]
AB14
CPU_TA
V13
VDD_IO
AA3
GPIO[8]
AB15
CPU_DATA[1]
V14
VDD_IO
AA4
GPIO[15]
AB16
CPU_DATA[7]
V15
VDD_IO
AA5
RAM_DATA[39]
AB17
CPU_DATA[12]
V16
VDD_IO
AA6
GND
AB18
CPU_DATA[22]
V17
VDD_IO
AA7
RAM_DATA[45]
AB19
CPU_DATA[30]
RAM_DATA[52]
AB20
†
M2_RXD[1]
M0_RXCLK
V18
VDD_IO
AA8
V21
M0_TXD[7]
AA9
VDD_CORE
AB21†
V22
M0_TXER
AA10
JTAG_TMS
AB22
V23
M0_TXEN
AA11
M2_TXER
CPU_ADDR[2]
AB23
†
M0_LINKUP_LED
M2_ACTIVE_LED
V24
M0_RXD[4]
AA12
CPU_ADDR[12]
AB24†
V25
M0_RXDV
AA13
VDD_CORE
AB25
M1_ACTIVE_LED
VDD_CORE
AB26
*
M3_ACTIVE_LED
V26
M0_RXER
AA14
W1
RAM_BW_E
AA15
CPU_DATA[8]
AC1
GPIO[12]
W2
RAM_BW_G
AA16
CPU_DATA[15]
AC2
GPIO[13]
W3
GPIO[0]
AA17
CPU_DATA[23]
AC3
RAM_DATA[37]
W4
GPIO[3]
AA18
VDD_CORE
AC4
RAM_DATA[42]
GPIO[9]
AA19†
M2_RXCLK
AC5
RAM_DATA[46]
M2_RXDV
AC6
RAM_DATA[49]
GND
AC7
RAM_DATA[59]
W5
†
W6
RAM_DATA[33]
AA20
W21
M0_TXD[2]
AA21
21
Zarlink Semiconductor Inc.
ZL50110/11/12/14
Data Sheet
Ball
Number
Signal Name
Ball
Number
Signal Name
Ball
Number
Signal Name
AC8
TEST_MODE[0]
AD20
CPU_DATA[20]
AF6
TEST_MODE[2]
AC9
JTAG_TDO
AD21
CPU_DATA[24]
AF7
JTAG_TDI
AC10
CPU_ADDR[4]
AD22
CPU_DATA[29]
AF8
IC_GND
CPU_ADDR[9]
AD23†
M2_TXD[2]
AF9
CPU_ADDR[5]
CPU_ADDR[16]
†
AD24
M2_RXD[0]
AF10
CPU_ADDR[10]
CPU_ADDR[22]
AD25†
M2_RXD[3]
AF11
CPU_ADDR[15]
AC14
CPU_CLK
AD26†
M2_TXCLK
AF12
CPU_ADDR[19]
AC15
CPU_DREQ0
AE1
RAM_DATA[35]
AF13
GND
AC16
IC
AE2
RAM_DATA[40]
AF14
CPU_CS
AC17
CPU_DATA[10]
AE3
RAM_DATA[48]
AF15
CPU_SDACK1
AC18
CPU_DATA[16]
AE4
RAM_DATA[54]
AF16
IC_VDD_IO
AC19
CPU_DATA[21]
AE5
RAM_DATA[57]
AF17
CPU_IREQ0
AC20
CPU_DATA[27]
AE6
RAM_DATA[62]
AF18
CPU_DATA[0]
AC21†
M2_TXD[1]
AE7
JTAG_TRST
AF19
CPU_DATA[5]
AC22†
AC11
AC12
AC13
M2_TXEN
AE8
IC_GND
AF20
CPU_DATA[2]
†
AC23
M2_RXD[2]
AE9
CPU_ADDR[3]
AF21
CPU_DATA[11]
AC24†
M2_RXER
AE10
CPU_ADDR[8]
AF22
CPU_DATA[17]
AC25†
M2_CRS
AE11
CPU_ADDR[13]
AF23
CPU_DATA[19]
AC26
M0_ACTIVE_LED
AE12
CPU_ADDR[18]
AF24
CPU_DATA[26]
AD1
RAM_DATA[34]
AE13
CPU_ADDR[20]
AF25
CPU_DATA[31]
AD2
RAM_DATA[36]
AE14
CPU_OE
AF26
GND
AD3
RAM_DATA[41]
AE15
CPU_TS_ALE
AD4
RAM_DATA[47]
AE16
CPU_DREQ1
AD5
RAM_DATA[53]
AE17
IC
AD6
RAM_DATA[58]
AE18
CPU_DATA[4]
AD7
RAM_DATA[63]
AE19
CPU_DATA[9]
AD8
JTAG_TCK
AE20
CPU_DATA[13]
AD9
IC_GND
AE21
CPU_DATA[18]
AD10
CPU_ADDR[7]
AE22
CPU_DATA[25]
AD11
CPU_ADDR[11]
AE23
CPU_DATA[28]
CPU_ADDR[17]
AE24
†
M2_TXD[0]
AD13
CPU_ADDR[21]
AE25†
M2_TXD[3]
AD14
CPU_WE
AE26†
M2_COL
AD15
CPU_SDACK2
AF1
GND
AD16
CPU_IREQ1
AF2
RAM_DATA[50]
AD17
CPU_DATA[3]
AF3
RAM_DATA[55]
AD18
CPU_DATA[6]
AF4
RAM_DATA[56]
AD19
CPU_DATA[14]
AF5
RAM_DATA[61]
AD12
22
Zarlink Semiconductor Inc.
* Not connected on ZL50112, ZL50110 and
ZL50114 - leave open circuit.
† Not Connected on ZL50110 and ZL50114 leave open circuit.
‡ Not Connected on ZL50114 - leave open
circuit.
N/C - Not Connected - leave open circuit.
* Internally Connected on ZL50112 - leave
open circuit.
IC - Internally Connected - leave open
circuit.
IC_GND - tie to ground
IC_VDD_IO - tie to VDD_IO
ZL50110/11/12/14
3.0
Data Sheet
External Interface Description
The following key applies to all tables:
3.1
I
Input
O
Output
D
Internal 100 kΩ pull-down resistor present
U
Internal 100 kΩ pull-up resistor present
T
Tri-state Output
TDM Interface
All TDM Interface signals are 5 V tolerant.
All TDM Interface inputs (including data, clock and frame pulse) have internal pull-down resistors so they can be
safely left unconnected if not used.
3.1.1
ZL50111 Variant TDM Stream Connection
Signal
TDM_STi[31:0]
I/O
ID
Package Balls
[31]
[30]
[29]
[28]
[27]
[26]
[25]
[24]
[23]
[22]
[21]
[20]
[19]
[18]
[17]
[16]
D26
E25
D25
C26
C25
E20
F18
B25
E18
C22
A23
A21
C18
A19
B17
C16
[15]
[14]
[13]
[12]
[11]
[10]
[9]
[8]
[7]
[6]
[5]
[4]
[3]
[2]
[1]
[0]
B16
D14
B14
D13
C12
B11
C11
D11
A8
A6
D8
B5
C5
B3
E9
D5
Description
TDM port serial data input streams. For
different standards these pins are given
different identities:
ST-BUS: TDM_STi[31:0]
H.110: TDM_D[31:0]
H-MVIP: TDM_HDS[31:0]
Triggered on rising edge or falling edge
depending on standard. At 8.192 Mbps only
streams [7:0] are used, with 128 channels
per stream. Streams [7:0] are used for J2,
and streams [1:0] are used for T3 and E3.
Table 2 - TDM Interface ZL50111 Stream Pin Definition
23
Zarlink Semiconductor Inc.
ZL50110/11/12/14
Signal
I/O
Package Balls
Data Sheet
Description
TDM_STo[31:0]
OT
[31]
[30]
[29]
[28]
[27]
[26]
[25]
[24]
[23]
[22]
[21]
[20]
[19]
[18]
[17]
[16]
G21
G22
E26
F24
D20
C23
D21
B23
E17
B21
A22
D18
B20
D17
F16
A17
[15]
[14]
[13]
[12]
[11]
[10]
[9]
[8]
[7]
[6]
[5]
[4]
[3]
[2]
[1]
[0]
E14
A15
A14
B13
F13
B10
C10
E11
A7
B7
A5
A4
D7
F8
A2
B2
TDM port serial data output streams. For
different standards these pins are given
different identities:
ST-BUS: TDM_STo[31:0]
H.110:
TDM_D[31:0]
H-MVIP: TDM_HDS[31:0]
Triggered on rising edge or falling edge
depending on standard. At 8.192 Mbps only
streams [7:0] are used, with 128 channels
per stream. Streams [7:0] are used for J2,
and streams [1:0] are used for T3 and E3.
TDM_CLKi[31:0]
ID
[31]
[30]
[29]
[28]
[27]
[26]
[25]
[24]
[23]
[22]
[21]
[20]
[19]
[18]
[17]
[16]
F22
E24
D24
E21
C24
D22
E19
C21
F19
F17
C20
A20
E16
B18
E15
D15
[15]
[14]
[13]
[12]
[11]
[10]
[9]
[8]
[7]
[6]
[5]
[4]
[3]
[2]
[1]
[0]
B15
F14
C13
B12
A11
A10
B9
E12
C8
C7
D9
E10
B4
F10
D6
E7
TDM port clock inputs. Programmable as
active high or low. Can accept frequencies
of 1.544 MHz, 2.048 MHz, 4.096 MHz,
6.312 MHz, 8.192 MHz, 16.384 MHz,
34.368 MHz or 44.736 MHz depending on
standard used. At 8.192 Mbps only streams
[7:0] are used. Streams [7:0] are used for
J2, and streams [1:0] are used for T3 and
E3.
Table 2 - TDM Interface ZL50111 Stream Pin Definition (continued)
24
Zarlink Semiconductor Inc.
ZL50110/11/12/14
Signal
TDM_CLKo[31:0]
I/O
O
Package Balls
[31]
[30]
[29]
[28]
[27]
[26]
[25]
[24]
[23]
[22]
[21]
[20]
[19]
[18]
[17]
[16]
F25
E23
F23
D23
B26
B24
A25
A24
B22
D19
C19
B19
D16
A18
C17
C15
[15]
[14]
[13]
[12]
[11]
[10]
[9]
[8]
[7]
[6]
[5]
[4]
[3]
[2]
[1]
[0]
A16
C14
A12
E13
D12
A9
C9
B8
D10
B6
F11
E8
A3
C6
C4
F9
Data Sheet
Description
TDM port clock outputs. Will generate
1.544 MHz, 2.048 MHz, 4.096 MHz,
6.312 MHz, 8.192 MHz, 16.384 MHz,
34.368 MHz or 44.736 MHz depending on
standard used. At 8.192 Mbps only streams
[7:0] are used. Streams [7:0] are used for
J2, and streams [1:0] are used for T3 and
E3.
Table 2 - TDM Interface ZL50111 Stream Pin Definition (continued)
Note: Speed modes:
2.048 Mbps - all 32 streams active (bits [31:0]), with 32 channels per stream - 1024 total channels.
8.192 Mbps - 8 streams active (bits [7:0]), with 128 channels per stream - 1024 total channels.
J2 - 8 streams active (bits [7:0]), with 98 channels per stream - 784 total channels.
E3 - 2 streams active (bits [1:0]), with 537 channels per stream - 1074 total channels.
T3 - 2 streams active (bits [1:0]), with 699 channels per stream - 1398 total channels.
Note: All TDM Interface inputs (including data, clock and frame pulse) have internal pull-down resistors so they can be safely left
unconnected if not used.
3.1.2
ZL50112 Variant TDM Stream Connection
Signal
TDM_STi[15:0]
I/O
ID
Package Balls
[15]
[14]
[13]
[12]
[11]
[10]
[9]
[8]
[7]
[6]
[5]
[4]
[3]
[2]
[1]
[0]
B16
D14
B14
D13
C12
B11
C11
D11
A8
A6
D8
B5
C5
B3
E9
D5
Description
TDM port serial data input streams. For
different standards these pins are given
different identities:
ST-BUS: TDM_STi[15:0]
H.110: TDM_D[15:0]
H-MVIP: TDM_HDS[15:0]
Triggered on rising edge or falling edge
depending on standard. At 8.192 Mbps only
streams [3:0] are used, with 128 channels
per stream. Streams [3:0] are used for J2.
Table 3 - TDM Interface ZL50112 Stream Pin Definition
25
Zarlink Semiconductor Inc.
ZL50110/11/12/14
Signal
I/O
Package Balls
Data Sheet
Description
TDM_STo[15:0]
OT
[15]
[14]
[13]
[12]
[11]
[10]
[9]
[8]
[7]
[6]
[5]
[4]
[3]
[2]
[1]
[0]
E14
A15
A14
B13
F13
B10
C10
E11
A7
B7
A5
A4
D7
F8
A2
B2
TDM port serial data output streams. For
different standards these pins are given
different identities:
ST-BUS: TDM_STo[15:0]
H.110:
TDM_D[15:0]
H-MVIP: TDM_HDS[15:0]
Triggered on rising edge or falling edge
depending on standard. At 8.192 Mbps only
streams [3:0] are used, with 128 channels
per stream. Streams [3:0] are used for J2.
TDM_CLKi[15:0]
ID
[15]
[14]
[13]
[12]
[11]
[10]
[9]
[8]
[7]
[6]
[5]
[4]
[3]
[2]
[1]
[0]
B15
F14
C13
B12
A11
A10
B9
E12
C8
C7
D9
E10
B4
F10
D6
E7
TDM port clock inputs. Programmable as
active high or low. Can accept frequencies
of 1.544 MHz, 2.048 MHz, 4.096 MHz,
6.312 MHz, 8.192 MHz, 16.384 MHz,
34.368 MHz or 44.736 MHz depending on
standard used. At 8.192 Mbps only streams
[3:0] are used. Streams [3:0] are used for
J2.
Table 3 - TDM Interface ZL50112 Stream Pin Definition (continued)
26
Zarlink Semiconductor Inc.
ZL50110/11/12/14
Signal
TDM_CLKo[15:0]
I/O
O
Package Balls
[15]
[14]
[13]
[12]
[11]
[10]
[9]
[8]
[7]
[6]
[5]
[4]
[3]
[2]
[1]
[0]
A16
C14
A12
E13
D12
A9
C9
B8
D10
B6
F11
E8
A3
C6
C4
F9
Data Sheet
Description
TDM port clock outputs. Will generate
1.544 MHz, 2.048 MHz, 4.096 MHz,
6.312 MHz, 8.192 MHz, 16.384 MHz
depending on standard used. At
8.192 Mbps only streams [3:0] are used.
Streams [3:0] are used for J2.
Table 3 - TDM Interface ZL50112 Stream Pin Definition (continued)
Note: Speed modes:
2.048 Mbps - all 16 streams active (bits [15:0]), with 32 channels per stream - 512 total channels.
8.192 Mbps - 4 streams active (bits [3:0]), with 128 channels per stream - 512 total channels.
J2 - 4 streams active (bits [3:0]), with 98 channels per stream - 392 total channels.
Note: All TDM Interface inputs (including data, clock and frame pulse) have internal pull-down resistors so they can be safely left
unconnected if not used.
27
Zarlink Semiconductor Inc.
ZL50110/11/12/14
3.1.3
Data Sheet
ZL50110 Variant TDM Stream Connection
Signal
I/O
Package Balls
Description
TDM_STi[7:0]
ID
[7]
[6]
[5]
[4]
[3]
[2]
[1]
[0]
A8
A6
D8
B5
C5
B3
E9
D5
TDM port serial data input streams. For
different standards these pins are given
different identities:
ST-BUS: TDM_STi[7:0]
H.110: TDM_D[7:0]
H-MVIP: TDM_HDS[7:0]
Triggered on rising edge or falling edge
depending on standard. At 8.192 Mbps only
streams [1:0] are used. Streams [1:0] are
used for J2.
TDM_STo[7:0]
OT
[7]
[6]
[5]
[4]
[3]
[2]
[1]
[0]
A7
B7
A5
A4
D7
F8
A2
B2
TDM port serial data output streams. For
different standards these pins are given
different identities:
ST-BUS: TDM_STo[7:0]
H.110:
TDM_D[7:0]
H-MVIP: TDM_HDS[7:0]
Triggered on rising edge or falling edge
depending on standard. At 8.192 Mbps only
streams [1:0] are used. Streams [1:0] are
used for J2.
TDM_CLKi[7:0]
ID
[7]
[6]
[5]
[4]
[3]
[2]
[1]
[0]
C8
C7
D9
E10
B4
F10
D6
E7
TDM port clock inputs
programmable as active high or low. Can
accept frequencies of 1.544 MHz,
2.048 MHz, 4.096 MHz, 8.192 MHz,
6.312 MHz or 16.384 MHz depending on
standard used. At 8.192 Mbps only
streams [1:0] are used. Streams [1:0] are
used for J2.
TDM_CLKo[7:0]
O
[7]
[6]
[5]
[4]
[3]
[2]
[1]
[0]
D10
B6
F11
E8
A3
C6
C4
F9
TDM port clock outputs. Will generate
1.544 MHz, 2.048 MHz, 4.096 MHz,
6.312 MHz, 8.192 MHz or 16.384 MHz
depending on standard used. At
8.192 Mbps only streams [1:0] are used.
Streams [1:0] are used for J2.
Table 4 - TDM Interface ZL50110 Stream Pin Definition
Note: Speed modes:
2.048 Mbps - all 8 streams active (bits [7:0]), with 32 channels per stream - 256 total channels.
8.192 Mbps - 2 streams active (bits [1:0]), with 128 channels per stream - 256 total channels.
J2 - 2 streams active (bits [1:0]), with 98 channels per stream - 196 total channels.
Note: All TDM Interface inputs (including data, clock and frame pulse) have internal pull-down resistors so they can be safely left
unconnected if not used.
28
Zarlink Semiconductor Inc.
ZL50110/11/12/14
3.1.4
Data Sheet
ZL50114 Variant TDM Stream Connection
Signal
I/O
Package Balls
Description
TDM_STi[3:0]
ID
[3]
[2]
[1]
[0]
C5
B3
E9
D5
TDM port serial data input streams. For
different standards these pins are given
different identities:
ST-BUS: TDM_STi[3:0]
H.110: TDM_D[3:0]
H-MVIP: TDM_HDS[3:0]
Triggered on rising edge or falling edge
depending on standard. At 8.192 Mbps
only streams [1:0] are used. Streams [1:0]
are used for J2.
TDM_STo[3:0]
OT
[3]
[2]
[1]
[0]
D7
F8
A2
B2
TDM port serial data output streams. For
different standards these pins are given
different identities:
ST-BUS: TDM_STo[3:0]
H.110:
TDM_D[3:0]
H-MVIP: TDM_HDS[3:0]
Triggered on rising edge or falling edge
depending on standard. At 8.192 Mbps only
streams [1:0] are used. Streams [1:0] are
used for J2.
TDM_CLKi[3:0]
ID
[3]
[2]
[1]
[0]
B4
F10
D6
E7
TDM port clock inputs
programmable as active high or low. Can
accept frequencies of 1.544 MHz,
2.048 MHz, 4.096 MHz, 8.192 MHz,
6.312 MHz or 16.384 MHz depending on
standard used. At 8.192 Mbps only
streams [1:0] are used. Streams [1:0] are
used for J2.
TDM_CLKo[3:0]
O
[3]
[2]
[1]
[0]
A3
C6
C4
F9
TDM port clock outputs. Will generate
1.544 MHz, 2.048 MHz, 4.096 MHz,
6.312 MHz, 8.192 MHz or 16.384 MHz
depending on standard used. At 8.192 Mbps
only streams [1:0] are used. Streams [1:0]
are used for J2.
Table 5 - TDM Interface ZL50114 Stream Pin Definition
Note: Speed modes:
2.048 Mbps - all 4 streams active (bits [3:0]), with 32 channels per stream - 128 total channels.
8.192 Mbps - 2 streams active (bits [1:0]), with 128 channels per stream - 256 total channels.
J2 - 2 streams active (bits [1:0]), with 98 channels per stream - 196 total channels.
Note: All TDM Interface inputs (including data, clock and frame pulse) have internal pull-down resistors so they can be safely left
unconnected if not used.
29
Zarlink Semiconductor Inc.
ZL50110/11/12/14
3.1.5
Data Sheet
TDM Signals Common to ZL50110, ZL50111, ZL50112 and ZL50114
Signal
I/O
Package Balls
Description
TDM_CLKi_REF
ID
C3
TDM port reference clock input for
backplane operation
TDM_CLKo_REF
O
E6
TDM port reference clock output for
backplane operation
TDM_FRMi_REF
ID
C2
TDM port reference frame input. For
different standards this pin is given a
different identity:
ST-BUS: TDM_F0i
H.110:
TDM_FRAME
H-MVIP: TDM_F0
Signal is normally active low, but can be
active high depending on standard.
Indicates the start of a TDM frame by
pulsing every 125 µs. Normally will straddle
rising edge or falling edge of clock pulse,
depending on standard and clock frequency.
TDM_FRMo_REF
O
B1
TDM port reference frame output. For
different standards this pin is given a
different identity:
ST-BUS: TDM_F0o
H.110:
TDM_FRAME
H-MVIP: TDM_F0
Signal is normally active low, but can be
active high depending on standard.
Indicates the start of a TDM frame by
pulsing every 125 µs. Normally will straddle
rising edge or falling edge of clock pulse,
depending on standard and clock frequency.
Table 6 - TDM Interface Common Pin Definition
30
Zarlink Semiconductor Inc.
ZL50110/11/12/14
3.2
Data Sheet
PAC Interface
All PAC Interface signals are 5 V tolerant
All PAC Interface outputs are high impedance while System Reset is LOW.
Signal
I/O
Package Balls
Description
TDM_CLKiP
ID
C1
Primary reference clock input. Should be
driven by external clock source to provide
locking reference to internal / optional
external DPLL in TDM master mode. Also
provides PRS clock for RTP timestamps in
synchronous modes.
Acceptable frequency range: 8 kHz 34.368 MHz (generally should be between
10 MHz and 25 MHz as per ITU-T Y.1413.
TDM_CLKiS
ID
D3
Secondary reference clock input. Backup
external reference for automatic switch-over
in case of failure of TDM_CLKiP source.
PLL_PRI
OT
U1
Primary reference output to optional
external DPLL.
Multiplexed & frequency divided reference
output for support of optional external DPLL.
Expected frequency range:
8 kHz - 16.384 MHz.
PLL_SEC
OT
V1
Secondary reference output to optional
external DPLL Multiplexed & frequency
divided reference output for support of
optional external DPLL.
Expected frequency range:
8 kHz - 16.384 MHz.
Table 7 - PAC Interface Package Ball Definition
31
Zarlink Semiconductor Inc.
ZL50110/11/12/14
3.3
Data Sheet
Packet Interfaces
For the ZL50111 and ZL50112 variants the packet interface is capable of either 3 MII interfaces, 2 redundant GMII
interfaces or 2 redundant TBI (1000 Mbps) interfaces. The TBI interface is a PCS interface supported by an
integrated 1000BASE-X PCS module. The ZL50110 and ZL50114 variants have either 2 MII interfaces, 2 redundant
GMII interfaces or 2 redundant TBI (1000 Mbps) interfaces. When the packet interface is programmed for PCS/TBI
mode, by default the hardware will not enable auto-negotiation. The TBI auto-negotiation must be done by
application software. Ports 2 and 3 are not available on the ZL50110 and ZL50114 devices.
NOTE: In GMII/TBI mode only 1 GMAC port may be used to receive data. The second GMAC port is for
redundancy purposes only.
Data for all three types of packet switching is based on Specification IEEE Std. 802.3 - 2000. The table below
highlights the valid Ethernet interface combinations:
MII Port 0
MII Port 1
MII Port 2*
MII Port 3**
GE
GE***
--
--
GE
--
FE
--
GE
--
--
FE
FE
FE
--
--
FE
FE
FE
--
FE
FE
--
FE
Note 1:
*ZL50111/112 only
Note 2:
**ZL50111 only
Note 3:
***Standby only
Note: Port 2 and Port 3 can not be used to receive data simultaneously, they are mutually exclusive for packet
reception. They may both be used for packet transmission if required.
The ZL50110/11/12/14 will not take action when receiving a PAUSE frame. It will not pause the transmission of
traffic. It is normally not required to stop CESoP traffic because it is generally constant bit rate and time sensitive. If
necessary, the limiting of egress non-CESoP traffic may be done external to the ZL50110/11/12/14 (e.g. in an
Ethernet switch).
Table 8 maps the signal pins used in the MII interface to those used in the GMII and TBI interface. Table 9 shows
MII Management Interface Package Ball Definition. Table 10, Table 11, Table 12, and Table 13 show respectively
the MII Port 0, Port 1, Port 2 and Port 3 Interface Package Ball Definition.
All Packet Interface signals are 5 V tolerant, and all outputs are high impedance while System Reset is LOW.
MII
GMII
TBI (PCS)
Mn_LINKUP_LED
Mn_LINKUP_LED
Mn_LINKUP_LED
Mn_ACTIVE_LED
Mn_ACTIVE_LED
Mn_ACTIVE_LED
-
Mn_GIGABIT_LED
Mn_GIGABIT_LED
-
Mn_REFCLK
Mn_REFCLK
Mn_RXCLK
Mn_RXCLK
Mn_RBC0
Table 8 - Packet Interface Signal Mapping - MII to GMII/TBI
32
Zarlink Semiconductor Inc.
ZL50110/11/12/14
Data Sheet
MII
GMII
TBI (PCS)
Mn_COL
Mn_COL
Mn_RBC1
Mn_RXD[3:0]
Mn_RXD[7:0]
Mn_RXD[7:0]
Mn_RXDV
Mn_RXDV
Mn_RXD[8]
Mn_RXER
Mn_RXER
Mn_RXD[9]
Mn_CRS
Mn_CRS
Mn_Signal_Detect
Mn_TXCLK
-
-
Mn_TXD[3:0]
Mn_TXD[7:0]
Mn_TXD[7:0]
Mn_TXEN
Mn_TXEN
Mn_TXD[8]
Mn_TXER
Mn_TXER
Mn_TXD[9]
-
Mn_GTX_CLK
Mn_GTX_CLK
Table 8 - Packet Interface Signal Mapping - MII to GMII/TBI
Note: Mn can be either M0, M1, M2, or M3 for ZL50111 and ZL50112 variants; and M0 or M1 for ZL50110 variant.
Signal
I/O
Package Balls
Description
M_MDC
O
H23
MII management data clock. Common for all
four MII ports. It has a minimum period of
400 ns (maximum freq. 2.5 MHz), and is
independent of the TXCLK and RXCLK.
M_MDIO
ID/
OT
G26
MII management data I/O. Common for all
four MII ports at up to 2.5 MHz. It is
bi-directional between the ZL50110/11/12/14
and the Ethernet station management entity.
Data is passed synchronously with respect
to M_MDC.
Table 9 - MII Management Interface Package Ball Definition
33
Zarlink Semiconductor Inc.
ZL50110/11/12/14
Data Sheet
MII Port 0
Signal
I/O
Package Balls
Description
M0_LINKUP_LED
O
G24 on ZL50110/4
AB23 on ZL50111/2
LED drive for MAC 0 to indicate port is
linked up.
Logic 0 output = LED on
Logic 1 output = LED off
M0_ACTIVE_LED
O
AC26
LED drive for MAC 0 to indicate port is
transmitting or receiving packet data.
Logic 0 output = LED on
Logic 1 output = LED off
M0_GIGABIT_LED
O
H22
LED drive for MAC 0 to indicate operation at
Gbps
Logic 0 output = LED on
Logic 1 output = LED off
M0_REFCLK
ID
AA24
GMII/TBI - Reference Clock input at
125 MHz. Can be used to lock receive
circuitry (RX) to M0_GTXCLK rather than
recovering the RXCLK (or RBC0 and
RBC1). Useful, for example, in the absence
of valid serial data.
NOTE: In MII mode this pin must be driven
with the same clock as M0_RXCLK.
M0_RXCLK
IU
AB22
GMII/MII - M0_RXCLK.
Accepts the following frequencies:
25.0 MHz
MII 100 Mbps
125.0 MHz
GMII 1 Gbps
M0_RBC0
IU
Y24
TBI - M0_RBC0.
Used as a clock when in TBI mode. Accepts
62.5 MHz, and is 180°C out of phase with
M0_RBC1. Receive data is clocked at
each rising edge of M1_RBC1 and
M1_RBC0, resulting in 125 MHz sample
rate.
M0_RBC1
IU
AA25
TBI - M0_RBC1
Used as a clock when in TBI mode. Accepts
62.5 MHz, and is 180°C out of phase with
M0_RBC0. Receive data is clocked at
each rising edge of M0_RBC1 and
M0_RBC0, resulting in 125 MHz sample
rate.
Table 10 - MII Port 0 Interface Package Ball Definition
34
Zarlink Semiconductor Inc.
ZL50110/11/12/14
Data Sheet
MII Port 0
Signal
I/O
Package Balls
Description
M0_COL
ID
Y25
GMII/MII - M0_COL.
Collision Detection. This signal is
independent of M0_TXCLK and
M0_RXCLK, and is asserted when a
collision is detected on an attempted
transmission. It is active high, and only
specified for half-duplex operation.
M0_RXD[7:0]
IU
[7]
[6]
[5]
[4]
M0_RXDV /
M0_RXD[8]
ID
V25
GMII/MII - M0_RXDV
Receive Data Valid. Active high. This
signal is clocked on the rising edge of
M0_RXCLK. It is asserted when valid data
is on the M0_RXD bus.
TBI - M0_RXD[8]
Receive Data. Clocked on the rising edges
of M0_RBC0 and M0_RBC1.
M0_RXER /
M0_RXD[9]
ID
V26
GMII/MII - M0_RXER
Receive Error. Active high signal indicating
an error has been detected. Normally valid
when M0_RXDV is asserted. Can be used
in conjunction with M0_RXD when
M0_RXDV signal is de-asserted to indicate
a False Carrier.
TBI - M0_RXD[9]
Receive Data. Clocked on the rising edges
of M0_RBC0 and M0_RBC1.
M0_CRS /
M0_Signal_Detect
ID
U25
GMII/MII - M0_CRS
Carrier Sense. This asynchronous signal is
asserted when either the transmission or
reception device is non-idle. It is active
high.
TBI - M0_Signal Detect
Similar function to M0_CRS.
M0_TXCLK
IU
U24
MII only - Transmit Clock
Accepts the following frequencies:
25.0 MHz
MII 100 Mbps
M0_TXD[7:0]
O
[7]
[6]
[5]
[4]
W25
W24
U23
V24
V21
W23
W22
Y23
[3]
[2]
[1]
[0]
[3]
[2]
[1]
[0]
W26
U22
Y26
AA26
AA23
W21
Y22
AA22
Receive Data. Only half the bus (bits [3:0])
are used in MII mode. Clocked on rising
edge of M0_RXCLK (GMII/MII) or the rising
edges of M0_RBC0 and M0_RBC1 (TBI).
Transmit Data. Only half the bus (bits [3:0])
are used in MII mode. Clocked on rising
edge of M0_TXCLK (MII) or the rising edge
of M0_GTXCLK (GMII/TBI).
Table 10 - MII Port 0 Interface Package Ball Definition (continued)
35
Zarlink Semiconductor Inc.
ZL50110/11/12/14
Data Sheet
MII Port 0
Signal
I/O
Package Balls
Description
M0_TXEN /
M0_TXD[8]
O
V23
GMII/MII - M0_TXEN
Transmit Enable. Asserted when the MAC
has data to transmit, synchronously to
M0_TXCLK with the first pre-amble of the
packet to be sent. Remains asserted until
the end of the packet transmission. Active
high.
TBI - M0_TXD[8]
Transmit Data. Clocked on rising edge of
M0_GTXCLK.
M0_TXER /
M0_TXD[9]
O
V22
GMII/MII - M0_TXER
Transmit Error. Transmitted synchronously
with respect to M0_TXCLK, and active high.
When asserted (with M0_TXEN also
asserted) the ZL50110/11/12/14 will
transmit a non-valid symbol, somewhere in
the transmitted frame.
TBI - M0_TXD[9]
Transmit Data. Clocked on rising edge of
M0_GTXCLK.
M0_GTX_CLK
O
U21
GMII/TBI only - Gigabit Transmit Clock
Output of a clock for Gigabit operation at
125 MHz.
Table 10 - MII Port 0 Interface Package Ball Definition (continued)
36
Zarlink Semiconductor Inc.
ZL50110/11/12/14
Data Sheet
MII Port 1
Signal
I/O
Package Balls
Description
M1_LINKUP_LED
O
G23 on ZL50110/4
F26 on ZL50111/2
LED drive for MAC 1 to indicate port is linked
up.
Logic 0 output = LED on
Logic 1 output = LED off
M1_ACTIVE_LED
O
AB25
LED drive for MAC 1 to indicate port is
transmitting or receiving packet data.
Logic 0 output = LED on
Logic 1 output = LED off
M1_GIGABIT_LED
O
G25
LED drive for MAC 1 to indicate operation at
Gbps.
Logic 0 output = LED on
Logic 1 output = LED off
M1_REFCLK
ID
M22
GMII/TBI - Reference Clock input at
125 MHz. Can be used to lock receive
circuitry (RX) to M1_GTXCLK rather than
recovering the RXCLK (or RBC0 and
RBC1). Useful, for example, in the absence
of valid serial data.
NOTE: In MII mode this pin must be driven
with the same clock as M1_RXCLK.
M1_RXCLK
IU
M23
GMII/MII - M1_RXCLK.
Accepts the following frequencies:
25.0 MHz
MII 100 Mbps
125.0 MHz
GMII 1 Gbps
M1_RBC0
IU
U26
TBI - M1_RBC0.
Used as a clock when in TBI mode. Accepts
62.5 MHz and is 180°C out of phase with
M1_RBC1. Receive data is clocked at
each rising edge of M1_RBC1 and
M1_RBC0, resulting in 125 MHz sample
rate.
M1_RBC1
IU
T25
TBI - M1_RBC1
Used as a clock when in TBI mode. Accepts
62.5 MHz, and is 180° out of phase with
M1_RBC0. Receive data is clocked at each
rising edge of M1_RBC1 and M1_RBC0,
resulting in 125 MHz sample rate.
M1_COL
ID
R25
GMII/MII - M1_COL.
Collision Detection. This signal is
independent of M1_TXCLK and
M1_RXCLK, and is asserted when a
collision is detected on an attempted
transmission. It is active high, and only
specified for half-duplex operation.
Table 11 - MII Port 1 Interface Package Ball Definition
37
Zarlink Semiconductor Inc.
ZL50110/11/12/14
Data Sheet
MII Port 1
Signal
I/O
Package Balls
M1_RXD[7:0]
IU
[7]
[6]
[5]
[4]
M1_RXDV /
M1_RXD[8]
ID
M26
GMII/MII - M1_RXDV
Receive Data Valid. Active high. This signal
is clocked on the rising edge of M1_RXCLK.
It is asserted when valid data is on the
M1_RXD bus.
TBI - M1_RXD[8]
Receive Data. Clocked on the rising edges
of M1_RBC0 and M1_RBC1.
M1_RXER /
M1_RXD[9]
ID
L21
GMII/MII - M1_RXER
Receive Error. Active high signal indicating
an error has been detected. Normally valid
when M1_RXDV is asserted. Can be used
in conjunction with M1_RXD when
M1_RXDV signal is de-asserted to indicate
a False Carrier.
TBI - M1_RXD[9]
Receive Data. Clocked on the rising edges
of M1_RBC0 and M1_RBC1.
M1_CRS /
M1_Signal_Detect
ID
L23
GMII/MII - M1_CRS
Carrier Sense. This asynchronous signal is
asserted when either the transmission or
reception device is non-idle. It is active high.
TBI - M1_Signal Detect
Similar function to M1_CRS.
M1_TXCLK
IU
L22
MII only - Transmit Clock
Accepts the following frequencies:
25.0 MHz
MII 100 Mbps
M1_TXD[7:0]
O
[7]
[6]
[5]
[4]
M1_TXEN /
M1_TXD[8]
O
P23
M25
P26
M24
P25
R24
P22
R23
T23
[3]
[2]
[1]
[0]
[3]
[2]
[1]
[0]
N25
N24
R26
T26
R22
P21
T22
R21
Description
Receive Data. Only half the bus (bits [3:0])
are used in MII mode. Clocked on rising
edge of M1_RXCLK (GMII/MII) or the rising
edges of M1_RBC0 and M1_RBC1 (TBI).
Transmit Data. Only half the bus (bits [3:0])
are used in MII mode. Clocked on rising
edge of M1_TXCLK (MII) or the rising edge
of M1_GTXCLK (GMII/TBI).
GMII/MII - M1_TXEN
Transmit Enable. Asserted when the MAC
has data to transmit, synchronously to
M1_TXCLK with the first pre-amble of the
packet to be sent. Remains asserted until
the end of the packet transmission. Active
high.
TBI - M1_TXD[8]
Transmit Data. Clocked on rising edge of
M1_GTXCLK.
Table 11 - MII Port 1 Interface Package Ball Definition (continued)
38
Zarlink Semiconductor Inc.
ZL50110/11/12/14
Data Sheet
MII Port 1
Signal
I/O
Package Balls
Description
M1_TXER /
M1_TXD[9]
O
N23
GMII/MII - M1_TXER
Transmit Error. Transmitted synchronously
with respect to M1_TXCLK, and active high.
When asserted (with M1_TXEN also
asserted) the ZL50110/11/12/14 will transmit
a non-valid symbol, somewhere in the
transmitted frame.
TBI - M1_TXD[9]
Transmit Data. Clocked on rising edge of
M1_GTXCLK.
M1_GTX_CLK
O
N21
GMII/TBI only - Gigabit Transmit Clock
Output of a clock for Gigabit operation at
125 MHz.
Table 11 - MII Port 1 Interface Package Ball Definition (continued)
MII Port 2 - ZL50111 and ZL50112 variants only.
Note: This port must not be used to receive data at the same time as port 3,
they are mutually exclusive.
Signal
I/O
Package Balls
Description
M2_LINKUP_LED
O
G23
LED drive for MAC 2 to indicate port is
linked up.
Logic 0 output = LED on
Logic 1 output = LED off
M2_ACTIVE_LED
O
AB24
LED drive for MAC 2 to indicate port is
transmitting or receiving packet data.
Logic 0 output = LED on
Logic 1 output = LED off
M2_RXCLK
IU
AA19
MII only - Receive Clock.
Accepts the following frequencies:
25.0 MHz
MII 100 Mbps
M2_COL
ID
AE26
Collision Detection. This signal is
independent of M2_TXCLK and
M2_RXCLK, and is asserted when a
collision is detected on an attempted
transmission. It is active high, and only
specified for half-duplex operation.
M2_RXD[3:0]
IU
[3]
[2]
M2_RXDV
ID
AA20
AD25
AC23
[1]
[0]
AB21
AD24
Receive Data. Clocked on rising edge of
M2_RXCLK.
Receive Data Valid. Active high. This signal
is clocked on the rising edge of M2_RXCLK.
It is asserted when valid data is on the
M2_RXD bus.
Table 12 - MII Port 2 Interface Package Ball Definition
39
Zarlink Semiconductor Inc.
ZL50110/11/12/14
Data Sheet
MII Port 2 - ZL50111 and ZL50112 variants only.
Note: This port must not be used to receive data at the same time as port 3,
they are mutually exclusive.
Signal
I/O
Package Balls
Description
M2_RXER
ID
AC24
Receive Error. Active high signal indicating
an error has been detected. Normally valid
when M2_RXDV is asserted. Can be used
in conjunction with M2_RXD when
M2_RXDV signal is de-asserted to indicate
a False Carrier.
M2_CRS
ID
AC25
Carrier Sense. This asynchronous signal is
asserted when either the transmission or
reception device is non-idle. It is active
high.
M2_TXCLK
IU
AD26
MII only - Transmit Clock
Accepts the following frequencies:
25.0 MHz
MII 100 Mbps
M2_TXD[3:0]
O
[3]
[2]
M2_TXEN
O
AC22
Transmit Enable. Asserted when the MAC
has data to transmit, synchronously to
M2_TXCLK with the first pre-amble of the
packet to be sent. Remains asserted until
the end of the packet transmission. Active
high.
M2_TXER
O
AB20
Transmit Error. Transmitted synchronously
with respect to M2_TXCLK, and active high.
When asserted (with M2_TXEN also
asserted) the ZL50110/12 will transmit a
non-valid symbol, somewhere in the
transmitted frame.
AE25
AD23
[1]
[0]
AC21
AE24
Transmit Data. Clocked on rising edge of
M2_TXCLK.
Table 12 - MII Port 2 Interface Package Ball Definition (continued)
MII Port 3 - ZL50111 variant only
Note: This port must not be used to receive data at the same time as port 2,
they are mutually exclusive.
Signal
I/O
Package Balls
Description
M3_LINKUP_LED
O
G24
LED drive for MAC 3 to indicate port is
linked up.
Logic 0 output = LED on
Logic 1 output = LED off
M3_ACTIVE_LED
O
AB26
LED drive for MAC 3 to indicate port is
transmitting or receiving packet data.
Logic 0 output = LED on
Logic 1 output = LED off
Table 13 - MII Port 3 Interface Package Ball Definition
40
Zarlink Semiconductor Inc.
ZL50110/11/12/14
Data Sheet
MII Port 3 - ZL50111 variant only
Note: This port must not be used to receive data at the same time as port 2,
they are mutually exclusive.
Signal
I/O
Package Balls
Description
M3_RXCLK
IU
K26
MII only - Receive Clock.
Accepts the following frequencies:
25.0 MHz
MII 100 Mbps
M3_COL
ID
J26
Collision Detection. This signal is
independent of M3_TXCLK and
M3_RXCLK, and is asserted when a
collision is detected on an attempted
transmission. It is active high, and only
specified for half-duplex operation.
M3_RXD[3:0]
IU
[3]
[2]
M3_RXDV
ID
J21
Receive Data Valid. Active high. This signal
is clocked on the rising edge of M3_RXCLK.
It is asserted when valid data is on the
M3_RXD bus.
M3_RXER
ID
H26
Receive Error. Active high signal indicating
an error has been detected. Normally valid
when M3_RXDV is asserted. Can be used
in conjunction with M3_RXD when
M3_RXDV signal is de-asserted to indicate
a False Carrier.
M3_CRS
ID
H24
Carrier Sense. This asynchronous signal is
asserted when either the transmission or
reception device is non-idle. It is active
high.
M3_TXCLK
IU
H25
MII only - Transmit Clock
Accepts the following frequencies:
25.0 MHz
MII 100 Mbps
M3_TXD[3:0]
O
[3]
[2]
M3_TXEN
O
K24
Transmit Enable. Asserted when the MAC
has data to transmit, synchronously to
M3_TXCLK with the first pre-amble of the
packet to be sent. Remains asserted until
the end of the packet transmission. Active
high.
M3_TXER
O
K25
Transmit Error. Transmitted synchronously
with respect to M3_TXCLK, and active high.
When asserted (with M3_TXEN also
asserted) the ZL50111 will transmit a
non-valid symbol, somewhere in the
transmitted frame.
J22
J23
K23
L26
[1]
[0]
[1]
[0]
J24
J25
L25
L24
Receive Data. Clocked on rising edge of
M3_RXCLK.
Transmit Data. Clocked on rising edge of
M3_TXCLK.
Table 13 - MII Port 3 Interface Package Ball Definition (continued)
41
Zarlink Semiconductor Inc.
ZL50110/11/12/14
3.4
Data Sheet
External Memory Interface
All External Memory Interface outputs are high impedance while System Reset is LOW.
If the External Memory Interface is unused, all input pins may be left unconnected.
Active low signals are designated by a # suffix, in accordance with the convention used in common memory data
sheets.
Signal
I/O
Package Balls
Description
RAM_DATA[63:0]
IU/
OT
[63]
[62]
[61]
[60]
[59]
[58]
[57]
[56]
[55]
[54]
[53]
[52]
[51]
[50]
[49]
[48]
[47]
[46]
[45]
[44]
[43]
[42]
[41]
[40]
[39]
[38]
[37]
[36]
[35
[34]
[33]
[32]
AD7
AE6
AF5
AB8
AC7
AD6
AE5
AF4
AF3
AE4
AD5
AA8
AB7
AF2
AC6
AE3
AD4
AC5
AA7
AB6
AB5
AC4
AD3
AE2
AA5
AB4
AC3
AD2
AE1
AD1
W6
Y5
[31]
[30]
[29]
[28]
[27]
[26]
[25]
[24]
[23]
[22]
[21]
[20]
[19]
[18]
[17]
[16]
[15]
[14]
[13]
[12]
[11]
[10]
[9]
[8]
[7]
[6]
[5]
[4]
[3]
[2]
[1]
[0]
K3
K4
J1
J2
J3
J4
H1
H2
H3
J5
G1
J6
H4
G2
H5
G3
F1
G4
F2
F3
G5
E1
E2
G6
F5
F4
E3
E4
D1
E5
D2
D4
Buffer memory data. Synchronous to rising
edge of SYSTEM_CLK.
RAM_PARITY[7:0]
IU/
OT
[7]
[6]
[5]
[4]
L1
L2
L3
L4
[3]
[2]
[1]
[0]
L5
L6
K1
K2
Buffer memory parity. Synchronous to rising
edge of SYSTEM_CLK. Bit [7] is parity for
data byte [63:56], bit [0] is parity for data
byte [7:0].
Table 14 - External Memory Interface Package Ball Definition
42
Zarlink Semiconductor Inc.
ZL50110/11/12/14
Signal
I/O
Package Balls
R4
T2
T1
P5
R3
R2
P4
R1
P3
P2
[9]
[8]
[7]
[6]
[5]
[4]
[3]
[2]
[1]
[0]
Data Sheet
Description
RAM_ADDR[19:0]
O
[19]
[18]
[17]
[16]
[15]
[14]
[13]
[12]
[11]
[10]
P1
N4
N3
N2
M1
M2
M4
M3
M6
M5
Buffer memory address output.
Synchronous to rising edge of
SYSTEM_CLK.
RAM_BW_A#
O
U2
Synchronous Byte Write Enable A (Active
Low). Must be asserted same clock cycle as
RAM_ADDR. Enables RAM_DATA[7:0].
RAM_BW_B#
O
T3
Synchronous Byte Write Enable B (Active
Low). Must be asserted same clock cycle as
RAM_ADDR. Enables RAM_DATA[15:8].
RAM_BW_C#
O
U3
Synchronous Byte Write Enable C (Active
Low). Must be asserted same clock cycle as
RAM_ADDR. Enables RAM_DATA[23:16].
RAM_BW_D#
O
V2
Synchronous Byte Write Enable D (Active
Low). Must be asserted same clock cycle as
RAM_ADDR. Enables RAM_DATA[31:24].
RAM_BW_E#
O
W1
Synchronous Byte Write Enable E (Active
Low). Must be asserted same clock cycle as
RAM_ADDR. Enables RAM_DATA[39:32].
RAM_BW_F#
O
V3
Synchronous Byte Write Enable F (Active
Low). Must be asserted same clock cycle as
RAM_ADDR. Enables RAM_DATA[47:40].
RAM_BW_G#
O
W2
Synchronous Byte Write Enable G (Active
Low). Must be asserted same clock cycle as
RAM_ADDR. Enables RAM_DATA[55:48].
RAM_BW_H#
O
Y1
Synchronous Byte Write Enable H (Active
Low). Must be asserted same clock cycle as
RAM_ADDR. Enables RAM_DATA[63:56].
RAM_RW#
O
U4
Read/Write Enable output
Read = high
Write = low
Table 14 - External Memory Interface Package Ball Definition (continued)
43
Zarlink Semiconductor Inc.
ZL50110/11/12/14
3.5
Data Sheet
CPU Interface
All CPU Interface signals are 5 V tolerant.
All CPU Interface outputs are high impedance while System Reset is LOW.
Signal
CPU_DATA[31:0]
CPU_ADDR[23:2]
I/O
I/
OT
I
Package Balls
Description
[31]
[30]
[29]
[28]
[27]
[26]
[25]
[24]
[23]
[22]
[21]
[20]
[19]
[18]
[17]
[16]
AF25
AB19
AD22
AE23
AC20
AF24
AE22
AD21
AA17
AB18
AC19
AD20
AF23
AE21
AF22
AC18
[15]
[14]
[13]
[12]
[11]
[10]
[9]
[8]
[7]
[6]
[5]
[4]
[3]
[2]
[1]
[0]
AA16
AD19
AE20
AB17
AF21
AC17
AE19
AA15
AB16
AD18
AF19
AE18
AD17
AF20
AB15
AF18
CPU Data Bus. Bi-directional data bus,
synchronously transmitted with
CPU_CLK rising edge.
[23]
[22]
[21]
[20]
[19]
[18]
[17]
[16]
[15]
[14]
[13]
[12]
AB13
AC13
AD13
AE13
AF12
AE12
AD12
AC12
AF11
AB12
AE11
AA12
[11]
[10]
[9]
[8]
[7]
[6]
[5]
[4]
[3]
[2]
AD11
AF10
AC11
AE10
AD10
AB11
AF9
AC10
AE9
AA11
CPU Address Bus. Address input from
processor to ZL50110/11/12/14,
synchronously transmitted with
CPU_CLK rising edge.
NOTE: as with all ports in the
ZL50110/11/12/14 device,
CPU_DATA[0] is the least significant bit
(lsb).
NOTE: as with all ports in the
ZL50110/11/12/14 device,
CPU_ADDR[2] is the least significant bit
(lsb).
CPU_CS
IU
AF14
CPU Chip Select. Synchronous to rising
edge of CPU_CLK and active low. Is
asserted with CPU_TS_ALE. Must be
asserted with CPU_OE to
asynchronously enable the CPU_DATA
output during a read, including DMA
read.
CPU_WE
I
AD14
CPU Write Enable. Synchronously
asserted with respect to CPU_CLK
rising edge, and active low. Used for
CPU writes from the processor to
registers within the ZL50110/11/12/14.
Asserted one clock cycle after
CPU_TS_ALE.
Table 15 - CPU Interface Package Ball Definition
44
Zarlink Semiconductor Inc.
ZL50110/11/12/14
Signal
I/O
Package Balls
Data Sheet
Description
CPU_OE
I
AE14
CPU Output Enable.
Synchronously asserted with respect to
CPU_CLK rising edge, and active low.
Used for CPU reads from the processor
to registers within the ZL50110/11/12/14.
Asserted one clock cycle after
CPU_TS_ALE. Must be asserted with
CPU_CS to asynchronously enable the
CPU_DATA output during a read,
including DMA read.
CPU_TS_ALE
I
AE15
Synchronous input with rising edge of
CPU_CLK.
Latch Enable (ALE), active high signal.
Asserted with CPU_CS, for a single
clock cycle.
CPU_SDACK1
I
AF15
CPU/DMA 1 Acknowledge Input. Active
low synchronous to CPU_CLK rising
edge. Used to acknowledge request
from ZL50110/11/12/14 for a DMA write
transaction. Only used for DMA
transfers, not for normal register access.
CPU_SDACK2
I
AD15
CPU/DMA 2 Acknowledge Input Active
low synchronous to CPU_CLK rising
edge. Used to acknowledge request
from ZL50110/11/12/14 for a DMA read
transaction. Only used for DMA
transfers, not for normal register access.
CPU_CLK
I
AC14
CPU PowerQUICC™ II Bus Interface
clock input. 66 MHz clock, with minimum
of 6 ns high/low time. Used to time all
host interface signals into and out of
ZL50110/11/12/14 device.
Table 15 - CPU Interface Package Ball Definition (continued)
45
Zarlink Semiconductor Inc.
ZL50110/11/12/14
Signal
I/O
Package Balls
Data Sheet
Description
CPU_TA
OT
AB14
CPU Transfer Acknowledge. Driven from
tri-state condition on the negative clock
edge of CPU_CLK following the
assertion of CPU_CS. Active low,
asserted from the rising edge of
CPU_CLK. For a read, asserted when
valid data is available at CPU_DATA.
The data is then read by the host on the
following rising edge of CPU_CLK. For a
write, is asserted when the
ZL50110/11/12/14 is ready to accept
data from the host. The data is written
on the rising edge of CPU_CLK
following the assertion. Returns to
tri-state from the negative clock edge of
CPU_CLK following the de-assertion of
CPU_CS.
CPU_DREQ0
OT
AC15
CPU DMA 0 Request Output Active low
synchronous to CPU_CLK rising edge.
Asserted by ZL50110/11/12/14 to
request the host initiates a DMA write.
Only used for DMA transfers, not for
normal register access.
CPU_DREQ1
OT
AE16
CPU DMA 1 Request
Active low synchronous to CPU_CLK
rising edge. Asserted by
ZL50110/11/12/14 to indicate packet
data is ready for transmission to the
CPU, and request the host initiates a
DMA read. Only used for DMA transfers,
not for normal register access.
CPU_IREQO
O
AF17
CPU Interrupt 0 Request (Active Low)
CPU_IREQ1
O
AD16
CPU Interrupt 1 Request (Active Low)
Table 15 - CPU Interface Package Ball Definition (continued)
46
Zarlink Semiconductor Inc.
ZL50110/11/12/14
3.6
Data Sheet
System Function Interface
All System Function Interface signals are 5 V tolerant.
The core of the chip will be held in reset for 16383 SYSTEM_CLK cycles after SYSTEM_RST has gone HIGH to
allow the PLL’s to lock. No chip access should occur at this time.
Signal
I/O
Package Balls
Description
SYSTEM_CLK
I
U6
System Clock Input. The system clock
frequency is 100 MHz. The quality of
SYSTEM_CLK, or the oscillator that
drives SYSTEM_CLK directly impacts
the adaptive clock recovery
performance. See Section 6.3.
SYSTEM_RST
I
V4
System Reset Input. Active low. The
system reset is asynchronous, and
causes all registers within the
ZL50110/11/12/14 to be reset to their
default state. Recommend external
pull-up.
SYSTEM_DEBUG
I
U5
System Debug Enable. This is an
asynchronous signal that, when
de-asserted, prevents the software
assertion of the debug-freeze command,
regardless of the internal state of
registers, or any error conditions. Active
high. Recommend external pull-down.
Table 16 - System Function Interface Package Ball Definition
47
Zarlink Semiconductor Inc.
ZL50110/11/12/14
3.7
3.7.1
Data Sheet
Test Facilities
Administration, Control and Test Interface
All Administration, Control and Test Interface signals are 5 V tolerant.
Signal
I/O
Package Balls
GPIO[15:0]
ID/
OT
[15]
[14]
[13]
[12]
[11]
[10]
[9]
[8]
AA4
AB3
AC2
AC1
AB2
Y4
W5
AA3
TEST_MODE[2:0]
ID
[2]
[1]
[0]
AF6
AB9
AC8
[7]
[6]
[5]
[4]
[3]
[2]
[1]
[0]
Description
AA2
Y3
AB1
Y2
W4
V5
AA1
W3
General Purpose I/O pins. Connected to an
internal register, so customer can set
user-defined parameters. Bits [4:0] reserved
at startup or reset for memory Tapped Delay
Line (TDL) setup. See the ZL50110/11/12/14
Programmers Model for more details.
Recommend 5 kohm pulldown on these
signals.
Test Mode input - ensure these pins are tied
to ground for normal operation.
000 SYS_NORMAL_MODE
001-010 RESERVED
011 SYS_TRISTATE_MODE
100-111 RESERVED
Table 17 - Administration/Control Interface Package Ball Definition
3.7.2
JTAG Interface
All JTAG Interface signals are 5 V tolerant, and conform to the requirements of IEEE1149.1 (2001).
Signal
I/O
Package Balls
Description
JTAG_TRST
IU
AE7
JTAG Reset. Asynchronous reset. In normal
operation this pin should be pulled low.
Recommend external pull-down.
JTAG_TCK
I
AD8
JTAG Clock - maximum frequency is
25 MHz, typically run at 10 MHz. In normal
operation this pin should be pulled either
high or low. Recommend external pull-down.
JTAG_TMS
IU
AA10
JTAG test mode select. Synchronous to
JTAG_TCK rising edge. Used by the Test
Access Port controller to set certain test
modes.
JTAG_TDI
IU
AF7
JTAG test data input. Synchronous to
JTAG_TCK.
JTAG_TDO
O
AC9
JTAG test data output. Synchronous to
JTAG_TCK.
Table 18 - JTAG Interface Package Ball Definition
The ZL50111 and ZL50112 share a common JTAG ID. They also share a common CHIP_ID register value.
48
Zarlink Semiconductor Inc.
ZL50110/11/12/14
3.8
Data Sheet
Miscellaneous Inputs
Signal
Package Balls
Description
IC_GND
AD9, AF8, R5, T4, AE8
Internally Connected. Tie to GND.
IC_VDD_IO
AF16
Internally Connected. Tie to VDD_IO.
Table 19 - Miscellaneous Inputs Package Ball Definitions
3.9
Power and Ground Connections
Signal
Package Balls
Description
VDD_IO
J9
J13
J17
L9
N9
R9
U9
V11
V15
J10
J14
J18
L18
N18
R18
U18
V12
V16
J11
J15
K9
M9
P9
T9
V9
V13
V17
J12
J16
K18
M18
P18
T18
V10
V14
V18
3.3 V VDD Power Supply for IO Ring
GND
A1
F6
L11
L15
M13
N1
N13
N22
P12
P16
R13
T5
T14
AA6
AF13
A13
F21
L12
L16
M14
N5
N14
N26
P13
P24
R14
T11
T15
AA21
AF26
A26
K5
L13
M11
M15
N11
N15
P6
P14
R11
R15
T12
T16
AB10
E22
K22
L14
M12
M16
N12
N16
P11
P15
R12
R16
T13
T24
AF1
0 V Ground Supply
VDD_CORE
F7
F20
K6
N6
Y6
AA13
F12
H6
K21
T21
Y21
AA14
F15
H21
M21
V6
AA9
AA18
A1VDD
T6
1.8 V VDD Power Supply for Core
Region
1.8 V PLL Power Supply
Table 20 - Power and Ground Package Ball Definition
49
Zarlink Semiconductor Inc.
ZL50110/11/12/14
3.10
Data Sheet
ZL50111, ZL50112, ZL50110 and ZA50114 Internal Connections
Signal
IC
Package Balls
Description
R6, AC16, AE17
Internally Connected. Must leave open
circuit.
Table 21 - No Connection Ball Definition
3.11
ZL50112 Internal Connections
Signal
IC
Package Balls
Description
G21, F25, E26. G22
Internally Connected. Must leave open
circuit.
Table 22 - No Connection Ball Definition
3.12
ZL50112 Auxiliary Clocks
Signal
Package Balls
Description
AUX2_CLKo[1:0]
C17, C15
Auxiliary clock output. Typically
AUX2_CLKo[1] is connected to
AUX2_CLKi[1] and AUX2_CLKo[0] is
connected to AUX2_CLKi[0] through a
zero ohm resistor.
AUX2_CLKi[1:0]
E15, D15
Auxiliary clock input. Typically
AUX2_CLKi[1] is connected to
AUX2_CLKo[1] and AUX2_CLKi[0] is
connected to AUX2_CLKo[0] through a
zero ohm resistor.
AUX1_CLKo[1:0]
D16, A18
Auxiliary clock output. Typically
AUX1_CLKo[1] is connected to
AUX1_CLKi[1] and AUX1_CLKo[0] is
connected to AUX1_CLKi[0]
AUX1_CLKi[1:0]
E16, B18
Auxiliary clock input. Typically
AUX1_CLKi[1] is connected to
AUX1_CLKo[1] and AUX1_CLKi[0] is
connected to AUX1_CLKo[0]
Table 23 - Auxiliary clock Ball Definition
4.0
Typical Applications
4.1
Leased Line Provision
Circuit emulation is typically used to support the provision of leased line services to customers using legacy TDM
equipment. For example, Figure 6 shows a leased line TDM service being carried across a packet network. The
advantages are that a carrier can upgrade to a packet switched network, whilst still maintaining their existing TDM
business.
50
Zarlink Semiconductor Inc.
ZL50110/11/12/14
Data Sheet
The ZL50110/11/12/14 is capable of handling circuit emulation of both structured T1, E1, and J2 links (e.g., for
support of fractional circuits) and unstructured (or clear channel) T1, E1, J2, T3 and E3 links. The device handles
the data-plane requirements of the provider edge inter-working function (with the exception of the physical
interfaces and line interface units). Control plane functions are forwarded to the host processor controlling the
ZL50110/11/12/14 device.
The ZL50110/11/12/14 provides a per-stream clock recovery function, in unstructured mode, to reproduce the TDM
service frequency at the egress of the packet network. This is required otherwise the queue at the egress of the
packet network will either fill up or empty, depending on whether the regenerated clock is slower or faster than the
original.
Carrier Network
TDM
Packet
Network
TDM to
packet
Customer
Premises
queue
TDM
fservice
~
~
fservice
fservice
Customer data
Customer data
Customer
Premises
Extract
Clock
Provider Edge
Interworking
Function
Provider Edge
Interworking
Function
Figure 6 - Leased Line Services Over a Circuit Emulation Link
4.2
Metropolitan Area Network Aggregation
The metro Ethernet application, shown in Figure 7, consists of the metro Ethernet service modules sitting on the
edge of the Metro Ethernet ring. The modules will connect Ethernet circuits and TDM circuits to the metro ring.
The ZL50110/11/12/14 is used to emulate leased line TDM circuits over Ethernet by establishing CESoP
connections over the Metro Ethernet ring between the MTUs/MDUs and the PSTN. The use of CESoP eliminates
the need for a separate TDM network in the metro core, thereby enabling convergence on a unified Ethernet
network.
OC-3, DS3
CESoP
CESoP
Metro
Core
Multi-Tenant
Units
Campus
Metropolitan
Access Network
(Resilient Packet Ring or
Metro Ethernet)
Metro
Access
Metro
Access
T1/E1
Links
T1/E1
Links
Figure 7 - Metropolitan Area Network Aggregation using CESoP
51
Zarlink Semiconductor Inc.
ZL50110/11/12/14
4.3
Data Sheet
Digital Loop Carrier
The Broadband Digital Loop Carrier (BBDLC) application, shown in Figure 8, consists of a BBDLC connected to the
Central Office (CO) by a dedicated fiber link running Gigabit Ethernet (GE) rather than by NxT1/E1 or DS3/E3.
The ZL50110/11/12/14 is used to emulate TDM circuits over Ethernet by establishing CESoP connections between
the BBDLC and the CO. At the CO the native IP or Ethernet traffic is split from the CESoP connections at sent
towards the packet network. Multiple T1/E1 CESoP connections from several BBDLC are aggregated in the CO
using a larger ZL50110/11/12/14 variant, converted back to TDM circuits, and connected to a class 5 switch
destined towards the PSTN.
In this configuration T3/E3 services can also be provided. Using CESoP allows voice and data traffic to be
converged onto a single link.
IP Edge Router or
Multi-Service
Switching Platform
POTS
Digital
Loop
Carrier
GIGE Over
Fiber
IP
Dedicated
Fiber Links
Central
Office
T1/E1
Broadband
DLC
N x GIGE
GIGE Over
Fiber
Central Office
Switch (Class 5)
N x T1/E1
PSTN
CESoP
Figure 8 - Digital Loop Carrier using CESoP
52
Zarlink Semiconductor Inc.
ZL50110/11/12/14
4.4
Data Sheet
Remote Concentrator
The remote concentrator application, shown in Figure 9, consists of a remote concentrators connected to the
Central Office (CO) by a dedicated fiber link running Gigabit Ethernet (GE) or Ethernet over SONET (EoS) rather
than by NxT1/E1 or DS3/E3. The remote concentrators provide both TDM service and native Ethernet service to
the MTU/MDU.
The ZL50110/11/12/14 is used to emulate TDM circuits over Ethernet by establishing CESoP connections between
the remote concentrator and the CO. The native IP or Ethernet traffic is multiplexed with the CESoP traffic inside
the remote concentrator and sent across the same GE connection to the CO. At the CO the native IP or Ethernet
traffic is split from the CESoP connections at sent towards the packet network. Multiple T1/E1 CESoP connections
from several remote concentrators are aggregated in the CO using a larger ZL50110/11/12/14 variant, converted
back to TDM circuits, and connected to the PSTN through a higher bandwidth TDM circuit such as OC-3 or STM-1.
The use of CESoP here allows the convergence of voice and data on a single access network based on Ethernet.
This convergence on Ethernet, a packet technology, rather than SONET/SDH, a switched circuit technology,
provides cost and operational savings.
Multi-Tenant / Multi-Dwelling Units
Ethernet
10/100 Mbps
Remote
Concentrator
T1/E1
Links
GIGE Over
Fiber
IP
Dedicated
Fiber Links
Ethernet
10/100 Mbps
Remote
Concentrator
T1/E1
Links
Nx GIGE
GIGE Over
Fiber
Central
Office
(Aggregation)
STM1- 4
PSTN
T1/E1
Links
CESoP
Figure 9 - Remote Concentrator using CESoP
53
Zarlink Semiconductor Inc.
ZL50110/11/12/14
4.5
Data Sheet
Cell Site Backhaul
The cell site backhaul application, shown in Figure 10, consists of 2G, 2.5G and 3G base stations, co-located at a
cell site, connected to their respective 2G, 2.5G base station controllers and 3G radio network controller. The
traditional leased T1/E1 lines between the cell site and the base station controllers is now replaced by a packet
network such as fixed wireless or Gigabit Ethernet (GE) fiber, that may be owned by the carrier or accessed
through a service provider.
The ZL50110/11/12/14 would sit in a box either external to the base stations, or integrated in them, and would
transparently carry multiple T1/E1s to the Base Station controllers/Radio Network controllers using CESoP
connections. At the base station controller location another ZL50110/11/12/14 would terminate the CESoP
connection and provide the T1/E1 line to the controllers.
The use of the ZL50110/11/12/14 would allow for lower cost transport between the two locations, due to the
replacement of the leased T1/E1 line cost. The CESoP connection would allow the T1/E1 to meet the strict timing
requirements for 3G base stations. Each T1/E1 may be asynchronous should a service provider be backhauling
T1/E1s from multiple carriers.
Co-Located
Base Stations
3G
Base
Station
ATM over
T1/E1
ATM over
T1/E1
3G
Radio
Network
Controller
ATM over
T1/E1
2.5G
Base
Station
Controller
TDM over
T1/E1
2G
Base
Station
Controller
DS3/
OC3
Packet
Switched
Network
2.5G
Base
Station
ATM over
T1/E1
CESoP
CESoP
DS3/
OC3
GIGE
over Fiber
2G
Base
Station
TDM over
T1/E1
CESoP
Figure 10 - Cell Site Backhaul using CESoP
54
Zarlink Semiconductor Inc.
DS3/
OC3
ZL50110/11/12/14
4.6
Data Sheet
Equipment Architecture Example
An equipment architecture example is shown in Figure 11, supporting T1/E1 ports is shown at the board level using
Zarlink’s CESoP processors. In this example, the equipment consists of three line cards and an uplink card
connected to a packet backplane.
The first line card supports up to 32 T1/E1 lines, containing up to 1024 DS0, for Nx64 kbps structured data transfer
(SDT) CESoP connections. The T1/E1 lines are broken down into DS0 channels on an H.110 bus. The
ZL50110/11/12/14 establishes CESoP connections, with each connection taking a number of DS0 channels from
the H.110 bus.
The third line card support up to 32 T1/E1 or 2 T3/E3 lines for private line unstructured data transfer (UDT) CESoP
connections. The T1/E1 lines are not terminated on the card by are transparently packetized into individual CESoP
connections by the ZL50110/11/12/14.
The second line card supports multiple 10/100/1000 Mbps Ethernet ports for native Internet, video and data service.
The uplink card multiplexes the Ethernet traffic from the three cards, and uplinks the CESoP, Internet, video and
data traffic to the packet switched network (PSN.)
Up to 32 T1/E1
or 1024 Channel
T1/E1
LIUs
Octal
T1/E1
Framers
MT9072
T1/E1
LIUs
Voice
and
Data
Services
H.110 / HMVIP BUS
Structured,
Structured, Synchronous
Synchronous CES
CES
Up to 32
Streams
CESoP
Processor
DPLL Output
ZL50111
Gigabit
Ethernet
Switch
MVTX2801
Ethernet
Concentrator
MVTX2601
MVTX2801
Ethernet
Traffic
Unstructured,
Unstructured, Asynchronous
Asynchronous CES
CES
Up to 32 T1/E1
or 2 T3/E3
T3/E3
or T1/E1
LIU
Per Port
Clock Recovery
2 GE
Ethernet
PHYs
Optical
Interface
& Drivers
2 GE
CESoP
Processor
T3/E3
or T1/E1
LIU
ZL50111
Figure 11 - Equipment example using CESoP
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Zarlink Semiconductor Inc.
Packet
Switched
Networks
ZL50110/11/12/14
5.0
Data Sheet
Functional Description
The ZL50110/11/12/14 family provides the data-plane processing to enable constant bit rate TDM services to be
carried over a packet switched network, such as an Ethernet, IP or MPLS network. The device segments the TDM
data into user-defined packets, and passes it transparently over the packet network to be reconstructed at the far
end. This has a number of applications, including emulation of TDM circuits and packet backplanes for TDM-based
equipment.
Transparent data flow between TDM equipment
TDM
equipment
constant bit rate
TDM link
ZL5011x
TDM-Packet
conversion
packet switched
network
interworking
function
ZL5011x
TDM-Packet
conversion
TDM
equipment
constant bit rate
TDM link
interworking
function
Figure 12 - ZL50110/11/12/14 Family Operation
Note: The ZL50110/11/12/14 does not support the transmission or reception of jumbo packets, or packet sizes
larger than 1522 bytes.
5.1
Block Diagram
A diagram of the ZL50110/11/12/14 device is given in Figure 13, which shows the major data flows between
functional components.
DMA
Control
TM
Compatible
Host Interface
Admin.
Payload
Assembly
Central
Task
Manager
Packet
Transmit
TDM
Formatter
Protocol
Engine
Packet
Receive
TDM
Interface
Clock
Recovery
Data Flows
Control Flows
Memory Management Unit
On-chip RAM and SSRAM Interface Controller
Off-chip Packet Memory
0-8 MBytes SSRAM
Triple
Packet
Interface
MAC
JTAG Test
Controller
JTAG Interface
Figure 13 - ZL50110/11/12/14 Data and Control Flows
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Zarlink Semiconductor Inc.
Up to triple 100 Mbps MII Fast Ethernet or
Dual Redundant 1000 Mbps GMII/TBI Gigabit Ethernet
Up to 32 T1, 32 E1, 8 J2, 2 T3 or 2 E3 port
H.110, H-MVIP, ST-BUS backplanes
Motorola PowerQUICC
ZL50110/11/12/14
5.2
Data Sheet
Data and Control Flows
There are numerous combinations that can be implemented to pass data through the ZL50110/11/12/14 device
depending on the application requirements. The Task Manager can be considered the central pivot, through which
all flows must operate.
The flow is determined by the Type field in the Task Message (see ZL50110/11/12/14 Programmers Model).
Flow Number
Flow Through Device
1
TDM to (TM) to PE to (TM) to PKT
2
PKT to (TM) to PE to (TM) to TDM
3
TDM to (TM) to PKT
4
PKT to (TM) to TDM
5
TDM to (TM) to CPU
6
TDM to (TM) to PE to (TM) to CPU
7
CPU to (TM) to TDM
8
PKT to (TM) to CPU
9
CPU to (TM) to PKT
101
TDM to (TM) to TDM
1
PKT to (TM) to PKT
11
Table 24 - Standard Device Flows
1. This flow is for loopback test purposes only
Each of the 11 data flows uses the Task Manager to route packet information to the next block or interface for
onward transmission. This section describes the flows between the TDM interface, the packet interface and the
Task Manager which are the main flow routes used in the ZL50110/11/12/14 family. For example, the TDM->TM
flow is used in flow types 1, 3, 5, and 6, and the TM->PKT flow is used in flow types 1, 3, and 9.
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Zarlink Semiconductor Inc.
ZL50110/11/12/14
5.3
Data Sheet
TDM Interface
The ZL50110/11/12/14 family offers the following types of TDM service across the packet network:
Service type
TDM interface
Interface type
Interfaces to
Unstructured
asynchronous
T1, E1, J2, E3 and T3
Bit clock in and out
Data in and out
Line interface unit
Structured synchronous
(N x 64 Kbps)
T1, E1 and J2
Framed TDM data streams at
2.048 and 8.192 Mbps
Bit clock out
Frame pulse out
Data in and out
Framers
TDM backplane (master)
Bit clock in
Frame in
Data in and out
Framers
TDM backplane (slave)
Table 25 - TDM Services Offered by the ZL50110/11/12/14 Family
Unstructured services are fully asynchronous, and include full support for clock recovery on a per stream basis.
Both adaptive and differential clock recovery mechanisms can be used. Structured services are synchronous, with
all streams driven by a common clock and frame reference. These services can be offered in two ways:
•
Synchronous master mode - the ZL50110/11/12/14 provides a common clock and frame pulse to all
streams, which may be locked to an incoming clock or frame reference
•
Synchronous slave mode - the ZL50110/11/12/14 accepts a common external clock and frame pulse to be
used by all streams
In either mode, N x 64 Kbps trunking is supported as detailed in “Structured Payload Order” on page 62.
The ZL50110/11/12/14 supports structured mode or unstructured mode, however it does not support structured
mode and unstructured mode at the same time, all ports are either structured or unstructured. In structured mode,
all TDM inputs must be synchronous.
In addition, it can be used with a variety of different protocols. It includes full support for the IETF RFCs for
CESoPSN (Circuit Emulation Services over Packet Switched Networks) and SAToP (Structure-Agnostic Transport
over Packet) protocols.
5.3.1
TDM Interface Block
The TDM Access Interface consists of up to 32 streams (depending on variant), each with an input and an output
data stream operating at either 1.544 Mbps or 2.048 Mbps. It contains two basic types of interface: unstructured
clock and data, for interfacing directly to a line interface unit; or structured, framed data, for interfacing to a framer
or TDM backplane.
Unstructured data is treated asynchronously, with every stream using its own clock. Clock recovery is provided on
each output stream, to reproduce the TDM service frequency at the egress of the packet network. Structured data is
treated synchronously, i.e., all data streams are timed by the same clock and frame references. These can either be
supplied from an external source (slave mode) or generated internally using the on-chip stratum 4/4E DPLL (master
mode).
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5.3.2
Data Sheet
Structured TDM Port Data Formats
The ZL50110/11/12/14 is programmable such that the frame/clock polarity and clock alignment can be set to any
desired combination. Table 26 shows a brief summary of four different TDM formats; ST-BUS, H.110, H-MVIP, and
Generic (synchronous mode only), for more information see the relevant specifications shown. There are many
additional formats for TDM transmission not depicted in Table 26, but the flexibility of the port will cover almost any
scenario. The overall data format is set for the entire TDM Interface device, rather than on a per stream basis. It is
possible to control the polarity of the master clock and frame pulse outputs, independent of the chosen data format
(used when operating in synchronous master mode).
Data
Format
Data
Rate
(Mbps)
Number
of
channels
per
frame
Clock
Freq.
Nominal
Frame
Pulse
Width
(MHz)
Frame
Pulse
Polarity
Frame Boundary
Alignment
Standard
clock
frame
pulse
(ns)
ST-bus
2.048
32
2.048
244
Negative
Rising
Edge
Straddles
boundary
2.048
32
4.096
244
Negative
Falling
Edge
Straddles
boundary
8.192
128
16.384
61
Negative
Falling
Edge
Straddles
boundary
H.110
8.192
128
8.192
122
Negative
Rising
edge
Straddles
boundary
ECTF
H.110
H-MVIP
2.048
32
2.048
244
Negative
Rising
Edge
Straddles
boundary
2.048
32
4.096
244
Negative
Falling
Edge
Straddles
boundary
H-MVIP
Release
1.1a
8.192
128
16.384
244
Negative
Falling
Edge
Straddles
boundary
2.048
32
2.048
488
Positive
Rising
Edge
Rising
edge of
clock
8.192
128
8.192
122
Positive
Rising
Edge
Rising
edge of
clock
Generic
MSAN-126
Rev B
(Issue 4)
Zarlink
Table 26 - Some of the TDM Port Formats Accepted by the ZL50110/11/12/14 Family
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Zarlink Semiconductor Inc.
ZL50110/11/12/14
5.3.3
Data Sheet
TDM Clock Structure
The TDM interface can operate in two modes, synchronous for structured TDM data, and asynchronous for
unstructured TDM data. The ZL50110/11/12/14 is capable of providing the TDM clock for either of the modes. The
ZL50110/11/12/14 supports clock recovery in both synchronous and asynchronous modes of operation. In
asynchronous operation each stream may have independent clock recovery.
5.3.3.1
Synchronous TDM Clock Generation
In synchronous mode all 32 streams will be driven by a common clock source. When the ZL50110/11/12/14 is
acting as a master device, the source can either be the internal DPLL or an external PLL. In both cases, the primary
and secondary reference clocks are taken from either two TDM input clocks, or two external clock sources driven to
the chip. The input clocks are then divided down where necessary and sent either to the internal DPLL or to the
output pins for connection to an external DPLL. The DPLL then provides the common clock and frame pulse
required to drive the TDM streams. See “DPLL Specification” on page 74 for further details.
TDM_CLKi[31:0]
PRS
PRD
PLL_PRI
DIV
PLL_SE
C
TDM_CLKiP
SRS
SRD
DIV
TDM_CLKiS
CLOCK
Internal
DPLL
FRAME
Figure 14 - Synchronous TDM Clock Generation
When the ZL50110/11/12/14 is acting as a slave device, the common clock and frame pulse signals are taken from
an external device providing the TDM master function.
5.3.3.2
Asynchronous TDM Clock Generation
Each stream uses a separate internal DCO to provide an asynchronous TDM clock output. The DCO can be
controlled to recover the clock from the original TDM source depending on the timing algorithm used.
5.4
Payload Assembly
Data traffic received on the TDM Access Interface is sampled in the TDM Interface block, and synchronized to the
internal clock. It is then forwarded to the payload assembly process. The ZL50110/11/12/14 Payload Assembler can
handle up to 128 active packet streams or “contexts” simultaneously. Packet payloads are assembled in the format
shown in Figure 15 - on page 61. This meets the requirements of the IETF CESoPSN standard (RFC 5086).
Alternatively, packet payloads are assembled in the format shown in Figure 17 - on page 62. This meets the
requirements of the IETF SAToP standard (RFC 4553).
The Packet Transmit (PTX) circuit adds Layer 2 and Layer 3 protocol headers. The chosen protocol header
combination for addition by the PTX must not exceed 64 bytes. The exception is context 127 (the 128th context),
which must not exceed 56 bytes.
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ZL50110/11/12/14
Data Sheet
Contexts in the TDM to PKT direction are placed in the UPDATE state when they are opened, pending the local
clock source generation. If there is no local clock source to generate packets, the context will remain in the
UPDATE state and cannot be closed. ZLAN-202 describes the procedure to close transmit contexts in the UPDATE
state.
When the payload has been assembled it is written into the centrally managed memory, and a task message is
passed to the Task Manager.
5.4.1
Structured Payload Operation
In structured mode a context may contain any number of 64 kbps channels. These channels need not be
contiguous and they may be selected from any input stream.
Channels may be added or deleted dynamically from a context. This feature can be used to optimize bandwidth
utilisation. Modifications to the context are synchronised with the start of a new packet.
The fixed header at the start of each packet is added by the Packet Transmit block. This consists of up to 64 bytes,
containing the Ethernet header, any upper layer protocol headers, and the two byte context descriptor field (see
section below). The header is entirely user programmable, enabling the use of any protocol.
The payload header and size must be chosen so that the overall packet size is not less than 64 bytes, the Ethernet
standard minimum packet size. Where this is likely to be the case, the header or data must be padded (as shown in
Figure 15 and Figure 17) to ensure the packet is large enough. This padding is added by the ZL50110/11/12/14 for
most applications.
Header
Ethernet Header
may include VLAN tagging
Network Layers
e.g. IPv4, IPv6, MPLS
(added by Packet Transmit)
Upper layers
(added by Protocol Engine)
e.g. UDP, L2TP, RTP,
CESoPSN, SAToP
Channel 1
Channel 2
Data for TDM Frame 1
Channel x
Channel 1
Channel 2
Data for TDM Frame 2
TDM Payload
Channel x
(constructed by Payload Assembler)
Channel 1
Channel 2
Data for TDM Frame n
Channel x
Static Padding
(if required to meet minimum payload size)
may also be placed in the
packet header
Ethernet FCS
Figure 15 - ZL50110/11/12/14 Packet Format - Structured Mode
In applications where large payloads are being used, the payload size must be chosen such that the overall packet
size does not exceed the maximum Ethernet packet size of 1518 bytes (1522 bytes with VLAN tags). Figure 15
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Zarlink Semiconductor Inc.
ZL50110/11/12/14
Data Sheet
shows the packet format for structured TDM data, where the payload is split into frames, and each frame
concatenated to form the packet.
5.4.1.1
Structured Payload Order
Packets are assembled sequentially, with each channel placed into the packet as it arrives at the TDM Access
Interface. A fixed order of channels is maintained (see Figure 16), with channel 0 placed before channel 1,
which is placed before channel 2. It is this order that allows the packet to be correctly disassembled at the far
end. A context must contain only unique channel numbers. As such a context that contains the same channel
from different streams, for example channel 1 from stream 2 and channel 1 from stream 5, would not be
permitted.
S tre a m 0
C hannel 0
C hannel 1
C hannel 2
C hannel 31
S tre a m 1
C hannel 0
C hannel 1
C hannel 2
C hannel 31
S tre a m 2
C hannel 0
C hannel 1
C hannel 2
C hannel 31
S tre a m 3 1
C hannel 0
C hannel 1
C hannel 2
C hannel 31
C h a n n e l A ss e m b ly O rd e r
Figure 16 - Channel Order for Packet Formation
Each packet contains one or more frames of TDM data, in sequential order. This groups the selected channels
for the first frame, followed by the same set of channels for the subsequent frame, and so on.
5.4.2
Unstructured Payload Operation
In unstructured mode, the payload is not split by defined frames or timeslots, so the packet consists of a continuous
stream of data. Each packet contains a programmable number of octets, as shown in Figure 17. The number of
octets in a packet need not be an integer number of frames. A typical value for N may be 192, as defined in the
IETF PWE3 RFC. For example, consider mapping the unstructured data of a 25 timeslot DS0 stream. The data for
each T1 frame would normally consist of 193 bits, 192 data bits and 1 framing bit. If the payload consists of 24
octets it will be 1 bit short of a complete frames worth of data, if the payload consists of 25 octets it will be 7 bits over
a complete frames worth of data. NOTE: No alignment of the octets with the T1 framing structure can be assumed.
Ethernet Header
Network Layers
Header
(added by Packet Transmit)
Upper layers
may include VLAN tagging
e.g. IPv4, IPv6, MPLS
e.g. UDP, L2TP, RTP,
CESoPSN, SAToP
(added by Protocol Engine)
N octets of data from unstructured stream
NOTE: No frame or channel alignment
Octet 1
Octet 2
Octet N
Static Padding
TDM Payload
(constructed by Payload Assembler)
46 to 1500 bytes
may also be placed in the
(if required to meet minimum payload size) packet header
Ethernet FCS
Figure 17 - ZL50110/11/12/14 Packet Format - Unstructured Mode
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Zarlink Semiconductor Inc.
ZL50110/11/12/14
Data Sheet
Note: To change the packet size of a context, first close the context and then re-open the context with a new packet
size.
5.5
Protocol Engine
In general, the next processing block for TDM packets is the Protocol Engine. This handles the data-plane
requirements of the main higher level protocols (layers 4 and 5) expected to be used in typical applications of the
ZL50110/11/12/14 family: UDP, RTP, L2TP, CESoPSN and SAToP. The Protocol Engine can add a header to the
datagram containing up to 24 bytes. This header is largely static information, and is programmed directly by the
CPU. It may contain a number of dynamic fields, including a length field, checksum, sequence number and a
timestamp. The location, and in some cases the length of these fields is also programmable, allowing the various
protocols to be placed at variable locations within the header.
5.6
Packet Transmission
Packets ready for transmission are queued to the switch fabric interface by the Queue Manager. Four classes of
service are provided, allowing some packet streams to be prioritized over others. On transmission, the Packet
Transmit block appends a programmable header, which has been set up in advance by the control processor.
Typically this contains the data-link and network layer headers (layers 2 and 3), such as Ethernet, IP (versions 4
and 6) and MPLS.
5.7
Packet Reception
Incoming data traffic on the packet interface is received by the MACs. The well-formed packets are forwarded to a
packet classifier to determine the destination. When a packet is successfully classified the destination can be the
TDM interface, the LAN interface or the host interface. TDM traffic is then further classified to determine the context
it is intended for.
Each TDM interface context has an individual queue, and the TDM re-formatting process re-creates the TDM
streams from the incoming packet streams. This queue is used as a jitter buffer, to absorb variation in packet delay
across the network. The size of the jitter buffer can be programmed in units of TDM frames (i.e., steps of 125 µs).
There is also a queue to the host interface, allowing a traffic flow to the host CPU for processing. Again the host’s
DMA controller can be used to retrieve packet data and write it out into the CPU’s own memory.
5.8
TDM Formatter
At the receiving end of the packet network, the original TDM data must be re-constructed from the packets
received. This is known as re-formatting, and follows the reverse process from the Payload Assembler. The TDM
Formatter plays out the packets in the correct sequence, directing each octet to the selected timeslot on the output
TDM interface.
When lost or late packets are detected, the TDM Formatter plays out underrun data for the same number of TDM
frames as were included in the missing packet. Underrun data can either be the last value played out on that
timeslot, or a pre-programmed value (e.g., 0xFF). If the packet subsequently turns up it is discarded. In this way, the
end-to-end latency through the system is maintained at a constant value.
Contexts in the Packet to TDM direction are placed in the UPDATE state when they are opened, pending first
packet arrival. If a packet never arrives the context will remain in the UDPATE state. ZLAN-202 describes the
procedure to close receive contexts in the UPDATE state.
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6.0
Data Sheet
Clock Recovery
One of the main issues with circuit emulation is that the clock used to drive the TDM link is not necessarily linked
into the central office reference clock, and hence may be any value within the tolerance defined for that service.
The reverse link may also be independently timed, and operating at a slightly different frequency. In the
plesiochronous digital hierarchy the difference in clock frequencies between TDM links is compensated for using bit
stuffing techniques, allowing the clock to be accurately regenerated at the remote end of the carrier network.
With a packet network, that connection between the ingress and egress frequency is broken, since packets are
discontinuous in time. From Figure 6, the TDM service frequency fservice at the customer premises must be exactly
reproduced at the egress of the packet network. The consequence of a long-term mismatch in frequency is that the
queue at the egress of the packet network will either fill up or empty, depending on whether the regenerated clock is
slower or faster than the original. This will cause loss of data and degradation of the service.
The ZL50110/11/12/14 provides clock recovery function to reproduce the TDM service frequency at the egress of
the packet network for structured and unstructured mode. Two schemes are employed, depending on the
availability of a common reference clock at each provider edge unit, differential and adaptive.
The adaptive and differential algorithms assume that there are no bit errors in the received packet header sequence
number or timestamp fields. If there are bit errors in the sequence number or timestamp fields, especially in the
most significant bits, then it is likely to cause a temporary degradation of the recovered clock performance. It is
advised to protect packets end-to-end (e.g. by using Ethernet FCS) such that packets with bit errors are discarded
and do not impact the recovered clock performance.
The clock recovery itself is performed by software in the host processor, with support from on-chip hardware to
gather the required statistics.
6.1
Differential Clock Recovery
For applications where the wander characteristics of the recovered clock are very important, such as when the
emulated circuit must be connected into the plesiochronous digital hierarchy (PDH), the ZL50110/11/12/14 also
offers a differential clock recovery technique. This relies on having a common reference clock available at each
provider edge point.
The differential algorithm assumes that the common clock is always present. There is no internal holdover
capability for the common clock source (e.g. TDM_CLKiP). If the availability of the common clock can not be
guaranteed, then it is recommended to use an external DPLL with holdover capability to provide a clock source at
all times. The external DPLL may enter holdover while the common clock is absent to maintain a relatively close
frequency to the original common clock.
In a differential technique, the timing of data packet formation is sent relative to the common reference clock. Since
the same reference is available at the packet egress point and the packet size is fixed, the original service clock
frequency can be recovered. This technique is unaffected by any low frequency components in the packet delay
variation. The disadvantage is the requirement for a common reference clock at each end of the packet network,
which could either be the central office TDM clock, or provided by a global position system (GPS) receiver.
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Zarlink Semiconductor Inc.
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Data Sheet
PRS
clock
Data
LIU
ZL5011x
source
node
ZL5011x
destination
node
Packets
Source
Clock
Packets
Network
Timestamp
generation
Timestamp
extraction
Data
Dest'n
Clock
LIU
DCO
Host CPU
Timing
recovery
Figure 18 - Differential Clock Recovery
For in-band differential algorithm, the ZL50110/11/12/14 inserts the timestamp after the packet payload is fully
assembled. The insertion-time may be in error by up to 8 UI of the nominal service clock (for example 8 * 488 ns of
an E1 interface).This variable error will occur in unstructured mode only, and result in degradation of performance
at the remote end, which uses the timestamps to recover a clock frequency. This error is most likely to occur when
there are many asynchronous (PDH) clocks that are close in frequency. In this case it is recommended to used the
Zarlink proprietary in-band differential.
Also, for in-band differential clock recovery, the frequency must be the same as the common clock frequency.
6.2
Adaptive Clock Recovery
For applications where there is no common reference clock between provider edge units, an adaptive clock
recovery technique is provided. The Adaptive clock recovery solution provided in the Zarlink CESoP products is a
combination hardware and software. The chip contains a DCO per TDM port in unstructured mode, that enables the
recovery of up to 32 independent clocks. The timing algorithm resides in the API and runs out of the host processor.
The basic information is transmitted using timestamps. Current CES standards allow for using of timestamps.
Timestamps may be implied by the value of the sequence numbers, or it can be formatted as RTP timestamps.
When a packet containing TDM data is sent, an RTP timestamp and/or sequence number is placed into the packet
header. On arrival at the receiving device, the arrival time is noted in the form of a local timestamp, driven by the
output clock of the TDM port it is destined for.
The recovered clock at the egress point of the ZL50110/11/12/14 is based on non-linear filtering of the timestamps
that are carried in the CESoP packets. The performance of the clock recovery is greatly improved by applying these
non-liner filtering techniques. The adaptive clock recovery performance is dependent on the network configuration
and operation, if the loading of the network is constrained, then the wander of the recovered clock will not exceed
the specified limits.
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Zarlink Semiconductor Inc.
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Data Sheet
ZL5011x
destination
node
ZL5011x
source
node
Packets
Packets
Network
Source
Clock
Queue
Dest'n
Clock
DCO
Time
Stamp
Host CPU
Queue
monitor
Figure 19 - Adaptive Clock Recovery
6.3
SYSTEM_CLK Considerations
The quality of the 100 MHz SYSTEM_CLK or the oscillator that drives SYSTEM_CLK directly impacts the adaptive
clock recovery performance. Zarlink has a recommended oscillator and guidelines for the selection of an oscillator.
Please review application note ZLAN-153 “External Component Selection” before choosing an oscillator.
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7.0
System Features
7.1
Latency
Data Sheet
The following lists the intrinsic processing latency of the ZL50110/11/12/14, regardless of the number of active
channels or contexts.
•
TDM to Packet transmission processing latency less than 125 µs
•
Packet to TDM transmission processing latency less than 250 µs (unstructured)
•
Packet to TDM transmission processing latency less than 250 µs (structured, more than 16 channels in
context)
•
Packet to TDM transmission processing latency less than 375 µs (structured, 16 or less channels in context)
End-to-end latency may be estimated as the transmit latency + packet network latency + receive latency. The
transmit latency is the sum of the transmit processing and the number of frames per packet x 125 µs. The receive
latency is the sum of the receive processing and the delay through the jitter buffer which is programmed to
compensate for packet network PDV.
The ZL50110/11/12/14 is capable of creating an extremely low latency connection, with end to end delays of less
than 0.5 ms, depending on user configuration.
7.2
Loopback Modes
The ZL50110/11/12/14 devices support loopback of the TDM circuits and the circuit emulation packets.
TDM loopback is achieved by first packetizing the TDM circuit as normal via the TDM Interface and Payload
Assembly blocks. The packetized data is then routed by the Task Manager back to the same TDM port via the TDM
Formatter and TDM Interface.
Loopback of the emulated services is achieved by redirecting classified packets from the Packet Receive blocks,
back to the packet network. The Packet Transmit blocks are setup to strip the original header and add a new
header directing the packets back to the source.
7.3
Host Packet Generation
The control processor can generate packets directly, allowing it to use the network for out-of-band communications.
This can be used for transmission of control data or network setup information, e.g., routing information. The host
interface can also be used by a local resource for network transmission of processed data.
The device supports dual address DMA transfers of packets to and from the CPU memory, using the host's own
DMA controller. Table 27 illustrates the maximum bandwidths achievable by an external DMA master.
DMA Path
Packet Size
Max Bandwidth Mbps1
ZL50110/11/12/14 to CPU only
ZL50110/11/12/14 to CPU only
CPU to ZL50110/11/12/14 only
CPU to ZL50110/11/12/14 only
Combined2
Combined2
>1000 bytes
60 bytes
>1000 bytes
60 bytes
>1000 bytes
60 bytes
50
6.7
60
43
58 (29 each way)
11 (5.5 each way)
Table 27 - DMA Maximum Bandwidths
Note 1:
Maximum bandwidths are the maximum the ZL50110/11/12/14 devices can transfer under host control, and assumes only
minimal packet processing by the host.
Note 2:
Combined figures assume the same amount of data is to be transferred each way.
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7.4
Data Sheet
Loss of Service (LOS)
During normal operation, a situation may arise where a Loss of Service occurs. This may be caused by a disruption
in the transmission line due to engineering works or cable disconnection, for example. The locally detected LOS
should be transferred across the emulated T1/E1 to the far end. The far end, in turn, should propagate AIS
downstream.
The handling of LOS over a CESoP connection is typically performed using (setting/clearing) the L bit in the
CESoPSN or SAToP control word of the packet header.
Refer to Application Note ZLAN-159, Section 4.1 for details on a variety of different ways that LOS may be handled
in an application.
7.5
External Memory Requirement
The ZL50110/11/12/14 family includes a large amount of on-chip memory, such that for most applications, external
memory will not be required. However, for certain combinations of header size, packet size and jitter buffer size,
there may be a requirement for external memory. Therefore the device allows the connection of up to 8 Mbytes of
synchronous ZBT-SRAM.
The following charts show how much memory is required by the ZL50111 (32 T1 streams) and the ZL50110 (8 T1
streams) for a variety of packet sizes (expressed in number of frames of TDM data) and jitter buffer sizes. It is
assumed that each packet contains a full Ethernet/MPLS/MPLS/RTP/CESoPSN header.
External Memory Requirements for different packet sizes
32 T1 streams, with Ethernet/MPLS/MPLS/RTP/CESoPSN headers
External memory requirement,
KBytes
8192
7168
6144
5120
1 frame packets
8 frame packets
16 frame packets
1 T3 stream (1 frame)
4096
3072
2048
1024
0
4
8
16
32
64
128
256
Jitter Buffer Size, ms
Figure 20 - External Memory Requirement for ZL50111
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Data Sheet
External Memory Requirements for different packet sizes
8 T1 streams, with Ethernet/MPLS/MPLS/RTP/CESoPSN headers
External memory requirement, KBytes
8192
7168
6144
5120
1 frame packets
8 frame packets
16 frame packets
4096
3072
2048
1024
0
4
8
16
32
64
128
256
Jitter Buffer Size, ms
Figure 21 - External Memory Requirement for ZL50110
7.6
GIGABIT Ethernet - Recommended Configurations
NOTE: In GMII/TBI mode only 1 GMAC port may be used. The second GMAC port is for redundancy purposes
only.
This section outlines connection methods for the ZL50110/11/12/14 in a Gigabit Ethernet environment
recommended to ensure optimum performance. Two areas are covered:
•
Central Ethernet Switch
•
Redundant Ethernet Switch
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7.6.1
Data Sheet
Central Ethernet Switch
Network
Ethernet Switch
GMII
GMII
GMII
GMII
GMII
GMII
GMII
GMII
ZL5011x
ZL5011x
ZL5011x
ZL5011x
TDM
TDM
TDM
TDM
Figure 22 - Gigabit Ethernet Connection - Central Ethernet Switch
TDM data and control packets are directed to the appropriate ZL50110/11/12/14 device through the Ethernet
Switch. There is no limit on the number of ZL50110/11/12/14 devices that can be connected in this configuration.
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7.6.2
Data Sheet
Redundant Ethernet Switch
Network
Network
Ethernet Switch
GMII
GMII
GMII
Ethernet Switch
GMII
GMII
GMII
GMII
GMII
ZL5011x
ZL5011x
ZL5011x
ZL5011x
TDM
TDM
TDM
TDM
Figure 23 - Gigabit Ethernet Connection - Redundant Ethernet Switch
The central Ethernet Switch configuration can be extended to include a redundant switch connected to the second
ZL50110/11/12/14 GMII port. One port should be used for all the TDM-to-Packet and Packet-to-TDM data with the
other port idle. If the current port fails then data must be transferred to the spare port.
7.7
Power Up sequence
To power up the ZL50110/11/12/14 the following procedure must be used:
•
The I/O supply should lead the Core supply, or both can be brought up together
•
The I/O supply must never exceed the Core supply by more than 2.0VDC
•
The Core supply must never exceed the I/O supply by more than 0.5VDC
•
The System Reset and the JTAG Reset must remain low until at least 100 µs after the 100 MHz system clock
has stabilised. Note that if JTAG Reset is not used it must be tied low.
This is illustrated in the diagram shown in Figure 24.
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Data Sheet
I/O supply (3.3 V)
VDD
<0.5 VDC
Core supply (1.8 V)
t
RST
t
> 100 µs
SCLK
t
10 ns
Figure 24 - Powering Up the ZL50110/11/12/14
7.8
JTAG Interface and Board Level Test Features
The JTAG interface is used to access the boundary scan logic for board level production testing.
7.9
7.9.1
External Component Requirements
Host Processor
ZL50110/11/12/14 family offers direct connection to PowerQUICC™ II (MPC8260) host processor and associated
memory, but can support other processors with appropriate interface logic.
7.9.2
Other components
•
TDM Framers and/or Line Interface Units
•
Ethernet PHY for each MAC port
•
Optional ZBT-SRAM for extended packet memory buffer depth
7.10
Miscellaneous Features
•
System clock speed of 100 MHz
•
Host clock speed of up to 66 MHz
•
Debug option to freeze all internal state machines
•
JTAG (IEEE1149) Test Access Port
•
3.3 V I/O Supply rail with 5 V tolerance
•
1.8 V Core Supply rail
•
Fully compatible with the MT90880/1/2/3 Zarlink products
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7.11
Data Sheet
Test Modes Operation
7.11.1
Overview
The ZL50110/11/12/14 family supports the following modes of operation.
7.11.1.1
System Normal Mode
This mode is the device's normal operating mode. Boundary scan testing of the peripheral ring is accessible in this
mode via the dedicated JTAG pins. The JTAG interface is compliant with the IEEE Std. 1149.1-2001; Test Access
Port and Boundary Scan Architecture.
Each variant has it's own dedicated.bsdl file which fully describes it's boundary scan architecture.
7.11.1.2
System Tri-State Mode
All output and I/O output drivers are tri-stated allowing the device to be isolated when testing or debugging the
development board.
7.11.2
Test Mode Control
The System Test Mode is selected using the dedicated device input bus TEST_MODE[2:0] as follows in Table 28.
System Test Mode
test_mode[2:0]
SYS_NORMAL_MODE
3’b000
SYS_TRI_STATE_MODE
3’b011
Table 28 - Test Mode Control
7.11.3
System Normal Mode
Selected by TEST_MODE[2:0] = 3'b000. As the test_mode[2:0] inputs have internal pull-downs this is the default
mode of operation if no external pull-up/downs are connected. The GPIO[15:0] bus is captured on the rising edge of
the external reset to provide internal bootstrap options. After the internal reset has been de-asserted the GPIO pins
may be configured by the ADM module as either inputs or outputs.
7.11.4
System Tri-state Mode
Selected by TEST_MODE[2:0] = 3'b011. All device output and I/O output drivers are tri-stated.
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8.0
Data Sheet
DPLL Specification
The ZL50110/11/12/14 family incorporates an internal DPLL that meets Telcordia GR-1244-CORE Stratum 4/4E
requirements, assuming an appropriate clock oscillator is connected to the system clock pin. It will meet the
jitter/wander tolerance, jitter/wander transfer, intrinsic jitter/wander, frequency accuracy, capture range, phase
change slope, holdover frequency and MTIE requirements for these specifications. In structured mode with the
ZL50110/11/12/14 device operating as a master the DPLL is used to provide clock and frame reference signals to
the internal and external TDM infrastructure. In structured mode, with the ZL50110/11/12/14 device operating as a
slave, the DPLL is not used. All TDM clock generation is performed externally and the input streams are
synchronised to the system clock by the TDM interface. The DPLL is not required in unstructured mode (hence it is
not available) because the TDM clocks and frame signals are generated by internal DCO’s assigned to each
individual stream.
8.1
Modes of Operation
It can be set into one of four operating modes: Locking mode, Holdover mode, Freerun mode and Powerdown
mode.
8.1.1
Locking Mode (normal operation)
The DPLL accepts a reference signal from either a primary or secondary source, providing redundancy in the event
of a failure. These references should have the same nominal frequencies but do not need to be identical as long as
their frequency offsets meet the appropriate Stratum requirements. Each source is selected from any one of the
available TDM input stream clocks (up to 32 on the ZL50111 variant), or from the external TDM_CLKiP (primary) or
TDM_CLKiS (secondary) input pins, as illustrated in Figure 14 - on page 60. It is possible to supply a range of input
frequencies as the DPLL reference source, depicted in Table 29. The PRD register Value is the number (in
hexadecimal) that must be programmed into the PRD register within the DPLL to obtain the divided down frequency
at PLL_PRI or PLL_SEC.
Divider
Ratio
PRD/SRD
Register
Value
(Hex)
(Note 1)
Frequency at
PLL_PRI or
PLL_SEC
(MHz)
Maximum
Acceptable
Input Wander
tolerance
(UI)
(Note 2)
30
1
1
0.008
±1
1.544
130
1
1
1.544
±1023
2.048
50
1
1
2.048
±1023
4.096
50
1
1
4.096
±1023
Source
Input Frequency
(MHz)
Tolerance
(±ppm)
0.008
8.192
50
1
1
8.192
±1023
16.384
50
1
1
16.384
±1023
6.312
30
1
1
6.312
±1023
22.368
20
2796
AEC
0.008
±1 (on 64k Hz)
34.368
20
537
219
0.064
±1 (on 64 kHz)
44.736 (Note 3)
20
699
2BB
0.064
±1 (on 64 kHz)
Table 29 - DPLL Input Reference Frequencies
Note 1:
A PRD/SRD value of 0 will suppress the clock, and prevent it from reaching the DPLL.
Note 2:
UI means Unit Interval - in this case periods of the time signal. So ±1UI on a 64 kHz signal means ±15.625 µs, the period of
the reference frequency. Similarly ±1023UI on a 4.096 MHz signal means ±250 µs.
Note 3:
This input frequency is supported with the use of an external divide by 2.
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Data Sheet
The maximum lock-in range can be programmed up to ±372 ppm regardless of the input frequency. The DPLL will
fail to lock if the source input frequency is absent, if it is not of approximately the correct frequency or if it is too
jittery. See Section 8.7 for further details. The Application Program Interface (API) software that accompanies the
ZL50110/11/12/14 family can be used to automatically set up the DPLL for the appropriate standard requirement.
The DPLL lock-in range can be programmed using the Lock Range register (see ZL50110/11/12/14 Programmers
Model document) in order to extend or reduce the capture envelope. The DPLL provides bit-error-free reference
switching, meeting the specification limits in the Telcordia GR-1244-CORE standard. If Stratum 4/4E accuracy is not
required, it is possible to use a more relaxed system clock tolerance.
The DPLL output consists of three signals; a common clock (comclk), a double-rate common clock (comclkx2), and
a frame reference (8 kHz). These are used to time the internal TDM Interface, and hence the corresponding TDM
infrastructure attached to the interface. The output clock options are either 2.048 Mbps (comclkx2 at 4.096 Mbps)
or 8.192 Mbps (comclkx2 at 16.384 Mbps), determined by setup in the DPLL control register. The frame pulse is
programmable for polarity and width.
8.1.2
Holdover Mode
In the event of a reference failure resulting in an absence of both the primary and secondary source, the DPLL
automatically reverts to Holdover mode. The last valid frequency value recorded before failure can be maintained
within the Stratum 3 limits of ±0.05 ppm. The hold value is wholly dependent on the drift and temperature
performance of the system clock. For example, a ±32 ppm oscillator may have a temperature coefficient of
±0.1 ppm/°C. Thus a 10°C ambient change since the DPLL was last in the Locking mode will change the holdover
frequency by an additional ±1 ppm, which is much greater than the ±0.05 ppm Stratum 3 specification. If the strict
target of Stratum 3 holdover accuracy is not required, a less restrictive oscillator can be used for the system clock.
Holdover mode is typically used for a short period of time until network synchronisation is re-established.
8.1.3
Freerun Mode
In freerun mode the DPLL is programmed with a centre frequency, and can output that frequency within the
Stratum 3 limits of ±4.6 ppm. To achieve this the 100 MHz system clock must have an absolute frequency accuracy
of ±4.6 ppm. The centre frequency is programmed as a fraction of the system clock frequency.
8.1.4
Powerdown Mode
It is possible to “power down” the DPLL when it is not in use. For example, an unstructured TDM system, or use of
an external DPLL would mean the internal DPLL could be switched off, saving power. The internal registers can still
be accessed while the DPLL is powered down.
8.2
Reference Monitor Circuit
There are two identical reference monitor circuits, one for the primary and one for the secondary source. Each
circuit will continually monitor its reference, and report the references validity. The validity criteria depends on the
frequency programmed for the reference. A reference must meet all the following criteria to maintain validity:
•
The “period in specified range” check is performed regardless of the programmed frequency. Each period
must be within a range, which is programmable for the application. Refer to the ZL50110/11/12/14
programmers model for details.
•
If the programmed frequency is 1.544 MHz or 2.048 MHz, the “n periods in specified range” check will be
performed. The time taken for n cycles must be within a programmed range, typically with n at 64, the time
taken for consecutive cycles must be between 62 and 66 periods of the programmed frequency.
The fail flags are independent of the preferred option for primary or secondary operation, will be asserted in the
event of an invalid signal regardless of mode.
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8.3
Data Sheet
Locking Mode Reference Switching
When the reference source the DPLL is currently locking to becomes invalid, the DPLL’s response depends on
which one of the failure detect modes has been chosen: autodetect, forced primary, or forced secondary. One of
these failure detect modes must be chosen via the FDM1:0 bits of the DOM register. After a device reset via the
SYSTEM_RESET pin, the autodetect mode is selected.
In autodetect mode (automatic reference switching) if both references are valid the DPLL will synchronise to the
preferred reference. If the preferred reference becomes unreliable, the DPLL continues driving its output clock in a
stable holdover state until it makes a switch to the backup reference. If the preferred reference recovers, the DPLL
makes a switch back to the preferred reference. If necessary, the switch back can be prevented by changing the
preferred reference using the REFSEL bit in the DOM register, after the switch to the backup reference has
occurred.
If both references are unreliable, the DPLL will drive its output clock using the stable holdover values until one of
the references becomes valid.
In forced primary mode, the DPLL will synchronise to the primary reference only. The DPLL will not switch to the
secondary reference under any circumstances including the loss of the primary reference. In this condition, the
DPLL remains in holdover mode until the primary reference recovers. Similarly in forced secondary mode, the
DPLL will synchronise to the secondary reference only, and will not switch to the primary reference. Again, a failure
of the secondary reference will cause the DPLL to enter holdover mode, until such time as the secondary reference
recovers. The choice of preferred reference has no effect in these modes.
When a conventional PLL is locked to its reference, there is no phase difference between the input reference and
the PLL output. For the DPLL, the input references can have any phase relationship between them. During a
reference switch, if the DPLL output follows the phase of the new reference, a large phase jump could occur. The
phase jump would be transferred to the TDM outputs. The DPLL’s MTIE (Maximum Time Interval Error) feature
preserves the continuity of the DPLL output so that it appears no reference switch had occurred. The MTIE circuit is
not perfect however, and a small Time Interval Error is still incurred per reference switch. To align the DPLL output
clock to the nearest edge of the selected input reference, the MTIE reset bit (MRST bit in the DOM register) can be
used.
Unlike some designs, switching between references which are at different nominal frequencies do not require
intervention such as a system reset.
8.4
Locking Range
The locking range is the input frequency range over which the DPLL must be able to pull into synchronization and to
maintain the synchronization. The locking range is programmable up to ±372 ppm.
Note that the locking range relates to the system clock frequency. If the external oscillator has a tolerance of
-100 ppm, and the locking range is programmed to ±200 ppm, the actual locking range is the programmed value
shifted by the system clock tolerance to become -300 ppm to +100 ppm.
8.5
Locking Time
The Locking Time is the time it takes the synchroniser to phase lock to the input signal. Phase lock occurs when the
input and output signals are not changing in phase with respect to each other (not including jitter).
Locking time is very difficult to determine because it is affected by many factors including:
•
initial input to output phase difference
•
initial input to output frequency difference
•
DPLL Loop Filter
•
DPLL Limiter (phase slope)
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Data Sheet
Although a short phase lock time is desirable, it is not always achievable due to other synchroniser requirements.
For instance, better jitter transfer performance is obtained with a lower frequency loop filter which increases locking
time; and a better (smaller) phase slope performance will increase locking time. Additionally, the locking time is
dependent on the p_shift value.
The DPLL Loop Filter and Limiter have been optimised to meet the Telcordia GR-1244-CORE jitter transfer and
phase alignment speed requirements. The phase lock time is guaranteed to be no greater than 30 seconds when
using the recommended Stratum 3 and Stratum 4/4E register settings.
8.6
Lock Status
The DPLL has a Lock Status Indicator and a corresponding Lock Change Interrupt. The response of the Lock
Status Indicator is a function of the programmed Lock Detect Interval (LDI) and Lock Detect Threshold (LDT) values
in the dpll_ldetect register. The LDT register can be programmed to set the jitter tolerance level of the Lock Status
Indicator. To determine if the DPLL has achieved lock the Lock Status Indicator must be high for a period of at least
30 seconds. When the DPLL loses lock the Lock Status Indicator will go low after LDI x 125 µs.
8.7
Jitter
The DPLL is designed to withstand, and improve inherent jitter in the TDM clock domain.
8.7.1
Acceptance of Input Wander
For T1(1.544 MHz), E1(2.048 MHz) and J2(6.312 MHz) input frequencies, the DPLL will accept a wander of up to
±1023UIpp at 0.1 Hz to conform with the relevant specifications. For the 8 kHz (frame rate) and 64 kHz (the divided
down output for T3/E3) input frequencies, the wander acceptance is limited to ±1 UI (0.1 Hz). This principle is
illustrated in Table 29.
8.7.2
Intrinsic Jitter
Intrinsic jitter is the jitter produced by a synchronizer and measured at its output. It is measured by applying a jitter
free reference signal to the input of the device, and measuring its output jitter. Intrinsic jitter may also be measured
when the device is in a non synchronizing mode such as free running or holdover, by measuring the output jitter of
the device. Intrinsic jitter is usually measured with various band-limiting filters, depending on the applicable
standards.
The intrinsic jitter in the DPLL is reduced to less than 1 ns p-p1 by an internal Tapped Delay Line (TDL).
8.7.3
Jitter Tolerance
Jitter tolerance is a measure of the ability of a PLL to operate properly without cycle slips (i.e. remain in lock and/or
regain lock in the presence of large jitter magnitudes at various jitter frequencies) when jitter is applied to its
reference. The applied jitter magnitude and the jitter frequency depends on the applicable standards.
The DPLL’s jitter tolerance can be programmed to meet Telcordia GR-1244-CORE DS1 reference input jitter
tolerance requirements.
8.7.4
Jitter Transfer
Jitter transfer or jitter attenuation refers to the magnitude of jitter at the output of a device for a given amount of jitter
at the input of the device. Input jitter is applied at various amplitudes and frequencies, and output jitter is measured
with various filters depending on the applicable standards.
1. There are 2 exceptions to this. a) When reference is 8 kHz, and reference frequency offset relative to the master is small, jitter up to 1 master
clock period is possible, i.e. 10 ns p-p. b) In holdover mode, if a huge amount of jitter had been present prior to entering holdover, then an
additional 2 ns p-p is possible.
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Data Sheet
Since intrinsic jitter is always present, jitter attenuation will appear to be lower for small input jitter signals than
larger ones. Consequently, accurate jitter transfer function measurements are usually made with large input jitter
signals (e.g., 75% of the specified maximum jitter tolerance).
The internal DPLL is a first order type 2 component, so a frequency offset doesn’t result in a phase offset. Stratum
3 requires a -3 dB frequency of less than 3 Hz. The nature of the filter results in some peaking, resulting in a -3 dB
frequency of 1.9 Hz and a 0.08 dB peak with a system clock frequency of 100 MHz assuming a p_shift value of 2.
The transfer function is illustrated in Figure 25 and in more detail in Figure 26. Increasing the p_shift value
increases the speed the DPLL will lock to the required frequency and reduces the peak, but also reduces the
tolerance to jitter - so the p_shift value must be programmed correctly to meet Stratum 3 or Stratum 4/4E jitter
transfer characteristics. This is done automatically in the API.
8.8
Maximum Time Interval Error (MTIE)
In order to meet several standards requirements, the phase shift of the DPLL output must be controlled. A potential
phase shift occurs every time the DPLL is re-arranged by changing reference source signal, or the mode. In order
to meet the requirements of Stratum 3, the DPLL will shift phase by no more than 20 ns per re-arrangement.
Additionally the speed at which the change occurs is also critical. A large step change in output frequency is
undesirable. The rate of change is programmable using the skew register, up to a maximum of 15.4 ns / 125 µs
(124 ppm).
Figure 25 - Jitter Transfer Function
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Data Sheet
Figure 26 - Jitter Transfer Function - Detail
9.0
Memory Map and Register Definitions
All memory map and register definitions are included in the ZL50110/11/12/14 Programmers Model document.
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10.0
Data Sheet
DC Characteristics
Absolute Maximum Ratings*
Parameter
Symbol
Min.
Max.
Units
VDD_IO
-0.5
5.0
V
Core Supply Voltage
VDD_CORE
-0.5
2.5
V
PLL Supply Voltage
VDD_PLL
-0.5
2.5
V
VI
-0.5
VDD + 0.5
V
Input Voltage (5 V tolerant inputs)
VI_5V
-0.5
7.0
V
Continuous current at digital inputs
IIN
-
±10
mA
Continuous current at digital outputs
IO
-
±15
mA
Package power dissipation
PD
-
3
W
Storage Temperature
TS
-55
+125
°C
I/O Supply Voltage
Input Voltage
* Exceeding these figures may cause permanent damage. Functional operation under these conditions is not guaranteed. Voltage
measurements are with respect to ground (VSS) unless otherwise stated.
* The core and PLL supply voltages must never be allowed to exceed the I/O supply voltage by more than 0.5 V during power-up. Failure to
observe this rule could lead to a high-current latch-up state, possibly leading to chip failure, if sufficient cross-supply current is available. To be
safe ensure the I/O supply voltage supply always rises earlier than the core and PLL supply voltages.
Recommended Operating Conditions
Characteristics
Symbol
Min.
Typ.
Max.
Units
TOP
-40
25
+85
°C
TJ
-40
-
125
°C
VDD_IO
3.0
3.3
3.6
V
Positive Supply Voltage, Core
VDD_CORE
1.65
1.8
1.95
V
Positive Supply Voltage, Core
VDD_PLL
1.65
1.8
1.95
V
Input Voltage Low - all inputs
VIL
-
-
0.8
V
Input Voltage High
VIH
2.0
-
VDD_IO
V
VIH_5V
2.0
-
5.5
V
Operating Temperature
Junction temperature
Positive Supply Voltage, I/O
Input Voltage High, 5V tolerant inputs
Test
Condition
Typical figures are at 25°C and are for design aid only, they are not guaranteed and not subject to production testing. Voltage measurements are
with respect to ground (VSS) unless otherwise stated.
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Data Sheet
DC Electrical Characteristics - Typical characteristics are at 1.8 V core, 3.3 V I/O, 25°C and typical processing. The min. and
max. values are defined over all process conditions, from -40 to 125°C junction temperature, core voltage 1.65 to 1.95 V and I/O
voltage 3.0 and 3.6 V unless otherwise stated.
Characteristics
Symbol
Min.
Typ.
Max.
Units.
Test Condition
Input Leakage
ILEIP
±1
µA
No pull up/down VDD_IO = 3.6 V
Output (High impedance)
Leakage
ILEOP
2
µA
No pull up/down VDD_IO = 3.6 V
Input Capacitance
CIP
1
pF
Output Capacitance
COP
4
pF
Pullup Current
IPU
-27
µA
Input at 0 V
IPU_5V
-110
µA
Input at 0 V
IPD
27
µA
Input at VDD_IO
IPD_5V
110
µA
Input at VDD_IO
Note 1,2
Pullup Current, 5 V tolerant
inputs
Pulldown Current
Pulldown Current, 5 V tolerant
inputs
Core 1.8 V supply current
IDD_CORE
950
mA
PLL 1.8 V supply current
IDD_PLL
1.30
mA
I/O 3.3 V supply current
IDD_IO
120
mA
Note 1,2
Note 1:
The IO and Core supply current worst case figures apply to different scenarios, e.g., internal or external memory and can not
simply be summed for a total figure. For a clearer indication of power consumption, please refer to Section 12.0
Note 2:
Worst case assumes the maximum number of active contexts and channels, i.e., 128 contexts/1024 channels. Figures are for
the ZL50111. For an indication of power consumption by the ZL50110 and ZL50114, please refer to Section 12.0 and choose
the appropriate memory configuration and number of contexts.
Input Levels
Characteristics
Symbol
Min.
Typ.
Max.
Units
0.8
V
Input Low Voltage
VIL
Input High Voltage
VIH
Positive Schmitt Threshold
VT+
1.6
V
Negative Schmitt Threshold
VT-
1.2
V
2.0
Test Condition
V
Output Levels
Characteristics
Symbol
Output Low Voltage
VOL
Output High Voltage
VOH
Min.
Typ.
Max.
Units
Test Condition
0.4
V
IOL = 6 mA.
IOL = 12 mA for packet interface
(m*) pins and GPIO pins.
IOL = 24 mA for LED pins.
V
IOH = 6 mA.
IOH = 12 mA for packet interface
(m*) pins and GPIO pins.
IOH = 24 mA for LED pins.
2.4
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Zarlink Semiconductor Inc.
ZL50110/11/12/14
11.0
AC Characteristics
11.1
TDM Interface Timing - ST-BUS
Data Sheet
The TDM Bus either operates in Slave mode, where the TDM clocks for each stream are provided by the device
sourcing the data, or Master mode, where the TDM clocks are generated from the ZL50110/11/12/14.
11.1.1
ST-BUS Slave Clock Mode
TDM ST-BUS Slave Timing Specification
Data Format
ST-BUS
8.192 Mbps
mode
ST-BUS
2.048 Mbps
mode
All Modes
Parameter
Symbol
Min.
Typ.
Max.
Units
Notes
TDM_CLKi Period
tC16IP
54
60
66
ns
TDM_CLKi High
tC16IH
27
-
33
ns
TDM_CLKi Low
tC16IL
27
-
33
ns
TDM_CLKi Period
tC4IP
-
244.1
-
ns
TDM_CLKi High
tC4IH
110
-
134
ns
TDM_CLKi Low
tC4IL
110
-
134
ns
TDM_F0i Width
8.192 Mbps
2.048 Mbps
tFOIW
50
200
-
300
TDM_F0i Setup Time
tFOIS
5
-
-
ns
With respect to
TDM_CLKi
falling edge
TDM_F0i Hold Time
tFOIH
5
-
-
ns
With respect to
TDM_CLKi
falling edge
TDM_STo Delay
tSTOD
1
-
20
ns
With respect to
TDM_CLKi
Load CL = 50 pF
TDM_STi Setup Time
tSTIS
5
-
-
ns
With respect to
TDM_CLKi
TDM_STi Hold Time
tSTIH
5
-
-
ns
With respect to
TDM_CLKi
ns
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Zarlink Semiconductor Inc.
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Data Sheet
In synchronous mode the clock must be within the locking range of the DPLL to function correctly (± 245 ppm). In
asynchronous mode, the clock may be any frequency.
Channel 127 bit 1
Channel 127 bit 0
Channel 0 bit 7
Channel 0 bit 6
tC16IP
TDM_CKLI
tFOIH
tFOIS
TDM_F0i
tSTIH
tSTIH
tSTIS
tSTIH
tSTIS
tSTIS
TDM_STi
Ch0 bit7
Channel 127 bit 1
TDM_STo
tSTOD
Channel 127 bit 0
tSTOD
Channel 0 bit 7
tSTOD
Figure 27 - TDM ST-BUS Slave Mode Timing at 8.192 Mbps
Channel 31 Bit 0
Channel 0 Bit 7
Channel 0 Bit 6
tC2IP
TDM_CLKI (2.048 MHz)
tC4IP
TDM_CLKI (4.096 MHz)
tFOIH
tFOIS
tFOIW
TDM_F0i
tSTIH
tSTIS
TDM_STi
tSTOD
tSTOD
TDM_STo
Ch 31 Bit 0
Ch 0 Bit 7
Ch 0 Bit 6
Figure 28 - TDM ST-BUS Slave Mode Timing at 2.048 Mbps
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Zarlink Semiconductor Inc.
ZL50110/11/12/14
11.1.2
Data Sheet
ST-BUS Master Clock Mode
Data Format
Parameter
Symbol
Min.
Typ.
Max.
Units
Notes
ST-BUS
8.192 Mbps
mode
TDM_CLKo Period
tC16OP
54.0
61.0
68.0
ns
TDM_CLKo High
tC16OH
23.0
-
37.0
ns
TDM_CLKo Low
tC16OL
23.0
-
37.0
ns
ST-BUS
2.048 Mbps
mode
TDM_CLKo Period
tC4OP
237.0
244.1
251.0
ns
TDM_CLKo High
tC4OH
115.0
-
129.0
ns
TDM_CLKo Low
tC4OL
115.0
-
129.0
ns
All Modes
TDM_F0o Delay
tFOD
-
-
25
ns
With respect to
TDM_CLKo
falling edge
TDM_STo Delay
Active-Active
tSTOD
-
-
5
ns
With respect to
TDM_CLKo
falling edge
TDM_STo Delay
Active to HiZ and
HiZ to Active
tDZ, tZD
-
-
33
ns
With respect to
TDM_CLKo
falling edge
TDM_STi Setup Time
tSTIS
5
-
-
ns
With respect to
TDM_CLKo
TDM_STi Hold Time
tSTIH
5
-
-
ns
With respect to
TDM_CLKo
Table 30 - TDM ST-BUS Master Timing Specification
Channel 127 Bit 0
Channel 0 Bit 7
Channel 0 Bit 6
tC16OP
TDM_CLKO
tFOD
tFOD
TDM_F0o
tSTIH
tSTIH
tSTIS
TDM_STi
tSTIS
B0
B7
tSTOD
TDM_STo
Ch 127 Bit 0
Ch 0 Bit 7
B6
tSTOD
Ch 0 Bit 6
Figure 29 - TDM Bus Master Mode Timing at 8.192 Mbps
84
Zarlink Semiconductor Inc.
ZL50110/11/12/14
Channel 31 Bit 0
Data Sheet
Channel 0 Bit 7
Channel 0 Bit 6
tC2OP
TDM_CLKO (2.048 MHz)
tC4OP
TDM_CLKO (4.096 MHz)
tFOD
tFOD
TDM_F0o
tSTIH
tSTIS
TDM_STi
tSTOD
TDM_STo
Ch 31 Bit 0
tSTOD
Ch 0 Bit 7
Ch 0 Bit 6
Figure 30 - TDM Bus Master Mode Timing at 2.048 Mbps
11.2
TDM Interface Timing - H.110 Mode
These parameters are based on the H.110 Specification from the Enterprise Computer Telephony Forum (ECTF)
1997.
Parameter
Symbol
Min.
Typ.
Max.
Units
TDM_C8 Period
tC8P
122.066-Φ
122
122.074+Φ
ns
TDM_C8 High
tC8H
63-Φ
-
69+Φ
ns
TDM_C8 Low
tC8L
63-Φ
-
69+Φ
ns
TDM_D Output Delay
tDOD
0
-
11
ns
Load - 12 pF
TDM_D Output to HiZ
tDOZ
-
-
33
ns
Load - 12 pF
Note 3
TDM_D HiZ to Output
tZDO
0
-
11
ns
Load - 12 pF
Note 3
TDM_D Input Delay to Valid
tDV
0
-
83
ns
Note 4
TDM_D Input Delay to Invalid
tDIV
102
-
112
ns
Note 4
TDM_FRAME width
tFP
90
122
180
ns
Note 5
TDM_FRAME setup
tFS
45
-
90
ns
TDM_FRAME hold
tFH
45
-
90
ns
F
0
-
10
ns
Phase Correction
Notes
Note 1
Note 2
Note 6
Table 31 - TDM H.110 Timing Specification
Note
Note
Note
Note
Note
1:
2:
3:
4:
5:
Note 6:
TDM_C8 and TDM_FRAME signals are required to meet the same timing standards and so are not defined independently.
TDM_C8 corresponds to pin TDM_CLKi.
tDOZ and t ZDO apply at every time-slot boundary.
Refer to H.110 Standard from Enterprise Computer Telephony Forum (ECTF) for the source of these numbers.
The TDM_FRAME signal is centred on the rising edge of TDM_C8. All timing measurements are based on this rising edge
point; TDM_FRAME corresponds to pin TDM_F0i.
Phase correction (Φ ) results from DPLL timing corrections.
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Zarlink Semiconductor Inc.
ZL50110/11/12/14
Ts 127 Bit 8
Data Sheet
Ts 0 Bit 1
tC8H
Ts 0 Bit 2
tC8L
tC8P
TDM_C8
tFH
tFS
tFP
TDM_FRAME
tDIV
tDV
TDM_D Input
tZDO
tDOD
tDOZ
TDM_D Output
Ts 127 Bit 8
Ts 0 Bit 1
Ts 0 Bit 2
Figure 31 - H.110 Timing Diagram
11.3
TDM Interface Timing - H-MVIP
These parameters are based on the Multi-Vendor Integration Protocol (MVIP) specification for an H-MVIP Bus,
Release 1.1a (1997).
Positive transitions of TDM_C2 are synchronous with the falling edges of TDM_C4 and TDM_C16. The signals
TDM_C2, TDM_C4 and TDM_C16 correspond with pins TDM_CLKi. The signals TDM_F0 correspond with pins
TDM_F0i. The signals TDM_HDS correspond with pins TDM_STi and TDM_STo.
Parameter
Symbol
Min.
Typ.
Max.
Units
TDM_C2 Period
tC2P
487.8
488.3
488.8
ns
TDM_C2 High
tC2H
220
-
268
ns
TDM_C2 Low
tC2L
220
-
268
ns
TDM_C4 Period
tC4P
243.9
244.1
244.4
ns
TDM_C4 High
tC4H
110
-
134
ns
TDM_C4 Low
tC4L
110
-
134
ns
TDM_C16 Period
tC16P
60.9
61.0
61.1
ns
TDM_C16 High
tC16H
30
-
31
ns
TDM_C16 Low
tC16L
30
-
31
ns
TDM_HDS Output Delay
tPD
-
-
30
ns
At
8.192 Mbps
TDM_HDS Output Delay
tPD
-
-
100
ns
At
2.048 Mbps
TDM_HDS Output to HiZ
tHZD
-
-
30
ns
Table 32 - TDM H-MVIP Timing Specification
86
Zarlink Semiconductor Inc.
Notes
ZL50110/11/12/14
Parameter
Data Sheet
Symbol
Min.
Typ.
Max.
Units
TDM_HDS Input Setup
tS
30
-
-
ns
TDM_HDS Input Hold
tH
30
-
-
ns
TDM_F0 width
tFW
200
244
300
ns
TDM_F0 setup
tFS
50
-
150
ns
TDM_F0 hold
tFH
50
-
150
ns
Notes
Table 32 - TDM H-MVIP Timing Specification (continued)
Ts 127 Bit 7
Ts 0 Bit 0
tC16P
Ts 0 Bit 1
tC16H
tC16L
TDM_C16
tFS
tFH
tFW
TDM_F0
tH
tS
TDM_HDS Input
tPD
tHZD
Ch 127 Bit 7
TDM_HDS Output
Ch 0 Bit 0
Figure 32 - TDM - H-MVIP Timing Diagram for 16 MHz Clock (8.192 Mbps)
11.4
TDM LIU Interface Timing
The TDM Interface can be used to directly drive into a Line Interface Unit (LIU). The interface can work in this mode
with E1, DS1, J2, E3 and DS3. The frame pulse is not present, just data and clock is transmitted and received.
Table 30 shows timing for DS3, which would be the most stringent requirement.
Parameter
Symbol
Min.
Typ.
Max.
22.353
Units
ns
TDM_TXCLK Period
tCTP
TDM_TXCLK High
tCTH
6.7
ns
TDM_TXCLK Low
tCTL
6.7
ns
TDM_RXCLK Period
tCRP
TDM_RXCLK High
tCRH
9.0
TDM_RXCLK Low
tCRL
9.0
TDM_TXDATA Output Delay
tPD
3
TDM_RXDATA Input Setup
tS
6
ns
TDM_RXDATA Input Hold
tH
3
ns
22.353
ns
ns
ns
-
10
Table 33 - TDM - LIU Structured Transmission/Reception
87
Zarlink Semiconductor Inc.
ns
Notes
DS3 clock
DS3 clock
ZL50110/11/12/14
tCTP
Data Sheet
tCTH
tCTL
TDM_TXCLK
tPD
TDM_TXDATA
tCRH
tCRP
tCRL
TDM_RXCLK
tS
tH
TDM_RXDATA
Figure 33 - TDM-LIU Structured Transmission/Reception
11.5
PAC Interface Timing
Parameter
Symbol
Min.
Typ.
Max.
Units
TDM_CLKiP High / Low
Pulsewidth
tCPP
10
-
-
ns
TDM_CLKiS High / Low
Pulsewidth
tCSP
10
-
-
ns
Notes
Table 34 - PAC Timing Specification
11.6
Packet Interface Timing
Data for the MII/GMII/TBI packet switching is based on Specification IEEE Std. 802.3 - 2000.
11.6.1
MII Transmit Timing
100 Mbps
Parameter
Symbol
Units
Min.
Typ.
Max.
Notes
TXCLK period
tCC
-
40
-
ns
TXCLK high time
tCHI
14
-
26
ns
TXCLK low time
tCLO
14
-
26
ns
TXCLK rise time
tCR
-
-
5
ns
TXCLK fall time
tCF
-
-
5
ns
TXCLK rise to TXD[3:0] active
delay (TXCLK rising edge)
tDV
1
-
25
ns
Load = 25 pF
TXCLK to TXEN active delay
(TXCLK rising edge)
tEV
1
-
25
ns
Load = 25 pF
Table 35 - MII Transmit Timing - 100 Mbps
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Zarlink Semiconductor Inc.
ZL50110/11/12/14
Data Sheet
100 Mbps
Parameter
Symbol
TXCLK to TXER active delay
(TXCLK rising edge)
Min.
Typ.
Max.
1
-
25
tER
Table 35 - MII Transmit Timing - 100 Mbps
tCC
tCL
tCH
TXCLK
tEV
tEV
TXEN
tDV
TXD[3:0]
tER
tER
TXER
Figure 34 - MII Transmit Timing Diagram
89
Zarlink Semiconductor Inc.
Units
Notes
ns
Load = 25 pF
ZL50110/11/12/14
11.6.2
Data Sheet
MII Receive Timing
100 Mbps
Parameter
Symbol
Units
Min.
Typ.
Max.
RXCLK period
tCC
-
40
-
ns
RXCLK high wide time
tCH
14
20
26
ns
RXCLK low wide time
tCL
14
20
26
ns
RXCLK rise time
tCR
-
-
5
ns
RXCLK fall time
tCF
-
-
5
ns
RXD[3:0] setup time (RXCLK
rising edge)
tDS
10
-
-
ns
RXD[3:0] hold time (RXCLK
rising edge)
tDH
5
-
-
ns
RXDV input setup time
(RXCLK rising edge)
tDVS
10
-
-
ns
RXDV input hold time (RXCLK
rising edge)
tDVH
5
-
-
ns
RXER input setup time (RXCL
edge)
tERS
10
-
-
ns
RXER input hold time (RXCLK
rising edge)
tERH
5
-
-
ns
Table 36 - MII Receive Timing - 100 Mbps
tCC
tCLO
tCHI
RXCLK
tDVS
tDVH
RXDV
tDH
tDS
RXD[3:0]
tERH
tERS
RXER
Figure 35 - MII Receive Timing Diagram
90
Zarlink Semiconductor Inc.
Notes
ZL50110/11/12/14
11.6.3
Data Sheet
GMII Transmit Timing
1000 Mbps
Parameter
Symbol
Units
Min.
Typ.
Max.
Notes
GTXCLK period
tGC
7.5
-
8.5
ns
GTXCLK high time
tGCH
2.5
-
-
ns
GTXCLK low time
tGCL
2.5
-
-
ns
GTXCLK rise time
tGCR
-
-
1
ns
GTXCLK fall time
tGCF
-
-
1
ns
GTXCLK rise to TXD[7:0]
active delay
tDV
1.5
-
6
ns
Load = 25 pF
GTXCLK rise to TXEN active
delay
tEV
2
-
6
ns
Load = 25 pF
GTXCLK rise to TXER active
delay
tER
1
-
6
ns
Load = 25 pF
Table 37 - GMII Transmit Timing - 1000 Mbps
tCC
tCL
tCH
GTXCLK
tEV
tEV
TXEN
tDV
TXD[3:0]
tER
tER
TXER
Figure 36 - GMII Transmit Timing Diagram
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11.6.4
Data Sheet
GMII Receive Timing
1000 Mbps
Parameter
Symbol
Units
Min.
Typ.
Max.
RXCLK period
tCC
7.5
-
8.5
ns
RXCLK high wide time
tCH
2.5
-
-
ns
RXCLK low wide time
tCL
2.5
-
-
ns
RXCLK rise time
tCR
-
-
1
ns
RXCLK fall time
tCF
-
-
1
ns
RXD[7:0] setup time (RXCLK
rising edge)
tDS
2
-
-
ns
RXD[7:0] hold time (RXCLK
rising edge)
tDH
1
-
-
ns
RXDV setup time (RXCLK
rising edge)
tDVS
2
-
-
ns
RXDV hold time (RXCLK
rising edge)
tDVH
1
-
-
ns
RXER setup time (RXCLK
rising edge)
tERS
2
-
-
ns
RXER hold time (RXCLK
rising edge)
tERH
1
-
-
ns
Table 38 - GMII Receive Timing - 1000 Mbps
tCC
tCLO
tCHI
RXCLK
tDVS
tDVH
RXDV
tDH
tDS
RXD[7:0]
tERH
tERS
RXER
Figure 37 - GMII Receive Timing Diagram
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Zarlink Semiconductor Inc.
Notes
ZL50110/11/12/14
11.6.5
Data Sheet
TBI Interface Timing
1000 Mbps
Parameter
Symbol
Units
Min.
Typ.
Max.
GTXCLK period
tGC
7.5
-
8.5
ns
GTXCLK high wide time
tGH
2.5
-
-
ns
GTXCLK low wide time
tGL
2.5
-
-
ns
TXD[9:0] Output Delay
(GTXCLK rising edge)
tDV
0.1
-
2.4
RCB0/RBC1 period
tRC
15
16
17
ns
RCB0/RBC1 high wide time
tRH
5
-
-
ns
RCB0/RBC1 low wide time
tRL
5
-
-
ns
RCB0/RBC1 rise time
tRR
-
-
2
ns
RCB0/RBC1 fall time
tRF
-
-
2
ns
RXD[9:0] setup time (RCB0
rising edge)
tDS
2
-
-
ns
RXD[9:0] hold time (RCB0
rising edge)
tDH
1
-
-
ns
REFCLK period
tFC
7.5
-
8.5
ns
REFCLK high wide time
tFH
2.5
-
-
ns
REFCLK low wide time
tFL
2.5
-
-
ns
Notes
Load = 10 pF
Note 1
Table 39 - TBI Timing - 1000 Mbps
Note1: These measurements were obtained through simulation and lab measurement using a 10pF load. See Application Note,
ZLAN-239 for proper operation when using the TBI interface.
tGC
GTXCLK
TXD[9:0]
/I/
tDV
/S/ /D/ /D/ /D/ /D/ /D/ /D/ /D/ /D/ /D/ /D/ /D/ /D/ /D/ /D/ /D/ /T/ /R/
Signal_Detect
Figure 38 - TBI Transmit Timing Diagram
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Zarlink Semiconductor Inc.
/I/
ZL50110/11/12/14
Data Sheet
tRC
RBC1
tRC
RBC0
tDH
/I/
RXD[9:0]
/S/ /D/
/D/
/D/
tDS
/D/ /D/
/D/
/D/
tDH
/D/
tDS
/D/ /D/
/D/
/D/
/T/
/R/
/I/
Signal_Detect
Figure 39 - TBI Receive Timing Diagram
11.6.6
Management Interface Timing
The management interface is common for all inputs and consists of a serial data I/O line and a clock line.
Parameter
Symbol
Min.
Typ.
Max.
Units
Notes
M_MDC Clock Output period
tMP
1990
2000
2010
ns
Note 1
M_MDC high
tMHI
900
1000
1100
ns
M_MDC low
tMLO
900
1000
1100
ns
M_MDC rise time
tMR
-
-
5
ns
M_MDC fall time
tMF
-
-
5
ns
M_MDIO setup time (MDC
rising edge)
tMS
10
-
-
ns
Note 1
M_MDIO hold time (M_MDC
rising edge)
tMH
0
-
-
ns
Note 1
M_MDIO Output Delay
(M_MDC falling edge)
tMD
1
-
300
ns
Note 2
Table 40 - MAC Management Timing Specification
Note 1:
Refer to Clause 22 in IEEE802.3 (2000) Standard for input/output signal timing characteristics.
Note 2:
Refer to Clause 22C.4 in IEEE802.3 (2000) Standard for output load description of MDIO.
tMHI
tMLO
M_MDC
tMS
tMH
M_MDIO
Figure 40 - Management Interface Timing for Ethernet Port - Read
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Zarlink Semiconductor Inc.
ZL50110/11/12/14
Data Sheet
tMP
Mn_MDC
tMD
Mn_MDIO
Figure 41 - Management Interface Timing for Ethernet Port - Write
11.7
External Memory Interface Timing
The timings for the External Memory Interface are based on the requirements of a ZBT-SRAM device, with the
system clock speed at 100 MHz.
Parameter
Symbol
Min.
Typ.
Max.
Units
Notes
RAM_DATA[63:0] Output Valid
Delay
tRDV
1
-
4
ns
Load CL = 30 pF
RAM_RW/RAM_ADDR[19:0]
Delay
tRAV
1
-
4
ns
Load CL = 30 pF
Note 1
RAM_BW[7:0]# Delay
tRBW
1
-
4
ns
Load CL = 30 pF
RAM_DATA[63:0] Setup Time
tRDS
2
-
-
ns
RAM_DATA[63:0] Hold Time
tRDH
0.5
-
-
ns
RAM_PARITY[7:0] Output Valid
Delay
tRPV
1
-
4
ns
RAM_PARITY[7:0] Setup Time
tRPS
2
-
-
ns
RAM_PARITY[7:0] Hold Time
tRPS
0.5
-
-
ns
Load CL = 30 pF
Table 41 - External Memory Timing
Note 1:
Must be capable of driving TWO separate RAM loads simultaneously.
n
Phase 1
Phase 2
Phase 3
Phase 4
Phase 5
Phase 6
A3
A4
A5
A6
Phase 7
Phase 8
SCLK
tRAV
RAM_ADDR[19:0]
A1
A1 - READ
tRAV
A2 - WRITE
A3 - WRITE
A6 - WRITE
A7
A8
tRAV
RAM_RW
A4 - READ
A5 - READ
tRAV
A2
tRBW
RAM_BW[7:0]
BW1
BW2
BW3
A7 - READ
A8 - WRITE
BW4
BW5
tRDH
tRDV
tRDS
RAM_DATA[63:0]
BW6
BW7
BW8
tRDH
D(A1)
Q(A2)
tRDS
Q(A3)
tRDV
D(A4)
D(A5)
Q(A6)
tRPH
tRPV
tRPS
RAM_PARITY[7:0]
P(A1)
P(A2)
tRPV
P(A3)
P(A4)
Figure 42 - External RAM Read and Write Timing
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P(A5)
P(A6)
ZL50110/11/12/14
11.8
Data Sheet
CPU Interface Timing
Parameter
Symbol
Min.
Typ.
Max.
15.152
Units
Notes
ns
CPU_CLK Period
tCC
CPU_CLK High Time
tCCH
6
ns
CPU_CLK Low Time
tCCL
6
ns
CPU_CLK Rise Time
tCCR
4
ns
CPU_CLK Fall Time
tCCF
4
ns
CPU_ADDR[23:2] Setup Time
tCAS
4
ns
CPU_ADDR[23:2] Hold Time
tCAH
2
ns
CPU_DATA[31:0] Setup Time
tCDS
4
ns
CPU_DATA[31:0] Hold Time
tCDH
2
ns
CPU_CS Setup Time
tCSS
4
ns
CPU_CS Hold Time
tCSH
2
ns
CPU_WE/CPU_OE Setup Time
tCES
5
ns
CPU_WE/CPU_OE Hold Time
tCEH
2
ns
CPU_TS_ALE Setup Time
tCTS
4
ns
CPU_TS_ALE Hold Time
tCTH
2
ns
CPU_SDACK1/CPU_SDACK2
Setup Time
tCKS
2
ns
CPU_SDACK1/CPU_SDACK2
Hold Time
tCKH
2
ns
Note 1
CPU_TA Output Valid Delay
tCTV
2
11.3
ns
Note 1, 2
CPU_DREQ0/CPU_DREQ1
Output Valid Delay
tCWV
2
6
ns
Note 1
CPU_IREQ0/CPU_IREQ1 Output
Valid Delay
tCRV
2
6
ns
Note 1
CPU_DATA[31:0] Output Valid
Delay
tCDV
2
7
ns
Note 1
CPU_CS to Output Data Valid
tSDV
3.2
10.4
ns
CPU_OE to Output Data Valid
tODV
3.3
10.4
ns
CPU_CLK(falling) to CPU_TA
Valid
tOTV
3.2
9.5
ns
Table 42 - CPU Timing Specification
Note 1:
Note 2:
Load = 50 pF maximum
The maximum value of t CTV may cause setup violations if directly connected to the MPC8260. See Section 13.2 for details of
how to accommodate this during board design.
The actual point where read/write data is transferred occurs at the positive clock edge following the assertion of
CPU_TA, not at the positive clock edge during the assertion of CPU_TA.
The CPU_TA maximum assertion time is 4 µs.
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Data Sheet
tCC
0 or more cycles
CPU_CLK
tCAH
tCAS
CPU_ADDR[23:2]
tCSS
tCSH
CPU_CS
tCES
tCEH
CPU_OE
CPU_WE
tCTS
tCTH
CPU_TS_ALE
tODV
tSDV
tODV
tSDV
tCDV
CPU_DATA[31:0]
tOTV
tCTV
tCTV
tOTV
CPU_TA
NOTE 1: CPU_DATA is valid when CPU_TA is asserted. CPU_DATA will remain valid while both CPU_CS
and CPU_OE are asserted. CPU_TA will continue to be driven until CPU_CS is deasserted.
CPU_CS and CPU_OE must BOTH be asserted to enable the CPU_DATA output.
NOTE 2: CPU_TS_ALE is no more than one clock cycle width and it can be delayed by one clock cycle from
CS assertion.
NOTE 3: The CPU_TA maximum assertion time is 4 µs.
Figure 43 - CPU Read - MPC8260
tCC
0 or more cycles
0 or more cycles
CPU_CLK
tCAS
tCAH
CPU_ADDR[23:2]
tCSS
tCSH
CPU_CS
CPU_OE
tCES
tCEH
CPU_WE
tCTH
tCTS
CPU_TS_ALE
tCDS
tCDH
CPU_DATA[31:0]
tOTV
tCTV
tCTV
tOTV
CPU_TA
NOTE 1: Following assertion of CPU_TA, CPU_CS may be deasserted. The MPC8260 will continue to assert CPU_CS
until CPU_TA has been synchronized internally. CPU_TA will continue to be driven until CPU_CS is
finally deasserted. During continued assertion of CPU_CS, CPU_WE and CPU_DATA may be removed.
NOTE 2: CPU_TS_ALE is no more than one clock cycle width and it can be delayed by one clock cycle from
CS assertion.
NOTE 3:The CPU_TA maximum assertion time is 4 µs.
Figure 44 - CPU Write - MPC8260
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Data Sheet
tCC
0 or more cycles
CPU_CLK
tCWV
tCWV
CPU_DREQ1
tCKH
tCKS
CPU_SDACK2
tCSS
tCSH
CPU_CS
tCES
tCEH
CPU_OE
CPU_WE
tCTH
tCTS
CPU_TS_ALE
tODV
tSDV
tODV
tSDV
tCDV
CPU_DATA[31:0]
tCTV
tOTV
tCTV
tOTV
CPU_TA
Note 1: CPU_SDACK2 must be asserted during the cycle shown. It may then be deasserted at any time. CPU_DATA is valid
when CPU_TA is asserted (always timed as shown). CPU_DATA will remain valid while CPU_CS and CPU_OE are asserted.
CPU_TA will continue to be driven until CPU_CS is deasserted. CPU_CS and CPU_OE must BOTH be asserted to enable
the CPU_DATA output.
Note 2: CPU_DREQ1 shown with positive polarity
CPU_SDACK1 shown with negative polarity
Figure 45 - CPU DMA Read - MPC8260
tCC
0 or more cycles
CPU_CLK
tCWV
tCWV
CPU_DREQ0
tCKH
tCKS
CPU_SDACK1
tCSS
tCSH
CPU_CS
CPU_OE
tCES
tCEH
CPU_WE
tCTH
tCTS
CPU_TS_ALE
tCDS
tCDH
CPU_DATA[31:0]
tOTV
tCTV
tCTV
CPU_TA
Note 1: CPU_SDACK1 must be asserted during the cycle shown. It may then be deasserted at any time.
Following assertion of CPU_TA (always timed as shown), CPU_CS may be deasserted. The MPC8260
will continue to assert CPU_CS until CPU_TA has been synchronized internally. CPU_TA will continue
to be driven until CPU_CS is finally deasserted. During continued assertion of CPU_CS, CPU_WE and
CPU_DATA may be removed.
Note 2: CPU_DREQ0 shown with positive polarity
CPU_SDACK1 shown with negative polarity
Figure 46 - CPU DMA Write - MPC8260
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ZL50110/11/12/14
11.9
Data Sheet
System Function Port
Parameter
Symbol
Min.
Typ.
Max.
Units
Notes
SYSTEM_CLK Frequency
CLKFR
-
100
-
MHz
Note 1, Note 2
and Note 5
SYSTEM_CLK accuracy
(synchronous master mode)
CLKACS
-
-
±30
ppm
Note 3
SYSTEM_CLK accuracy
(synchronous slave mode and
asynchronous mode)
CLKACA
-
-
±200
ppm
Note 4
Table 43 - System Clock Timing
Note 1:
The system clock frequency stability affects the holdover-operating mode of the DPLL. Holdover Mode is typically used for a
short duration while network synchronisation is temporarily disrupted. Drift on the system clock directly affects the Holdover
Mode accuracy. Note that the absolute system clock accuracy does not affect the Holdover accuracy, only the change in the
system clock (SYSTEM_CLK) accuracy while in Holdover. For example, if the system clock oscillator has a temperature
coefficient of 0.1 ppm/ºC, a 10ºC change in temperature while the DPLL is in will result in a frequency accuracy offset of
1ppm. The intrinsic frequency accuracy of the DPLL Holdover Mode is 0.06 ppm, excluding the system clock drift.
Note 2:
The system clock frequency affects the operation of the DPLL in free-run mode. In this mode, the DPLL provides timing and
synchronisation signals which are based on the frequency of the accuracy of the master clock (i.e. frequency of clock output
equals 8.192 MHz ± SYSTEM_CLK accuracy ± 0.005 ppm).
Note 3:
The absolute SYSTEM_CLK accuracy must be controlled to ± 30 ppm in synchronous master mode to enable the internal
DPLL to function correctly.
Note 4:
In asynchronous mode and in synchronous slave mode the DPLL is not used. Therefore the tolerance on SYSTEM_CLK may
be relaxed slightly.
Note 5:
The quality of SYSTEM_CLK, or the oscillator that drives SYSTEM_CLK directly impacts the adaptive clock recovery
performance. See Section 6.3.
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11.10
Data Sheet
JTAG Interface Timing
Parameter
Symbol
Min.
Typ.
Max.
JTAG_CLK period
tJCP
40
100
JTAG_CLK clock pulse width
tLOW,
tHIGH
20
-
-
Units
ns
ns
tJRF
0
-
3
ns
JTAG_TRST setup time
tRSTSU
10
-
-
ns
JTAG_TRST assert time
tRST
10
-
-
ns
JTAG_CLK rise and fall time
Notes
With respect to
JTAG_CLK
falling edge.
Note 1
Input data setup time
tJSU
5
-
-
ns
Note 2
Input Data hold time
tJH
15
-
-
ns
Note 2
JTAG_CLK to Output data valid
tJDV
0
-
20
ns
Note 3
JTAG_CLK to Output data high
impedance
tJZ
0
-
20
ns
Note 3
JTAG_TMS, JTAG_TDI setup time
tTPSU
5
-
-
ns
JTAG_TMS, JTAG_TDI hold time
tTPH
15
-
-
ns
tTOPDV
0
-
15
ns
tTPZ
0
-
15
ns
JTAG_TDO delay
JTAG_TDO delay to high
impedance
Table 44 - JTAG Interface Timing
Note 1:
JTAG_TRST is an asynchronous signal. The setup time is for test purposes only.
Note 2:
Non Test (other than JTAG_TDI and JTAG_TMS) signal input timing with respect to JTAG_CLK.
Note 3:
Non Test (other than JTAG_TDO) signal output with respect to JTAG_CLK.
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Data Sheet
tLOW
tHIGH
tJCP
JTAG_TCK
tTPH
tTPSU
JTAG_TMS
tTPSU
JTAG_TDI
tTPH
Don't Care
DC
tTPZ
tTOPDV
JTAG_TDO
HiZ
HiZ
Figure 47 - JTAG Signal Timing
tLOW
tHIGH
JTAG_TCK
tRST
tRSTSU
JTAG_TRST
Figure 48 - JTAG Clock and Reset Timing
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12.0
Data Sheet
Power Characteristics
The following graph in Figure 49 illustrates typical power consumption figures for the ZL50110/11/12/14 family.
Typical characteristics are at 1.8 V core, 3.3 V I/O, 25°C and typical processing. Power is plotted against the
number of active contexts, which is the dominant factor for power consumption.
ZL501x Power Consumption (Typical Conditions)
2
1.8
1.6
Power (W)
1.4
1.2
1
0.8
0.6
0.4
0.2
0
0
8
16
24
32
40
48
56
64
72
80
88
96 104 112 120 128
Number of Active Contexts
Figure 49 - ZL50110/11/12/14 Power Consumption Plot
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13.0
Data Sheet
Design and Layout Guidelines
This guide will provide information and guidance for PCB layouts when using the ZL50110/11/12/14. Specific areas
of guidance are:
•
High Speed Clock and Data, Outputs and Inputs
•
CPU_TA Output
13.1
High Speed Clock & Data Interfaces
On the ZL50110/11/12/14 series of devices there are four high-speed data interfaces that need consideration when
laying out a PCB to ensure correct termination of traces and the reduction of crosstalk noise. The interfaces being:
•
External Memory Interface
•
GMAC Interfaces
•
TDM Interface
•
CPU Interface
It is recommended that the outputs are suitably terminated using a series termination through a resistor as close to
the output pin as possible. The purpose of the series termination resistor is to reduce reflections on the line. The
value of the series termination and the length of trace the output can drive will depend on the driver output
impedance, the characteristic impedance of the PCB trace (recommend 50 ohm), the distributed trace capacitance
and the load capacitance. As a general rule of thumb, if the trace length is less than 1/6th of the equivalent length of
the rise and fall times, then a series termination may not be required.
the equivalent length of rise time = rise time (ps) / delay (ps/mm)
For example:
Typical FR4 board delay = 6.8 ps/mm
Typical rise/fall time for a ZL50110/11/12/14 output = 2.5 ns
critical track length = (1/6) x (2500/6.8) = 61 mm
Therefore tracks longer than 61 mm will require termination.
As a signal travels along a trace it creates a magnetic field, which induces noise voltages in adjacent traces, this is
crosstalk. If the crosstalk is of sufficiently strong amplitude, false data can be induced in the trace and therefore it
should be minimized in the layout. The voltage that the external fields cause is proportional to the strength of the
field and the length of the trace exposed to the field. Therefore to minimize the effect of crosstalk some basic
guidelines should be followed.
First, increase separation of sensitive signals, a rough rule of thumb is that doubling the separation reduces the
coupling by a factor of four. Alternatively, shield the victim traces from the aggressor by either routing on another
layer separated by a power plane (in a correctly decoupled design the power planes have the same AC potential) or
by placing guard traces between the signals usually held ground potential.
Particular effort should be made to minimize crosstalk from ZL50110/11/12/14 outputs and ensuring fast rise time to
these inputs.
In Summary:
•
Place series termination resistors as close to the pins as possible
•
Minimize output capacitance
•
Keep common interface traces close to the same length to avoid skew
•
Protect input clocks and signals from crosstalk
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13.1.1
Data Sheet
External Memory Interface - special considerations during layout
The timing of address, data and control are all related to the system clock which is also used by the external
SSRAM to clock these signals. Therefore the propagation delay of the clock to the ZL50110/11/12/14 and the
SSRAM must be matched to within 250 ps, worst case conditions. Trace lengths of theses signals must also be
minimized (<100 mm) and matched to ensure correct operation under all conditions.
13.1.2
GMAC Interface - special considerations during layout
The GMII interface passes data to and from the ZL50110/11/12/14 with their related transmit and receive clocks. It
is therefore recommended that the trace lengths for transmit related signals and their clock and the receive related
signals and their clock are kept to the same length. By doing this the skew between individual signals and their
related clock will be minimized.
13.1.3
TDM Interface - special considerations during layout
Although the data rate of this interface is low the outputs edge speeds share the characteristics of the higher data
rate outputs and therefore must be treated with the same care extended to the other interfaces with particular
reference to the lower stream numbers which support the higher data rates. The TDM interface has numerous
clocking schemes and as a result of this the input clock traces to the ZL50110/11/12/14 devices should be treated
with care.
13.1.4
Summary
Particular effort should be made to minimize crosstalk from ZL50110/11/12/14 outputs and ensuring fast rise time to
these inputs.
In Summary:
•
Place series termination resistors as close to the pins as possible
•
Minimize output capacitance
•
Keep common interface traces close to the same length to avoid skew
•
Protect input clocks and signals from crosstalk
13.2
CPU TA Output
The CPU_TA output signal from the ZL50110/11/12/14 is a critical handshake signal to the CPU that ensures the
correct completion of a bus transaction between the two devices. As the signal is critical, it is recommend that the
circuit shown in Figure 50 - CPU_TA Board Circuit is implemented in systems operating above 40 MHz bus
frequency to ensure robust operation under all conditions.
The following external logic is required to implement the circuit:
•
74LCX74 dual D-type flip-flop (one section of two)
•
74LCX08 quad AND gate (one section of four)
•
74LCX125 quad tri-state buffer (one section of four)
•
4K7 resistor x2
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Data Sheet
+3V3
+3V3
R2
4K7
R1
4K7
CPU_TA
from ZL50110/11/12/14
CPU_TA
to CPU
D
CPU_CLK
to ZL50110/11/12/14
Q
CPU_CS
to ZL50110/11/14
Figure 50 - CPU_TA Board Circuit
The function of the circuit is to extend the TA signal, to ensure the CPU correctly registers it. Resistor R2 must be
fitted to ensure correct operation of the TA input to the processor. It is recommended that the logic is fitted close to
the ZL50110/11/12/14 and that the clock to the 74LCX74 is derived from the same clock source as that input to the
ZL50110/11/12/14.
13.3
Mx_LINKUP_LED Outputs
The ZL50111/2 and ZL50110/4 have different Mx_LINKUP_LED pin assignments as shown in Table 46.
Signal
ZL50111/2 Pin
ZL50110/4 Pin
M0_LINKUP_LED
AB23
G24
M1_LINKUP_LED
F26
G23
M2_LINKUP_LED
G23
NC
M3_LINKUP_LED
G24
NC
Table 45 - Mx_LINKUP_LED Pin Assignments
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Data Sheet
To generate a pin for pin compatible PCB for all three variants, the following stuffing options may be used as shown
in Figure 51. For the ZL50111 and ZL50112 variants, resistors R4 and R6 are not populated. For the ZL50110 and
ZL50114 variants, resistors R1, R2, R3 and R5 as well as LEDs for M2 and M3 are not populated.
VDD_IO
M0_LINKUP_LED
R1
M0_LINKUP_LED
(AB23)
VDD_IO
M1_LINKUP_LED
M1_LINKUP_LED
(F26)
R2
VDD_IO
ZL50110/1/4
M2_LINKUP_LED
M1/2_LINKUP_LED
(G23)
R3
R4
VDD_IO
M3_LINKUP_LED
M0/3_LINKUP_LED
(G24)
R5
R6
Figure 51 - Mx_LINKUP_LED Stuffing Option
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Data Sheet
Table 46 lists the various components that are used for each variant.
Component
ZL50111/2
ZL50110/4
R1
√
-
R2
√
-
R3
√
-
R4
-
√
R5
√
-
R6
-
√
M0 LED
√
√
M1 LED
√
√
M2 LED
√
-
M3 LED
√
-
Table 46 - Mx_LINKUP_LED Stuffing Option
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14.0
Reference Documents
14.1
External Standards/Specifications
Data Sheet
•
IEEE Standard 1149.1-2001; Test Access Port and Boundary Scan Architecture
•
IEEE Standard 802.3-2000; Local and Metropolitan Networks CSMA/CD Access Method and Physical Layer
•
ECTF H.110 Revision 1.0; Hardware Compatibility Specification
•
H-MVIP (GO-MVIP) Standard Release 1.1a; Multi-Vendor Integration Protocol
•
MPC8260AEC/D Revision 0.7; Motorola MPC8260 Family Hardware Specification
•
RFC 768; UDP
•
RFC 791; IPv4
•
RFC 2460; IPv6
•
RFC 1889; RTP
•
RFC 2661; L2TP
•
RFC 1213; MIB II
•
RFC 1757; Remote Network Monitoring MIB (for SMIv1)
•
RFC 2819; Remote Network Monitoring MIB (for SMIv2)
•
RFC 2863; Interfaces Group MIB
•
CCITT G.712; TDM Timing Specification (Method 2)
•
G.823; Control of Jitter/Wander with digital networks based on the 2.048 Mbps hierarchy
•
G.824; Control of Jitter/Wander with digital networks based on the 1.544 Mbps hierarchy
•
G.8261; Timing and Synchronization aspects in Packet Networks
•
ANSI T1.101 Stratum 3/4
•
Telcordia GR-1244-CORE Stratum 3/4/4e
•
IETF PWE3 draft-ietf-l2tpext-l2tp-base
•
IETF PWE3 draft-ietf-pwe3-cesop
•
RFC4553; Structure-Agnostic TDM over Packet (SAToP)
•
ITU-T Y.1413 TDM-MPLS Network Interworking
•
Optional Packet Memory Device - Micron MT55L128L32P1 8 Mb ZBT-SRAM
14.2
•
Zarlink Standards
MSAN-126 Revision B, Issue 4; ST-BUS Generic Device Specification
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15.0
Data Sheet
Glossary
API
Application Program Interface
ATM
Asynchronous Transfer Mode
CDP
Context Descriptor Protocol (the protocol used by Zarlink’s MT9088x family of TDM-Packet devices)
CESoP
Circuit Emulation Services over Packet
CESoPSN Circuit Emulation Services over Packet Switched Networks (draft-ietf-pwe3-cesopsn)
CONTEXT A programmed connection of a number of TDM timeslots assembled into a unique packet stream.
CPU
Central Processing Unit
DMA
Direct Memory Access
DPLL
Digital Phase Locked Loop
DSP
Digital Signal Processor
GMII
Gigabit Media Independent Interface
H.100/H.110High capacity TDM backplane standards
H-MVIP
High-performance Multi-Vendor Integration Protocol (a TDM bus standard)
IA
Implementation Agreement
IETF
Internet Engineering Task Force
IP
Internet Protocol (version 4, RFC 791, version 6, RFC 2460)
JTAG
Joint Test Algorithms Group (generally used to refer to a standard way of providing a board-level test
facility)
L2TP
Layer 2 Tunneling Protocol (RFC 2661)
LAN
Local Area Network
LIU
Line Interface Unit
MAC
Media Access Control
MEF
Metro Ethernet Forum
MFA
MPLS and Frame Relay Alliance
MII
Media Independent Interface
MIB
Management Information Base
MPLS
Multi Protocol Label Switching
MTIE
Maximum Time Interval Error
MVIP
Multi-Vendor Integration Protocol (a TDM bus standard)
OC3
Optical Carrier 3 - 155.52 Mbps leased line
PDH
Plesiochronous Digital Hierarchy
PLL
Phase Locked Loop
PRS
Primary Reference Source
PRX
Packet Receive
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PSTN
Public Switched Telephone Circuit
PTX
Packet Transmit
PWE3
Pseudo-Wire Emulation Edge to Edge (a working group of the IETF)
QOS
Quality of Service
RTP
Real Time Protocol (RFC 1889)
PE
Protocol Engine
SAToP
Structure-Agnostic Transport over Packet
SSRAM
Synchronous Static Random Access Memory
ST BUS
Standard Telecom Bus, a standard interface for TDM data streams
TDL
Tapped Delay Line
TDM
Time Division Multiplexing
UDP
User Datagram Protocol (RFC 768)
UI
Unit Interval
VLAN
Virtual Local Area Network
WFQ
Weighted Fair Queuing
ZBT
Zero Bus Turnaround, a type of synchronous SRAM
110
Zarlink Semiconductor Inc.
Data Sheet
Package Code
c Zarlink Semiconductor 2003 All rights reserved.
ISSUE
1
ACN
213837
DATE
12Dec02
APPRD.
2
19Aug03
Previous package codes
For more information about all Zarlink products
visit our Web Site at
www.zarlink.com
Information relating to products and services furnished herein by Zarlink Semiconductor Inc. or its subsidiaries (collectively “Zarlink”) is believed to be reliable.
However, Zarlink assumes no liability for errors that may appear in this publication, or for liability otherwise arising from the application or use of any such
information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or
use. Neither the supply of such information or purchase of product or service conveys any license, either express or implied, under patents or other intellectual
property rights owned by Zarlink or licensed from third parties by Zarlink, whatsoever. Purchasers of products are also hereby notified that the use of product in
certain ways or in combination with Zarlink, or non-Zarlink furnished goods or services may infringe patents or other intellectual property rights owned by Zarlink.
This publication is issued to provide information only and (unless agreed by Zarlink in writing) may not be used, applied or reproduced for any purpose nor form part
of any order or contract nor to be regarded as a representation relating to the products or services concerned. The products, their specifications, services and other
information appearing in this publication are subject to change by Zarlink without notice. No warranty or guarantee express or implied is made regarding the
capability, performance or suitability of any product or service. Information concerning possible methods of use is provided as a guide only and does not constitute
any guarantee that such methods of use will be satisfactory in a specific piece of equipment. It is the user’s responsibility to fully determine the performance and
suitability of any equipment using such information and to ensure that any publication or data used is up to date and has not been superseded. Manufacturing does
not necessarily include testing of all functions or parameters. These products are not suitable for use in any medical products whose failure to perform may result in
significant injury or death to the user. All products and materials are sold and services provided subject to Zarlink’s conditions of sale which are available on request.
Purchase of Zarlink’s I2C components conveys a licence under the Philips I2C Patent rights to use these components in and I2C System, provided that the system
conforms to the I2C Standard Specification as defined by Philips.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright Zarlink Semiconductor Inc. All Rights Reserved.
TECHNICAL DOCUMENTATION - NOT FOR RESALE