CESoP PROCESSORS ZL50118/19/20 PRODUCT PREVIEW The ZL50120 family of low-density Circuit Emulation Services-over-Packet processors offers a powerful and flexible approach to carrying TDM voice and data traffic, with associated timing and signaling, across Ethernet, IP, and MPLS networks. Each device provides a flexible TDM interface with embedded timing that fully meets T1/E1 timing and synchronization standards, allowing a seamless interface with T1/E1 equipment. With an integrated digital PLL, internal jitter buffer memory and dual packet interface, the ZL50120 family reduces bill of material costs and board space, and simplifies access equipment design. Complimenting the ZL50111 family of high-density CES-over-Packet chips, Zarlink offers a complete portfolio of bridging devices capable of sending from one to 32 T1/E1 streams of TDM traffic over any PSN (packet-switched network). ;-4JNQMJmFE#MPDL%JBHSBN 5&PS 5&QPSUPS )).7*1 45#64 CBDLQMBOF .CQT &UIFSOFU .VMUJ1SPUPDPM 1BDLFU 1SPDFTTJOH &OHJOF %VBM 1BDLFU *OUFSGBDF ."$ $&4P14/4"5P1 3516%1*1W*1W .1-4&$*%7-"/ 6TFS%FmOFE .**(.**5#* -*6'SBNFS #BDLQMBOF 1FSQPSU%$0 GPS$MPDL 3FDPWFSZ .CQT PS(CQT &UIFSOFU +JUUFS#VGGFS$PNQFOTBUJPOGPSNTPG1BDLFU%FMBZ7BSJBUJPO %VBM3FGFSFODF 4UBSUVN%1-- )PTU1SPDFTTPS *OUFSGBDF Nx64 kbps trunking enables traffic grooming, fractional T1/E1 services Fast Ethernet port allows Ethernet and TDM traffic aggregation, simplifying system-level design Programmable multi-protocol packet encapsulation supports RTP, UDP, Ethernet VLANs, IPv4, IPv6 and evolving MPLS, PWE3 and MEF Circuit Emulation standards Patented hardware/software techniques for clock recovery and synchronization Advanced QoS mechanism allows traffic prioritization Extremely low and stable latency, intrinsic delays < 500 microseconds Embedded Timing 0O$IJQ.FNPSZ #BDLQMBOF $MPDLT Flexible TDM access interface supports T1/E1, T3/E3, H.110, HMVIP and ST-BUS streams Carrier-Grade Voice Quality $IBOOFM$&4P11SPDFTTPS 5%. *OUFSGBDF CESoP Processors Expand Reach +5"( ZL50118 1 T1 or 1 E1 stream or 1 MVIP/ST-BUS stream at 2.048 Mbps or 1 H.110/H-MVIP/ST-BUS streams at 8.192 Mbps ZL50119 2 T1 or 2 E1 streams or 2 MVIP/ST-BUS streams at 2.048 Mbps or 1 H.110/H-MVIP/ST-BUS streams at 8.192 Mbps ZL50120 4 T1 or 4 E1 streams or 1 J2, 1 T3, 1 E3 or 1 STS-1 stream or 4 MVIP/ST-BUS streams at 2.048 Mbps or 1 H.110/H-MVIP/ST-BUS streams at 8.192 Mbps Applications TDM traffic over packet networks 3G Wireless Backhaul PON, FTTx, Broadband access IP DSLAM, NG-DLC TDM over Wi-Fi and WiMAX MDU/MTU Embedded timing recovers clocks across packet networks Per-port T1/E1 clock recovery in unstructured CES mode Adaptive clock recovery meets G.823 for E1, G.824 for T1 timing Dual-reference Stratum 3 DPLL supports TDM H.110 and HMVIP master/slave timing operation Standard Compliant ITU-T recommendation Y.1413 IETF PWE3 draft standards CESoPSN and SAToP MEF implementation agreement for PDH circuits MPLS forum draft CESoMPLS implementation agreement Evaluation boards and API are available ZL50118/19/20 CESoP PROCESSORS APPLICATION EPON (Ethernet Passive Optical Network) Facing growing data traffic volumes and increased compe- The per-port DCO (Digitally Controlled Oscillator) ensures tition, carriers are extending their packet networks to cost- precise synchronization of TDM and T1/E1 traffic across effectively deliver multiple services to end users. an EPON. Patented hardware/software techniques support The diagram below shows how the ZL50120 low-density adaptive and differential timing and synchronization. CES-over-Packet processor may be used in the ONU/ONT The dual Ethernet interface enables local Ethernet and TDM (Optical Networking Unit/Terminal) of an EPON (Ethernet traffic to be aggregated onto the Fast/Gigabit Ethernet net- Passive Optical Network) to provide POTS, T1/E1, fractional work uplink. T1/E1 and Ethernet services. Together with the high-density ZL50111 CESoP processor The flexible TDM interface allows the device to be used di- located in the Central Office’s OLT (Optical Line Terminal), rectly with CODECs and framers in structured CES mode. In Zarlink offers the industry’s only end-to-end portfolio of cir- unstructured CES mode, the device interfaces directly to LIUs cuit-to-packet devices for carrying TDM traffic over packet providing independent timing recovery for each TDM port. networks. $VTUPNFS1SFNJTFT $FOUSBM0GmDF 1054 5& &UIFSOFU 0-5 0/6 0/5 0QUJDBM 4QMJUUFS 6QUP -PDBUJPOT 6QUP7PJDF 4VCTDSJCFSTPS5& 1054 145/ $I $&4P1 1SPDFTTPS ;- *1 0/60/5 4-*$T $PEFDT 4USVDUFSFE $&4.PEF 'SBDUJPOBM 5& 5& &UIFSOFU 5SBGmD 5& 5SBOTDFJWFS .5 5& 5SBOTDFJWFS .5 .CQT &UIFSOFU 1IZ 6OTUSVDUFSFE $&4.PEF $IBOOFM $&4P1 1SPDFTTPS ;- .**(.**5#* /FUXPSL 6QMJOL1PSU &10/ ."$ .**6TFS 1PSU Information relating to products and services furnished herein by Zarlink Semiconductor Inc. or its subsidiaries is believed to be reliable. The products, their specifications, services and other information appearing in this publication are subject to change by Zarlink without notice. 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