CYPRESS CY7C1480BV33

CY7C1480BV33, CY7C1482BV33, CY7C1486BV33
72-Mbit (2 M × 36/4 M × 18/1 M × 72)
Pipelined Sync SRAM
72-Mbit (2 M × 36/4 M × 18/1 M × 72) Pipelined Sync SRAM
Features
Functional Description
■
Supports bus operation up to 250 MHz
■
Available speed grades are 250, 200, and 167 MHz
■
Registered inputs and outputs for pipelined operation
■
3.3 V core power supply
■
2.5 V/3.3 V I/O operation
■
Fast clock-to-output times
❐ 3.0 ns (for 250 MHz device)
■
Provide high performance 3-1-1-1 access rate
The CY7C1480BV33, CY7C1482BV33, and CY7C1486BV33
SRAM integrates 2 M × 36/4 M × 18/1 M × 72 SRAM cells with
advanced synchronous peripheral circuitry and a 2-bit counter
for internal burst operation. All synchronous inputs are gated by
registers controlled by a positive-edge-triggered Clock Input
(CLK). The synchronous inputs include all addresses, all data
inputs, address-pipelining Chip Enable (CE1), depth-expansion
Chip Enables (CE2 and CE3), Burst Control inputs (ADSC,
ADSP, and ADV), Write Enables (BWX, and BWE), and Global
Write (GW). Asynchronous inputs include the Output Enable
(OE) and the ZZ pin.
■
User selectable burst counter supporting Intel® Pentium®
interleaved or linear burst sequences
■
Separate processor and controller address strobes
■
Synchronous self timed writes
■
Asynchronous output enable
■
Single cycle chip deselect
■
CY7C1480BV33, CY7C1482BV33 available in JEDECstandard Pb-free 100-pin thin quad flat pack (TQFP), Pb-free
and non Pb-free 165-ball fine-pitch ball grid array (FBGA)
package. CY7C1486BV33 available in Pb-free and
non-Pb-free 209-ball FBGA package
■
IEEE 1149.1 JTAG-compatible boundary scan
■
“ZZ” sleep mode option
Addresses and chip enables are registered at the rising edge of
the clock when either address strobe processor (ADSP) or
Address Strobe Controller (ADSC) are active. Subsequent burst
addresses may be internally generated as controlled by the
advance pin (ADV).
Address, data inputs, and write controls are registered on-chip
to initiate a self timed write cycle.This part supports byte write
operations (see sections Pin Definitions on page 8 and Truth
Table on page 11 for further details). Write cycles can be one to
two or four bytes wide as controlled by the byte write control
inputs. GW when active LOW causes all bytes to be written.
The CY7C1480BV33, CY7C1482BV33, and CY7C1486BV33
operates from a +3.3 V core power supply while all outputs may
operate with either a +2.5 or +3.3 V supply. All inputs and outputs
are JEDEC standard JESD8-5 compatible. For best practices
recommendations, refer to the Cypress application note AN1064
“SRAM System Guidelines”.
Selection Guide
Description
250 MHz
200 MHz
167 MHz
Unit
Maximum access time
3.0
3.0
3.4
ns
Maximum operating current
500
500
450
mA
Maximum CMOS standby current
120
120
120
mA
Cypress Semiconductor Corporation
Document Number: 001-15145 Rev. *F
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised June 30, 2011
[+] Feedback
CY7C1480BV33, CY7C1482BV33, CY7C1486BV33
Logic Block Diagram – CY7C1480BV33 (2 M × 36)
A 0, A1, A
ADDRESS
REGISTER
2
A [1:0]
MODE
ADV
CLK
Q1
BURST
COUNTER
CLR AND
LOGIC
ADSC
Q0
ADSP
BW D
DQ D ,DQP D
BYTE
WRITE REGISTER
DQ D ,DQPD
BYTE
WRITE DRIVER
BW C
DQ C ,DQP C
BYTE
WRITE REGISTER
DQ C ,DQP C
BYTE
WRITE DRIVER
DQ B ,DQP B
BYTE
WRITE REGISTER
DQ B ,DQP B
BYTE
WRITE DRIVER
BW B
BW A
BWE
ZZ
SENSE
AMPS
OUTPUT
REGISTERS
OUTPUT
BUFFERS
E
DQs
DQP A
DQP B
DQP C
DQP D
DQ A ,DQP A
BYTE
WRITE DRIVER
DQ A ,DQP A
BYTE
WRITE REGISTER
GW
CE 1
CE 2
CE 3
OE
MEMORY
ARRAY
ENABLE
REGISTER
INPUT
REGISTERS
PIPELINED
ENABLE
SLEEP
CONTROL
Logic Block Diagram – CY7C1482BV33 (4 M × 18)
A0, A1, A
ADDRESS
REGISTER
2
MODE
A[1:0]
BURST Q1
COUNTER AND
LOGIC
CLR
Q0
ADV
CLK
ADSC
ADSP
BW B
DQ B, DQP B
WRITE DRIVER
DQ B, DQP B
WRITE REGISTER
MEMORY
ARRAY
BW A
DQ A, DQP A
WRITE DRIVER
DQ A, DQP A
WRITE REGISTER
SENSE
AMPS
OUTPUT
REGISTERS
OUTPUT
BUFFERS
DQs
DQP A
DQP B
E
BWE
GW
CE 1
CE2
CE3
ENABLE
REGISTER
PIPELINED
ENABLE
INPUT
REGISTERS
OE
ZZ
SLEEP
CONTROL
Document Number: 001-15145 Rev. *F
Page 2 of 36
[+] Feedback
CY7C1480BV33, CY7C1482BV33, CY7C1486BV33
Logic Block Diagram – CY7C1486BV33 (1 M × 72)
ADDRESS
REGISTER
A 0, A1,A
A[1:0]
MODE
Q1
BINARY
COUNTER
CLR
Q0
ADV
CLK
ADSC
ADSP
BW H
DQ H , DQPH
WRITE DRIVER
DQ H , DQPH
WRITE DRIVER
BW G
DQ F, DQPF
WRITE DRIVER
DQ G , DQPG
WRITE DRIVER
BW F
DQ F, DQPF
WRITE DRIVER
DQ F, DQPF
WRITE DRIVER
BW E
DQ E , DQPE
WRITE DRIVER
DQ
E , DQP
BYTE
“a” E
WRITE DRIVER
BW D
DQ D , DQPD
WRITE DRIVER
DQ D , DQPD
WRITE DRIVER
BW C
DQ C, DQPC
WRITE DRIVER
DQ C, DQPC
WRITE DRIVER
MEMORY
ARRAY
SENSE
AMPS
BW B
BW A
BWE
GW
CE1
CE2
CE3
OE
ZZ
DQ B , DQPB
WRITE DRIVER
DQ B , DQPB
WRITE DRIVER
OUTPUT
BUFFERS
E
DQ A , DQPA
WRITE DRIVER
DQ A , DQPA
WRITE DRIVER
ENABLE
REGISTER
OUTPUT
REGISTERS
PIPELINED
ENABLE
INPUT
REGISTERS
DQs
DQP A
DQP B
DQP C
DQP D
DQP E
DQP F
DQP G
DQP H
SLEEP
CONTROL
Document Number: 001-15145 Rev. *F
Page 3 of 36
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CY7C1480BV33, CY7C1482BV33, CY7C1486BV33
Contents
Pin Configurations ........................................................... 5
Pin Definitions .................................................................. 8
Functional Overview ........................................................ 9
Single Read Accesses ................................................ 9
Single Write Accesses Initiated by ADSP ................... 9
Single Write Accesses Initiated by ADSC ................. 10
Burst Sequences ....................................................... 10
Sleep Mode ............................................................... 10
Interleaved Burst Address Table
(MODE = Floating or VDD) ............................................. 10
Linear Burst Address Table (MODE = GND) ................ 10
ZZ Mode Electrical Characteristics ............................... 10
Truth Table ...................................................................... 11
Truth Table for Read/Write ............................................ 12
Truth Table for Read/Write ............................................ 12
Truth Table for Read/Write ............................................ 12
IEEE 1149.1 Serial Boundary Scan (JTAG) .................. 13
Disabling the JTAG Feature ...................................... 13
Test Access Port (TAP) ............................................. 13
PERFORMING A TAP RESET .................................. 13
TAP REGISTERS ...................................................... 13
TAP Instruction Set ................................................... 14
TAP Controller State Diagram ....................................... 15
TAP Controller Block Diagram ...................................... 16
3.3-V TAP AC Test Conditions ...................................... 17
3.3-V TAP AC Output Load Equivalent ......................... 17
2.5-V TAP AC Test Conditions ...................................... 17
2.5-V TAP AC Output Load Equivalent ......................... 17
TAP DC Electrical Characteristics
and Operating Conditions ............................................. 17
Document Number: 001-15145 Rev. *F
TAP AC Switching Characteristics ............................... 18
TAP Timing ...................................................................... 18
Identification Register Definitions ................................ 19
Scan Register Sizes ....................................................... 19
Identification Codes ....................................................... 19
Boundary Scan Exit Order (2 M × 36) ........................... 20
Boundary Scan Exit Order (4 M × 18) ........................... 20
Boundary Scan Exit Order (1 M × 72) ........................... 21
Maximum Ratings ........................................................... 22
Operating Range ............................................................. 22
Electrical Characteristics ............................................... 22
Capacitance .................................................................... 23
Thermal Resistance ........................................................ 23
Switching Characteristics .............................................. 25
Switching Waveforms .................................................... 26
Ordering Information ...................................................... 30
Ordering Code Definitions ......................................... 30
Package Diagrams .......................................................... 31
Reference Information ................................................... 34
Acronyms .................................................................. 34
Document Conventions ............................................. 34
Document History Page ................................................. 35
Sales, Solutions, and Legal Information ...................... 36
Worldwide Sales and Design Support ....................... 36
Products .................................................................... 36
PSoC Solutions ......................................................... 36
Page 4 of 36
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CY7C1480BV33, CY7C1482BV33, CY7C1486BV33
Pin Configurations
Figure 2. CY7C1482BV33 100-pin TQFP Pinout
NC
NC
NC
VDDQ
VSSQ
NC
NC
DQB
DQB
VSSQ
VDDQ
DQB
DQB
NC
VDD
NC
VSS
DQB
DQB
VDDQ
VSSQ
DQB
DQB
DQPB
NC
VSSQ
VDDQ
NC
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
CY7C1482BV33
(4 M × 18)
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
Document Number: 001-15145 Rev. *F
A
NC
NC
VDDQ
VSSQ
NC
DQPA
DQA
DQA
VSSQ
VDDQ
DQA
DQA
VSS
NC
VDD
ZZ
DQA
DQA
VDDQ
VSSQ
DQA
DQA
NC
NC
VSSQ
VDDQ
NC
NC
NC
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
DQPB
DQB
DQB
VDDQ
VSSQ
DQB
DQB
DQB
DQB
VSSQ
VDDQ
DQB
DQB
VSS
NC
VDD
ZZ
DQA
DQA
VDDQ
VSSQ
DQA
DQA
DQA
DQA
VSSQ
VDDQ
DQA
DQA
DQPA
MODE
A
A
A
A
A1
A0
A
A
VSS
VDD
CY7C1480BV33
(2 M × 36)
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
MODE
A
A
A
A
A1
A0
A
A
VSS
VDD
DQPC
DQC
DQc
VDDQ
VSSQ
DQC
DQC
DQC
DQC
VSSQ
VDDQ
DQC
DQC
NC
VDD
NC
VSS
DQD
DQD
VDDQ
VSSQ
DQD
DQD
DQD
DQD
VSSQ
VDDQ
DQD
DQD
DQPD
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
A
A
CE1
CE2
NC
NC
BWB
BWA
CE3
VDD
VSS
CLK
GW
BWE
OE
ADSC
ADSP
ADV
A
A
A
A
CE1
CE2
BWD
BWC
BWB
BWA
CE3
VDD
VSS
CLK
GW
BWE
OE
ADSC
ADSP
ADV
A
A
Figure 1. CY7C1480BV33 100-pin TQFP Pinout
Page 5 of 36
[+] Feedback
CY7C1480BV33, CY7C1482BV33, CY7C1486BV33
Pin Configurations (continued)
165-ball FBGA (15 × 17 × 1.4 mm) Pinout
CY7C1480BV33 (2 M × 36)
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
NC/288M
R
2
3
4
5
6
7
8
9
10
11
NC
CE1
BWC
BWB
CE3
BWE
ADSC
ADV
A
NC/144M
A
CE2
BWD
BWA
CLK
GW
OE
ADSP
A
NC/576M
DQPC
DQC
NC
DQC
VDDQ
VDDQ
VSS
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDDQ
VDDQ
NC/1G
DQB
DQPB
DQB
DQC
DQC
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQB
DQB
DQC
DQC
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQB
DQB
DQC
NC
DQD
DQC
NC
DQD
VDDQ
NC
VDDQ
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDD
VDD
VDDQ
NC
VDDQ
DQB
NC
DQA
DQB
ZZ
DQA
DQD
DQD
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQA
DQA
DQD
DQD
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQA
DQA
DQD
DQPD
DQD
NC
VDDQ
VDDQ
VDD
VSS
VSS
NC
VSS
A
VSS
NC
VDD
VSS
VDDQ
VDDQ
DQA
NC
DQA
DQPA
NC
A
A
A
TDI
A1
TDO
A
A
A
A
MODE
A
A
A
TMS
TCK
A
A
A
A
A
A0
CY7C1482BV33 (4 M × 18)
1
2
3
4
5
6
7
8
9
10
11
A
B
C
D
E
F
G
H
J
K
L
M
N
P
NC/288M
A
CE1
CE2
BWB
NC
CE3
CLK
ADV
ADSP
A
BWA
ADSC
OE
A
NC
BWE
GW
VSS
VDD
VSS
VSS
VSS
VSS
VDD
VDDQ
VSS
VSS
VSS
VDDQ
NC/1G
NC
R
NC/144M
A
NC
NC
NC
DQB
VDDQ
VDDQ
A
NC/576M
DQPA
DQA
NC
DQB
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
NC
DQA
NC
DQB
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
NC
DQA
NC
NC
DQB
DQB
NC
NC
VDDQ
NC
VDDQ
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDD
VDD
VDD
VDDQ
NC
VDDQ
NC
NC
DQA
DQA
ZZ
NC
DQB
NC
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQA
NC
DQB
NC
VDDQ
VDD
VSS
VSS
VSS
VDD
VDDQ
DQA
NC
DQB
DQPB
NC
NC
VDDQ
VDDQ
VDD
VSS
VSS
NC
VSS
A
VSS
NC
VDD
VSS
VDDQ
VDDQ
DQA
NC
NC
NC
NC
A
A
A
TDI
A1
TDO
A
A
A
A
MODE
A
A
A
TMS
A0
TCK
A
A
A
A
Document Number: 001-15145 Rev. *F
Page 6 of 36
[+] Feedback
CY7C1480BV33, CY7C1482BV33, CY7C1486BV33
Pin Configurations (continued)
209-ball FBGA (14 × 22 × 1.76 mm) Pinout
CY7C1486BV33 (1 M × 72)
1
2
3
4
5
6
7
8
9
10
11
A
DQG
DQG
A
CE2
ADSP
ADSC
ADV
CE3
A
DQB
DQB
B
DQG
DQG
BWSC
BWSG NC/288M
BWE
A
BWSB
BWSF
DQB
DQB
C
DQG
DQG
BWSH
BWSD NC/144M
CE1
NC/576M BWSE
BWSA
DQB
DQB
D
DQG
DQG
VSS
NC
NC/1G
OE
GW
NC
VSS
DQB
DQB
E
DQPG
DQPC
VDDQ
VDDQ
VDD
VDD
VDD
VDDQ
VDDQ
DQPF
DQPB
F
DQC
DQC
VSS
VSS
VSS
NC
VSS
VSS
VSS
DQF
DQF
G
DQC
DQC
VDDQ
VDDQ
VDD
NC
VDD
VDDQ
VDDQ
DQF
DQF
H
DQC
DQC
VSS
VSS
VSS
NC
VSS
VSS
VSS
DQF
DQF
J
DQC
DQC
VDDQ
VDDQ
VDD
NC
VDD
VDDQ
VDDQ
DQF
DQF
K
NC
NC
CLK
NC
VSS
VSS
VSS
NC
NC
NC
NC
L
DQH
DQH
VDDQ
VDDQ
VDD
NC
VDD
VDDQ
VDDQ
DQA
DQA
M
DQH
DQH
VSS
VSS
VSS
NC
VSS
VSS
VSS
DQA
DQA
N
DQH
DQH
VDDQ
VDDQ
VDD
NC
VDD
VDDQ
VDDQ
DQA
DQA
P
DQH
DQH
VSS
VSS
VSS
ZZ
VSS
VSS
VSS
DQA
DQA
R
DQPD
DQPH
VDDQ
VDDQ
VDD
VDD
VDD
VDDQ
VDDQ
DQPA
T
DQD
DQD
VSS
NC
NC
MODE
NC
NC
VSS
DQE
DQE
U
DQD
DQD
A
A
A
A
A
A
A
DQE
DQE
V
DQD
DQD
A
A
A
A1
A
A
A
DQE
DQE
W
DQD
DQD
TMS
TDI
A
A0
A
TCK
DQE
DQE
Document Number: 001-15145 Rev. *F
TDO
DQPE
Page 7 of 36
[+] Feedback
CY7C1480BV33, CY7C1482BV33, CY7C1486BV33
Pin Definitions
Pin Name
I/O
Description
A0, A1, A
InputSynchronous
Address inputs used to select one of the address locations. Sampled at the rising
edge of the CLK if ADSP or ADSC is active LOW, and CE1, CE2, and CE3 are sampled
active. A1: A0 are fed to the 2-bit counter.
BWA,BWB,BWC,BWD,
BWE,BWF,BWG,BWH
InputSynchronous
Byte write select inputs, active LOW. Qualified with BWE to conduct byte writes to the
SRAM. Sampled on the rising edge of CLK.
GW
InputSynchronous
Global write enable input, active LOW. When asserted LOW on the rising edge of CLK,
a global write is conducted (all bytes are written, regardless of the values on BWX and
BWE).
BWE
InputSynchronous
Byte write enable input, active LOW. Sampled on the rising edge of CLK. This signal
must be asserted LOW to conduct a byte write.
CLK
InputClock
Clock input. Used to capture all synchronous inputs to the device. Also used to
increment the burst counter when ADV is asserted LOW during a burst operation.
CE1
InputSynchronous
Chip enable 1 input, active LOW. Sampled on the rising edge of CLK. Used in
conjunction with CE2 and CE3 to select or deselect the device. ADSP is ignored if CE1
is HIGH. CE1 is sampled only when a new external address is loaded.
CE2
InputSynchronous
Chip enable 2 input, active HIGH. Sampled on the rising edge of CLK. Used in
conjunction with CE1 and CE3 to select or deselect the device. CE2 is sampled only when
a new external address is loaded.
CE3
InputSynchronous
Chip enable 3 input, active LOW. Sampled on the rising edge of CLK. Used in
conjunction with CE1 and CE2 to select or deselect the device. CE3 is sampled only when
a new external address is loaded.
OE
InputAsynchronous
Output enable, asynchronous input, active LOW. Controls the direction of the I/O pins.
When LOW, the I/O pins behave as outputs. When deasserted HIGH, I/O pins are
tri-stated, and act as input data pins. OE is masked during the first clock of a read cycle
when emerging from a deselected state.
ADV
InputSynchronous
Advance input signal, sampled on the rising edge of CLK, active LOW. When
asserted, it automatically increments the address in a burst cycle.
ADSP
InputSynchronous
Address strobe from processor, sampled on the rising edge of CLK, active LOW.
When asserted LOW, addresses presented to the device are captured in the address
registers. A1: A0 are also loaded into the burst counter. When ADSP and ADSC are both
asserted, only ADSP is recognized. ASDP is ignored when CE1 is deasserted HIGH.
ADSC
InputSynchronous
Address strobe from controller, sampled on the rising edge of CLK, active LOW.
When asserted LOW, addresses presented to the device are captured in the address
registers. A1: A0 are also loaded into the burst counter. When ADSP and ADSC are both
asserted, only ADSP is recognized.
ZZ
InputAsynchronous
ZZ “Sleep” input, active HIGH. When asserted HIGH, places the device in a
non-time-critical “sleep” condition with data integrity preserved. For normal operation,
this pin must be LOW or left floating. ZZ pin has an internal pull-down.
DQs, DQPs
I/OSynchronous
Bidirectional data I/O lines. As inputs, they feed into an on-chip data register that is
triggered by the rising edge of CLK. As outputs, they deliver the data contained in the
memory location specified by the addresses presented during the previous clock rise of
the read cycle. The direction of the pins is controlled by OE. When OE is asserted LOW,
the pins behave as outputs. When HIGH, DQs and DQPX are placed in a tri-state
condition.
VDD
Power Supply
Power supply inputs to the core of the device.
VSS
Ground
VSSQ
[1]
I/O Ground
Ground for the core of the device.
Ground for the I/O circuitry.
Note
1. Applicable for TQFP package. For BGA package VSS serves as ground for the core and the I/O circuitry.
Document Number: 001-15145 Rev. *F
Page 8 of 36
[+] Feedback
CY7C1480BV33, CY7C1482BV33, CY7C1486BV33
Pin Definitions (continued)
Pin Name
VDDQ
I/O
I/O power supply Power supply for the I/O circuitry.
MODE
TDO
Description
Input static
Selects burst order. When tied to GND selects linear burst sequence. When tied to VDD
or left floating selects interleaved burst sequence. This is a strap pin and must remain
static during device operation. Mode Pin has an internal pull-up.
JTAG serial
output
synchronous
Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK. If the
JTAG feature is not used, this pin must be disconnected. This pin is not available on
TQFP packages.
TDI
JTAG serial input Serial data-in to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG
synchronous feature is not used, this pin can be disconnected or connected to VDD. This pin is not
available on TQFP packages.
TMS
JTAG serial input Serial data-in to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG
synchronous feature is not used, this pin can be disconnected or connected to VDD. This pin is not
available on TQFP packages.
TCK
JTAG clock
Clock input to the JTAG circuitry. If the JTAG feature is not used, this pin must be
connected to VSS. This pin is not available on TQFP packages.
NC
–
No connects. Not internally connected to the die. 144M, 288M, 576M, and 1G are
address expansion pins and are not internally connected to the die.
Functional Overview
All synchronous inputs pass through input registers controlled by
the rising edge of the clock. All data outputs pass through output
registers controlled by the rising edge of the clock. Maximum
access delay from the clock rise (tCO) is 3.0 ns (250 MHz device).
The CY7C1480BV33, CY7C1482BV33, and CY7C1486BV33
support secondary cache in systems using either a linear or
interleaved burst sequence. The interleaved burst order
supports Pentium and i486™ processors. The linear burst
sequence is suited for processors that use a linear burst
sequence. The burst order is user selectable, and is determined
by sampling the MODE input. Accesses may be initiated with the
Processor Address Strobe (ADSP) or the Controller Address
Strobe (ADSC). Address advancement through the burst
sequence is controlled by the ADV input. A two-bit on-chip
wraparound burst counter captures the first address in a burst
sequence and automatically increments the address for the rest
of the burst access.
Byte Write operations are qualified with the Byte Write Enable
(BWE) and Byte Write Select (BWX) inputs. A Global Write
Enable (GW) overrides all byte write inputs and writes data to all
four bytes. All writes are simplified with on-chip synchronous
self-timed write circuitry.
Three synchronous Chip Selects (CE1, CE2, and CE3) and an
asynchronous Output Enable (OE) provide easy bank selection
and output tri-state control. ADSP is ignored if CE1 is HIGH.
Single Read Accesses
This access is initiated when the following conditions are
satisfied at clock rise: (1) ADSP or ADSC is asserted LOW,
(2) CE1, CE2, CE3 are all asserted active, and (3) the write
signals (GW, BWE) are all deasserted HIGH. ADSP is ignored if
CE1 is HIGH. The address presented to the address inputs (A)
is stored into the address advancement logic and the Address
Register while being presented to the memory array. The
Document Number: 001-15145 Rev. *F
corresponding data is allowed to propagate to the input of the
Output Registers. At the rising edge of the next clock the data is
allowed to propagate through the output register and onto the
data bus within 3.0 ns (250 MHz device) if OE is active LOW. The
only exception occurs when the SRAM is emerging from a
deselected state to a selected state; its outputs are always
tri-stated during the first cycle of the access. After the first cycle
of the access, the outputs are controlled by the OE signal.
Consecutive single read cycles are supported. After the SRAM
is deselected at clock rise by the chip select and either ADSP or
ADSC signals, its output tri-states immediately.
Single Write Accesses Initiated by ADSP
This access is initiated when both of the following conditions are
satisfied at clock rise: (1) ADSP is asserted LOW, and (2) CE1,
CE2, CE3 are all asserted active. The address presented to A is
loaded into the address register and the address advancement
logic while being delivered to the memory array. The write signals
(GW, BWE, and BWX) and ADV inputs are ignored during this
first cycle.
ADSP triggered write accesses require two clock cycles to
complete. If GW is asserted LOW on the second clock rise, the
data presented to the DQs inputs is written into the corresponding address location in the memory array. If GW is HIGH,
then the write operation is controlled by BWE and BWX signals.
The CY7C1480BV33, CY7C1482BV33, and CY7C1486BV33
provide byte write capability that is described in the section Truth
Table for Read/Write on page 12. Asserting the Byte Write
Enable input (BWE) with the selected Byte Write (BWX) input,
selectively writes to only the desired bytes. Bytes not selected
during a Byte Write operation remain unaltered. A synchronous
self-timed Write mechanism is provided to simplify the Write
operations.
Because the CY7C1480BV33, CY7C1482BV33, and
CY7C1486BV33 are a common I/O device, the Output Enable
(OE) must be deasserted HIGH before presenting data to the
Page 9 of 36
[+] Feedback
CY7C1480BV33, CY7C1482BV33, CY7C1486BV33
DQs inputs. Doing so tri-states the output drivers. As a safety
precaution, DQs are automatically tri-stated whenever a Write
cycle is detected, regardless of the state of OE.
Asserting ADV LOW at clock rise automatically increments the
burst counter to the next address in the burst sequence. Both
Read and Write burst operations are supported.
Single Write Accesses Initiated by ADSC
Sleep Mode
ADSC Write accesses are initiated when the following conditions
are satisfied: (1) ADSC is asserted LOW, (2) ADSP is deasserted
HIGH, (3) CE1, CE2, CE3 are all asserted active, and (4) the
appropriate combination of the Write inputs (GW, BWE, and
BWX) are asserted active to conduct a Write to the desired byte.
ADSC-triggered Write accesses require a single clock cycle to
complete. The address presented to A is loaded into the address
register and the address advancement logic when being
delivered to the memory array. The ADV input is ignored during
this cycle. If a global Write is conducted, the data presented to
the DQs is written into the corresponding address location in the
memory core. If a Byte Write is conducted, only the selected
bytes are written. Bytes not selected during a Byte Write
operation remain unaltered. A synchronous self-timed Write
mechanism is provided to simplify the Write operations.
The ZZ input pin is an asynchronous input. Asserting ZZ places
the SRAM in a power conservation “sleep” mode. Two clock
cycles are required to enter into or exit from this “sleep” mode.
When in this mode, data integrity is guaranteed. Accesses
pending when entering the “sleep” mode are not considered
valid, and the completion of the operation is not guaranteed. The
device must be deselected before entering the “sleep” mode.
CE1, CE2, CE3, ADSP, and ADSC must remain inactive for the
duration of tZZREC after the ZZ input returns LOW.
Because the CY7C1480BV33, CY7C1482BV33, and
CY7C1486BV33 are a common I/O device, the Output Enable
(OE) must be deasserted HIGH before presenting data to the
DQs inputs. Doing so tri-states the output drivers. As a safety
precaution, DQs are automatically tri-stated whenever a Write
cycle is detected, regardless of the state of OE.
Interleaved Burst Address Table
(MODE = Floating or VDD)
First
Address
A1: A0
Second
Address
A1: A0
Third
Address
A1: A0
Fourth
Address
A1: A0
00
01
10
11
01
00
11
10
10
11
00
01
11
10
01
00
Burst Sequences
The CY7C1480BV33, CY7C1482BV33, and CY7C1486BV33
provide a 2-bit wraparound counter, fed by A1: A0, that
implements either an interleaved or linear burst sequence. The
interleaved burst sequence is designed specifically to support
Intel Pentium applications. The linear burst sequence is
designed to support processors that follow a linear burst
sequence. The burst sequence is user selectable through the
MODE input.
Linear Burst Address Table (MODE = GND)
First
Address
A1: A0
Second
Address
A1: A0
Third
Address
A1: A0
Fourth
Address
A1: A0
00
01
10
11
01
10
11
00
10
11
00
01
11
00
01
10
ZZ Mode Electrical Characteristics
Parameter
Description
Test Conditions
Min
Max
Unit
IDDZZ
Sleep mode standby current
ZZ > VDD – 0.2 V
–
120
mA
tZZS
Device operation to ZZ
ZZ > VDD – 0.2 V
–
2tCYC
ns
tZZREC
ZZ recovery time
ZZ < 0.2 V
2tCYC
–
ns
tZZI
ZZ Active to Sleep current
This parameter is sampled
–
2tCYC
ns
tRZZI
ZZ Inactive to exit Sleep current
This parameter is sampled
0
–
ns
Document Number: 001-15145 Rev. *F
Page 10 of 36
[+] Feedback
CY7C1480BV33, CY7C1482BV33, CY7C1486BV33
Truth Table
The truth table for CY7C1480BV33, CY7C1482BV33, and CY7C1486BV33 follows.[2, 3, 4, 5, 6]
Operation
Add. Used
CE1
CE2
CE3
ZZ
ADSP
ADSC
ADV
Deselect cycle, power-down
None
H
X
X
L
Deselect cycle, power-down
None
L
L
X
L
Deselect cycle, power-down
None
L
X
H
Deselect cycle, power-down
None
L
L
X
WRITE OE CLK
DQ
X
L
X
X
X
L-H Tri-state
L
X
X
X
X
L-H Tri-state
L
L
X
X
X
X
L-H Tri-state
L
H
L
X
X
X
L-H Tri-state
L-H Tri-state
Deselect cycle, power-down
None
L
X
H
L
H
L
X
X
X
Sleep mode, power-down
None
X
X
X
H
X
X
X
X
X
Read cycle, begin burst
External
L
H
L
L
L
X
X
X
Read cycle, begin burst
External
L
H
L
L
L
X
X
X
Write cycle, begin burst
External
L
H
L
L
H
L
X
L
X
L-H
D
Read cycle, begin burst
External
L
H
L
L
H
L
X
H
L
L-H
Q
Read cycle, begin burst
X
Tri-state
L
L-H
Q
H
L-H Tri-state
External
L
H
L
L
H
L
X
H
H
L-H Tri-state
Read cycle, continue burst
Next
X
X
X
L
H
H
L
H
L
L-H
Read cycle, continue burst
Next
X
X
X
L
H
H
L
H
H
L-H Tri-state
Read cycle, continue burst
Next
H
X
X
L
X
H
L
H
L
L-H
Read cycle, continue burst
Next
H
X
X
L
X
H
L
H
H
L-H Tri-state
Write cycle, continue burst
Next
X
X
X
L
H
H
L
L
X
L-H
Write cycle, continue burst
Next
H
X
X
L
X
H
L
L
X
L-H
D
Read cycle, suspend burst
Current
X
X
X
L
H
H
H
H
L
L-H
Q
Read cycle, suspend burst
Current
X
X
X
L
H
H
H
H
H
L-H Tri-state
Read cycle, suspend burst
Current
H
X
X
L
X
H
H
H
L
L-H
Read cycle, suspend burst
Current
H
X
X
L
X
H
H
H
H
L-H Tri-state
Write cycle, suspend burst
Current
X
X
X
L
H
H
H
L
X
L-H
D
Write cycle, suspend burst
Current
H
X
X
L
X
H
H
L
X
L-H
D
Q
Q
D
Q
Notes
2. X = Do Not Care, H = Logic HIGH, L = Logic LOW.
3. WRITE = L when any one or more Byte Write enable signals and BWE = L or GW = L. WRITE = H when all Byte write enable signals, BWE, GW = H.
4. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.
5. The SRAM always initiates a read cycle when ADSP is asserted, regardless of the state of GW, BWE, or BWX. Writes may occur only on subsequent clocks after the
ADSP or with the assertion of ADSC. As a result, OE must be driven HIGH before the start of the write cycle to allow the outputs to tri-state. OE is a do not care for
the remainder of the write cycle.
6. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle all data bits are tri-state when OE is inactive
or when the device is deselected, and all data bits behave as outputs when OE is active (LOW).
Document Number: 001-15145 Rev. *F
Page 11 of 36
[+] Feedback
CY7C1480BV33, CY7C1482BV33, CY7C1486BV33
Truth Table for Read/Write
The read/write truth table for CY7C1480BV33 follows.[7]
Function (CY7C1480BV33)
GW
BWE
BWD
BWC
BWB
BWA
Read
H
H
X
X
X
X
Read
H
L
H
H
H
H
Write byte A – (DQA and DQPA)
H
L
H
H
H
L
Write byte B – (DQB and DQPB)
H
L
H
H
L
H
Write bytes B, A
H
L
H
H
L
L
Write byte C – (DQC and DQPC)
H
L
H
L
H
H
Write bytes C, A
H
L
H
L
H
L
Write bytes C, B
H
L
H
L
L
H
Write bytes C, B, A
H
L
H
L
L
L
Write byte D – (DQD and DQPD)
H
L
L
H
H
H
Write bytes D, A
H
L
L
H
H
L
Write bytes D, B
H
L
L
H
L
H
Write bytes D, B, A
H
L
L
H
L
L
Write bytes D, C
H
L
L
L
H
H
Write bytes D, C, A
H
L
L
L
H
L
Write bytes D, C, B
H
L
L
L
L
H
Write all bytes
H
L
L
L
L
L
Write all bytes
L
X
X
X
X
X
GW
BWE
BWB
BWA
Read
H
H
X
X
Read
H
L
H
H
Write byte A – (DQA and DQPA)
H
L
H
L
Write byte B – (DQB and DQPB)
H
L
L
H
Write bytes B, A
H
L
L
L
Write all bytes
H
L
L
L
Write all bytes
L
X
X
X
GW
BWE
BWX
Read
H
H
X
Read
H
L
All BW = H
Truth Table for Read/Write
The read/write truth table for CY7C1482BV33 follows.[7]
Function (CY7C1482BV33)
Truth Table for Read/Write
The read/write truth table for CY7C1486BV33 follows.[7]
Function (CY7C1486BV33)
Write byte x – (DQx and DQPx)
H
L
L
Write all bytes
H
L
All BW = L
Write all bytes
L
X
X
Note
7. BWx represents any byte write signal BW[0..7].To enable any byte write BWx, a Logic LOW signal must be applied at clock rise. Any number of bye writes can be
enabled at the same time for any write.
Document Number: 001-15145 Rev. *F
Page 12 of 36
[+] Feedback
CY7C1480BV33, CY7C1482BV33, CY7C1486BV33
IEEE 1149.1 Serial Boundary Scan (JTAG)
The CY7C1480BV33, CY7C1482BV33, and CY7C1486BV33
incorporate a serial boundary scan test access port (TAP). This
port operates in accordance with IEEE Standard 1149.1-1990
but does not have the set of functions required for full 1149.1
compliance. These functions from the IEEE specification are
excluded because their inclusion places an added delay in the
critical speed path of the SRAM. Note that the TAP controller
functions in a manner that does not conflict with the operation of
other devices using 1149.1 fully compliant TAPs. The TAP
operates using JEDEC-standard 3.3 V or 2.5 V I/O logic levels.
Performing a TAP Reset
Perform a RESET by forcing TMS HIGH (VDD) for five rising
edges of TCK. This RESET does not affect the operation of the
SRAM and may be performed while the SRAM is operating.
At power-up, the TAP is reset internally to ensure that TDO
comes up in a High Z state.
TAP Registers
The CY7C1480BV33, CY7C1482BV33, and CY7C1486BV33
contain a TAP controller, instruction register, boundary scan
register, bypass register, and ID register.
Registers are connected between the TDI and TDO balls and
enable data to be scanned into and out of the SRAM test circuitry.
Only one register can be selected at a time through the
instruction register. Data is serially loaded into the TDI ball on the
rising edge of TCK. Data is output on the TDO ball on the falling
edge of TCK.
Disabling the JTAG Feature
Instruction Register
It is possible to operate the SRAM without using the JTAG
feature. To disable the TAP controller, tie TCK LOW (VSS) to
prevent device clocking. TDI and TMS are internally pulled up
and may be unconnected. They may alternatively be connected
to VDD through a pull-up resistor. TDO must be left unconnected.
At power-up, the device comes up in a reset state, which does
not interfere with the operation of the device.
Three-bit instructions can be serially loaded into the instruction
register. This register is loaded when it is placed between the TDI
and TDO balls as shown in the TAP Controller Block Diagram on
page 16. At power-up, the instruction register is loaded with the
IDCODE instruction. It is also loaded with the IDCODE
instruction if the controller is placed in a reset state, as described
in the previous section.
The 0/1 next to each state represents the value of TMS at the
rising edge of TCK.
When the TAP controller is in the Capture-IR state, the two least
significant bits are loaded with a binary “01” pattern to enable
fault isolation of the board-level serial test data path.
Test Access Port (TAP)
Test Clock (TCK)
The test clock is used only with the TAP controller. All inputs are
captured on the rising edge of TCK. All outputs are driven from
the falling edge of TCK.
Test Mode Select (TMS)
The TMS input gives commands to the TAP controller and is
sampled on the rising edge of TCK. Leave this ball unconnected
if the TAP is not used. The ball is pulled up internally, resulting in
a logic HIGH level.
Test Data-In (TDI)
The TDI ball serially inputs information into the registers and can
be connected to the input of any of the registers. The register
between TDI and TDO is chosen by the instruction that is loaded
into the TAP instruction register. For information about loading
the instruction register, see the TAP Controller State Diagram on
page 15. TDI is internally pulled up and can be unconnected if
the TAP is unused in an application. TDI is connected to the most
significant bit (MSB) of any register. (See the TAP Controller
Block Diagram on page 16.)
Test Data-Out (TDO)
The TDO output ball serially clocks data-out from the registers.
The output is active depending upon the current state of the TAP
state machine. The output changes on the falling edge of TCK.
TDO is connected to the least significant bit (LSB) of any register.
(See the TAP Controller State Diagram on page 15.)
Document Number: 001-15145 Rev. *F
Bypass Register
To save time when serially shifting data through registers, it is
sometimes advantageous to skip certain chips. The bypass
register is a single-bit register that can be placed between the
TDI and TDO balls. This enables data to be shifted through the
SRAM with minimal delay. The bypass register is set LOW (VSS)
when the BYPASS instruction is executed.
Boundary Scan Register
The boundary scan register is connected to all the input and
bidirectional balls on the SRAM. The x36 configuration has a
73-bit-long register, and the x18 configuration has a 54-bit-long
register.
The boundary scan register is loaded with the contents of the
RAM I/O ring when the TAP controller is in the Capture-DR state
and is then placed between the TDI and TDO balls when the
controller is moved to the Shift-DR state. The EXTEST,
SAMPLE/PRELOAD, and SAMPLE Z instructions can be used
to capture the contents of the I/O ring.
The Boundary Scan Order tables show the order in which the bits
are connected. Each bit corresponds to one of the bumps on the
SRAM package. The MSB of the register is connected to TDI and
the LSB is connected to TDO.
Identification (ID) Register
The ID register is loaded with a vendor-specific, 32-bit code
during the Capture-DR state when the IDCODE command is
loaded in the instruction register. The IDCODE is hardwired into
the SRAM and can be shifted out when the TAP controller is in
the Shift-DR state. The ID register has a vendor code and other
information described in the section Identification Register
Definitions on page 19.
Page 13 of 36
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CY7C1480BV33, CY7C1482BV33, CY7C1486BV33
TAP Instruction Set
Overview
Eight different instructions are possible with the three-bit
instruction register. All combinations are listed in Identification
Codes on page 19. Three of these instructions are listed as
RESERVED and must not be used. The other five instructions
are described in detail in this section.
The TAP controller used in this SRAM is not fully compliant to
the 1149.1 convention because some of the mandatory 1149.1
instructions are not fully implemented.
The TAP controller cannot be used to load address data or
control signals into the SRAM and cannot preload the I/O
buffers. The SRAM does not implement the 1149.1 commands
EXTEST or INTEST or the PRELOAD portion of
SAMPLE/PRELOAD; rather, it performs a capture of the I/O
ring when these instructions are executed.
Instructions are loaded into the TAP controller during the
Shift-IR state when the instruction register is placed between
TDI and TDO. During this state, instructions are shifted
through the instruction register through the TDI and TDO balls.
To execute the instruction after it is shifted in, the TAP
controller must be moved into the Update-IR state.
EXTEST
EXTEST is a mandatory 1149.1 instruction, which must be
executed whenever the instruction register is loaded with all
zeros. EXTEST is not implemented in this SRAM TAP
controller, and therefore this device is not compliant to 1149.1.
The TAP controller does recognize an all-zero instruction.
When an EXTEST instruction is loaded into the instruction
register, the SRAM responds as if a SAMPLE/PRELOAD
instruction has been loaded. There is one difference between
the two instructions. Unlike the SAMPLE/PRELOAD
instruction, EXTEST places the SRAM outputs in a High Z
state.
IDCODE
The IDCODE instruction causes a vendor-specific, 32-bit code
to be loaded into the instruction register. It also places the
instruction register between the TDI and TDO balls and
enables the IDCODE to be shifted out of the device when the
TAP controller enters the Shift-DR state.
The IDCODE instruction is loaded into the instruction register
at power-up or whenever the TAP controller is in a test logic
reset state.
SAMPLE/PRELOAD
SAMPLE/PRELOAD is a 1149.1 mandatory instruction. The
PRELOAD portion of this instruction is not implemented, so
the device TAP controller is not fully 1149.1 compliant.
When the SAMPLE/PRELOAD instruction is loaded into the
instruction register and the TAP controller is in the Capture-DR
state, a snapshot of data on the inputs and bidirectional balls
is captured in the boundary scan register.
Be aware that the TAP controller clock can only operate at a
frequency up to 10 MHz, while the SRAM clock operates more
than an order of magnitude faster. Because there is a large
difference in the clock frequencies, it is possible that during the
Capture-DR state, an input or output may undergo a transition.
The TAP may then try to capture a signal when in transition
(metastable state). This does not harm the device, but there is
no guarantee as to the value that may be captured.
Repeatable results may not be possible.
To guarantee that the boundary scan register captures the
correct value of a signal, the SRAM signal must be stabilized
long enough to meet the TAP controller’s capture setup plus
hold time (tCS plus tCH).
The SRAM clock input might not be captured correctly if there
is no way in a design to stop (or slow) the clock during a
SAMPLE/PRELOAD instruction. If this is an issue, it is still
possible to capture all other signals and simply ignore the
value of the CLK captured in the boundary scan register.
After the data is captured, the data is shifted out by putting the
TAP into the Shift-DR state. This places the boundary scan
register between the TDI and TDO balls.
Note that because the PRELOAD part of the command is not
implemented, putting the TAP to the Update-DR state when
performing a SAMPLE/PRELOAD instruction has the same
effect as the Pause-DR command.
BYPASS
When the BYPASS instruction is loaded in the instruction
register and the TAP is placed in a Shift-DR state, the bypass
register is placed between the TDI and TDO balls. The
advantage of the BYPASS instruction is that it shortens the
boundary scan path when multiple devices are connected
together on a board.
Reserved
These instructions are not implemented but are reserved for
future use. Do not use these instructions.
SAMPLE Z
The SAMPLE Z instruction causes the boundary scan register
to be connected between the TDI and TDO balls when the TAP
controller is in a Shift-DR state. It also places all SRAM outputs
into a High Z state.
Document Number: 001-15145 Rev. *F
Page 14 of 36
[+] Feedback
CY7C1480BV33, CY7C1482BV33, CY7C1486BV33
TAP Controller State Diagram
1
TEST-LOGIC
RESET
0
0
RUN-TEST/
IDLE
1
SELECT
DR-SCA N
1
SELECT
IR-SCAN
0
1
0
1
CAPTURE-DR
CAPTURE-IR
0
0
SHIFT-DR
0
SHIFT-IR
1
1
EXIT1-IR
0
0
PAUSE-IR
1
0
1
EXIT2-DR
0
EXIT2-IR
1
1
UPDATE-DR
Document Number: 001-15145 Rev. *F
1
0
PAUSE-DR
1
0
1
EXIT1-DR
0
1
0
UPDATE-IR
1
0
Page 15 of 36
[+] Feedback
CY7C1480BV33, CY7C1482BV33, CY7C1486BV33
TAP Controller Block Diagram
0
Bypass Register
2 1 0
TDI
Selection
Circuitry
Instruction Register
Selection
Circuitry
TDO
31 30 29 . . . 2 1 0
Identification Register
x . . . . . 2 1 0
Boundary Scan Register
TCK
TM S
Document Number: 001-15145 Rev. *F
TAP CONTROLLER
Page 16 of 36
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CY7C1480BV33, CY7C1482BV33, CY7C1486BV33
3.3-V TAP AC Test Conditions
2.5-V TAP AC Test Conditions
Input pulse levels................................................VSS to 3.3 V
Input pulse levels................................................ VSS to 2.5 V
Input rise and fall times....................................................1 ns
Input rise and fall time .....................................................1 ns
Input timing reference levels.......................................... 1.5 V
Input timing reference levels........................................ 1.25 V
Output reference levels ................................................. 1.5 V
Output reference levels ............................................... 1.25 V
Test load termination supply voltage ............................. 1.5 V
Test load termination supply voltage ........................... 1.25 V
3.3-V TAP AC Output Load Equivalent
2.5-V TAP AC Output Load Equivalent
1.5V
1.25V
50Ω
50Ω
TDO
TDO
Z O= 50Ω
20pF
Z O= 50Ω
20pF
TAP DC Electrical Characteristics and Operating Conditions
(0 °C < TA < +70 °C; VDD = 3.135 to 3.6 V unless otherwise noted)[8]
Parameter
Description
Test Conditions
IOH = –4.0 mA, VDDQ = 3.3 V
Min
Max
Unit
2.4
–
V
VOH1
Output HIGH voltage
IOH = –1.0 mA, VDDQ = 2.5 V
2.0
–
V
VOH2
Output HIGH voltage
IOH = –100 µA
VDDQ = 3.3 V
2.9
–
V
VDDQ = 2.5 V
2.1
–
V
VOL1
Output LOW voltage
IOL = 8.0 mA
VDDQ = 3.3 V
–
0.4
V
IOL = 1.0 mA
VDDQ = 2.5 V
–
0.4
V
VOL2
Output LOW voltage
IOL = 100 µA
VDDQ = 3.3 V
–
0.2
V
VDDQ = 2.5 V
–
0.2
V
VIH
Input HIGH voltage
VDDQ = 3.3 V
2.0
VDD + 0.3
V
VDDQ = 2.5 V
1.7
VDD + 0.3
V
VIL
Input LOW voltage
VDDQ = 3.3 V
–0.3
0.8
V
VDDQ = 2.5 V
–0.3
0.7
V
IX
Input load current
–5
5
µA
GND < VIN < VDDQ
Note
8. All voltages referenced to VSS (GND).
Document Number: 001-15145 Rev. *F
Page 17 of 36
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CY7C1480BV33, CY7C1482BV33, CY7C1486BV33
TAP AC Switching Characteristics
Over the Operating Range[9, 10]
Parameter
Description
Min
Max
Unit
Clock
tTCYC
TCK clock cycle time
50
–
ns
tTF
TCK clock frequency
–
20
MHz
tTH
TCK clock HIGH time
20
–
ns
tTL
TCK clock LOW time
20
–
ns
Output Times
tTDOV
TCK clock LOW to TDO valid
–
10
ns
tTDOX
TCK clock LOW to TDO invalid
0
–
ns
Setup Times
tTMSS
TMS setup to TCK clock rise
5
–
ns
tTDIS
TDI setup to TCK Clock rise
5
–
ns
tCS
Capture setup to TCK rise
5
–
ns
Hold Times
tTMSH
TMS hold after TCK clock rise
5
–
ns
tTDIH
TDI hold after clock rise
5
–
ns
tCH
Capture hold after clock rise
5
–
ns
TAP Timing
Figure 3. TAP Timing
1
2
Test Clock
(TCK )
3
t TH
t TM SS
t TM SH
t TDIS
t TDIH
t
TL
4
5
6
t CY C
Test M ode Select
(TM S)
Test Data-In
(TDI)
t TDOV
t TDOX
Test Data-Out
(TDO)
DON’T CA RE
UNDEFINED
Notes
9. tCS and tCH refer to the setup and hold time requirements of latching data from the boundary scan register.
10. Test conditions are specified using the load in TAP AC Test Conditions. tR/tF = 1 ns.
Document Number: 001-15145 Rev. *F
Page 18 of 36
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CY7C1480BV33, CY7C1482BV33, CY7C1486BV33
Identification Register Definitions
Instruction Field
CY7C1480BV33
(2 M × 36)
CY7C1482BV33
(4 M × 18)
CY7C1486BV33
(1 M × 72)
000
000
000
01011
01011
01011
000000
000000
000000
Revision number (31:29)
Device depth (28:24)
Architecture/Memory type(23:18)
Bus width/density(17:12)
Description
Describes the version number
Reserved for internal use
Defines memory type and architecture
100100
010100
110100
Cypress JEDEC ID Code (11:1)
00000110100
00000110100
00000110100
Enables unique identification of SRAM
vendor
Defines width and density
ID register presence indicator (0)
1
1
1
Indicates the presence of an ID register
Scan Register Sizes
Register Name
Instruction
Bit Size (× 36)
Bit Size (× 18)
Bit Size (× 72)
3
3
3
Bypass
1
1
1
ID
32
32
32
Boundary scan order – 165-ball FBGA
73
54
–
Boundary scan order – 209-ball BGA
–
–
112
Identification Codes
Instruction
Code
Description
EXTEST
000
Captures the I/O ring contents.
IDCODE
001
Loads the ID register with the vendor ID code and places the register between
TDI and TDO. This operation does not affect SRAM operations.
SAMPLE Z
010
Captures I/O ring contents. Places the boundary scan register between TDI
and TDO. Forces all SRAM output drivers to a High Z state.
RESERVED
011
Do Not Use: This instruction is reserved for future use.
SAMPLE/PRELOAD
100
Captures I/O ring contents. Places the boundary scan register between TDI
and TDO. Does not affect SRAM operation.
RESERVED
101
Do Not Use: This instruction is reserved for future use.
RESERVED
110
Do Not Use: This instruction is reserved for future use.
BYPASS
111
Places the bypass register between TDI and TDO. This operation does not
affect SRAM operations.
Document Number: 001-15145 Rev. *F
Page 19 of 36
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CY7C1480BV33, CY7C1482BV33, CY7C1486BV33
Boundary Scan Exit Order (2 M × 36)
Bit #
165-ball ID
Bit #
165-ball ID
Bit #
165-ball ID
Bit #
165-ball ID
1
C1
21
R3
41
L10
61
B8
2
D1
22
P2
42
K11
62
A7
3
E1
23
R4
43
J11
63
B7
4
D2
24
P6
44
K10
64
B6
5
E2
25
R6
45
J10
65
A6
6
F1
26
N6
46
H11
66
B5
7
G1
27
P11
47
G11
67
A5
8
F2
28
R8
48
F11
68
A4
9
G2
29
P3
49
E11
69
B4
10
J1
30
P4
50
D10
70
B3
11
K1
31
P8
51
D11
71
A3
12
L1
32
P9
52
C11
72
A2
13
J2
33
P10
53
G10
73
B2
14
M1
34
R9
54
F10
15
N1
35
R10
55
E10
16
K2
36
R11
56
A10
17
L2
37
N11
57
B10
18
M2
38
M11
58
A9
19
R1
39
L11
59
B9
20
R2
40
M10
60
A8
Boundary Scan Exit Order (4 M × 18)
Bit #
165-ball ID
Bit #
165-ball ID
Bit #
165-ball ID
1
D2
19
R8
37
C11
2
E2
20
P3
38
A11
3
F2
21
P4
39
A10
4
G2
22
P8
40
B10
5
J1
23
P9
41
A9
6
K1
24
P10
42
B9
7
L1
25
R9
43
A8
8
M1
26
R10
44
B8
9
N1
27
R11
45
A7
10
R1
28
M10
46
B7
11
R2
29
L10
47
B6
12
R3
30
K10
48
A6
13
P2
31
J10
49
B5
14
R4
32
H11
50
A4
15
P6
33
G11
51
B3
16
R6
34
F11
52
A3
17
N6
35
E11
53
A2
18
P11
36
D11
54
B2
Document Number: 001-15145 Rev. *F
Page 20 of 36
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CY7C1480BV33, CY7C1482BV33, CY7C1486BV33
Boundary Scan Exit Order (1 M × 72)
Bit #
209-ball ID
Bit #
209-ball ID
Bit #
209-ball ID
Bit #
209-ball ID
1
A1
29
T1
57
V10
85
C11
2
A2
30
T2
58
U11
86
C10
3
B1
31
U1
59
U10
87
B11
4
B2
32
U2
60
T11
88
B10
5
C1
33
V1
61
T10
89
A11
6
C2
34
V2
62
R11
90
A10
7
D1
35
W1
63
R10
91
A9
8
D2
36
W2
64
P11
92
U8
9
E1
37
T6
65
P10
93
A7
10
E2
38
V3
66
N11
94
A5
11
F1
39
V4
67
N10
95
A6
12
F2
40
U4
68
M11
96
D6
13
G1
41
W5
69
M10
97
B6
14
G2
42
V6
70
L11
98
D7
15
H1
43
W6
71
L10
99
K3
16
H2
44
U3
72
P6
100
A8
17
J1
45
U9
73
J11
101
B4
18
J2
46
V5
74
J10
102
B3
19
L1
47
U5
75
H11
103
C3
20
L2
48
U6
76
H10
104
C4
21
M1
49
W7
77
G11
105
C8
22
M2
50
V7
78
G10
106
C9
23
N1
51
U7
79
F11
107
B9
24
N2
52
V8
80
F10
108
B8
25
P1
53
V9
81
E10
109
A4
26
P2
54
W11
82
E11
110
C6
27
R2
55
W10
83
D11
111
B7
28
R1
56
V11
84
D10
112
A3
Document Number: 001-15145 Rev. *F
Page 21 of 36
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CY7C1480BV33, CY7C1482BV33, CY7C1486BV33
Maximum Ratings
Current into outputs (LOW) ......................................... 20 mA
Exceeding maximum ratings may shorten the useful life of the
device. User guidelines are not tested.
Static discharge voltage.......................................... > 2001 V
(MIL-STD-883, Method 3015)
Storage temperature................................. –65 °C to +150 °C
Latch-up current .................................................... > 200 mA
Ambient temperature with
power applied ........................................... –55 °C to +125 °C
Operating Range
Ambient
Temperature
0 °C to +70 °C
–40 °C to +85 °C
Range
Supply voltage on VDD relative to GND ........–0.3 V to +4.6 V
Commercial
Industrial
Supply voltage on VDDQ relative to GND....... –0.3 V to +VDD
DC voltage applied to outputs
in tri-state...........................................–0.5 V to VDDQ + 0.5 V
VDD
VDDQ
3.3 V – 5% /
+ 10%
2.5 V – 5%
to VDD
DC input voltage .................................. –0.5 V to VDD + 0.5 V
Electrical Characteristics
Over the Operating Range[11, 12]
Parameter
Description
VDD
Power supply voltage
VDDQ
I/O supply voltage
Test Conditions
V
3.135
VDD
V
2.375
2.625
V
For 3.3-V I/O, IOH = –4.0 mA
2.4
–
V
For 2.5-V I/O, IOH = –1.0 mA
2.0
–
V
–
0.4
V
VOL
Output LOW voltage
For 3.3-V I/O, IOL = 8.0 mA
VIH
Input HIGH voltage[11]
For 3.3-V I/O
VIL
Input LOW voltage[11]
IX
Input leakage current except GND ≤ VI ≤ VDDQ
ZZ and MODE
Input current of MODE
For 2.5-V I/O, IOL = 1.0 mA
–
0.4
V
2.0
VDD + 0.3 V
V
For 2.5-V I/O
1.7
VDD + 0.3 V
V
For 3.3-V I/O
–0.3
0.8
V
For 2.5-V I/O
–0.3
0.7
V
–5
5
μA
Input = VSS
–30
–
μA
Input = VDD
–
5
μA
Input = VSS
–5
–
μA
Input = VDD
–
30
μA
GND ≤ VI ≤ VDDQ, output disabled
IOZ
Output leakage current
IDD [13]
VDD operating supply current VDD = Max, IOUT = 0 mA,
f = fMAX = 1/tCYC
Automatic CE power-down
current—TTL Inputs
Unit
3.6
For 2.5-V I/O
Output HIGH voltage
ISB1
Max
For 3.3-V I/O
VOH
Input current of ZZ
Min
3.135
VDD = Max, device deselected,
VIN ≥ VIH or VIN ≤ VIL
f = fMAX = 1/tCYC
–5
5
μA
4.0 ns cycle, 250 MHz
–
500
mA
5.0 ns cycle, 200 MHz
–
500
mA
6.0 ns cycle, 167 MHz
–
450
mA
4.0 ns cycle, 250 MHz
–
245
mA
5.0 ns cycle, 200 MHz
–
245
mA
6.0 ns cycle, 167 MHz
–
245
mA
Notes
11. Overshoot: VIH(AC) < VDD +1.5V (Pulse width less than tCYC/2). Undershoot: VIL(AC) > –2V (Pulse width less than tCYC/2).
12. Power-up: Assumes a linear ramp from 0V to VDD(min.) within 200 ms. During this time VIH < VDD and VDDQ < VDD.
13. The operation current is calculated with 50% read cycle and 50% write cycle.
Document Number: 001-15145 Rev. *F
Page 22 of 36
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CY7C1480BV33, CY7C1482BV33, CY7C1486BV33
Electrical Characteristics
Over the Operating Range[11, 12] (continued)
Min
Max
Unit
ISB2
Parameter
Automatic CE power-down
current—CMOS inputs
VDD = Max, device deselected,
All speeds
VIN ≤ 0.3 V or VIN > VDDQ – 0.3 V, f = 0
–
120
mA
ISB3
Automatic CE power-down
current—CMOS inputs
VDD = Max, device deselected, or VIN 4.0 ns cycle, 250 MHz
≤ 0.3 V or VIN > VDDQ – 0.3 V,
5.0 ns cycle, 200 MHz
f = fMAX = 1/tCYC
6.0 ns cycle, 167 MHz
–
245
mA
–
245
mA
–
245
mA
Automatic CE power-down
current—TTL inputs
VDD = Max, device deselected,
VIN ≥ VIH or VIN ≤ VIL, f = 0
–
135
mA
ISB4
Description
Test Conditions
All speeds
Capacitance
Tested initially and after any design or process change that may affect these parameters.
Parameter
Description
CADDRESS
Address input capacitance
CDATA
Data input capacitance
Test Conditions
TA = 25 °C, f = 1 MHz,
VDD = 3.3 V
VDDQ = 2.5 V
100-pin TQFP 165-ball FBGA 209-ball FBGA Unit
Max
Max
Max
6
6
6
pF
5
5
5
pF
CCTRL
Control input capacitance
8
8
8
pF
CCLK
Clock input capacitance
6
6
6
pF
CI/O
I/O capacitance
5
5
5
pF
Thermal Resistance
Tested initially and after any design or process change that may affect these parameters.
Parameter
Description
θJA
Thermal resistance
(junction to ambient)
θJC
Thermal resistance
(junction to case)
Document Number: 001-15145 Rev. *F
Test Conditions
Test conditions follow
standard test methods and
procedures for measuring
thermal impedance,
according to EIA/JESD51.
100-pin TQFP 165-ball FBGA 209-ball FBGA Unit
Package
Package
Package
24.63
16.3
15.2
°C/W
2.28
2.1
1.7
°C/W
Page 23 of 36
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CY7C1480BV33, CY7C1482BV33, CY7C1486BV33
Figure 4. AC Test Loads and Waveforms
3.3 V I/O Test Load
R = 317 Ω
3.3 V
OUTPUT
ALL INPUT PULSES
VDDQ
OUTPUT
RL = 50 Ω
Z0 = 50 Ω
10%
90%
10%
90%
GND
5 pF
R = 351 Ω
≤ 1 ns
≤ 1 ns
VL = 1.5 V
INCLUDING
JIG AND
SCOPE
(a)
(c)
(b)
2.5 V I/O Test Load
R = 1667 Ω
2.5 V
OUTPUT
Z0 = 50 Ω
10%
R = 1538 Ω
VL = 1.25 V
Document Number: 001-15145 Rev. *F
INCLUDING
JIG AND
SCOPE
90%
10%
90%
GND
5 pF
(a)
ALL INPUT PULSES
VDDQ
OUTPUT
RL = 50 Ω
(b)
≤ 1 ns
≤ 1 ns
(c)
Page 24 of 36
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CY7C1480BV33, CY7C1482BV33, CY7C1486BV33
Switching Characteristics
Over the Operating Range[14, 15]
Parameter
tPOWER
Description
VDD(typical) to the first access[16]
250 MHz
200 MHz
167 MHz
Unit
Min
Max
Min
Max
Min
Max
1
–
1
–
1
–
ms
Clock
tCYC
Clock cycle time
4.0
–
5.0
–
6.0
–
ns
tCH
Clock HIGH
2.0
–
2.0
–
2.4
–
ns
tCL
Clock LOW
2.0
–
2.0
–
2.4
–
ns
Output Times
tCO
Data output valid after CLK rise
–
3.0
–
3.0
–
3.4
ns
tDOH
Data output hold after CLK rise
1.3
–
1.3
–
1.5
–
ns
tCLZ
Clock to
low-Z[17, 18, 19]
1.3
–
1.3
–
1.5
–
ns
tCHZ
Clock to
high-Z[17, 18, 19]
–
3.0
–
3.0
–
3.4
ns
tOEV
OE LOW to output valid
–
3.0
–
3.0
–
3.4
ns
OE LOW to output
low-Z[17, 18, 19]
0
–
0
–
0
–
ns
OE HIGH to output
high-Z[17, 18, 19]
–
3.0
–
3.0
–
3.4
ns
tOELZ
tOEHZ
Setup Times
tAS
Address setup before CLK rise
1.4
–
1.4
–
1.5
–
ns
tADS
ADSC, ADSP setup before CLK rise
1.4
–
1.4
–
1.5
–
ns
tADVS
ADV setup before CLK rise
1.4
–
1.4
–
1.5
–
ns
tWES
GW, BWE, BWX setup before CLK rise
1.4
–
1.4
–
1.5
–
ns
tDS
Data input setup before CLK rise
1.4
–
1.4
–
1.5
–
ns
tCES
Chip enable setup before CLK rise
1.4
–
1.4
–
1.5
–
ns
tAH
Address hold after CLK rise
0.4
–
0.4
–
0.5
–
ns
tADH
ADSP, ADSC hold after CLK rise
0.4
–
0.4
–
0.5
–
ns
tADVH
ADV hold after CLK rise
0.4
–
0.4
–
0.5
–
ns
tWEH
GW, BWE, BWX hold after CLK rise
0.4
–
0.4
–
0.5
–
ns
tDH
Data input hold after CLK rise
0.4
–
0.4
–
0.5
–
ns
tCEH
Chip enable hold after CLK rise
0.4
–
0.4
–
0.5
–
ns
Hold Times
Notes
14. Timing reference level is 1.5 V when VDDQ = 3.3 V and is 1.25 V when VDDQ = 2.5 V.
15. Test conditions shown in (a) of Figure 4 on page 24 unless otherwise noted.
16. This part has an internal voltage regulator; tPOWER is the time that the power needs to be supplied above VDD(minimum) initially before a read or write operation can
be initiated.
17. tCHZ, tCLZ,tOELZ, and tOEHZ are specified with AC test conditions shown in part (b) of Figure 4 on page 24. Transition is measured ±200 mV from steady-state voltage.
18. At any supplied voltage and temperature, tOEHZ is less than tOELZ and tCHZ is less than tCLZ to eliminate bus contention between SRAMs when sharing the same data
bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed to achieve
high-Z before low-Z under the same system conditions.
19. This parameter is sampled and not 100% tested.
Document Number: 001-15145 Rev. *F
Page 25 of 36
[+] Feedback
CY7C1480BV33, CY7C1482BV33, CY7C1486BV33
Switching Waveforms
Figure 3 shows read cycle timing.[18]
Figure 3. Read Cycle Timing
t CYC
CLK
t
t
ADS
CH
t
CL
t
ADH
ADSP
t ADS
tADH
ADSC
t AS
tAH
A1
ADDRESS
A2
t WES
A3
Burst continued with
new base address
tWEH
GW, BWE,
BWx
t CES
Deselect
cycle
tCEH
CE
t ADVS
tADVH
ADV
ADV
suspends
burst.
OE
t OEHZ
t CLZ
Data Out (Q)
High-Z
Q(A1)
t OEV
t CO
t OELZ
t DOH
Q(A2)
t CHZ
Q(A2 + 1)
Q(A2 + 2)
Q(A2 + 3)
Q(A2)
Q(A2 + 1)
t CO
Burst wraps around
to its initial state
Single READ
BURST READ
DON’T CARE
UNDEFINED
Note
18. On this diagram, when CE is LOW: CE1 is LOW, CE2 is HIGH, and CE3 is LOW. When CE is HIGH: CE1 is HIGH, CE2 is LOW, or CE3 is HIGH.
Document Number: 001-15145 Rev. *F
Page 26 of 36
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CY7C1480BV33, CY7C1482BV33, CY7C1486BV33
Switching Waveforms (continued)
Figure 4 shows write cycle timing.[19, 20]
Figure 4. Write Cycle Timing
t CYC
CLK
tCH
t ADS
tCL
tADH
ADSP
t ADS
ADSC extends burst
tADH
t ADS
tADH
ADSC
t AS
tAH
A1
ADDRESS
A2
A3
Byte write signals are
ignored for first cycle when
ADSP initiates burst
t WES tWEH
BWE,
BW X
t WES tWEH
GW
t CES
tCEH
CE
t
t
ADVS ADVH
ADV
ADV suspends burst
OE
t DS
Data In (D)
High-Z
t
OEHZ
tDH
D(A1)
D(A2)
D(A2 + 1)
D(A2 + 1)
D(A2 + 2)
D(A2 + 3)
D(A3)
D(A3 + 1)
D(A3 + 2)
Data Out (Q)
BURST READ
Single WRITE
BURST WRITE
DON’T CARE
Extended BURST WRITE
UNDEFINED
Notes
19. On this diagram, when CE is LOW: CE1 is LOW, CE2 is HIGH, and CE3 is LOW. When CE is HIGH: CE1 is HIGH, CE2 is LOW, or CE3 is HIGH.
20. Full width write can be initiated by either GW LOW; or by GW HIGH, BWE LOW, and BWX LOW.
Document Number: 001-15145 Rev. *F
Page 27 of 36
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CY7C1480BV33, CY7C1482BV33, CY7C1486BV33
Switching Waveforms (continued)
Figure 5 shows read-write cycle timing.[21, 22, 23]
Figure 5. Read/Write Cycle Timing
tCYC
CLK
tCL
tCH
t ADS
tADH
t AS
tAH
ADSP
ADSC
ADDRESS
A1
A2
A3
A4
A5
A6
t WES tWEH
BWE,
BW X
t CES
tCEH
CE
ADV
OE
t DS
tCO
tDH
t OELZ
Data In (D)
High-Z
tCLZ
Data Out (Q)
High-Z
Q(A1)
tOEHZ
D(A5)
D(A3)
Q(A4)
Q(A2)
Back-to-Back READs
Single WRITE
Q(A4+1)
BURST READ
DON’T CARE
Q(A4+2)
D(A6)
Q(A4+3)
Back-to-Back
WRITEs
UNDEFINED
Notes
21. On this diagram, when CE is LOW: CE1 is LOW, CE2 is HIGH, and CE3 is LOW. When CE is HIGH: CE1 is HIGH, CE2 is LOW, or CE3 is HIGH.
22. The data bus (Q) remains in high-Z following a write cycle, unless a new read access is initiated by ADSP or ADSC.
23. GW is HIGH.
Document Number: 001-15145 Rev. *F
Page 28 of 36
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CY7C1480BV33, CY7C1482BV33, CY7C1486BV33
Switching Waveforms (continued)
Figure 6 shows ZZ mode timing.[24, 25]
Figure 6. ZZ Mode Timing
CLK
t ZZ
ZZ
I
t ZZREC
t ZZI
SUPPLY
I DDZZ
t RZZI
ALL INPUTS
(except ZZ)
Outputs (Q)
DESELECT or READ Only
High-Z
DON’T CARE
Notes
24. Device must be deselected when entering ZZ mode. See the section Truth Table on page 11 for all possible signal conditions to deselect the device.
25. DQs are in High Z when exiting ZZ sleep mode.
Document Number: 001-15145 Rev. *F
Page 29 of 36
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CY7C1480BV33, CY7C1482BV33, CY7C1486BV33
Ordering Information
Table 1 lists the key package features and ordering codes. The table contains only the parts that are currently available. If you do not
see what you are looking for, contact your local sales representative. For more information, visit the Cypress website at
www.cypress.com and refer to the product summary page at http://www.cypress.com/products.
Table 1. Key Features and Ordering Informations
Part and Package Type
Ordering Code
165-ball FBGA (15 × 17 × 1.4 mm) Pb-free
CY7C1480BV33-167BZXC
100-pin TQFP (14 × 20 × 1.4 mm) Pb-free
CY7C1480BV33-167AXI
100-pin TQFP (14 × 20 × 1.4 mm) Pb-free
CY7C1480BV33-200AXC
165-ball FBGA (15 × 17 × 1.4 mm)
CY7C1482BV33-200BZI
165-ball FBGA (15 × 17 × 1.4 mm)
CY7C1480BV33-250BZI
Speed Package
(MHz) Diagram
167
Operating
Range
51-85165 Commercial
51-85050 lndustrial
200
51-85050 Commercial
51-85165 lndustrial
250
51-85165 Industrial
Ordering Code Definitions
CY 7C 148X B V33 - XXX XX X
X
Temperature Range: X = C or I
C = Commercial; I = Industrial
Pb-free
Package Type: XX = BZ or AX
BZ = 165-ball FBGA
AX = 100-pin TQFP
Frequency Range: XXX = 167 MHz or 200 MHz or 250 MHz
V33 = 3.3 V
Die Revision
148X = 1480 or 1482
1480 = SCD, 2 Mb × 36 (72 Mb)
1482 = SCD, 4 Mb × 18 (72 Mb)
Marketing Code: 7C = SRAM
Company ID: CY = Cypress
Document Number: 001-15145 Rev. *F
Page 30 of 36
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CY7C1480BV33, CY7C1482BV33, CY7C1486BV33
Package Diagrams
Figure 7. 100-pin TQFP (14 × 20 × 1.4 mm)
51-85050 *D
Document Number: 001-15145 Rev. *F
Page 31 of 36
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CY7C1480BV33, CY7C1482BV33, CY7C1486BV33
Package Diagrams (continued)
Figure 8. 165-ball FBGA (15 × 17 × 1.4 mm)
51-85165 *C
Document Number: 001-15145 Rev. *F
Page 32 of 36
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CY7C1480BV33, CY7C1482BV33, CY7C1486BV33
Package Diagrams (continued)
Figure 9. 209-ball FBGA (14 × 22 × 1.76 mm)
51-85167 *A
Document Number: 001-15145 Rev. *F
Page 33 of 36
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CY7C1480BV33, CY7C1482BV33, CY7C1486BV33
Reference Information
Acronyms
Document Conventions
Table 2. Acronyms
Units of Measure
Acronym
Description
Table 3. Units of Measure
FBGA
fine-pitch ball grid array
I/O
input/output
°C
degree Celcius
JTAG
joint test action group
kW
kilo ohm
LSB
least significant bit
MHz
megahertz
MSB
most significant bit
µA
microampere
PLL
phase-locked loop
µs
microsecond
SRAM
static random access memory
mA
milliampere
TAP
test access port
mm
millimeter
TCK
test clock
ms
millisecond
TDI
test data-in
mV
millivolt
TDO
test data-out
ns
nanosecond
TMS
test mode select
W
ohm
TQFP
thin quad flat pack
%
percent
pF
picofarad
V
volt
W
watt
Document Number: 001-15145 Rev. *F
Symbol
Unit of Measure
Page 34 of 36
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Document History Page
Document Title: CY7C1480BV33/CY7C1482BV33/CY7C1486BV33, 72-Mbit (2 M × 36/4 M × 18/1 M × 72) Pipelined Sync SRAM
Document Number: 001-15145
Revision
ECN
Orig. of
Change
Submission
Date
**
1024385
VKN/KKVTMP
See ECN
New Datasheet
*A
2183566
VKN/PYRS
See ECN
Converted from preliminary to final
Added footnote 14 related to IDD
*B
2898663
NJY
03/24/2010
Removed inactive parts from Ordering Information table; Updated package
diagram.
*C
2905654
VKN
06/04/2010
Removed inactive parts
CY7C1480BV33-167AXC,CY7C1480BV33-200BZXI from the ordering
information table.
*D
3069168
NJY
10/23/10
The part CY7C1482BV33-200BZXC is not available in Oracle PLM and
therefore, it has been removed from the ordering information list.
Added Ordering code definitions.
*E
3207715
NJY
03/28/2011
Updated Ordering Information.
Updated Package Diagrams.
Updated in new template.
*F
3298193
OSN
06/30/2011
Updated template and styles to meet current CY standards.
Added Acronyms and Units tables.
Updated package diagram:
51-85165 – *B to *C revision
Document Number: 001-15145 Rev. *F
Description of Change
Page 35 of 36
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CY7C1480BV33, CY7C1482BV33, CY7C1486BV33
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
Products
Automotive
Clocks & Buffers
Interface
Lighting & Power Control
PSoC Solutions
cypress.com/go/automotive
cypress.com/go/clocks
psoc.cypress.com/solutions
cypress.com/go/interface
PSoC 1 | PSoC 3 | PSoC 5
cypress.com/go/powerpsoc
cypress.com/go/plc
Memory
Optical & Image Sensing
cypress.com/go/memory
cypress.com/go/image
PSoC
Touch Sensing
cypress.com/go/psoc
cypress.com/go/touch
USB Controllers
Wireless/RF
cypress.com/go/USB
cypress.com/go/wireless
© Cypress Semiconductor Corporation, 2007-2011. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 001-15145 Rev. *F
Revised June 30, 2011
Page 36 of 36
i486 is a trademark and Intel and Pentium are registered trademarks of Intel Corporation. All products and company names mentioned in this document may be the trademarks of their respective holders.
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