QIMONDA HYS72T512020HR

September 2006
HYS72T512020HR–[3.7/5]–A
240-Pin Registered-DDR2-SDRAM Modules
DDR2 SDRAM
RoHS Compliant
Internet Data Sheet
Rev. 1.11
Internet Data Sheet
HYS72T512020HR–[3.7/5]–A
Registered DDR2 SDRAM Modules
HYS72T512020HR–[3.7/5]–A
Revision History: 2006-09, Rev. 1.11
Page
Subjects (major changes since last revision)
All
Qimonda Update
All
Adapted internet edition
Previous Revision: 2005-05, Rev. 1.0
27,31
SPD Update
36
Package outline figure updated
Previous Revision: 2005-02, Rev. 0.5
26, 27
Corrected IDD Currents
26, 27
Removed IDD6(l) from IDD specification tables
Previous Revision: 2005-02, Rev. 0.5
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qag_techdoc_rev400 / 3.2 QAG / 2006-07-21
03062006-TZ8J-GNDA
2
Internet Data Sheet
HYS72T512020HR–[3.7/5]–A
Registered DDR2 SDRAM Modules
1
Overview
1.1
Features
This chapter contains features and the description
• 240-pin PC2-4200 and PC2-3200 DDR2 SDRAM memory
modules for PC, Workstation and Server main memory
applications
• Two ranks 512M x 72 module organization with 256M ×4
chip organization
• Standard Double-Data-Rate-Two Synchronous DRAMs
(DDR2 SDRAM) with a single + 1.8 V (± 0.1 V) power
supply
• Built with 1-Gbit DDR2 SDRAMs in P-TFBGA-68 chipsize
packages.
• Programmable CAS Latencies (3, 4 & 5), Burst Length (4
& 8) and Burst Type
• Auto Refresh (CBR) and Self Refresh
• All inputs and outputs SSTL_1.8 compatible
• Off-Chip Driver Impedance Adjustment (OCD) and On-Die
Termination (ODT)
• Serial Presence Detect with E2PROM
• RDIMM Dimensions (nominal): 50.00 mm high, 133.35
mm wide
• Qimonda Proprietary Raw Card Layout
• RoHS compliant products1)
TABLE 1
Performance for DDR2-533 and DDR2-400
Product Type Speed Code
–3.7
–5
Units
Speed Grade
PC2–4200 4–4–4
PC2–3200 3–3–3
—
266
200
MHz
266
200
MHz
200
200
MHz
15
15
ns
15
15
ns
45
40
ns
60
55
ns
Max. Clock Frequency
@CL5
@CL4
@CL3
Min. RAS-CAS-Delay
Min. Row Precharge Time
Min. Row Active Time
Min. Row Cycle Time
fCK5
fCK4
fCK3
tRCD
tRP
tRAS
tRC
1) RoHS Compliant Product: Restriction of the use of certain hazardous substances (RoHS) in electrical and electronic equipment as defined
in the directive 2002/95/EC issued by the European Parliament and of the Council of 27 January 2003. These substances include mercury,
lead, cadmium, hexavalent chromium, polybrominated biphenyls and polybrominated biphenyl ethers.
Rev. 1.11, 2006-09
03062006-TZ8J-GNDA
3
Internet Data Sheet
HYS72T512020HR–[3.7/5]–A
Registered DDR2 SDRAM Modules
1.2
Description
The Qimonda HYS72T512020HR–[3.7/5]–A module family
are Registered DIMM modules “RDIMMs” with 50,0 mm
height based on DDR2 technology.
DIMMs are available as ECC modules in 512M x 72
(4 GByte) organization and density, intended for mounting
into 240-Pin connector sockets.The memory array is
designed with 1-Gbit Double-Data-Rate-Two (DDR2)
Synchronous DRAMs. All control and address signals are re-
driven on the DIMM using register devices and a PLL for the
clock distribution. This reduces capacitive loading to the
system bus, but adds one cycle to the SDRAM timing.
Decoupling capacitors are mounted on the PCB board. The
DIMMs feature serial presence detect based on a serial
E2PROM device using the 2-pin I2C protocol. The first
128 bytes are programmed with configuration data and the
second 128 bytes are available to the customer.
TABLE 2
Ordering Information for RoHS Compliant Products
Product Type1)
Compliance Code2)
Description
SDRAM Technology
4 GB 2R×4 PC2–4200R–444–11–ZZ
2 Ranks, ECC
1 Gbit (×4)
4 GB 2R×4 PC2–3200R–333–11–ZZ
2 Ranks, ECC
1 Gbit (×4)
PC2–4200
HYS72T512020HR–3.7–A
PC2-3200
HYS72T512020HR–5–A
1) All part numbers end with a place code, designating the silicon die revision. Example: HYS72T512020HR–5–A, indicating Rev. “A” dies
are used for DDR2 SDRAM components. For all Qimonda DDR2 module and component nomenclature see Chapter 6 of this data sheet.
2) The Compliance Code is printed on the module label and describes the speed grade, for example “PC2–4200R–444–11–ZZ”, where
4200R means Registered DIMM modules with 4.26 GB/sec Module Bandwidth and “444-11” means Column Address Strobe (CAS) latency
= 4, Row Column Delay (RCD) latency = 4 and Row Precharge (RP) latency = 4 using the latest JEDEC SPD Revision 1.1 and produced
on the Raw Card “ZZ”
TABLE 3
Address Format
DIMM
Density
Module
Organization
Memory
Ranks
ECC/
Non-ECC
# of
SDRAMs
# of row/bank/columns bits
Raw Card
4 GB
512M × 72
2
ECC
36
14/3/11
ZZ
TABLE 4
Components on Modules
Product Type1)
DRAM Components1)
DRAM Density
DRAM Organization
HYS72T512020HR
HYB18T1G400AF
1 Gbit
256M × 4
Note 2)
1) Green Product
2) For a detailed description of all available functions of the DRAM components on these modules see the component data sheet.
Rev. 1.11, 2006-09
03062006-TZ8J-GNDA
4
Internet Data Sheet
HYS72T512020HR–[3.7/5]–A
Registered DDR2 SDRAM Modules
2
Pin Configuration
2.1
Pin Configuration
The pin configuration of the Registered DDR2 SDRAM DIMM
is listed by function in Table 5 (240 pins). The abbreviations
used in columns Pin and Buffer Type are explained in Table 6
and Table 7 respectively. The pin numbering is depicted in
Figure 1.
TABLE 5
Pin Configuration of RDIMM
Ball No.
Name
Pin
Type
Buffer
Type
Function
CK0
I
SSTL
Clock Signal CK0, Complementary Clock Signal CK0
Clock Signals
185
186
CK0
I
SSTL
52
CKE0
I
SSTL
171
CKE1
I
SSTL
NC
NC
—
Not Connected
Note: 1-Rank module
193
S0
I
SSTL
76
S1
I
SSTL
Chip Select Rank 1:0
Note: 2-Ranks module
NC
NC
—
Not Connected
Note: 1-Rank module
192
RAS
I
SSTL
74
CAS
I
SSTL
Row Address Strobe (RAS), Column Address Strobe (CAS), Write
Enable (WE)
73
WE
I
SSTL
18
RESET
I
CMOS
Register Reset
71
BA0
I
SSTL
Bank Address Bus 1:0
190
BA1
I
SSTL
54
BA2
I
SSTL
Bank Address Bus 2
NC
I
SSTL
Not Connected
Clock Enables 1:0
Note: 2-Ranks module
Control Signals
Address Signals
Rev. 1.11, 2006-09
03062006-TZ8J-GNDA
6
Internet Data Sheet
HYS72T512020HR–[3.7/5]–A
Registered DDR2 SDRAM Modules
Ball No.
Name
Pin
Type
Buffer
Type
Function
188
A0
I
SSTL
Address Bus 12:0, Address Signal 10/AutoPrecharge
183
A1
I
SSTL
63
A2
I
SSTL
182
A3
I
SSTL
61
A4
I
SSTL
60
A5
I
SSTL
180
A6
I
SSTL
58
A7
I
SSTL
179
A8
I
SSTL
177
A9
I
SSTL
70
A10
I
SSTL
AP
I
SSTL
57
A11
I
SSTL
176
A12
I
SSTL
196
A13
I
SSTL
Address Signal 13
174
173
NC
NC
—
Not Connected
A14
I
SSTL
Address Signal 14
NC
NC
—
Not Connected
A15
I
SSTL
Address Signal 14
NC
NC
—
Not Connected
Rev. 1.11, 2006-09
03062006-TZ8J-GNDA
7
Internet Data Sheet
HYS72T512020HR–[3.7/5]–A
Registered DDR2 SDRAM Modules
Ball No.
Name
Pin
Type
Buffer
Type
Function
3
DQ0
I/O
SSTL
Data Bus 63:0
4
DQ1
I/O
SSTL
9
DQ2
I/O
SSTL
10
DQ3
I/O
SSTL
122
DQ4
I/O
SSTL
123
DQ5
I/O
SSTL
128
DQ6
I/O
SSTL
129
DQ7
I/O
SSTL
12
DQ8
I/O
SSTL
13
DQ9
I/O
SSTL
21
DQ10
I/O
SSTL
22
DQ11
I/O
SSTL
131
DQ12
I/O
SSTL
132
DQ13
I/O
SSTL
140
DQ14
I/O
SSTL
141
DQ15
I/O
SSTL
24
DQ16
I/O
SSTL
25
DQ17
I/O
SSTL
30
DQ18
I/O
SSTL
31
DQ19
I/O
SSTL
143
DQ20
I/O
SSTL
144
DQ21
I/O
SSTL
149
DQ22
I/O
SSTL
150
DQ23
I/O
SSTL
33
DQ24
I/O
SSTL
34
DQ25
I/O
SSTL
39
DQ26
I/O
SSTL
40
DQ27
I/O
SSTL
152
DQ28
I/O
SSTL
153
DQ29
I/O
SSTL
158
DQ30
I/O
SSTL
159
DQ31
I/O
SSTL
80
DQ32
I/O
SSTL
81
DQ33
I/O
SSTL
86
DQ34
I/O
SSTL
87
DQ35
I/O
SSTL
199
DQ36
I/O
SSTL
200
DQ37
I/O
SSTL
205
DQ38
I/O
SSTL
Data Signals
Rev. 1.11, 2006-09
03062006-TZ8J-GNDA
8
Internet Data Sheet
HYS72T512020HR–[3.7/5]–A
Registered DDR2 SDRAM Modules
Ball No.
Name
Pin
Type
Buffer
Type
Function
206
DQ39
I/O
SSTL
Data Bus 63:0
89
DQ40
I/O
SSTL
90
DQ41
I/O
SSTL
95
DQ42
I/O
SSTL
96
DQ43
I/O
SSTL
208
DQ44
I/O
SSTL
209
DQ45
I/O
SSTL
214
DQ46
I/O
SSTL
215
DQ47
I/O
SSTL
98
DQ48
I/O
SSTL
99
DQ49
I/O
SSTL
107
DQ50
I/O
SSTL
108
DQ51
I/O
SSTL
217
DQ52
I/O
SSTL
218
DQ53
I/O
SSTL
226
DQ54
I/O
SSTL
227
DQ55
I/O
SSTL
110
DQ56
I/O
SSTL
111
DQ57
I/O
SSTL
116
DQ58
I/O
SSTL
117
DQ59
I/O
SSTL
229
DQ60
I/O
SSTL
230
DQ61
I/O
SSTL
235
DQ62
I/O
SSTL
236
DQ63
I/O
SSTL
42
CB0
I/O
SSTL
43
CB1
I/O
SSTL
48
CB2
I/O
SSTL
49
CB3
I/O
SSTL
161
CB4
I/O
SSTL
162
CB5
I/O
SSTL
167
CB6
I/O
SSTL
168
CB7
I/O
SSTL
Check Bits
Rev. 1.11, 2006-09
03062006-TZ8J-GNDA
Check Bits 7:0
9
Internet Data Sheet
HYS72T512020HR–[3.7/5]–A
Registered DDR2 SDRAM Modules
Ball No.
Name
Pin
Type
Buffer
Type
Function
7
DQS0
I/O
SSTL
Data Strobes 17:0
6
DQS0
I/O
SSTL
16
DQS1
I/O
SSTL
15
DQS1
I/O
SSTL
28
DQS2
I/O
SSTL
27
DQS2
I/O
SSTL
37
DQS3
I/O
SSTL
36
DQS3
I/O
SSTL
84
DQS4
I/O
SSTL
83
DQS4
I/O
SSTL
93
DQS5
I/O
SSTL
92
DQS5
I/O
SSTL
105
DQS6
I/O
SSTL
104
DQS6
I/O
SSTL
114
DQS7
I/O
SSTL
113
DQS7
I/O
SSTL
46
DQS8
I/O
SSTL
45
DQS8
I/O
SSTL
125
DQS9
I/O
SSTL
126
DQS9
I/O
SSTL
134
DQS10
I/O
SSTL
135
DQS10
I/O
SSTL
146
DQS11
I/O
SSTL
147
DQS11
I/O
SSTL
155
DQS12
I/O
SSTL
156
DQS12
I/O
SSTL
202
DQS13
I/O
SSTL
203
DQS13
I/O
SSTL
211
DQS14
I/O
SSTL
212
DQS14
I/O
SSTL
223
DQS15
I/O
SSTL
224
DQS15
I/O
SSTL
232
DQS16
I/O
SSTL
233
DQS16
I/O
SSTL
164
DQS17
I/O
SSTL
165
DQS17
I/O
SSTL
Data Strobe Bus
Rev. 1.11, 2006-09
03062006-TZ8J-GNDA
10
Internet Data Sheet
HYS72T512020HR–[3.7/5]–A
Registered DDR2 SDRAM Modules
Ball No.
Name
Pin
Type
Buffer
Type
Function
125
DM0
I
SSTL
134
DM1
I
SSTL
Data Masks 8:0
Note: ×8 based module
146
DM2
I
SSTL
155
DM3
I
SSTL
202
DM4
I
SSTL
211
DM5
I
SSTL
223
DM6
I
SSTL
232
DM7
I
SSTL
164
DM8
I
SSTL
120
SCL
I
CMOS
Serial Bus Clock
119
SDA
I/O
OD
Serial Bus Data
239
SA0
I
CMOS
Serial Address Select Bus 2:0
240
SA1
I
CMOS
101
SA2
I
CMOS
Data Mask
EEPROM
Parity
55
ERR_OUT
O
CMOS
PAR_IN
I
CMOS
VREF
VDDSPD
VDDQ
AI
—
I/O Reference Voltage
PWR
—
EEPROM Power Supply
PWR
—
I/O Driver Power Supply
VDD
PWR
—
Power Supply
2, 5, 8, 11, 14, 17, VSS
20, 23, 26, 29, 32,
35, 38, 41, 44, 47,
50, 65, 66, 79, 82,
85, 88, 91, 94, 97,
100, 103, 106, 109,
112, 115, 118, 121,
124, 127, 130, 133,
136, 139, 142, 145,
148, 151, 154, 157,
160, 163, 166, 169,
198, 201, 204, 207,
210, 213, 216, 219,
222, 225, 228, 231,
234, 237
GND
—
Ground Plane
Parity bits
Power Supplies
1
238
51, 56, 62, 72, 75,
78, 170, 175,, 181,
191, 194
53, 59, 64, 67, 69,
172, 178, 184,,
187, 189, 197
Rev. 1.11, 2006-09
03062006-TZ8J-GNDA
11
Internet Data Sheet
HYS72T512020HR–[3.7/5]–A
Registered DDR2 SDRAM Modules
Ball No.
Name
Pin
Type
Buffer
Type
Function
19, 55, 68, 102,
NC
137, 138, 173, 220,
221
NC
—
Not connected
195
ODT0
I
SSTL
77
ODT1
I
SSTL
On-Die Termination Control 1:0
Note: 2-Ranks module
NC
NC
—
Other Pins
Note: 1-Rank modules
TABLE 6
Abbreviations for Buffer Type
Abbreviation
Description
SSTL
Serial Stub Terminated Logic (SSTL_18)
CMOS
CMOS Levels
OD
Open Drain. The corresponding pin has 2 operational states, active low and tristate,
and allows multiple devices to share as a wire-OR.
TABLE 7
Abbreviations for Pin Type
Abbreviation
Description
I
Standard input-only pin. Digital levels.
O
Output. Digital levels.
I/O
I/O is a bidirectional input/output signal.
AI
Input. Analog levels.
PWR
Power
GND
Ground
NU
Not Usable
NC
Not Connected
Rev. 1.11, 2006-09
03062006-TZ8J-GNDA
12
Internet Data Sheet
HYS72T512020HR–[3.7/5]–A
Registered DDR2 SDRAM Modules
FIGURE 1
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0337
Internet Data Sheet
HYS72T512020HR–[3.7/5]–A
Registered DDR2 SDRAM Modules
3
Electrical Characteristics
This chapter lists the electrical characteristics.
3.1
Absolute Maximum Ratings
This chapter contains the absolute maximum ratings table.
TABLE 8
Absolute Maximum Ratings
Parameter
Symbol
Voltage on any pins relative to VSS
Voltage on VDD relative to VSS
Voltage on VDD Q relative to VSS
Storage Humidity (without condensation)
Values
VIN, VOUT
VDD
VDDQ
HSTG
Unit
Note
Min.
Max.
–0.5
2.3
V
1)
–1.0
2.3
V
1)
–0.5
2.3
V
1)
5
95
%
1)
1) Stresses greater than those listed may cause permanent damage to the device. This is a stress rating only, and device functional operation
at or above the conditions indicated is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
reliability
3.2
DC Operating Conditions
This chapter describes the operating conditions.
TABLE 9
Operating Conditions
Parameter
Symbol
Values
Unit
Min.
Max.
0
+55
°C
0
+95
°C
Storage Temperature
TOPR
TCASE
TSTG
–50
+100
°C
Barometric Pressure (operating & storage)
PBar
+69
+105
kPa
Operating Humidity (relative)
HOPR
10
90
%
DIMM Module Operating Temperature Range (ambient)
DRAM Component Case Temperature Range
1)
2)
3)
4)
Note
1)2)3)4)
5)
DRAM Component Case Temperature is the surface temperature in the center on the top side of any of the DRAMs.
Within the DRAM Component Case Temperature range all DRAM specification will be supported.
Above 85 °C DRAM case temperature the Auto-Refresh command interval has to be reduced to tREFI = 3.9 µs.
Self-Refresh period is hard-coded in the DRAMs and therefore it is imperative that the system ensures the DRAM is below 85 °C case
temperature before initiating self-refresh operation.
5) Up to 3000 m
Rev. 1.11, 2006-09
03062006-TZ8J-GNDA
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Internet Data Sheet
HYS72T512020HR–[3.7/5]–A
Registered DDR2 SDRAM Modules
TABLE 10
Supply Voltage Levels and DC Operating Conditions
Parameter
Device Supply Voltage
Output Supply Voltage
Input Reference Voltage
SPD Supply Voltage
DC Input Logic High
DC Input Logic Low
Symbol
VDD
VDDQ
VREF
VDDSPD
VIH (DC)
VIL (DC)
IL
Values
Unit
Min.
Nom.
Max.
1.7
1.8
1.9
V
1.7
1.8
1.9
V
1)
0.49 x VDDQ
0.5 x VDDQ
0.51 x VDDQ
V
2)
1.7
—
3.6
V
VREF + 0.125
—
V
–0.30
—
VDDQ + 0.3
VREF – 0.125
V
In / Output Leakage Current
–5
—
5
µA
1) Under all conditions, VDDQ must be less than or equal to VDD
2) Peak to peak AC noise on VREF may not exceed ± 2% VREF (DC).VREF is also expected to track noise variations in VDDQ.
3) Input voltage for any connector pin under test of 0 V ≤ VIN ≤ VDDQ + 0.3 V; all other pins at 0 V. Current is per pin
Rev. 1.11, 2006-09
03062006-TZ8J-GNDA
Note
16
3)
Internet Data Sheet
HYS72T512020HR–[3.7/5]–A
Registered DDR2 SDRAM Modules
3.3
AC Characteristics
This chapter describes the AC characteristics.
3.3.1
Speed Grades Definitions
This chapter contains the Speed Grade Definition tables.
TABLE 11
Speed Grade Definition Speed Bins for DDR2-533 and DDR2-400
Speed Grade
DDR2–533C
DDR2–400B
IFX Sort Name
–3.7
–5
CAS-RCD-RP latencies
4–4–4
3–3–3
Parameter
Clock Frequency
@ CL = 3
@ CL = 4
@ CL = 5
Row Active Time
Row Cycle Time
RAS-CAS-Delay
Row Precharge Time
Unit
Note
tCK
Symbol
Min.
Max.
Min.
Max.
—
tCK
tCK
tCK
tRAS
tRC
tRCD
tRP
5
8
5
8
ns
1)2)3)4)
3.75
8
5
8
ns
1)2)3)4)
3.75
8
5
8
ns
1)2)3)4)
45
70000
40
70000
ns
1)2)3)4)5)
60
—
55
—
ns
1)2)3)4)
15
—
15
—
ns
1)2)3)4)
15
—
15
—
ns
1)2)3)4)
1) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew
Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode. Timings are further guaranteed for normal
OCD drive strength (EMRS(1) A1 = 0) only.
2) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross. The DQS / DQS, RDQS / RDQS,
input reference level is the crosspoint when in differential strobe mode
3) Inputs are not recognized as valid until VREF stabilizes. During the period before VREF stabilizes, CKE = 0.2 x VDDQ is recognized as low.
4) The output timing reference voltage level is VTT.
5) tRAS.MAX is calculated from the maximum amount of time a DDR2 device can operate without a refresh command which is equal to 9 x tREFI.
Rev. 1.11, 2006-09
03062006-TZ8J-GNDA
17
Internet Data Sheet
HYS72T512020HR–[3.7/5]–A
Registered DDR2 SDRAM Modules
3.3.2
AC Timing Parameters
This chapter contains the AC Timing Parameters.
TABLE 12
Timing Parameter by Speed Grade - DDR2-400 & DDR2-533
Parameter
Symbol
DDR2–533
Unit Note1)2)
DDR2–400
3)4)5)6)7)
DQ output access time from CK/CK
CAS A to CAS B command period
CK,CK high-level width
CKE minimum high and low pulse
width
CK,CK low-level width
Auto-Precharge write recovery +
precharge time
Min.
Max.
Min.
Max.
tAC
tCCD
tCH
tCKE
–500
+500
–600
+600
ps
2
—
2
—
0.45
0.55
0.45
0.55
3
—
3
—
tCK
tCK
tCK
tCL
tDAL
0.45
0.55
0.45
0.55
WR + tRP
—
WR + tRP
—
tCK
tCK
tIS + tCK + tIH ––
tIS + tCK + tIH —
ns
Minimum time clocks remain ON after tDELAY
CKE asynchronously drops LOW
DQ and DM input hold time
(differential data strobe)
tDH(base)
225
––
275
––
ps
DQ and DM input hold time (single
ended data strobe)
tDH1(base)
–25
—
25
—
ps
DQ and DM input pulse width (each
input)
tDIPW
0.35
—
0.35
—
tCK
DQS output access time from CK/CK
tDQSCK
tDQSL,H
–450
+450
–500
+500
ps
0.35
—
0.35
—
tCK
—
300
—
350
ps
DQS input low (high) pulse width
(write cycle)
DQS-DQ skew (for DQS & associated tDQSQ
DQ signals)
Write command to 1st DQS latching
transition
tDQSS
– 0.25
+ 0.25
– 0.25
+ 0.25
tCK
DQ and DM input setup time
(differential data strobe)
tDS(base)
100
—
150
—
ps
DQ and DM input setup time (single
ended data strobe)
tDS1(base)
–25
—
25
—
ps
DQS falling edge hold time from CK
(write cycle)
tDSH
0.2
—
0.2
—
tCK
DQS falling edge to CK setup time
(write cycle)
tDSS
0.2
—
0.2
—
tCK
Four Activate Window period
tFAW
37.5
—
37.5
—
ns
50
—
50
—
ns
Clock half period
Data-out high-impedance time from
CK/CK
Address and control input hold time
Rev. 1.11, 2006-09
03062006-TZ8J-GNDA
tHP
tHZ
MIN. (tCL, tCH)
—
tAC.MAX
—
tAC.MAX
ps
tIH(base)
375
—
475
—
ps
18
MIN. (tCL, tCH)
8)
Internet Data Sheet
HYS72T512020HR–[3.7/5]–A
Registered DDR2 SDRAM Modules
Parameter
Symbol
DDR2–533
Unit Note1)2)
DDR2–400
3)4)5)6)7)
Min.
Max.
Min.
Max.
0.6
—
0.6
—
tCK
250
—
350
—
ps
2 x tAC.MIN
2 ξ tAC.MIN
tAC.MIN
tAC.MAX
tAC.MAX
ps
tAC.MIN
tAC.MAX
tAC.MAX
0
12
0
12
ns
Mode register set command cycle time tMRD
2
—
2
—
tCK
tOIT
tQH
tQHS
tREFI
0
12
0
12
ns
tHP – tQHS
—
tHPQ – tQHS
—
—
400
—
450
ps
—
7.8
—
7.8
µs
9)
—
3.9
—
3.9
µs
10)
Address and control input pulse width tIPW
(each input)
Address and control input setup time
tIS(base)
DQ low-impedance time from CK / CK tLZ(DQ)
DQS low-impedance from CK / CK
Mode register set command to ODT
update delay
OCD drive mode output delay
Data output hold time from DQS
Data hold skew factor
Average periodic refresh Interval
tLZ(DQS)
tMOD
ps
Auto-Refresh to Active/Auto-Refresh
command period
tRFC
127.5
—
127.5
—
ns
Precharge-All (8 banks) command
period
tRP
15 + 1tCK
—
15 + 1tCK
—
ns
Read preamble
tRPRE
tRPST
tRRD
0.9
1.1
0.9
1.1
0.40
0.60
0.40
0.60
tCK
tCK
7.5
—
7.5
—
ns
7.5
—
7.5
—
ns
Read postamble
Active bank A to Active bank B
command period
Internal Read to Precharge command tRTP
delay
0.35 x tCK
—
0.35 x tCK
—
0.40
0.60
0.40
0.60
tCK
tCK
15
—
15
—
ns
Write recovery time for write with Auto- WR
Precharge
tWR/tCK
—
tWR/tCK
—
tCK
Internal Write to Read command delay tWTR
7.5
—
10
—
ns
2
—
2
—
tCK
6 – AL
—
6 – AL
—
tCK
Write preamble
Write postamble
Write recovery time for write without
Auto-Precharge
Exit power down to any valid
command
(other than NOP or Deselect)
tWPRE
tWPST
tWR
tXARD
Exit active power-down mode to Read tXARDS
command (slow exit, lower power)
Exit precharge power-down to any
valid command (other than NOP or
Deselect)
tXP
2
—
2
—
tCK
Exit Self-Refresh to non-Read
command
tXSNR
tRFC +10
—
tRFC +10
—
ns
Exit Self-Refresh to Read command
tXSRD
200
—
200
—
tCK
1) For details and notes see the relevant QIMONDA component data sheet
2) VDDQ = 1.8 V ± 0.1 V; VDD = 1.8 V ± 0.1 V. See notes 4)5)6)7)
Rev. 1.11, 2006-09
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11)
Internet Data Sheet
HYS72T512020HR–[3.7/5]–A
Registered DDR2 SDRAM Modules
3) Timing that is not specified is illegal and after such an event, in order to guarantee proper operation, the DRAM must be powered down
and then restarted through the specified initialization sequence before normal operation can continue.
4) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew
Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode.
5) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross. The DQS/DQS, RDQS/RDQS,
input reference level is the crosspoint when in differential strobe mode
6) Inputs are not recognized as valid until VREF stabilizes. During the period before VREF stabilizes, CKE = 0.2 x VDDQ is recognized as low.
7) The output timing reference voltage level is VTT.
8) x16 (2k page size), not on 256 Mbit component
9) 0 ≤ TCASE ≤ 85 °C
10) 85 °C < TCASE ≤ 95 °C
11) x4 & x8
Rev. 1.11, 2006-09
03062006-TZ8J-GNDA
20
Internet Data Sheet
HYS72T512020HR–[3.7/5]–A
Registered DDR2 SDRAM Modules
3.3.3
ODT AC Electrical Characteristics
This chapter contains the ODT AC electrical characteristics tables.
TABLE 13
ODT AC Characteristics and Operating Conditions for DDR2-533/DDR2-400
Symbol
tAOND
tAON
tAONPD
tAOFD
tAOF
tAOFPD
tANPD
tAXPD
Parameter / Condition
Values
Unit
Min.
Max.
ODT turn-on delay
2
2
tCK
ODT turn-on
tAC.MIN
tAC.MIN + 2 ns
tAC.MAX + 1 ns
2 tCK + tAC.MAX + 1 ns
ns
ODT turn-on (Power-Down Modes)
Note
1)
ns
ODT turn-off delay
2.5
2.5
tCK
ODT turn-off
tAC.MAX + 0.6 ns
2.5 tCK + tAC.MAX + 1 ns
ns
ODT turn-off (Power-Down Modes)
tAC.MIN
tAC.MIN + 2 ns
ODT to Power Down Mode Entry Latency
3
—
ODT Power Down Exit Latency
8
—
tCK
tCK
2)
ns
1) ODT turn on time min. is when the device leaves high impedance and ODT resistance begins to turn on. ODT turn on time max is when
the ODT resistance is fully on. Both are measure from tAOND.
2) ODT turn off time min. is when the device starts to turn off ODT resistance. ODT turn off time max is when the bus is in high impedance.
Both are measured from tAOFD.
Rev. 1.11, 2006-09
03062006-TZ8J-GNDA
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Internet Data Sheet
HYS72T512020HR–[3.7/5]–A
Registered DDR2 SDRAM Modules
3.4
Currents Specifications and Conditions
TABLE 14
IDD Measurement Conditions
Parameter
Symbol
Operating Current 0
IDD0
One bank Active - Precharge; tCK = tCK.MIN, tRC = tRC.MIN, tRAS = tRAS.MIN, CKE is HIGH, CS is
HIGH between valid commands. Address and control inputs are SWITCHING, Databus inputs
are SWITCHING.
Operating Current 1
One bank Active - Read - Precharge; IOUT = 0 mA, BL = 4, tCK = tCK.MIN, tRC = tRC.MIN, tRAS =
tRAS.MIN, tRCD = tRCD.MIN, AL = 0, CL = CL.MIN; CKE is HIGH, CS is HIGH between valid
commands. Address and control inputs are SWITCHING, Databus inputs are SWITCHING.
IDD1
Precharge Standby Current
All banks idle; CS is HIGH; CKE is HIGH; tCK = tCK.MIN; Other control and address inputs are
SWITCHING, Data bus inputs are SWITCHING
IDD2N
Precharge Power-Down Current
Other control and address inputs are STABLE, Data bus inputs are FLOATING.
IDD2P
Precharge Quiet Standby Current
All banks idle; CS is HIGH; CKE is HIGH; tCK = tCK.MIN; Other control and address inputs are
STABLE, Data bus inputs are FLOATING.
IDD2Q
Active Power-Down Current
IDD3P(0)
All banks open; tCK = tCK.MIN, CKE is LOW; Other control and address inputs are STABLE, Data
bus inputs are FLOATING. MRS A12 bit is set to LOW (Fast Power-down Exit);
Active Power-Down Current
IDD3P(1)
All banks open; tCK = tCK.MIN, CKE is LOW; Other control and address inputs are STABLE, Data
bus inputs are FLOATING. MRS A12 bit is set to HIGH (Slow Power-down Exit);
Active Standby Current
IDD3N
Burst Read: All banks open; Continuous burst reads; BL = 4; AL = 0, CL = CLMIN; tCK = tCK.MIN;
tRAS = tRAS.MAX, tRP = tRP.MIN; CKE is HIGH, CS is HIGH between valid commands. Address
inputs are SWITCHING; Data Bus inputs are SWITCHING; IOUT = 0 mA.
Operating Current
IDD4R
Burst Read: All banks open; Continuous burst reads; BL = 4; AL = 0, CL = CLMIN; tCK = tCK.MIN;
tRAS = tRAS.MAX., tRP = tRP.MIN; CKE is HIGH, CS is HIGH between valid commands. Address
inputs are SWITCHING; Data Bus inputs are SWITCHING; IOUT = 0 mA.
Operating Current
IDD4W
Burst Write: All banks open; Continuous burst writes; BL = 4; AL = 0, CL = CLMIN; tCK = tCK.MIN;
tRAS = tRAS.MAX., tRP = tRP.MAX; CKE is HIGH, CS is HIGH between valid commands. Address
inputs are SWITCHING; Data Bus inputs are SWITCHING;
Burst Refresh Current
IDD5B
tCK = tCK.MIN., Refresh command every tRFC = tRFC.MIN interval, CKE is HIGH, CS is HIGH
between valid commands, Other control and address inputs are SWITCHING, Data bus inputs
are SWITCHING.
Distributed Refresh Current
IDD5D
tCK = tCK.MIN, Refresh command every tRFC = tREFI interval, CKE is LOW and CS is HIGH
between valid commands, Other control and address inputs are SWITCHING, Data bus inputs
are SWITCHING.
Rev. 1.11, 2006-09
03062006-TZ8J-GNDA
22
Note1)2)3)4)5)6)7)8)
Internet Data Sheet
HYS72T512020HR–[3.7/5]–A
Registered DDR2 SDRAM Modules
Parameter
Symbol
Self-Refresh Current
CKE ≤ 0.2 V; external clock off, CK and CK at 0 V; Other control and address inputs are
FLOATING, Data bus inputs are FLOATING. RESET is LOW. IDD6 current values are
guaranteed up to TCASE of 85 °C max.
IDD6
Note1)2)3)4)5)6)7)8)
All Bank Interleave Read Current
IDD7
All banks are being interleaved at minimum tRC without violating tRRD using a burst length of 4.
Control and address bus inputs are STABLE during DESELECTS. IOUT = 0 mA.
1) VDDQ = 1.8 V ± 0.1 V; VDD = 1.8 V ± 0.1 V
2) IDD specifications are tested after the device is properly initialized and IDD parameter are specified with ODT disabled.
3) Definitions for IDD see Table 15
4) IDD1, IDD4R and IDD7 current measurements are defined with the outputs disabled (IOUT = 0 mA). To achieve this on module level the output
buffers can be disabled using an EMRS(1) (Extended Mode Register Command) by setting A12 bit to HIGH.
5) For two rank modules: for all active current measurements the other rank is in Precharge Power-Down Mode IDD2P
6) RESET signal is HIGH for all currents, except for IDD6 (Self Refresh)
7) All current measurements includes Register and PLL current consumption
8) For details and notes see the relevant QIMONDA component data sheet
TABLE 15
Definitions for IDD
Parameter
Description
LOW
VIN ≤ VIL(ac).MAX, HIGH is defined as VIN ≥ VIH(ac).MIN
STABLE
inputs are stable at a HIGH or LOW level
FLOATING
inputs are VREF = VDDQ /2
SWITCHING
inputs are changing between HIGH and LOW every other clock (once per 2 cycles) for address and control
signals, and inputs changing between HIGH and LOW every other data transfer (once per cycle) for DQ
signals not including mask or strobes.
Rev. 1.11, 2006-09
03062006-TZ8J-GNDA
23
Internet Data Sheet
HYS72T512020HR–[3.7/5]–A
Registered DDR2 SDRAM Modules
TABLE 16
IDD Specification for HYS72T512020HR-3.7-A
Product Type
HYS72T512020HR–3.7–A
Organization
4G
Unit
Note1)
2 Ranks
×72
–3.7
Symbol
Max.
IDD0
IDD1
IDD2N
IDD2P
IDD2Q
IDD3N
IDD3P( MRS = 0)
IDD3P( MRS = 1)
IDD4R
IDD4W
IDD5B
IDD5D
IDD6
IDD7
1950
mA
2)
2130
mA
2)
2160
mA
3)
710
mA
3)
1650
mA
3)
2300
mA
3)
1110
mA
3)
720
mA
3)
3210
mA
2)
3120
mA
2)
3930
mA
2)
750
mA
3)
205
mA
3)
4740
mA
2)
1) ModuleIDDis calculated on the basis of component IDDand includes currents of Registers and PLL. ODT disabled. IDD1, IDD4R, and IDD7, are
defined with the outputs disabled.
2) The other rank is in IDD2P Precharge Power-Down Standby Current mode
3) Both ranks are in the same IDDcurrent mode
Rev. 1.11, 2006-09
03062006-TZ8J-GNDA
24
Internet Data Sheet
HYS72T512020HR–[3.7/5]–A
Registered DDR2 SDRAM Modules
TABLE 17
IDD Specification for HYS72T512020HR–5–A
Product Type
HYS72T512020HR–5–A
Organization
4G
Unit
Note1)
2 Ranks
×72
–5
Symbol
Max.
IDD0
IDD1
IDD2N
IDD2P
IDD2Q
IDD3N
IDD3P( MRS = 0)
IDD3P( MRS = 1)
IDD4R
IDD4W
IDD5B
IDD5D
IDD6
IDD7
1770
mA
2)
1950
mA
2)
1670
mA
3)
610
mA
3)
1410
mA
3)
1850
mA
3)
870
mA
3)
620
mA
3)
2580
mA
2)
2490
mA
2)
3750
mA
2)
660
mA
3)
205
mA
3)
4200
mA
2)
1) ModuleIDD is calculated on the basis of component IDDand includes currents of Registers and PLL. ODT disabled. IDD1, IDD4R, and IDD7, are
defined with the outputs disabled.
2) The other rank is in IDD2P Precharge Power-Down Standby Current mode
3) Both ranks are in the same IDDcurrent mode
Rev. 1.11, 2006-09
03062006-TZ8J-GNDA
25
Internet Data Sheet
HYS72T512020HR–[3.7/5]–A
Registered DDR2 SDRAM Modules
3.4.1
Currents Test Conditions
For testing the IDD parameters, the following timing parameters are used:
TABLE 18
IDD Measurement Test Conditions for DDR2–400 and DDR2–533
Parameter
Symbol
CAS Latency
Clock Cycle Time
Active to Read or Write delay
Active to Active / Auto-Refresh command period
–3.7
–5
Unit
DDR2–533C
DDR2–400B
CL(IDD)
tCK(IDD)
tRCD(IDD)
tRC(IDD)
4
3
tCK
3.75
5
ns
15
15
ns
60
55
ns
tRAS.MIN(IDD)
tRAS.MAX(IDD)
tRP(IDD)
tRFC(IDD)
tREFI
45
40
ns
70000
70000
ns
15
15
ns
127.5
127.5
ns
7.8
7.8
µs
Active bank A to Active bank B command delay
Active to Precharge Command
Precharge Command Period
Auto-Refresh to Active / Auto-Refresh command period
Average periodic Refresh interval
3.4.2
On Die Termination (ODT) Current
The ODT function adds additional current consumption to the
DDR2 SDRAM when enabled by the EMRS(1). Depending on
address bits A[6,2] in the EMRS(1) a “weak” or “strong”
termination can be selected. The current consumption for any
terminated input pin, depends on the input pin is in tri-state or
driving 0 or 1, as long a ODT is enabled during a given period
of time.
TABLE 19
ODT current per terminated pin
Parameter
Symbol
Enabled ODT current per DQODT is HIGH; Data IODTO
Bus inputs are FLOATING
Active ODT current per DQODT is HIGH; worst
case of Data Bus inputs are STABLE or
SWITCHING.
Rev. 1.11, 2006-09
03062006-TZ8J-GNDA
IODTT
26
Min.
Typ.
Max.
Unit
EMRS(1) State
5
6
7.5
mA/DQ
A6 = 0, A2 = 1
2.5
3
3.75
mA/DQ
A6 = 1, A2 = 0
10
12
15
mA/DQ
A6 = 0, A2 = 1
5
6
7.5
mA/DQ
A6 = 1, A2 = 0
Internet Data Sheet
HYS72T512020HR–[3.7/5]–A
Registered DDR2 SDRAM Modules
4
SPD Codes
This chapter lists all hexadecimal byte values stored in the EEPROM of the products described in this data sheet. SPD stands
for serial presence detect. All values with XX in the table are module specific bytes which are defined during production.
List of SPD Code Tables
• Table 20 “SPD codes for PC2–4200R–444” on Page 27
• Table 21 “SPD codes for PC2–3200R–333” on Page 31
TABLE 20
SPD codes for PC2–4200R–444
Product Type
HYS72T512020HR–3.7–A
Organization
4 GByte
×72
2 Ranks (×4)
Label Code
PC2–4200R–444
JEDEC SPD Revision
Rev. 1.1
Byte#
Description
HEX
0
Programmed SPD Bytes in EEPROM
80
1
Total number of Bytes in EEPROM
08
2
Memory Type (DDR2)
08
3
Number of Row Addresses
0E
4
Number of Column Addresses
0B
5
DIMM Rank and Stacking Information
61
6
Data Width
48
7
Not used
00
8
Interface Voltage Level
05
9
tCK @ CLMAX (Byte 18) [ns]
tAC SDRAM @ CLMAX (Byte 18) [ns]
50
11
Error Correction Support (non-ECC, ECC)
02
12
Refresh Rate and Type
82
13
Primary SDRAM Width
04
10
3D
14
Error Checking SDRAM Width
04
15
Not used
00
16
Burst Length Supported
0C
17
Number of Banks on SDRAM Device
08
18
Supported CAS Latencies
38
19
DIMM Mechanical Characteristics
00
20
DIMM Type Information
01
Rev. 1.11, 2006-09
03062006-TZ8J-GNDA
27
Internet Data Sheet
HYS72T512020HR–[3.7/5]–A
Registered DDR2 SDRAM Modules
Product Type
HYS72T512020HR–3.7–A
Organization
4 GByte
×72
2 Ranks (×4)
Label Code
PC2–4200R–444
JEDEC SPD Revision
Rev. 1.1
Byte#
HEX
Description
21
DIMM Attributes
07
22
Component Attributes
01
23
tCK @ CLMAX -1 (Byte 18) [ns]
tAC SDRAM @ CLMAX -1 [ns]
tCK @ CLMAX -2 (Byte 18) [ns]
tAC SDRAM @ CLMAX -2 [ns]
tRP.MIN [ns]
tRRD.MIN [ns]
tRCD.MIN [ns]
tRAS.MIN [ns]
24
25
26
27
28
29
30
3D
50
50
60
3C
1E
3C
2D
31
Module Density per Rank
02
32
tAS.MIN and tCS.MIN [ns]
tAH.MIN and tCH.MIN [ns]
tDS.MIN [ns]
tDH.MIN [ns]
tWR.MIN [ns]
tWTR.MIN [ns]
tRTP.MIN [ns]
25
33
34
35
36
37
38
37
10
22
3C
1E
1E
39
Analysis Characteristics
00
40
06
45
tRC and tRFC Extension
tRC.MIN [ns]
tRFC.MIN [ns]
tCK.MAX [ns]
tDQSQ.MAX [ns]
tQHS.MAX [ns]
46
PLL Relock Time
47
TCASE.MAX Delta / ∆T4R4W Delta
51
48
Psi(T-A) DRAM
60
49
∆T0 (DT0)
37
50
∆T2N (DT2N, UDIMM) or ∆T2Q (DT2Q, RDIMM)
1D
51
∆T2P (DT2P)
23
52
∆T3N (DT3N)
1E
53
∆T3P.fast (DT3P fast)
1F
41
42
43
44
Rev. 1.11, 2006-09
03062006-TZ8J-GNDA
3C
7F
80
1E
28
0F
28
Internet Data Sheet
HYS72T512020HR–[3.7/5]–A
Registered DDR2 SDRAM Modules
Product Type
HYS72T512020HR–3.7–A
Organization
4 GByte
×72
2 Ranks (×4)
Label Code
PC2–4200R–444
JEDEC SPD Revision
Rev. 1.1
Byte#
Description
HEX
54
∆T3P.slow (DT3P slow)
16
55
∆T4R (DT4R) / ∆T4R4W Sign (DT4R4W)
43
56
∆T5B (DT5B)
22
57
∆T7 (DT7)
2A
58
Psi(ca) PLL
C4
59
Psi(ca) REG
8C
60
∆TPLL (DTPLL)
61
61
∆TREG (DTREG) / Toggle Rate
78
62
SPD Revision
11
63
Checksum of Bytes 0-62
A7
64
Manufacturer’s JEDEC ID Code (1)
7F
65
Manufacturer’s JEDEC ID Code (2)
7F
66
Manufacturer’s JEDEC ID Code (3)
7F
67
Manufacturer’s JEDEC ID Code (4)
7F
68
Manufacturer’s JEDEC ID Code (5)
7F
69
Manufacturer’s JEDEC ID Code (6)
51
70
Manufacturer’s JEDEC ID Code (7)
00
71
Manufacturer’s JEDEC ID Code (8)
00
72
Module Manufacturer Location
xx
73
Product Type, Char 1
37
74
Product Type, Char 2
32
75
Product Type, Char 3
54
76
Product Type, Char 4
35
77
Product Type, Char 5
31
78
Product Type, Char 6
32
79
Product Type, Char 7
30
80
Product Type, Char 8
32
81
Product Type, Char 9
30
82
Product Type, Char 10
48
83
Product Type, Char 11
52
84
Product Type, Char 12
33
85
Product Type, Char 13
2E
86
Product Type, Char 14
37
Rev. 1.11, 2006-09
03062006-TZ8J-GNDA
29
Internet Data Sheet
HYS72T512020HR–[3.7/5]–A
Registered DDR2 SDRAM Modules
Product Type
HYS72T512020HR–3.7–A
Organization
4 GByte
×72
2 Ranks (×4)
Label Code
PC2–4200R–444
JEDEC SPD Revision
Rev. 1.1
Byte#
Description
HEX
87
Product Type, Char 15
41
88
Product Type, Char 16
20
89
Product Type, Char 17
20
90
Product Type, Char 18
20
91
Module Revision Code
5x
92
Test Program Revision Code
xx
93
Module Manufacturing Date Year
xx
94
Module Manufacturing Date Week
xx
95 - 98
Module Serial Number
xx
99 - 127 Not used
00
128 255
FF
Blank for customer use
Rev. 1.11, 2006-09
03062006-TZ8J-GNDA
30
Internet Data Sheet
HYS72T512020HR–[3.7/5]–A
Registered DDR2 SDRAM Modules
TABLE 21
SPD codes for PC2–3200R–333
Product Type
HYS72T512020HR–5–A
Organization
4 GByte
×72
2 Ranks (×4)
Label Code
PC2–3200R–333
JEDEC SPD Revision
Rev. 1.1
Byte#
Description
HEX
0
Programmed SPD Bytes in EEPROM
80
1
Total number of Bytes in EEPROM
08
2
Memory Type (DDR2)
08
3
Number of Row Addresses
0E
4
Number of Column Addresses
0B
5
DIMM Rank and Stacking Information
61
6
Data Width
48
7
Not used
00
8
Interface Voltage Level
05
9
tCK @ CLMAX (Byte 18) [ns]
tAC SDRAM @ CLMAX (Byte 18) [ns]
60
11
Error Correction Support (non-ECC, ECC)
02
12
Refresh Rate and Type
82
13
Primary SDRAM Width
04
10
50
14
Error Checking SDRAM Width
04
15
Not used
00
16
Burst Length Supported
0C
17
Number of Banks on SDRAM Device
08
18
Supported CAS Latencies
38
19
DIMM Mechanical Characteristics
00
20
DIMM Type Information
01
21
DIMM Attributes
07
22
Component Attributes
01
23
tCK @ CLMAX -1 (Byte 18) [ns]
tAC SDRAM @ CLMAX -1 [ns]
tCK @ CLMAX -2 (Byte 18) [ns]
tAC SDRAM @ CLMAX -2 [ns]
tRP.MIN [ns]
tRRD.MIN [ns]
tRCD.MIN [ns]
50
24
25
26
27
28
29
Rev. 1.11, 2006-09
03062006-TZ8J-GNDA
60
50
60
3C
1E
3C
31
Internet Data Sheet
HYS72T512020HR–[3.7/5]–A
Registered DDR2 SDRAM Modules
Product Type
HYS72T512020HR–5–A
Organization
4 GByte
×72
2 Ranks (×4)
Label Code
PC2–3200R–333
JEDEC SPD Revision
Rev. 1.1
Byte#
Description
HEX
30
tRAS.MIN [ns]
28
31
Module Density per Rank
02
32
38
tAS.MIN and tCS.MIN [ns]
tAH.MIN and tCH.MIN [ns]
tDS.MIN [ns]
tDH.MIN [ns]
tWR.MIN [ns]
tWTR.MIN [ns]
tRTP.MIN [ns]
39
Analysis Characteristics
40
tRC and tRFC Extension
tRC.MIN [ns]
tRFC.MIN [ns]
tCK.MAX [ns]
tDQSQ.MAX [ns]
tQHS.MAX [ns]
33
34
35
36
37
41
42
43
44
45
35
47
15
27
3C
28
1E
00
06
37
7F
80
23
2D
46
PLL Relock Time
0F
47
TCASE.MAX Delta / ∆T4R4W Delta
51
48
Psi(T-A) DRAM
60
49
∆T0 (DT0)
33
50
∆T2N (DT2N, UDIMM) or ∆T2Q (DT2Q, RDIMM)
1A
51
∆T2P (DT2P)
23
52
∆T3N (DT3N)
18
53
∆T3P.fast (DT3P fast)
18
54
∆T3P.slow (DT3P slow)
16
55
∆T4R (DT4R) / ∆T4R4W Sign (DT4R4W)
35
56
∆T5B (DT5B)
21
57
∆T7 (DT7)
25
58
Psi(ca) PLL
C4
59
Psi(ca) REG
8C
60
∆TPLL (DTPLL)
59
61
∆TREG (DTREG) / Toggle Rate
5C
62
SPD Revision
11
Rev. 1.11, 2006-09
03062006-TZ8J-GNDA
32
Internet Data Sheet
HYS72T512020HR–[3.7/5]–A
Registered DDR2 SDRAM Modules
Product Type
HYS72T512020HR–5–A
Organization
4 GByte
×72
2 Ranks (×4)
Label Code
PC2–3200R–333
JEDEC SPD Revision
Rev. 1.1
Byte#
HEX
Description
63
Checksum of Bytes 0-62
D5
64
Manufacturer’s JEDEC ID Code (1)
7F
65
Manufacturer’s JEDEC ID Code (2)
7F
66
Manufacturer’s JEDEC ID Code (3)
7F
67
Manufacturer’s JEDEC ID Code (4)
7F
68
Manufacturer’s JEDEC ID Code (5)
7F
69
Manufacturer’s JEDEC ID Code (6)
51
70
Manufacturer’s JEDEC ID Code (7)
00
71
Manufacturer’s JEDEC ID Code (8)
00
72
Module Manufacturer Location
xx
73
Product Type, Char 1
37
74
Product Type, Char 2
32
75
Product Type, Char 3
54
76
Product Type, Char 4
35
77
Product Type, Char 5
31
78
Product Type, Char 6
32
79
Product Type, Char 7
30
80
Product Type, Char 8
32
81
Product Type, Char 9
30
82
Product Type, Char 10
48
83
Product Type, Char 11
52
84
Product Type, Char 12
35
85
Product Type, Char 13
41
86
Product Type, Char 14
20
87
Product Type, Char 15
20
88
Product Type, Char 16
20
89
Product Type, Char 17
20
90
Product Type, Char 18
20
91
Module Revision Code
5x
92
Test Program Revision Code
xx
93
Module Manufacturing Date Year
xx
94
Module Manufacturing Date Week
xx
95 - 98
Module Serial Number
xx
Rev. 1.11, 2006-09
03062006-TZ8J-GNDA
33
Internet Data Sheet
HYS72T512020HR–[3.7/5]–A
Registered DDR2 SDRAM Modules
Product Type
HYS72T512020HR–5–A
Organization
4 GByte
×72
2 Ranks (×4)
Label Code
PC2–3200R–333
JEDEC SPD Revision
Rev. 1.1
Byte#
HEX
Description
99 - 127 Not used
00
128 255
FF
Blank for customer use
Rev. 1.11, 2006-09
03062006-TZ8J-GNDA
34
Internet Data Sheet
HYS72T512020HR–[3.7/5]–A
Registered DDR2 SDRAM Modules
5
Package Outlines
FIGURE 2
Package Outline Raw Card ZZ L-DIM-240-42
!8
’ ! " # X
"
#
›
!
›
›
"
-).
›
$ETAILO
FC O
NTACTS
› ! " #
"URRM
AX
A
LLOW
E
D
Rev. 1.11, 2006-09
03062006-TZ8J-GNDA
',$
35
Internet Data Sheet
HYS72T512020HR–[3.7/5]–A
Registered DDR2 SDRAM Modules
6
Product Type Nomenclature
Qimonda’s nomenclature uses simple coding combined with
some propriatory coding. Table 22 provides examples for
module and component product type number as well as the
field number. The detailed field description together with
possible values and coding explanation is listed for modules
in Table 23 and for components in Table 24.
TABLE 22
Nomenclature Fields and Examples
Example for
Field Number
1
2
3
Micro-DIMM
HYS
64
T
DDR2 DRAM
HYB
18
T
4
1G
5
6
7
8
9
10
11
0
2
0
K
M
–5
–A
0
A
C
–5
16
TABLE 23
DDR2 DIMM Nomenclature
Field
Description
Values
Coding
1
Qimonda Module Prefix
HYS
Constant
2
Module Data Width [bit]
64
Non-ECC
72
ECC
3
DRAM Technology
T
DDR2
4
Memory Density per I/O [Mbit];
Module Density1)
32
256 MByte
64
512 MByte
128
1 GByte
256
2 GByte
512
4 GByte
5
Raw Card Generation
0 .. 9
Look up table
6
Number of Module Ranks
0, 2, 4
1, 2, 4
7
Product Variations
0 .. 9
Look up table
8
Package, Lead-Free Status
A .. Z
Look up table
9
Module Type
D
SO-DIMM
Rev. 1.11, 2006-09
03062006-TZ8J-GNDA
M
Micro-DIMM
R
Registered
U
Unbuffered
F
Fully Buffered
36
Internet Data Sheet
HYS72T512020HR–[3.7/5]–A
Registered DDR2 SDRAM Modules
Field
Description
Values
Coding
10
Speed Grade
–2.5F
PC2–6400 5–5–5
–2.5
PC2–6400 6–6–6
11
Die Revision
–3
PC2–5300 4–4–4
–3S
PC2–5300 5–5–5
–3.7
PC2–4200 4–4–4
–5
PC2–3200 3–3–3
–A
First
–B
Second
1) Multiplying “Memory Density per I/O” with “Module Data Width” and dividing by 8 for Non-ECC and 9 for ECC modules gives the overall
module memory density in MBytes as listed in column “Coding”.
TABLE 24
DDR2 DRAM Nomenclature
Field
Description
Values
Coding
1
2
Qimonda Component Prefix
HYB
Constant
Interface Voltage [V]
18
SSTL_18
3
DRAM Technology
T
DDR2
4
Component Density [Mbit]
256
256 Mbit
512
512 Mbit
1G
1 Gbit
2G
2 Gbit
40
×4
80
×8
16
×16
0 .. 9
Look up table
5+6
Number of I/Os
7
Product Variations
8
Die Revision
9
10
Package, Lead-Free Status
Speed Grade
Rev. 1.11, 2006-09
03062006-TZ8J-GNDA
A
First
B
Second
C
FBGA, lead-containing
F
FBGA, lead-free
–25F
DDR2-800 5-5-5
–2.5
DDR2-800 6-6-6
–3
DDR2-667 4-4-4
–3S
DDR2-667 5-5-5
–3.7
DDR2-533 4-4-4
–5
DDR2-400 3-3-3
37
Internet Data Sheet
HYS72T512020HR–[3.7/5]–A
Registered DDR2 SDRAM Modules
Table of Contents
1
1.1
1.2
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2
2.1
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3
3.1
3.2
3.3
3.3.1
3.3.2
3.3.3
3.4
3.4.1
3.4.2
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DC Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Speed Grades Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AC Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ODT AC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Currents Specifications and Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Currents Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
On Die Termination (ODT) Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4
SPD Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
5
Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
6
Product Type Nomenclature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
15
15
15
17
17
17
21
22
26
26
Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Rev. 1.11, 2006-09
03062006-TZ8J-GNDA
38
Internet Data Sheet
Edition 2006-09
Published by Qimonda AG
Gustav-Heinemann-Ring 212
D-81739 München, Germany
© Qimonda AG 2006.
All Rights Reserved.
Legal Disclaimer
The information given in this Internet Data Sheet shall in no event be regarded as a guarantee of conditions or characteristics
(“Beschaffenheitsgarantie”). With respect to any examples or hints given herein, any typical values stated herein and/or any
information regarding the application of the device, Qimonda hereby disclaims any and all warranties and liabilities of any kind,
including without limitation warranties of non-infringement of intellectual property rights of any third party.
Information
For further information on technology, delivery terms and conditions and prices please contact your nearest Qimonda Office.
Warnings
Due to technical requirements components may contain dangerous substances. For information on the types in question please
contact your nearest Qimonda Office.
Qimonda Components may only be used in life-support devices or systems with the express written approval of Qimonda, if a
failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect
the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human
body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health
of the user or other persons may be endangered.
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