W3EG6433S-AD4 -BD4 White Electronic Designs PRELIMINARY* 256MB - 32Mx64 DDR SDRAM UNBUFFERED, w/PLL FEATURES DESCRIPTION The W3EG6433S is a 32Mx64 Double Data Rate SDRAM memory module based on 256Mb DDR SDRAM component. The module consists of eight 32Mx8 DDR SDRAMs in 66 pin TSOP package mounted on a 200 Pin FR4 substrate. DDR200, DDR266 and DDR333 Double-data-rate architecture Bi-directional data strobes (DQS) Differential clock inputs (CK & CK#) Programmable Read Latency 2,2.5 (clock) Programmable Burst Length (2,4,8) Programmable Burst type (sequential & interleave) Edge aligned data output, center aligned data input Auto and self refresh Serial presence detect Power supply: 2.5V ± 0.20V JEDEC standard 200 pin SO-DIMM package Synchronous design allows precise cycle control with the use of system clock. Data I/O transactions are possible on both edges and Burst Lenths allow the same device to be useful for a variety of high bandwidth, high performance memory system applications. * This product is under development, is not qualified or characterized and is subject to change without notice. • Package height options: AD4: 35.5mm (1.38") BD4: 31.75mm (1.25") NOTE: Consult factory for availability of: • Lead-Free or RoHS Products • Vendor source control options • Industrial temperature option OPERATING FREQUENCIES DDR333 @CL=2.5 DDR266 @CL=2 DDR266 @CL=2.5 DDR200 @CL=2 Clock Speed 166MHz 133MHz 133MHz 100MHz CL-tRCD-tRP 2.5-3-3 2-2-2 2.5-3-3 2-2-2 White Electronic Designs Corp. reserves the right to change products or specifications without notice. May 2005 Rev. 1 1 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com W3EG6433S-AD4 -BD4 White Electronic Designs PRELIMINARY PIN CONFIGURATIONS PIN NAMES Pin Symbol Pin Symbol Pin Symbol Pin Symbol 1 VREF 51 VSS 101 A9 151 DQ42 2 VREF 52 VSS 102 A8 152 DQ46 3 VSS 53 DQ19 103 VSS 153 DQ43 4 VSS 54 DQ23 104 VSS 154 DQ47 5 DQ0 55 DQ24 105 A7 155 VCC 6 DQ4 56 DQ28 106 A6 156 VCC 7 DQ1 57 VCC 107 A5 157 VCC 8 DQ5 58 VCC 108 A4 158 NC 9 VCC 59 DQ25 109 A3 159 VSS 10 VCC 60 DQ29 110 A2 160 NC 11 DQS0 61 DQS3 111 A1 161 VSS 12 DQM0 62 DQM3 112 A0 162 VSS 13 DQ2 63 VSS 113 VCC 163 DQ48 14 DQ6 64 VSS 114 VCC 164 DQ52 15 VSS 65 DQ26 115 A10/AP 165 DQ49 16 VSS 66 DQ30 116 BA1 166 DQ53 17 DQ3 67 DQ27 117 BA0 167 VCC 18 DQ7 68 DQ31 118 RAS# 168 VCC 19 DQ8 69 VCC 119 WE# 169 DQS6 20 DQ12 70 VCC 120 CAS# 170 DQM6 21 VCC 71 NC 121 CS0# 171 DQ50 22 VCC 72 NC 122 NC 172 DQ54 23 DQ9 73 NC 123 NC 173 VSS 24 DQ13 74 NC 124 NC 174 VSS DQ51 25 DQS1 75 VSS 125 VSS 175 26 DQM1 76 VSS 126 VSS 176 DQ55 27 VSS 77 DQS8 127 DQ32 177 DQ56 DQ60 28 VSS 78 DQM8 128 DQ36 178 29 DQ10 79 NC 129 DQ33 179 VCC 30 DQ14 80 NC 130 DQ37 180 VCC DQ57 31 DQ11 81 VCC 131 VCC 181 32 DQ15 82 VCC 132 VCC 182 DQ61 33 VCC 83 NC 133 DQS4 183 DQS7 34 VCC 84 NC 134 DQM4 184 DQM7 35 CK0 85 NC 135 DQ34 185 VSS 36 VCC 86 NC 136 DQ38 186 VSS 37 CK0# 87 VSS 137 VSS 187 DQ58 38 VSS 88 VSS 138 VSS 188 DQ62 39 VSS 89 NC 139 DQ35 189 DQ59 40 VSS 90 VSS 140 DQ39 190 DQ63 41 DQ16 91 NC 141 DQ40 191 VCC 42 DQ20 92 VCC 142 DQ44 192 VCC 43 DQ17 93 VCC 143 VCC 193 SDA 44 DQ21 94 VCC 144 VCC 194 SA0 45 VCC 95 NC 145 DQ41 195 SCL 46 VCC 96 CKE0 146 DQ45 196 SA1 47 DQS2 97 NC 147 DQS5 197 VCCSPD 48 DQM2 98 NC 148 DQM5 198 SA2 49 DQ18 99 A12 149 VSS 199 VCCID 50 DQ22 100 A11 150 VSS 200 NC A0 – A12 BA0-BA1 DQ0-DQ63 DQS0-DQS8 CK0 CK0# CKE0 CS0# RAS# CAS# WE# DQM0-DQM8 VCC VCCQ VSS VREF VCCSPD SDA SCL SA0-SA2 VCCID NC Address input (Multiplexed) Bank Select Address Data Input/Output Data Strobe Input/Output Clock input Clock input Clock Enable Input Chip select Input Row Address Strobe Column Address Strobe Write Enable Data-In Mask Power Supply Power Supply for DQS Ground Power Supply for Reference Serial EEPROM Power Supply Serial data I/O Serial clock Address in EEPROM VCC Identification Flag No Connect White Electronic Designs Corp. reserves the right to change products or specifications without notice. May 2005 Rev. 1 2 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com W3EG6433S-AD4 -BD4 White Electronic Designs PRELIMINARY FUNCTIONAL BLOCK DIAGRAM S0# DQS0 DQS1 DM0 DM1 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DM CS# DQS DQ DQ DQ DQ DQ DQ DQ DQ DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQS2 DQS3 DM2 DM3 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DM CS# DQS DQ DQ DQ DQ DQ DQ DQ DQ DQS5 DM4 DM5 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DM CS# DQS DQ DQ DQ DQ DQ DQ DQ DQ DQS6 CK0 120Ω DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQS4 DM CS# DQS DQ DQ DQ DQ DQ DQ DQ DQ DM CS# DQS DQ DQ DQ DQ DQ DQ DQ DQ PLL CK0# BA0, BA1 BA0, BA1: DDR SDRAMs A0-A12 A0-A12: DDR SDRAMs RAS# DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DM CS# DQS DQ DQ DQ DQ DQ DQ DQ DQ DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 DM CS# DQS DQ DQ DQ DQ DQ DQ DQ DQ DDR SDRAM DDR SDRAM DDR SDRAM DDR SDRAM DDR SDRAM DDR SDRAM DDR SDRAM DDR SDRAM RAS#: DDR SDRAMs WE# WE#: DDR SDRAMs CKE0 CKE0: DDR SDRAMs CAS# CAS#: DDR SDRAMs SERIAL PD SCL WP SDA A0 A1 A2 DQS7 DM6 SA0 SA1 SA2 DM7 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DM CS# DQS DQ DQ DQ DQ DQ DQ DQ DQ VCCSPD SPD/EEPROM VCC DDR SDRAMS VREF DDR SDRAMS VSS DDR SDRAMS NOTE: All resistor values are 22 ohms unless otherwise specified. White Electronic Designs Corp. reserves the right to change products or specifications without notice. May 2005 Rev. 1 3 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com W3EG6433S-AD4 -BD4 White Electronic Designs PRELIMINARY ABSOLUTE MAXIMUM RATINGS Parameter Symbol Value Units Voltage on any pin relative to VSS VIN, VOUT -0.5 to 3.6 V Voltage on VCC supply relative to VSS VCC, VCCQ -1.0 to 3.6 V TSTG -55 to +150 °C Storage Temperature Power Dissipation PD 8 W Short Circuit Current IOS 50 mA Note: Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded. Functional operation should be restricted to recommended operating condition. Exposure to higher than recommended voltage for extended periods of time could affect device reliability. DC CHARACTERISTICS 0°C ≤ TA ≤ 70°C, VCC = 2.5V ± 0.2V Parameter Symbol Min Max Unit Supply Voltage VCC 2.3 2.7 V Supply Voltage VCCQ 2.3 2.7 V Reference Voltage VREF VCCQ/2 - 50mV VCCQ/2 + 50mV V Termination Voltage VTT VREF - 0.04 VREF + 0.04 V Input High Voltage VIH VREF + 0.15 VCCQ + 0.3 V Input Low Voltage VIL -0.3 VREF - 0.15 V Output High Voltage VOH VTT + 0.76 — V Output Low Voltage VOL — VTT - 0.76 V Symbol Max Unit CIN1 29 pF Input Capacitance (RAS#, CAS#, WE#) CIN2 29 pF Input Capacitance (CKE0) CIN3 29 pF CAPACITANCE TA = 25°C, f = 1MHz, VCC = 3.3V, VREF =1.4V ± 200mV Parameter Input Capacitance (A0-A12) Input Capacitance (CK0,CK0#) CIN4 5.5 pF Input Capacitance (CS0#) CIN5 29 pF Input Capacitance (DQM0-DQM8) CIN6 8 pF Input Capacitance (BA0-BA1) CIN7 29 pF Data input/output capacitance (DQ0-DQ63)(DQS) COUT 8 pF White Electronic Designs Corp. reserves the right to change products or specifications without notice. May 2005 Rev. 1 4 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com W3EG6433S-AD4 -BD4 White Electronic Designs PRELIMINARY IDD SPECIFICATIONS AND TEST CONDITIONS Recommended operating conditions, 0°C ≤ TA ≤ 70°C, VCCQ = 2.5V ±0.2V, VCC = 2.5V ±0.2V DDR333@CL=2.5 DDR266@CL=2, 2.5 Parameter Symbol Conditions DDR200@CL=2 Max Max Max Units 1275 1276 1235 mA Operating Current IDD0 One device bank; Active - Precharge; tRC=tRC(MIN); tCK=tCK(MIN); DQ,DM and DQS inputs changing once per clock cycle; Address and control inputs changing once every two cycles. 1555 1435 mA IDD1 One device bank; Active-Read-Precharge; Burst = 2; tRC=tRC(MIN);tCK=tCK(MIN); Iout = 0mA; Address and control inputs changing once per clock cycle. 1635 Operating Current Precharge Power-Down Standby Current IDD2P All device banks idle; Power- down mode; tCK=tCK(MIN); CKE=(low) 32 32 32 mA 675 635 635 mA Idle Standby Current IDD2F CS# = High; All device banks idle; tCK=tCK(MIN); CKE = high; Address and other control inputs changing once per clock cycle. Vin = Vref for DQ, DQS and DM. Active Power-Down Standby Current IDD3P One device bank active; Power-down mode; tCK(MIN); CKE=(low) 240 200 240 mA 755 675 675 mA IDD3N CS# = High; CKE = High; One device bank; Active-Precharge; tRC=tRAS(MAX); tCK=tCK(MIN); DQ, DM and DQS inputs changing twice per clock cycle; Address and other control inputs changing once per clock cycle. 1675 1475 1475 mA IDD4R Burst = 2; Reads; Continous burst; One device bank active;Address and control inputs changing once per clock cycle; tCK=tCK(MIN); Iout = 0mA. 1675 1475 1475 mA IDD4W Burst = 2; Writes; Continous burst; One device bank active; Address and control inputs changing once per clock cycle; tCK=tCK(MIN); DQ,DM and DQS inputs changing twice per clock cycle. Auto Refresh Current IDD5 tRC=tRC(MIN) 2315 2155 2235 mA Self Refresh Current IDD6 CKE ≤ 0.2V 307 307 307 mA 3075 3195 mA IDD7A Four bank interleaving Reads (BL=4) with auto precharge with tRC=tRC (MIN); tCK=tCK(MIN); Address and control inputs change only during Active Read or Write commands. 3555 Operating Current Active Standby Current Operating Current Operating Current * For DDR333 consult factory White Electronic Designs Corp. reserves the right to change products or specifications without notice. May 2005 Rev. 1 5 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com W3EG6433S-AD4 -BD4 White Electronic Designs PRELIMINARY DETAILED TEST CONDITIONS FOR DDR SDRAM IDD1 & IDD7A IDD1 : OPERATING CURRENT : ONE BANK IDD7A : OPERATING CURRENT : FOUR BANKS 1. Typical Case : VCC=2.5V, T=25°C 1. Typical Case : VCC=2.5V, T=25°C 2. Worst Case : VCC=2.7V, T=10°C 2. Worst Case : VCC=2.7V, T=10°C 3. Only one bank is accessed with tRC (min), Burst Mode, Address and Control inputs on NOP edge are changing once per clock cycle. IOUT = 0mA 3. Four banks are being interleaved with tRC (min), Burst Mode, Address and Control inputs on NOP edge are not changing. Iout=0mA 4. Timing Patterns : 4. Timing Patterns : • DDR200 (100 MHz, CL=2) : tCK=10ns, CL2, BL=4, tRCD=2*tCK, tRAS=5*tCK Read : A0 N R0 N N P0 N A0 N - repeat the same timing with random address changing; 50% of data changing at every burst • DDR266 (133MHz, CL=2.5) : tCK=7.5ns, CL=2.5, BL=4, tRCD=3*tCK, tRC=9*tCK, tRAS=5*tCK Read : A0 N N R0 N P0 N N N A0 N - repeat the same timing with random address changing; 50% of data changing at every burst • DDR266 (133MHz, CL=2) : tCK=7.5ns, CL=2, BL=4, tRCD=3*tCK, tRC=9*tCK, tRAS=5*tCK Read : A0 N N R0 N P0 N N N A0 N - repeat the same timing with random address changing; 50% of data changing at every burst • DDR333 (166MHz, CL=2.5) : tCK=6ns, BL=4, tRCD=10*tCK, tRAS=7*tCK Read : A0 N N R0 N P0 N N N A0 N - repeat the same timing with random address changing; 50% of data changing at every burst • DDR200 (100 MHz, CL=2) : tCK=10ns, CL2, BL=4, tRRD=2*tCK, tRCD=3*tCK, Read with Autoprecharge Read : A0 N A1 R0 A2 R1 A3 R2 A0 R3 A1 R0 - repeat the same timing with random address changing; 100% of data changing at every burst • DDR266 (133MHz, CL=2.5) : tCK=7.5ns, CL=2.5, BL=4, tRRD=3*tCK, tRCD=3*tCK Read with Autoprecharge Read : A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N A1 R0 - repeat the same timing with random address changing; 100% of data changing at every burst • DDR266 (133MHz, CL=2) : tCK=7.5ns, CL2=2, BL=4, tRRD=2*tCK, tRCD=2*tCK Read : A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N A1 R0 - repeat the same timing with random address changing; 100% of data changing at every burst • DDR333 (166MHz, CL=2.5) : tCK=6ns, BL=4, tRRD=3*tCK, tRCD=3*tCK, Read with Autoprecharge Read : A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N A1 R0 - repeat the same timing with random address changing; 100% of data changing at every burst Legend : A = Activate, R = Read, W = Write, P = Precharge, N = NOP A (0-3) = Activate Bank 0-3 R (0-3) = Read Bank 0-3 White Electronic Designs Corp. reserves the right to change products or specifications without notice. May 2005 Rev. 1 6 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com W3EG6433S-AD4 -BD4 White Electronic Designs PRELIMINARY DDR SDRAM COMPONENT ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS AC CHARACTERISTICS 335 PARAMETER 262 265/202 UNITS NOTES SYMBOL MIN MAX MIN MAX MIN MAX Access window of DQs from CK/CK# tAC -0.70 +0.70 -0.75 +0.75 -0.75 +0.75 ns CK high-level width tCH 0.45 0.55 0.45 0.55 0.45 0.55 tCK CK low-level width tCL 0.45 0.55 0.45 0.55 0.45 0.55 tCK 26 CL = 2.5 tCK (2.5) 6 13 7.5 13 7.5 13 ns 40, 45 CL = 2 tCK (2) 7.5 13 7.5 13 7.5/10 13 tDH 0.45 DQ and DM input setup time relative to DQS tDS 0.45 0.5 DQ and DM input pulse width (for each input) tDIPW 1.75 1.75 Access window of DQS from CK/CK# tDQSCK -0.60 DQS input high pulse width tDQSH 0.35 DQS input low pulse width tDQSL 0.35 DQS-DQ skew, DQS to last DQ valid, per group, per access tDQSQ Write command to first DQS latching transition tDQSS 0.75 DQS falling edge to CK rising - setup time tDSS 0.20 0.20 0.20 tCK DQS falling edge from CK rising - hold time tDSH 0.20 0.20 0.20 tCK Half clock period tHP tCH,tCL Data-out high-impedance window from CK/CK# tHZ Clock cycle time DQ and DM input hold time relative to DQS 0.5 +0.60 -0.75 +0.75 1.25 40, 45 23, 27 0.5 ns 23, 27 1.75 ns 27 -0.75 1.25 tCH,tCL +0.70 0.75 tCK 0.5 ns 1.25 tCK tCH,tCL +0.75 ns tCK 0.35 0.5 0.75 +0.75 0.35 0.35 0.4 ns ns 0.5 0.35 26 +0.75 22, 23 ns 8 ns 16, 37 Data-out low-impedance window from CK/CK# tLZ -0.70 -0.75 -0.75 ns 16, 37 Address and control input hold time (fast slew rate) tIHF 0.75 0.90 0.90 ns 12 Address and control input setup time (fast slew rate) tISF 0.75 0.90 .900 ns 12 Address and control input hold time (slow slew rate) tIHS 0.8 1 1 ns 12 Address and control input setup time (slow slew rate) tISS 0.8 1 1 ns 12 Address and Control input pulse width (for each input) tIPW 2.2 2.2 2.2 ns LOAD MODE REGISTER command cycle time tMRD 12 15 15 ns White Electronic Designs Corp. reserves the right to change products or specifications without notice. May 2005 Rev. 1 7 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com W3EG6433S-AD4 -BD4 White Electronic Designs PRELIMINARY DDR SDRAM COMPONENT ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS (Continued) AC CHARACTERISTICS PARAMETER 335 262 MAX MIN 265/202 MAX NOTES ns 22, 23 SYMBOL MIN DQ-DQS hold, DQS to first DQ to go non-valid, per access tQH tHP - tQHS Data hold skew factor tQHS ACTIVE to PRECHARGE command tRAS 42 ACTIVE to READ with Auto precharge command tRAP 15 15 20 ns ACTIVE to ACTIVE/AUTO REFRESH command period tRC 60 60 65 ns AUTO REFRESH command period tRFC 72 75 75 ns ACTIVE to READ or WRITE delay tRCD 15 15 20 ns PRECHARGE command period tRP 15 15 20 ns DQS read preamble tRPRE 0.9 1.1 0.9 1.1 0.9 1.1 tCK 38 DQS read postamble tRPST 0.4 0.6 0.4 0.6 0.4 0.6 tCK 38 tHP - tQHS 0.55 70,000 MIN UNITS 0.75 40 MAX tHP - tQHS 120,000 40 0.75 ns 120,000 ns ACTIVE bank a to ACTIVE bank b command tRRD 12 15 15 ns DQS write preamble tWPRE 0.25 0.25 0.25 tCK DQS write preamble setup time tWPRES 0 DQS write postamble tWPST 0.4 Write recovery time tWR 15 15 15 ns Internal WRITE to READ command delay tWTR 1 1 1 tCK Data valid output window NA 0 0.6 tQH -tDQSQ 0.4 0 0.6 tQH -tDQSQ 0.4 0.6 tQH -tDQSQ 31, 48 43 ns 18, 19 tCK 17 ns 22 REFRESH to REFRESH command interval tREFC 70.3 70.3 70.3 µs 21 Average periodic refresh interval tREFI 7.8 7.8 7.8 µs 21 Terminating voltage delay to VDD tVTD 0 0 0 ns Exit SELF REFRESH to non-READ command tXSNR 75 75 75 ns Exit SELF REFRESH to READ command tXSRD 200 200 200 tCK White Electronic Designs Corp. reserves the right to change products or specifications without notice. May 2005 Rev. 1 8 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com W3EG6433S-AD4 -BD4 White Electronic Designs PRELIMINARY Notes 1. All voltages referenced to VSS. 2. Tests for AC timing, IDD, and electrical AC and DC characteristics may be conducted at nominal reference/supply voltage levels, but the related specifications and device operation are guaranteed for the full voltage range specified. 3. Outputs measured with equivalent load: 16. 17. VTT Output (VOUT) 18. 50Ω Reference Point 30pF 19. 20. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. AC timing and IDD tests may use a VIL-to-VIH swing of up to 1.5V in the test environment, but input timing is still referenced to VREF (or to the crossing point for CK/CK#), and parameter specifications are guaranteed for the specified AC input levels under normal use conditions. The mini-mum slew rate for the input signals used to test the device is 1V/ns in the range between VIL(AC) and VIH(AC). The AC and DC input level specifications are as defined in the SSTL_2 Standard (i.e., the receiver will effectively switch as a result of the signal crossing the AC input level, and will remain in that state as long as the signal does not ring back above [below] the DC input LOW [HIGH] level). VREF is expected to equal VCCQ/2 of the transmitting device and to track variations in the DC level of the same. Peak-to-peak noise (non-common mode) on VREF may not exceed ±2 percent of the DC value. Thus, from VCCQ/2, VREF is allowed ±25mV for DC error and an additional ±25mV for AC noise. This measurement is to be taken at the nearest VREF bypass capacitor. VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF and must track variations in the DC level of VREF. IDD is dependent on output loading and cycle rates. Specified values are obtained with mini-mum cycle time at CL = 2 for 262, 263, and 202, CL = 2.5 for 335 and 265 with the outputs open. Enables on-chip refresh and address counters. IDD specifications are tested after the device is properly initialized, and is averaged at the defined cycle rate. This parameter is sampled. VCC = +2.5V ±0.2V, VCCQ = +2.5V ±0.2V, VREF = VSS, f = 100 MHz, = 25°C, VOUT(DC) = VCCQ/2, VOUT (peak to peak) TA = 0.2V. DM input is grouped with I/O pins, reflecting the fact that they are matched in loading. For slew rates less than 1 V/ns and greater than or equal to 0.5 V/ns. If slew rate is less than 0.5 V/ns, timing must be derated: tIS has an additional 50ps per each 100mV/ns reduction in slew rate from 500mV/ns, while tIH is unaffected. If slew rate exceeds 4.5 V/ns, functionality is uncertain. For 335, slew rates must be ≥ 0.5 V/ns. The CK/CK# input reference level (for timing referenced to CK/CK#) is the point at which CK and CK# cross; the input reference level for signals other than CK/CK# is VREF. Inputs are not recognized as valid until VREF stabilizes. Exception: during the period before VREF stabilizes, CKE < 0.3 x VCCQ is recognized as LOW. The output timing reference level, as measured at the timing reference point indicated in Note 3, is VTT. 21. 22. 23. 24. 25. 26. 27. 28. 29. 30. 31. 32. tHZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not referenced to a specific voltage level, but specify when the device output is no longer driving (HZ) or begins driving (LZ). The intent of the Don’t Care state after completion of the postamble is the DQSdriven signal should either be high, low, or high-Z and that any signal transition within the input switching region must follow valid input requirements. That is, if DQS transitions high (above VIH DC (MIN) then it must not transition low (below VIH DC) prior to tDQSH (MIN). This is not a device limit. The device will operate with a negative value, but system performance could be degraded due to bus turnaround. It is recommended that DQS be valid (HIGH or LOW) on or before the WRITE command. The case shown (DQS going from High-Z to logic LOW) applies when no WRITEs were previously in progress on the bus. If a previous WRITE was in progress, DQS could be HIGH during this time, depending on tDQSS. MIN (tRC or tRFC) for IDD measurements is the smallest multiple of tCK that meets the minimum absolute Value for the respective parameter. tRAS (MAX) for IDD measurements is the largest multiple of tCK that meets the maximum absolute value for tRAS. The refresh period 64ms. This equates to an aver-age refresh rate of 7.8125µs. However, an AUTO REFRESH command must be asserted at least once every 70.3µs; burst refreshing or posting by the DRAM controller greater than eight refresh cycles is not allowed. The valid data window is derived by achieving other specifications: tHP (tCK/2), tDQSQ, and tQH (tQH = tHP - tQHS). The data valid window derates directly porportional with the clock duty cycle and a practical data valid window can be derived. The clock is allowed a maximum duty cycle variation of 45/55, beyond which functionality is uncertain. Figure 8, Derating Data Valid Window, shows derating curves for duty cycles ranging between 50/50 and 45/55. Each byte lane has a corresponding DQS. This limit is actually a nominal value and does not result in a fail value. CKE is HIGH during REFRESH command period (tRFC [MIN]) else CKE is LOW (i.e., during standby). To maintain a valid level, the transitioning edge of the input must: a. Sustain a constant slew rate from the current AC level through to the target AC level, VIL(AC) or VIH(AC). b. Reach at least the target AC level.After the AC target level is reached, continue to maintain at least the target DC level, VIL(DC) or VIH(DC). JEDEC specifies CK and CK# input slew rate must be ≥ 1V/ns (2V/ns differentially). DQ and DM input slew rates must not deviate from DQS by more than 10 percent. If the DQ/ DM/DQS slew rate is less than 0.5V/ns, timing must be derated: 50ps must be added to tDS and tDH for each 100mv/ns reduction in slew rate. If slew rate exceeds 4V/ns, functionality is uncertain. For 335, slew rates must be ≥ 0.5 V/ns. VCC must not vary more than 4 percent if CKE is not active while any bank is active. The clock is allowed up to ±150ps of jitter. Each timing parameter is allowed to vary by the same amount. tHP min is the lesser of tCL minimum and tCH minimum actually applied to the device CK and CK# inputs, collectively during bank active. READs and WRITEs with auto precharge are not allowed to be issued until tRAS(MIN) can be satisfied prior to the internal precharge command being issued. Any positive glitch must be less than 1/3 of the clock and not more than +400mV or 2.9V, whichever is less. Any negative glitch must be less than 1/3 of the clock cycle and not exceed either -300mV or 2.2V, whichever is more positive. White Electronic Designs Corp. reserves the right to change products or specifications without notice. May 2005 Rev. 1 9 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com W3EG6433S-AD4 -BD4 White Electronic Designs PRELIMINARY 33. 34. 35. 36. 37. Normal Output Drive Curves: a. The full variation in driver pull-down current from minimum to maximum process, temperature and voltage will lie within the outer bounding lines of the V-I curve of Figure 9, Pull-Down Characteristics. b. The variation in driver pull-down current within nominal limits of voltage and temperature is expected, but not guaranteed, to lie within the inner bounding lines of the V-I curve of Figure 9, Pull-Down Characteristics. c. The full variation in driver pull-up current from minimum to maximum process, temperature and voltage will lie within the outer bounding lines of the V-I curve of Figure 10, Pull-Up Characteristics. d. The variation in driver pull-up current within nominal limits of voltage and temperature is expected, but not guaranteed, to lie within the inner bounding lines of the V-I curve of Figure 10, Pull-Up Characteristics. e. The full variation in the ratio of the maximum to minimum pull-up and pulldown current should be between 0.71 and 1.4, for device drain-to-source voltages from 0.1V to 1.0V, and at the same voltage and temperature. f. The full variation in the ratio of the nominal pull-up to pull-down current should be unity ±10 percent, for device drain-to-source volt-ages from 0.1V to 1.0V. The voltage levels used are derived from a mini-mum VCC level and the referenced test load. In practice, the voltage levels obtained from a properly terminated bus will provide significantly different voltage values. VIH overshoot: VIH (MAX) = VCCQ + 1.5V for a pulse width ≤ 3ns and the pulse width can not be greater than 1/3 of the cycle rate. VIL undershoot: VIL (MIN) = -1.5V for a pulse width ≤ 3ns and the pulse width can not be greater than 1/3 of the cycle rate. VCC and VCCQ must track each other. tHZ (MAX) will prevail over tDQSCK (MAX) + tRPST (MAX) condition. tLZ (MIN) will 38. 39. 40. 41. 42. 43. 44. 45. 46. 47. 48. prevail over tDQSCK (MIN) + tRPRE (MAX) condition. tRPST end point and tRPRE begin point are not referenced to a specific voltage level but specify when the device output is no longer driving (tRPST), or begins driving (tRPRE). During Initialization, VCCQ, VTT, and VREF must be equal to or less than VCC + 0.3V. Alternatively, VTT may be 1.35V maximum during power up, even if VCC/ VCCQ are 0.0V, provided a minimum of 42 0 of series resistance is used between the VTT supply and the input pin. The current part operates below the slowest JEDEC operating frequency of 83 MHz. As such, future die may not reflect this option. Random addressing changing and 50 percent of data changing at every transfer. Random addressing changing and 100 percent of data changing at every transfer. CKE must be active (high) during the entire time a refresh command is executed. That is, from the time the AUTO REFRESH command is registered, CKE must be active at each rising clock edge, until tREF later. IDD2N specifies the DQ, DQS, and DM to be driven to a valid high or low logic level. IDD2Q is similar to IDD2F except IDD2Q specifies the address and control inputs to remain stable. Although IDD2F, IDD2N, and IDD2Q are similar, IDD2F is “worst case.” Whenever the operating frequency is altered, not including jitter, the DLL is required to be reset. This is followed by 200 clock cycles. Leakage number reflects the worst case leakage possible through the module pin, not what each memory device contributes. When an input signal is HIGH or LOW, it is defined as a steady state logic HIGH or LOW. The 335 speed grade will operate with tRAS (MIN) = 40ns and tRAS (MAX) = 120,000ns at any slower frequency. White Electronic Designs Corp. reserves the right to change products or specifications without notice. May 2005 Rev. 1 10 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com W3EG6433S-AD4 -BD4 White Electronic Designs PRELIMINARY ORDERING INFORMATION FOR AD4 Part Number Speed CAS Latency tRCD tRP Height* W3EG6433S335AD4 166MHz/333Mb/s 2.5 3 3 35.05 (1.38") W3EG6433S262AD4 133MHz/266Mb/s 2 2 2 35.05 (1.38") W3EG6433S265AD4 133MHz/266Mb/s 2.5 3 3 35.05 (1.38") W3EG6433S202AD4 100MHz/200Mb/s 2 2 2 35.05 (1.38") NOTES: • Consult Factory for availability of Lead-Free or RoHS products. (F = Lead-Free, G = RoHS Compliant) • Vendor specific part numbers are used to provide memory components source control. The place holder for this is shown as lower case “x” in the part numbers above and is to be replaced with the respective vendors code. Consult factory for qualified sourcing options. (M = Micron, S = Samsung & consult factory for others) • Consult factory for availability of industrial temperature (-40°C to 85°C) option PACKAGE DIMENSIONS FOR AD4 67.56 (2.66) MAX. 3.81 (0 .150) MAX. 2.0 (0.079) 3.98 ± 0.1 (0.157 ± 0.004) 35.05 (1.38) MAX. 20 (0.787) P1 2.31 (0.091) REF. 4.19 (0.165) 1.80 (0.071) 3.98 (0.157) MIN. 47.40 (1.866) 1.0 ± 0.1 (0.039 ± 0.004) 11.40 (0.449) * ALL DIMENSIONS ARE IN MILLIMETERS AND (INCHES) White Electronic Designs Corp. reserves the right to change products or specifications without notice. May 2005 Rev. 1 11 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com W3EG6433S-AD4 -BD4 White Electronic Designs PRELIMINARY ORDERING INFORMATION FOR BD4 Part Number Speed CAS Latency tRCD tRP Height* W3EG6433S335BD4 166MHz/333Mb/s 2.5 3 3 31.75 (1.25") W3EG6433S262BD4 133MHz/266Mb/s 2 2 2 31.75 (1.25") W3EG6433S265BD4 133MHz/266Mb/s 2.5 3 3 31.75 (1.25") W3EG6433S202BD4 100MHz/200Mb/s 2 2 2 31.75 (1.25") NOTES: • Consult Factory for availability of Lead-Free or RoHS products. (F = Lead-Free, G = RoHS Compliant) • Vendor specific part numbers are used to provide memory components source control. The place holder for this is shown as lower case “x” in the part numbers above and is to be replaced with the respective vendors code. Consult factory for qualified sourcing options. (M = Micron, S = Samsung & consult factory for others) • Consult factory for availability of industrial temperature (-40°C to 85°C) option PACKAGE DIMENSIONS FOR BD4 3.81 (0.150) MAX. 67.56 (2.666) MAX C27 R17 R5 R18 R19 R20 R9 R10 R2 R11 R4 U9 U7 31.75 (1.25) U1 R16 R7 R15 R6 3.98 ± 0.1 (0.157 ± 0.004) U5 R14 U3 R13 R12 20 (0.787) C28 R8 R3 C29 C3 C5 RP1 2.31 (0.091) REF. RP5 RP9 RP14 R21 C6 C3 C2 RP18 RP13 4.19 (0.165) 1.80 (0.071) RP19 C18 RP4 RP7 C7 RP12 C8 RP20 C26 RP22 3.98 (0.157) MIN. 47.40 (1.866) 1.0 ± 0.1 (0.039 ± 0.004) 11.40 (0.449) * ALL DIMENSIONS ARE IN MILLIMETERS AND (INCHES) White Electronic Designs Corp. reserves the right to change products or specifications without notice. May 2005 Rev. 1 12 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com W3EG6433S-AD4 -BD4 White Electronic Designs PRELIMINARY Document Title 256MB - 32Mx64 DDR SDRAM UNBUFFERED, w/PLL Revision History Rev # History Release Date Status Rev A Created 7-21-03 Advanced 0.1 Update to CAP, IDD and AC specs 12-04 Preliminary 5-05 Preliminary Rev 0 0.2 Added BD4 package option 0.3 Added lead-free and RoHS notes 0.4 Moved from Advanced to Preliminary 0.5 Removed "ED" from part number Rev 1 1.1 Added new lead-free, RoHS, source control and industrial notes 1.2 Updated new CAP and IDD specs White Electronic Designs Corp. reserves the right to change products or specifications without notice. May 2005 Rev. 1 13 White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com