WEDC W3EG72255S202JD3XG

W3EG72255S-D3
-JD3
-AJD3
White Electronic Designs
PRELIMINARY*
2GB – 2x128Mx72 DDR SDRAM REGISTERED ECC, w/PLL
FEATURES
DESCRIPTION
Double-data-rate architecture
DDR200, DDR266 and DDR333:
The W3EG72255S is a 2x128Mx72 Double Data Rate
SDRAM memory module based on 512Mb DDR SDRAM
components. The module consists of eighteen 256Mx4
stacks, in 66 pin TSOP packages mounted on a 184 pin
FR4 substrate.
• JEDEC design specifications
Bi-directional data strobes (DQS)
Differential clock inputs (CK & CK#)
Programmable Read Latency 2,2.5 (clock)
Programmable Burst Length (2,4,8)
Programmable Burst type (sequential & interleave)
Edge aligned data output, center aligned data input.
Auto and self refresh
Serial presence detect
Dual Rank
Power supply: VCC = 2.5V ± 0.2V
JEDEC standard 184 pin DIMM package
Synchronous design allows precise cycle control with the
use of system clock. Data I/O transactions are possible
on both edges and Burst Lengths allow the same
device to be useful for a variety of high bandwidth, high
performance memory system applications.
* wThis product is under development, is not qualified or characterized and is subject
to change without notice.
• Package height options:
JD3: 30.48mm (1.2"),
AJD3: 28.70mm (1.13")
NOTE: Consult factory for availability of:
• RoHS compliant products
• Vendor source control options
• Industrial temperature option
OPERATING FREQUENCIES
DDR333 @CL=2.5
DDR266 @CL=2
DDR266 @CL=2
DDR266 @CL=2.5
DDR200 @CL=2
Clock Speed
166MHz
133MHz
133MHz
133MHz
100MHz
CL-tRCD-tRP
2.5-3-3
2-2-2
2-3-3
2.5-3-3
2-2-2
November 2004
Rev. 2
1
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
W3EG72255S-D3
-JD3
-AJD3
White Electronic Designs
PRELIMINARY
PIN CONFIGURATION
PIN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
SYMBOL
VREF
DQ0
VSS
DQ1
DQS0
DQ2
VCC
DQ3
NC
RESET#
VSS
DQ8
DQ9
DQS1
VCCQ
NC
NC
VSS
DQ10
DQ11
CKE0
VCCQ
DQ16
DQ17
DQS2
VSS
A9
DQ18
A7
VCCQ
DQ19
A5
DQ24
VSS
DQ25
DQS3
A4
VCC
DQ26
DQ27
A2
VSS
A1
CB0
CB1
VCC
November 2004
Rev. 2
PIN
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
SYMBOL
DQS8
A0
CB2
VSS
CB3
BA1
DQ32
VCCQ
DQ33
DQS4
DQ34
VSS
BA0
DQ35
DQ40
VCCQ
WE#
DQ41
CAS#
VSS
DQS5
DQ42
DQ43
VCC
NC
DQ48
DQ49
VSS
NC
NC
VCCQ
DQS6
DQ50
DQ51
VSS
VCCID
DQ56
DQ57
VCC
DQS7
DQ58
DQ59
VSS
NC
SDA
SCL
PIN
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
SYMBOL
VSS
DQ4
DQ5
VCCQ
DQS9
DQ6
DQ7
VSS
NC
NC
NC
VCCQ
DQ12
DQ13
DQS10
VCC
DQ14
DQ15
CKE1
VCCQ
NC
DQ20
A12
VSS
DQ21
A11
DQS11
VCC
DQ22
A8
DQ23
VSS
A6
DQ28
DQ29
VCCQ
DQS12
A3
DQ30
VSS
DQ31
CB4
CB5
VCCQ
CK0
CK0#
PIN NAMES
PIN
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
SYMBOL
VSS
DQS17
A10
CB6
VCCQ
CB7
VSS
DQ36
DQ37
VCC
DQS13
DQ38
DQ39
VSS
DQ44
RAS#
DQ45
VCCQ
CS0#
CS1#
DQS14
VSS
DQ46
DQ47
NC
VCCQ
DQ52
DQ53
NC
VCC
DQS15
DQ54
DQ55
VCCQ
NC
DQ60
DQ61
VSS
DQS16
DQ62
DQ63
VCCQ
SA0
SA1
SA2
VCCSPD
2
A0-A12
BA0-BA1
DQ0-DQ63
CB0-CB7
DQS0-DQS17
CK0
CK0#
CKE0, CKE1
CS0#, CS1#
RAS#
CAS#
WE#
VCC
VCCQ
VSS
VREF
VCCSPD
SDA
SCL
SA0-SA2
VCCID
NC
RESET#
Address input (Multiplexed)
Bank Select Address
Data Input/Output
Check bits
Data Strobe Input/Output
Clock Input
Clock Input
Clock Enable input
Chip Select Input
Row Address Strobe
Column Address Strobe
Write Enable
Power Supply
Power Supply for DQS
Ground
Power Supply for Reference
Serial EEPROM Power Supply
Serial data I/O
Serial clock
Address in EEPROM
VCC Indentification Flag
No Connect
Reset Enable
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
W3EG72255S-D3
-JD3
-AJD3
White Electronic Designs
PRELIMINARY
FUNCTIONAL BLOCK DIAGRAM
VSS
RCS1#
RCS0#
DQS0
DQS9
DQS
I/O 3
I/O 2
I/O 1
I/O 0
CS# DM
DQ0
DQ1
DQ2
DQ3
DQS
I/O 3
I/O 2
I/O 1
I/O 0
CS#
DQ8
DQ9
DQ10
DQ11
DQS
I/O 3
I/O 2
I/O 1
I/O 0
CS#
DQ16
DQ17
DQ18
DQ19
DQS
I/O 3
I/O 2
I/O 1
I/O 0
CS#
DQ24
DQ25
DQ26
DQ27
DQS
I/O 3
I/O 2
I/O 1
I/O 0
CS#
DQ32
DQ33
DQ34
DQ35
DQS
I/O 3
I/O 2
I/O 1
I/O 0
CS# DM
DQ40
DQ41
DQ42
DQ43
DQS
I/O 3
I/O 2
I/O 1
I/O 0
CS#
DQ48
DQ49
DQ50
DQ51
DQS
I/O 3
I/O 2
I/O 1
I/O 0
CS#
DQ56
DQ57
DQ58
DQ59
DQS
I/O 3
I/O 2
I/O 1
I/O 0
CS#
CB0
CB1
CB2
CB3
DQS
I/O 3
I/O 2
I/O 1
I/O 0
CS#
DQS
I/O 3
I/O 2
I/O 1
I/O 0
CS#
DQS
I/O 3
I/O 2
I/O 1
I/O 0
CS#
DQS
I/O 3
I/O 2
I/O 1
I/O 0
CS#
DQS
I/O 3
I/O 2
I/O 1
I/O 0
CS#
DQS
I/O 3
I/O 2
I/O 1
I/O 0
CS#
DQS
I/O 3
I/O 2
I/O 1
I/O 0
CS#
DQS
I/O 3
I/O 2
I/O 1
I/O 0
CS#
DQS
I/O 3
I/O 2
I/O 1
I/O 0
CS# DM
DQS
I/O 3
I/O 2
I/O 1
I/O 0
CS#
DM
DQS
I/O 3
I/O 2
I/O 1
I/O 0
CS#
DM
DQ4
DQ5
DQ6
DQ7
DQS
I/O 3
I/O 2
I/O 1
I/O 0
CS#
DM
DQS
I/O 3
I/O 2
I/O 1
I/O 0
CS#
DM
DQ12
DQ13
DQ1
DQ14
DQ15
DQS
I/O 3
I/O 2
I/O 1
I/O 0
CS#
DM
DQS
I/O 3
I/O 2
I/O 1
I/O 0
CS#
DM
DQ20
DQ21
DQ2
DQ22
DQ23
DQS
I/O 3
I/O 2
I/O 1
I/O 0
CS#
DM
DQS
I/O 3
I/O 2
I/O 1
I/O 0
CS#
DM
DQ28
DQ29
DQ30
DQ31
DQS
I/O 3
I/O 2
I/O 1
I/O 0
CS#
DM
DQS
I/O 3
I/O 2
I/O 1
I/O 0
CS#
DM
DQ36
DQ37
DQ38
DQ39
DQS
I/O 3
I/O 2
I/O 1
I/O 0
CS#
DM
DQS
I/O 3
I/O 2
I/O 1
I/O 0
CS#
DM
DQ44
DQ45
DQ46
DQ47
DQS
I/O 3
I/O 2
I/O 1
I/O 0
CS#
DM
DQS
I/O 3
I/O 2
I/O 1
I/O 0
CS#
DM
DQ52
DQ53
DQ54
DQ55
DQS
I/O 3
I/O 2
I/O 1
I/O 0
CS#
DM
DQS
I/O 3
I/O 2
I/O 1
I/O 0
CS#
DM
DQ60
DQ61
DQ62
DQ63
DQS
I/O 3
I/O 2
I/O 1
I/O 0
CS#
DM
DQS
I/O 3
I/O 2
I/O 1
I/O 0
CS#
DM
CB4
CB5
CB6
CB7
DM
DQS1
DQS10
DM
DM
DQS2
DQS11
DM
DM
DQS3
DQS12
DM
DM
DQS13
DQS4
DM
DM
DQS14
DQS5
DM
DQS15
DQS6
DM
DM
DQS16
DQS7
DM
DM
DQS8
DQS17
DM
VCCSPD
CK0
PLL
CK0#
CS0#
CS1#
BA0,BA1
A0-A12
RAS#
CAS#
CKE0
CKE1
WE#
R
E
G
I
S
T
E
R
REGISTER
RCS0#
RCS1#
RBA0,RBA1
RA0-RA12
RRAS#
RCAS#
RCKE0
RCKE1
RWE#
PCK
PCK#
BA0,BA1: DDR SDRAMs
A0-A12: DDR SDRAMs
RAS#: DDR SDRAMs
CAS#: DDR SDRAMs
CKE: DDR SDRAMs
CKE: DDR SDRAMs
WE#: DDR SDRAMs
VCC/VCCQ
DDR SDRAMs
VREF
DDR SDRAMs
VSS
DDR SDRAMs
SERIAL PD
SCL
WP
SDA
A0
A1
SA0
SA1
A2
SA2
Notes:
1.
DQ-to-I/O wiring is shown as recommended but may be changed.
2.
DQ/DQS/DM/CKE/S relationships must be maintained as shown.
RESET#
NOTE: All resistor values are 22 ohms unless otherwise specified
November 2004
Rev. 2
SPD
SDRAM
3
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
W3EG72255S-D3
-JD3
-AJD3
White Electronic Designs
PRELIMINARY
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Value
Units
Voltage on any pin relative to VSS
VIN, VOUT
-0.5 - 3.6
V
Voltage on VCC supply relative to VSS
VCC, VCCQ
-1.0 - 3.6
V
TSTG
-55 - +150
°C
Power Dissipation
PD
27
W
Short Circuit Current
I0S
50
mA
Storage Temperature
Note: Permanent device damage may occur if ‘ABSOLUTE MAXIMUM RATINGS’ are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability
DC CHARACTERISTICS
0°C ≤ TA ≤ 70°C, VCC = 2.5V ± 0.2V
Parameter
Symbol
Min
Max
Unit
Supply Voltage
VCC
2.3
2.7
V
Supply Voltage
VCCQ
2.3
2.7
V
Reference Voltage
VREF
1.15
1.35
V
Termination Voltage
VTT
1.15
1.35
V
Input High Voltage
VIH
VREF + 0.15
VCCQ + 0.3
V
Input Low Voltage
VIL
-0.3
VREF - 0.15
V
Output High Voltage
VOH
VTT + 0.76
—
V
Output Low Voltage
VOL
—
VTT - 0.76
V
CAPACITANCE
TA = 25°C, f = 1MHz, VCC = 2.5V ± 0.2V
Parameter
Symbol
Max
Unit
Input Capacitance (A0-A12)
CIN1
6.25
pF
Input Capacitance (RAS#, CAS#, WE#)
CIN2
6.25
pF
Input Capacitance (CKE0)
CIN3
6.25
pF
pF
Input Capacitance (CK0,CK0#)
CIN4
5.5
Input Capacitance (CS0#)
CIN5
6.25
pF
Input Capacitance (DQM0-DQM8)
CIN6
13.0
pF
Input Capacitance (BA0-BA1)
CIN7
6.25
pF
Data input/output capacitance (DQ0-DQ63)(DQS)
COUT
13.0
pF
Data input/output capacitance (CB0-CB7)
COUT
13.0
pF
November 2004
Rev. 2
4
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
W3EG72255S-D3
-JD3
-AJD3
White Electronic Designs
PRELIMINARY
IDD SPECIFICATIONS AND TEST CONDITIONS
0°C ≤ TA ≤ +70°C, VCCQ = 2.5V ± 0.2V, VCC = 2.5V ± 0.2V.
Includes DDR SDRAM components only
Units
Rank 2
Standby
State
Operating Current
IDD0
One device bank; Active - Precharge; tRC
= tRC (MIN); tCK = tCK (MIN); DQ,DM and
DQS inputs changing once per clock cycle;
Address and control inputs changing once
every two cycles.
4140
4140
4140
mA
IDD3N
Operating Current
IDD1
One device bank; Active-Read-Precharge
Burst = 2; tRC = tRC (MIN); tCK = tCK (MIN);
lOUT = 0mA; Address and control inputs
changing once per clock cycle.
4680
4680
4680
mA
IDD3N
Precharge PowerDown Standby Current
IDD2P
All device banks idle; Power-down mode;
tCK = tCK (MIN); CKE = (low)
180
180
180
rnA
IDD2P
Idle Standby Current
IDD2F
CS# = High; All device banks idle;
tCK = tCK (MIN); CKE = High; Address
and other control inputs changing once
per clock cycle. VIN = VREF for DQ, DQS
and DM.
1620
1620
1620
mA
IDD2F
Active Power-Down
Standby Current
IDD3P
One device bank active; Power-Down
mode; tCK (MIN); CKE = (low)
1260
1260
1260
mA
IDD3P
Active Standby Current
IDD3N
CS# = High; CKE = High; One device
bank; Active-Precharge;tRC = tRAS (MAX);
tCK = tCK (MIN); DQ, DM and DQS inputs
changing twice per clock cycle; Address
and other control inputs changing once per
clock cycle.
1800
1800
1800
mA
IDD3N
Operating Current
IDD4R
Burst = 2; Reads; Continuous burst; One
device bank active; Address and control
inputs changing once per clock cycle; tCK =
tCK (MIN); lOUT = 0mA.
4770
4770
4770
mA
IDD3N
Operating Current
IDD4W
Burst = 2; Writes; Continuous burst; One
device bank active; Address and control
inputs changing once per clock cycle;
tCK = tCK (MIN); DQ,DM and DQS inputs
changing once per clock cycle.
4590
4590
4590
rnA
IDD3N
Auto Refresh Current
IDD5
tRC = tRC (MIN)
7020
7020
7020
mA
IDD3N
Self Refresh Current
IDD6
CKE ≤ 0.2V
180
180
180
mA
IDD6
Operating Current
IDD7A
Four bank interleaving Reads (BL=4)
with auto precharge with tRC=tRC (MIN);
tCK=tCK(MIN); Address and control inputs
change only during Active Read or Write
commands.
9090
9000
9000
mA
IDD3N
Parameter
November 2004
Rev. 2
Symbol
Rank 1
Conditions
DDR333@CL=2.5
Max
DDR266:@CL=2, 2.5
Max
DDR200@CL=2
Max
5
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
W3EG72255S-D3
-JD3
-AJD3
White Electronic Designs
PRELIMINARY
IDD SPECIFICATIONS AND TEST CONDITIONS
0°C ≤ TA ≤ +70°C, VCCQ = 2.5V ± 0.2V, VCC = 2.5V ± 0.2V.
Includes PLL and register power
Units
Rank 2
Standby
State
Operating Current
IDD0
One device bank; Active - Precharge;
tRC = tRC (MIN); tCK = tCK (MIN); DQ,DM
and DQS inputs changing once per
clock cycle; Address and control inputs
changing once every two cycles.
4725
4725
4725
mA
IDD3N
Operating Current
IDD1
One device bank; Active-ReadPrecharge Burst = 2; tRC = tRC (MIN);
tCK = tCK (MIN); lOUT = 0mA; Address
and control inputs changing once per
clock cycle.
5265
5265
5265
mA
IDD3N
Precharge PowerDown Standby Current
IDD2P
All device banks idle; Power-down mode;
tCK = tCK (MIN); CKE = (low)
180
180
180
rnA
IDD2P
Idle Standby Current
IDD2F
CS# = High; All device banks idle;
tCK = tCK (MIN); CKE = High; Address
and other control inputs changing once
per clock cycle. VIN = VREF for DQ, DQS
and DM.
1930
1930
1930
mA
IDD2F
Active Power-Down Standby
Current
IDD3P
One device bank active; Power-Down
mode; tCK (MIN); CKE = (low)
1260
1260
1260
mA
IDD3P
Active Standby Current
IDD3N
CS# = High; CKE = High; One device
bank; Active-Precharge;tRC = tRAS (MAX);
tCK = tCK (MIN); DQ, DM and DQS inputs
changing twice per clock cycle; Address
and other control inputs changing once
per clock cycle.
2110
2110
2110
mA
IDD3N
Operating Current
IDD4R
Burst = 2; Reads; Continuous burst; One
device bank active; Address and control
inputs changing once per clock cycle; tCK
= tCK (MIN); lOUT = 0mA.
5355
5355
5355
mA
IDD3N
Operating Current
IDD4W
Burst = 2; Writes; Continuous burst; One
device bank active; Address and control
inputs changing once per clock cycle;
tCK = tCK (MIN); DQ,DM and DQS inputs
changing once per clock cycle.
5535
5175
5175
rnA
IDD3N
Auto Refresh Current
IDD5
tRC = tRC (MIN)
7640
7640
7640
mA
IDD3N
Self Refresh Current
IDD6
CKE ≤ 0.2V
455
455
455
mA
IDD6
Operating Current
IDD7A
Four bank interleaving Reads (BL=4)
with auto precharge with tRC=tRC (MIN);
tCK=tCK(MIN); Address and control inputs
change only during Active Read or Write
commands.
9675
9585
9585
mA
IDD3N
Parameter
November 2004
Rev. 2
Symbol
Rank 1
Conditions
DDR333@CL=2.5
Max
DDR266:@CL=2, 2.5
Max
DDR200@CL=2
Max
6
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
White Electronic Designs
W3EG72255S-D3
-JD3
-AJD3
PRELIMINARY
DETAILED TEST CONDITIONS FOR DDR SDRAM IDD1 & IDD7A
IDD1 : OPERATING CURRENT: ONE BANK
IDD7A: OPERATING CURRENT: FOUR BANKS
1. Typical Case: VCC = 2.5V, T = 25°C
2. Worst Case: VCC = 2.7V, T = 10°C
3. Only one bank is accessed with tRC (min), Burst
Mode, Address and Control inputs on NOP edge are
changing once per clock cycle. lOUT = 0mA
4. Timing patterns
• DDR200 (100MHz, CL = 2) : tCK = 10ns, CL2, BL =
4, tRCD = 2*tCK, tRAg = 5*tCK
Read: A0 N R0 N N P0 N A0 N - repeat the same
timing with random address changing; 50% of data
changing at every burst
• DDR266 (133MHz, CL = 2.5) : tCK = 7.5ns, CL =
2.5, BL = 4, tRCD = 3*tCK, tRC = 9*tCK, tRAg = 5*tCK
Read: A0 N N R0 N P0 N N N A0 N - repeat the
same timing with random address changing; 50% of
data changing at every burst
• DDR266 (133MHz, CL = 2) : tCK = 7.5ns, CL = 2, BL
= 4, tRCD = 3*tCK, tRC = 9*tCK, tRAg = 5*tCK
Read: A0 N N R0 N P0 N N N A0 N - repeat the
same timing with random address changing; 50% of
data changing at every burst
• DDR333 (166MHz, CL = 2.5) : tCK = 6ns, BL = 4,
tRCD = 10*tCK, tRAg = 7*tCK
Read: A0 N N R0 N P0 N N N A0 N — repeat the
same timing with random address changing; 50% of
data changing at every burst
1. Typical Case: VCC = 2.5V, T = 25°C
2. Worst Case: VCC = 2.7V, T = 10°C
3. Four banks are being interleaved with tRC (min), Burst
Mode, Address and Control inputs on NOP edge are
not changing.
lout = 0mA
4. Timing patterns
• DDR200 (100MHz, CL = 2) : tCK = 10ns, CL2,
BL = 4, tRRD = 2*tCK, tRCD = 3*tCK, Read with
autoprecharge
Read: A0 N A1 R0 A2 R1 A3 R2 A0 R3 A1 R0
- repeat the same timing with random address
changing; 100% of data changing at every burst
• DDR266 (133MHz, CL = 2.5) : tCK = 7.5ns, CL =
2.5, BL = 4, tRRD = 3*tCK, tRCD = 3*tCK Read with
autoprecharge
Read: A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N A1
R0 - repeat the same timing with random address
changing; 100% of data changing at every burst
• DDR266 (133MHz, CL = 2): tCK = 7.5ns, CL2 = 2,
BL = 4, tRRD = 2*tCK, tRCD = 3*tCK
Read: A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N A1
R0 - repeat the same timing with random address
changing; 100% of data changing at every burst
• DDR333 (166MHz, CL = 2.5) : tCK = 6ns, BL = 4,
tRRD = 3*tCK, tRCD = 3*tCK, Read with autoprecharge
Read: A0 N A1 R0 A2 R1 A3 R2 N R3 A0 N A1
R0 - repeat the same timing with random address
changing; 100% of data changing at every burst
Legend: A = Activate, R = Read, W = Write, P =
Precharge, N = NOP
A (0-3) = Activate Bank 0-3
R (0-3) = Read Bank 0-3
November 2004
Rev. 2
7
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
W3EG72255S-D3
-JD3
-AJD3
White Electronic Designs
PRELIMINARY
DDR SDRAM COMPONENT ELECTRICAL CHARACTERISTICS AND
RECOMMENDED AC OPERATING CONDITIONS
0°C ≤ TA ≤ +70°C; VCC = +2.5V ±0.2V, VCCQ = +2.5V ±0.2V
AC Characteristics
335
Parameter
262/263/265
202
Symbol
Min
Max
Min
Max
Min
Max
Units
Access window of DQs from CK, CK#
tAC
-0.7
+0.7
-0.75
+0.75
-0.8
+0.8
ns
CK high-level width
tCH
0.45
0.55
0.45
0.55
0.45
0.55
tCK
16
CK low-level width
tCL
0.45
0.55
0.45
0.55
0.45
0.55
tCK
16
Clock cycle time
Notes
CL=2.5
tCK (2.5)
6
13
7.5
13
8
13
ns
22
CL=2
tCK (2)
7.5
13
7.5
13
10
13
ns
22
DQ and DM input hold time relative to DQS
tDH
0.45
0.5
0.6
ns
14,17
DQ and DM input setup time relative to DQS
tDS
0.45
0.5
0.6
ns
14,17
ns
17
DQ and DM input pulse width (for each input)
tDIPW
1.75
Access window of DQS from CK, CK#
tDQSCK
-0.60
1.75
+0.60
-0.75
2
+0.75
-0.8
+0.8
DQS input high pulse width
tDQSH
0.35
0.35
0.35
DQS input low pulse width
tDQSL
0.35
0.35
0.35
DQS-DQ skew, DQS to last DQ valid, per group, per access
tDQSQ
0.45
ns
tCK
tCK
0.5
0.5
ns
1.25
tCK
Write command to first DQS latching transition
tDQSS
0.75
DQS falling edge to CK rising - setup time
tDSS
0.2
DQS falling edge from CK rising - hold time
tDSH
0.2
Half clock period
tHP
Data-out high-impedance window from CK, CK#
tHZ
Data-out low-impedance window from CK, CK#
tLZ
-0.70
-0.75
-0.8
Address and control input hold time (fast slew rate)
tIHf
0.75
0.90
Address and control input set-up time (fast slew rate)
tISf
0.75
0.90
Address and control input hold time (slow slew rate)
tIHs
0.80
Address and control input setup time (slow slew rate)
tISs
0.80
Address and control input pulse width (for each input)
tIPW
LOAD MODE REGISTER command cycle time
tMRD
DQ-DQS hold, DQS to first DQ to go non-valid, per access
tQH
Data hold skew factor
tQHS
ACTIVE to PRECHARGE command
tRAS
42
ACTIVE to READ with Auto precharge command
tRAP
15
15
15
ns
ACTIVE to ACTIVE/AUTO REFRESH command period
tRC
60
65
70
ns
AUTO REFRESH command period
tRFC
72
75
75
ns
November 2004
Rev. 2
1.25
0.75
1.25
0.2
0.2
0.2
tCH, tCL
0.75
13,14
tCK
0.2
tCK
tCH, tCL
ns
18
ns
8,19
ns
8,20
1.1
ns
6
1.1
ns
6
1
1.1
ns
6
1
1.1
ns
6
2.2
2.2
2.2
ns
12
15
16
+0.70
+0.75
tHP-tQHS
8
+0.8
tHP-tQHS
0.55
70,000
tCH, tCL
0.75
40
120,000
ns
tHP-tQHS
40
ns
.75
ns
120,000
ns
13,14
15
21
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
W3EG72255S-D3
-JD3
-AJD3
White Electronic Designs
PRELIMINARY
DDR SDRAM COMPONENT ELECTRICAL CHARACTERISTICS AND
RECOMMENDED AC OPERATING CONDITIONS (continued)
0°C ≤ TA ≤ +70°C; VCC = +2.5V ±0.2V, VCCQ = +2.5V ±0.2V
AC Characteristics
Parameter
ACTIVE to READ or WRITE delay
PRECHARGE command period
335
Symbol
Min
tRCD
15
262/263/265
Max
Min
Max
15
202
Min
Max
15
Units
tRP
15
DQS read preamble
tRPRE
0.9
1.1
0.9
1.1
0.9
1.1
tCK
DQS read postamble
tRPST
0.4
0.6
0.4
0.6
0.4
0.6
tCK
ACTIVE bank a to ACTIVE bank b command
tRRD
12
15
15
ns
15
Notes
ns
15
ns
19
DQS write preamble
tWPRE
0.25
0.25
0.25
tCK
DQS write preamble setup time
tWPRES
0
0
0
ns
10,11
DQS write postamble
tCK
9
tWPST
0.4
Write recovery time
tWR
15
Internal WRITE to READ command delay
tWTR
1
Data valid output window
NA
REFRESH to REFRESH command interval
tREFC
0.6
0.4
0.6
15
0.6
15
1
tQH-tDQSQ
0.4
ns
1
tQH-tDQSQ
70.3
tCK
tQH-tDQSQ
70.3
ns
13
70.3
μs
12
7.8
μs
12
Average periodic refresh interval
tREFI
Terminating voltage delay to VCC
tVTD
Exit SELF REFRESH to non-READ command
tXSNR
75
75
75
ns
Exit SELF REFRESH to READ command
tXSRD
200
200
200
tCK
November 2004
Rev. 2
7.8
0
7.8
0
9
0
ns
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
White Electronic Designs
W3EG72255S-D3
-JD3
-AJD3
PRELIMINARY
Notes
1.
All voltages referenced to VSS
2.
Tests for AC timing, IDD, and electrical AC and DC characteristics
may be conducted at normal reference / supply voltage levels, but
the related specifications and device operations are guaranteed for
the full voltage range specified.
3.
Outputs are measured with equivalent load:
11.
It is recommended that DQS be valid (HIGH or LOW) on or before
the WRITE command. The case shown (DQS going from High-Z to
logic LOW) applies when no WRITEs were previously in progress
on the bus. If a previous WRITE was in progress, DQS could be
high during this time, depending on tDQSS.
12.
The refresh period is 64ms. This equates to an average refresh
rate of 7.8125µs. However, an AUTO REFRESH command must
be asserted at least once every 70.3µs; burst refreshing or posting
by the DRAM controller greater than eight refresh cycles is not
allowed.
13.
The valid data window is derived by achieving other specifications
- tHP (tCK/2), tDQSQ, and tQH (tQH = tHP - tQHS). The data valid
window derates directly proportional with the clock duty cycle
and a practical data valid window can be derived. The clock is
allowed a maximum duty cycled variation of 45/55. Functionality
is uncertain when operating beyond a 45/55 ratio. The data valid
window derating curves are provided below for duty cycles ranging
between 50/50 and 45/55.
14.
Referenced to each output group: x4 = DQS with DQ0-DQ3.
15.
READs and WRITEs with auto precharge are not allowed to be
issued until tRAS (MIN) can be satisfied prior to the internal precharge
command being issued.
16.
JEDEC specifies CK and CK# input slew rate must be > 1V/ns
(2V/ns differentially).
17.
DQ and DM input slew rates must not deviate from DQS by more
than 10%. If the DQ/DM/DQS slew rate is less than 0.5V/ns,
timing must be derated: 50ps must be added to tDS and tDH for
each 100mV/ns reduction in slew rate. If slew rates exceed 4V/ns,
functionality is uncertain.
18.
tHP min is the lesser of tCL min and tCH min actually applied to the
device CK and CK# inputs, collectively during bank active.
VTT
Output
(VOUT)
4.
5.
6.
50
50Ω
Reference
Point
30pF
AC timing and IDD tests may use a VIL-to-VIH swing of up to 1.5V
in the test environment, but input timing is still referenced to VREF
(or to the crossing point for CK/CK#), and parameter specifications
are guaranteed for the specified AC input levels under normal use
conditions. The minimum slew rate for the input signals used to
test the device is 1V/ns in the range between VIL(AC) and VIH(AC).
The AC and DC input level specifications are defined in the SSTL_
2 standard (i.e., the receiver will effectively switch as a result of the
signal crossing the AC input level, and will remain in that state as
long as the signal does not ring back above [below] the DC input
LOW [high] level).
For slew rates less than 1V/ns and greater than or equal to 0.5V/
ns. If the slew rate is less than 0.5V/ns, timing must be derated: tIS
has an additional 50ps per each 100mV/ns reduction in slew rate
from the 500mV/ns. tIH has 0ps added, that is, it remains constant.
If the slew rate exceeds 4.5V/ns, functionality is uncertain. For
335, slew rates must be greater than or equal to 0.5V/ns.
7.
Inputs are not recognized as valid until VREF stabilizes. Exception:
during the period before VREF stabilizes, CKE ≤ 0.3 x VCCQ is
recognized as LOW.
19.
tHZ (MAX) will prevail over the tDQSCK (MAX) + tRPST (MAX)
condition. tLZ (MIN) will prevail over tDQSCK (MIN) + PRE (MAX)
condition.
8.
tHZ and tLZ transitions occur in the same access time windows as
valid data transitions. These parameters are not referenced to a
specific voltage level, but specify when the device output is no
longer driving (HZ) and begins driving (LZ).
20.
For slew rates greater than 1V/ns the (LZ) transition will start about
310ps earlier.
21.
CKE must be active (High) during the entire time a refresh
command is executed. That is, from the time the AUTO REFRESH
command is registered, CKE must be active at each rising clock
edge, until tRFC has been satisfied.
22.
Whenever the operating frequency is altered, not including jitter,
the DLL is required to be reset. This is followed by 200 clock cycles
(before READ commands).
9.
10.
The intent of the “Don’t Care” state after completion of the
postamble is the DQS-driven signal should either be HIGH, LOW,
or high-Z, and that any signal transition within the input switching
region must follow valid input requirements. That is, if DQS
transitions HIGH (above VIHDC (MIN) then it must not transition
LOW (below VIHDC) prior to tDQSH (MIN).
This is not a device limit. The device will operate with a negative
value, but system performance could be degraded due to bus
turnaround.
November 2004
Rev. 2
10
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
W3EG72255S-D3
-JD3
-AJD3
White Electronic Designs
PRELIMINARY
ORDERING INFORMATION FOR JD3
Part Number
Speed
CAS Latency
tRCD
tRP
Height*
W3EG72255S335JD3xG
166MHz/333Mb/s
2.5
3
3
30.48 (1.20")
W3EG72255S262JD3xG
133MHz/266Mb/s
2
2
2
30.48 (1.20")
W3EG72255S263JD3xG
133MHz/266Mb/s
2
3
3
30.48 (1.20")
W3EG72255S265JD3xG
133MHz/266Mb/s
2.5
3
3
30.48 (1.20")
W3EG72255S202JD3xG
100MHz/200Mb/s
2
2
2
30.48 (1.20")
NOTES:
• Consult Factory for availability of RoHS compliant products. (G = RoHS Compliant)
• Vendor specific part numbers are used to provide memory components source control. The place holder for this is shown as lower case “x” in the part numbers above and is to
be replaced with the respective vendors code. Consult factory for qualified sourcing options. (M = Micron, S = Samsung & consult factory for others)
• Consult factory for availability of industrial temperature (-40°C to 85°C) option
PACKAGE DIMENSIONS FOR JD3
133.48
(5.255" MAX.)
131.34
(5.171")
128.95
(5.077")
3.99
(0.157 (2x))
6.35
(0.250 MAX)
30.48
(1.20 MAX)
17.78
(0.700)
10.0
(0.394)
6.36
(0.250)
64.77
(2.550)
6.35
(0.250)
49.53
(1.950)
1.27
(0.050 TYP.)
1.78
(0.070)
2.31
(0.091)
3.99
(2x)
(0.157)
(MIN)
3.00
(0.118)
(4x)
1.27
± 0.10
(0.050)
(± 0.004)
* ALL DIMENSIONS ARE IN MILLIMETERS AND (INCHES).
November 2004
Rev. 2
11
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
W3EG72255S-D3
-JD3
-AJD3
White Electronic Designs
PRELIMINARY
ORDERING INFORMATION FOR AJD3
Part Number
Speed
CAS Latency
tRCD
tRP
Height*
W3EG72255S335AJD3xG
166MHz/333Mb/s
2.5
3
3
28.70 (1.13")
W3EG72255S262AJD3xG
133MHz/266Mb/s
2
2
2
28.70 (1.13")
W3EG72255S263AJD3xG
133MHz/266Mb/s
2
3
3
28.70 (1.13")
W3EG72255S265AJD3xG
133MHz/266Mb/s
2.5
3
3
28.70 (1.13")
W3EG72255S202AJD3xG
100MHz/200Mb/s
2
2
2
28.70 (1.13")
NOTES:
• Consult Factory for availability of RoHS compliant products. (G = RoHS Compliant)
• Vendor specific part numbers are used to provide memory components source control. The place holder for this is shown as lower case “x” in the part numbers above and is to
be replaced with the respective vendors code. Consult factory for qualified sourcing options. (M = Micron, S = Samsung & consult factory for others)
• Consult factory for availability of industrial temperature (-40°C to 85°C) option
PACKAGE DIMENSIONS FOR AJD3
133.48
(5.255" MAX.)
131.34
(5.171")
128.95
(5.077")
3.99
(0.157 (2x))
6.35
(0.250 MAX)
28.70
(1.13 MAX)
17.78
(0.700)
10.0
(0.394)
6.35
(0.250)
64.77
(2.550)
6.35
(0.250)
49.53
(1.950)
1.27
(0.050 TYP.)
1.78
(0.070)
2.31
(0.091)
3.99
(2x)
(0.157)
(MIN)
3.00
(0.118)
(4x)
1.27
± 0.10
(0.050)
(± 0.004)
* ALL DIMENSIONS ARE IN MILLIMETERS AND (INCHES).
November 2004
Rev. 2
12
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
W3EG72255S-D3
-JD3
-AJD3
White Electronic Designs
PRELIMINARY
ORDERING INFORMATION FOR D3
Part Number
Speed
CAS Latency
tRCD
tRP
Height*
W3EG72255S335D3xG
166MHz/333Mb/s
2.5
3
3
28.58 (1.125")
W3EG72255S262D3xG
133MHz/266Mb/s
2
2
2
28.58 (1.125")
W3EG72255S263D3xG
133MHz/266Mb/s
2
3
3
28.58 (1.125")
W3EG72255S265D3xG
133MHz/266Mb/s
2.5
3
3
28.58 (1.125")
W3EG72255S202D3xG
100MHz/200Mb/s
2
2
2
28.58 (1.125")
NOTES:
• Consult Factory for availability of RoHS compliant products. (G = RoHS Compliant)
• Vendor specific part numbers are used to provide memory components source control. The place holder for this is shown as lower case “x” in the part numbers above and is to
be replaced with the respective vendors code. Consult factory for qualified sourcing options. (M = Micron, S = Samsung & consult factory for others)
• Consult factory for availability of industrial temperature (-40°C to 85°C) option
PACKAGE DIMENSIONS FOR D3
133.48
(5.255" MAX.)
131.34
(5.171")
128.95
(5.077")
3.99
(0.157 (2x))
6.35
(.250 MAX)
28.58
(1.125 MAX)
17.78
(0.700)
10.0
(0.394)
6.35
(0.250)
64.77
(2.550)
6.35
(0.250)
49.53
(1.950)
1.27
(0.050 TYP.)
1.78
(0.070)
2.31
(0.091)
3.99
(2x)
(0.157)
(MIN)
3.00
(0.118)
(4x)
1.27
± 0.10
(0.050)
(± 0.004)
* ALL DIMENSIONS ARE IN MILLIMETERS AND (INCHES).
November 2004
Rev. 2
13
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
White Electronic Designs
W3EG72255S-D3
-JD3
-AJD3
PRELIMINARY
PART NUMBERING GUIDE
W 3 E G 72 255M S xxx D3 x G
WEDC
SDRAM
DDR
GOLD
BUS WIDTH
DEPTH (Dual Rank):
256 = 256Mb
2.5V
SPEED (MHz):
166, 133, 100MHZ
PACKAGE:
JD3 or AJD3
COMPONENT VENDOR:
M = Micron, S = Samsung
RoHS COMPLIANT
November 2004
Rev. 2
14
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
W3EG72255S-D3
-JD3
-AJD3
White Electronic Designs
PRELIMINARY
Document Title
2GB – 2x128Mx72, DDR SDRAM Registered ECC, w/PLL
Revision History
Rev #
History
Release Date
Status
Rev 0
Initial Release
5-2-03
Advanced
Rev 1
Package dimension change
3-3-04
Preliminary
11-04
Preliminary
1.1 Added JD3 and AJD3 package options
1.2 Incorporated millimeter and inch measurements
1.3 Updated all abbreviations
—
1.4 Changed all / &
to #
1.5 Added "Not Recommended for New Designs" to D3
1.6 Added IDD specifications and test conditions for DDR
SDRAM components
1.7 Removed "ED" from part marking
1.8 Added document title page
Rev 2
2.1 Added Lead-Free and RoHS note
2.2 Added vendor code options
M = Micron
S = Samsung
November 2004
Rev. 2
15
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com