WEDC W3E232M16S

White Electronic Designs
W3E232M16S-XSTX
PRELIMINARY*
2x32Mx16bit DDR SDRAM
FEATURES
Bidirectional data strobe (DQS) transmitted/
received with data, i.e., source-synchronous data
capture (one per byte)
DQS edge-aligned with data for READs; centeraligned with data for WRITEs
Double-data-rate architecture; two data transfers
per clock cycle
Data rate = 200, 266, 333, 400 Mbs
Package:
Four internal banks for concurrent operation
• 66pin TSOP II package
Data mask (DM) pins for masking write data
(one per byte)
2.5V ±0.2V core power supply
2.5V I/O (SSTL_2 compatible)
Programmable IOL/IOH option
Differential clock inputs(CK and CK#)
Auto precharge option
DLL aligns DQ and DQS transition with CK
Auto Refresh and Self Refresh Modes
MRS cycle with address key programs
Commercial, and Industrial Temperature Ranges
• Read latency : 2, 2.5 , 3 (Clock)
Organized as 2X32M x 16
• Burst length (2, 4, or 8)
* This product is under development, is not qualified +and is subject to change
without notice.
• Burst type (sequential & interleave)
Auto & Self refresh Modes
RoHS Compliant
Commands entered on each positive CK edge
Internal pipelined double-data-rate (DDR)
architecture; two data accesses per clock cycle
OPERATING FREQUENCIES
DDR400
DDR333
DDR266
DDR200
Speed @CL2
—
133MHz
133MHz
100MHz
Speed @CL2.5
166MHz
166MHz
133MHz
133MHz
Speed @CL3
200MHz
—
—
—
* CL = CAS Latency
FUNCTIONAL BLOCK DIAGRAM
CK, CK#, CAS, LDM, UDM
RAS#, WE#, UDQS, LDQS
CS0#, CKE0
32Mx16
32Mx16
CS1#, CKE1
A0-A12, BA0, BA1
I/O0 ~ I/O15
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PRELIMINARY*
PIN CONFIGURATION
VCC
1
66
VSS
DQ0
2
65
DQ15
VCCQ
3
64
VSSQ
DQ1
4
63
DQ14
DQ2
5
62
DQ13
VSSQ
6
61
VCCQ
DQ3
7
60
DQ12
DQ4
8
59
DQ11
VCCQ
9
58
VSSQ
DQ5
10
57
DQ10
DQ6
11
56
DQ9
VSSQ
12
55
VCCQ
DQ7
13
54
DQ8
NC
14
53
NC
VCCQ
15
52
VSSQ
LDQS
16
51
UDQS
NC
17
50
DNU
VCC
18
49
VREF
DNU
19
48
VSS
LDM
20
47
UDM
WE#
21
46
CK#
CAS#
22
45
CK
RAS#
23
44
CKE0
CS0#
24
43
CKE1
CS1#
25
42
A12
BA0
26
41
A11
BA1
27
40
A9
AP/A10
28
39
A8
A0
29
38
A7
A1
30
37
A6
A2
31
36
A5
A3
32
35
A4
VCC
33
34
VSS
66Pin TSOPII
(400mil x 875mil)
(0.65mm Pin Pitch)
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W3E232M16S-XSTX
PRELIMINARY*
PACKAGE DIMENSIONS
0.105”/+0.005”/-0.00”
0.483” MIN
0.487” MAX
#66
#1
0.026”/±0.003”
0.880”/±0.005”
0.012”/±0.003”
#34
#33
Top View
Side View
Bottom View
0.483” MIN
0.487” MAX
0.105”/+0.005”/-0.00”
TSOP
TSOP
MAIN PCB
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W3E232M16S-XSTX
PRELIMINARY*
GENERAL DESCRIPTION
bandwidth by hiding row precharge and activation time.
The 2x32Mx16 (1Gb) DDR SDRAM is a high-speed CMOS,
dynamic random-access, memory using 2 chips containing
536,870,912 bits. Each chip is internally configured as a
quad-bank DRAM.
An auto refresh mode is provided, along with a powersaving power-down mode. All inputs are compatible with
the Jedec Standard for SSTL_2. All full drive options
outputs are SSTL_2, Class II compatible.
The 2x32Mx16 DDR SDRAM uses a double data rate
ar chi tec ture to achieve high-speed operation. The
double data rate architecture is essentially a 2n-prefetch
architecture with an interface designed to transfer two data
words per clock cycle at the I/O pins. A single read or write
access for the 2x32Mx16 DDR SDRAM effectively consists
of a single 2n-bit wide, one-clock-cycle data tansfer at the
internal DRAM core and two corresponding n-bit wide,
one-half-clock-cycle data transfers at the I/O pins.
FUNCTIONAL DESCRIPTION
Read and write accesses to the DDR SDRAM are burst
oriented; accesses start at a selected location and continue
for a programmed number of locations in a programmed
sequence. Accesses begin with the registration of an
ACTIVE command which is then followed by a READ or
WRITE command. The address bits registered coincident
with the ACTIVE command are used to select the bank and
row to be accessed (BA0 and BA1 select the bank, A0-12
select the row). The address bits registered coincident
with the READ or WRITE command are used to select the
starting column location for the burst access.
A bi-directional data strobe (DQS) is transmitted externally,
along with data, for use in data capture at the receiver.
strobe transmitted by the DDR SDRAM during READs and
by the memory contoller during WRITEs. DQS is edgealigned with data for READs and center-aligned with data
for WRITEs. Each chip has two data strobes, one for the
lower byte and one for the upper byte.
Prior to normal operation, the DDR SDRAM must be
initialized. The following sections provide detailed
information covering device initialization, register definition,
command descriptions and device operation.
The 2x32Mx16 DDR SDRAM operates from a differential
clock (CK and CK#); the crossing of CK going HIGH and
CK# going LOW will be referred to as the positive edge of
CK. Commands (address and control signals) are registered
at every positive edge of CK. Input data is registered on
both edges of DQS, and output data is referenced to both
edges of DQS, as well as to both edges of CK.Read and
write accesses to the DDR SDRAM are burst oriented;
accesses start at a selected location and continue for
a programmed number of locations in a programmed
sequence. Accesses begin with the registration of an
ACTIVE command, which is then followed by a READ or
WRITE command. The address bits registered coincident
with the ACTIVE command are used to select the bank
and row to be accessed. The address bits registered
coincident with the READ or WRITE command are used
to select the bank and the starting column location for the
burst access.
INITIALIZATION
The DDR SDRAM provides for programmable READ
or WRITE burst lengths of 2, 4, or 8 locations. An auto
precharge function may be enabled to provide a selftimed row precharge that is initiated at the end of the
burst access.
DDR SDRAMs must be powered up and initialized in a
predefined manner. Operational procedures other than
those specified may result in undefined operation. Power
must first be applied to VCC and VCCQ simultaneously, and
then to VREF (and to the system VTT). VTT must be applied
after VCCQ to avoid device latch-up, which may cause
permanent damage to the device. VREF can be applied any
time after VCCQ but is expected to be nominally coincident
with VTT. Except for CKE, inputs are not recognized as
valid until after VREF is applied. CKE is an SSTL_2 input
but will detect an LVCMOS LOW level after VCC is applied.
After CKE passes through VIH, it will transition to an
SSTL_2 signal and remain as such until power is cycled.
Maintaining an LVCMOS LOW level on CKE during powerup is required to ensure that the DQ and DQS outputs will
be in the High-Z state, where they will remain until driven
in normal operation (by a read access). After all power
supply and reference voltages are stable, and the clock
is stable, the DDR SDRAM requires a 200µs delay prior
to applying an executable command.
The pipelined, multibank architecture of DDR SDRAMs allows
for concurrent operation, thereby providing high effective
Once the 200µs delay has been satisfied, a DESELECT
or NOP command should be applied, and CKE should
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PRELIMINARY*
be brought HIGH. Following the NOP command, a
PRECHARGE ALL command should be applied. Next a
LOAD MODE REGISTER command should be issued for
the extended mode register (BA1 LOW and BA0 HIGH)
to enable the DLL, followed by another LOAD MODE
REGISTER command to the mode register (BA0/BA1
both LOW) to reset the DLL and to program the operating
parameters. Two-hundred clock cy cles are required
between the DLL reset and any READ command. A
PRECHARGE ALL command should then be applied,
placing the device in the all banks idle state.
BURST LENGTH
Read and write accesses to the DDR SDRAM are burst
oriented, with the burst length being programmable,
as shown in Fig ure 3. The burst length determines
the maximum number of column locations that can be
accessed for a given READ or WRITE command. Burst
lengths of 2, 4 or 8 locations are available for both the
sequential and the interleaved burst types.
Reserved states should not be used, as unknown operation
or incompatibility with future versions may result.
When a READ or WRITE command is issued, a block of
columns equal to the burst length is effectively selected.
All accesses for that burst take place within this block,
meaning that the burst will wrap within the block if a
boundary is reached. The block is uniquely selected by
A1-Ai when the burst length is set to two; by A2-Ai when the
burst length is set to four (where Ai is the most significant
column address for a given configuration); and by A3-Ai
when the burst length is set to eight. The remaining (least
significant) address bit(s) is (are) used to select the starting
location within the block. The programmed burst length
applies to both READ and WRITE bursts.
Once in the idle state, two AUTO REFRESH cycles must
be performed (tRFC must be satisfied.) Additionally, a LOAD
MODE REGISTER command for the mode register with
the reset DLL bit deactivated (i.e., to program operating
pa ram e ters without resetting the DLL) is required.
Following these requirements, the DDR SDRAM is ready
for normal operation.
REGISTER DEFINITION
MODE REGISTER
The Mode Register is used to define the specific mode of
operation of the DDR SDRAM. This definition includes the
selection of a burst length, a burst type, a CAS latency,
and an operating mode, as shown in Figure 3. The Mode
Register is programmed via the MODE REGISTER SET
command (with BA0 = 0 and BA1 = 0) and will retain
the stored information until it is programmed again or
the device loses power. (Except for bit A8 which is self
clearing).
BURST TYPE
Accesses within a given burst may be programmed to be
either sequential or interleaved; this is referred to as the
burst type and is selected via bit M3.
The ordering of accesses within a burst is determined by
the burst length, the burst type and the starting column
address, as shown in Table 1.
READ LATENCY
Reprogramming the mode register will not alter the contents
of the memory, provided it is performed correctly. The Mode
Register must be loaded (reloaded) when all banks are
idle and no bursts are in progress, and the controller must
wait the specified time before initiating the subsequent
operation. Violating either of these requirements will result
in unspecified operation.
The READ latency is the delay, in clock cycles, between
the registration of a READ command and the availability
of the first bit of output data. The latency can be set to 2
or 2.5 clocks.
If a READ command is registered at clock edge n, and the
latency is m clocks, the data will be available by clock edge
n+m. Table 2 below indicates the operating frequencies at
which each CAS latency setting can be used.
Mode register bits A0-A2 specify the burst length, A3
specifies the type of burst (sequential or interleaved),
A4-A6 specify the CAS latency, and A7-A12 specify the
operating mode.
Reserved states should not be used as unknown operation
or incompatibility with future versions may result.
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PRELIMINARY*
controller must wait the specified time before initiating
any sub se quent operation. Violating either of these
requirements could result in unspecified operation.
OPERATING MODE
The normal operating mode is selected by issuing a MODE
REGISTER SET command with bits A7-A12 each set to
zero, and bits A0-A6 set to the desired values. A DLL reset
is initiated by issuing a MODE REGISTER SET command
with bits A7 and A9-A12 each set to zero, bit A8 set to one,
and bits A0-A6 set to the desired values. Although not
required, JEDEC specifications recommend when a LOAD
MODE REGISTER command is issued to reset the DLL, it
should always be followed by a LOAD MODE REGISTER
command to select normal operating mode.
OUTPUT DRIVE STRENGTH
The normal full drive strength for all outputs are specified to
be SSTL2, Class II. The DDR SDRAM supports an option
for reduced drive. This option is intended for the support
of the lighter load and/or point-to-point environments. The
selection of the reduced drive strength will alter the DQs
and DQSs from SSTL2, Class II drive strength to a reduced
drive strength, which is approximately 54 percent of the
SSTL2, Class II drive strength.
All other combinations of values for A7-A12 are reserved
for future use and/or test modes. Test modes and reserved
states should not be used because unknown operation or
incompatibility with future versions may result.
DLL ENABLE/DISABLE
When the part is running without the DLL enabled, device
functionality may be altered. The DLL must be enabled for
normal operation. DLL enable is required during powerup initialization and upon returning to normal operation
after having disabled the DLL for the purpose of debug or
evaluation. (When the device exits self refresh mode, the
DLL is enabled automatically.) Any time the DLL is enabled,
200 clock cycles with CKE high must occur before a READ
command can be issued.device loses power. The enabling
of the DLL should always be followed by a LOAD MODE
REGISTER command to the mode register (BA0/BA1
both LOW) to reset the DLL.The extended mode register
must be loaded when all banks are idle and no bursts are
in progress, and the controller must wait the specified
time before initiating any subsequent operation. Violating
either of these requirements could result in unspecified
operation.
EXTENDED MODE REGISTER
The extended mode register controls functions beyond
those controlled by the mode register; these additional
functions are DLL enable/disable, output drive strength,
and QFC. These functions are controlled via the bits shown
TABLE 2 - CAS LATENCY
ALLOWABLE OPERATING
FREQUENCY (MHz)
CAS
LATENCY = 2
CAS
LATENCY = 2.5
CAS
LATENCY = 3
-200
≤ 75
≤ 100
-
-266
≤ 100
≤ 133
-
-333
−
≤ 166
≤ 166
-400
-
≤ 166
≤ 200
SPEED
COMMANDS
The Truth Table provides a quick reference of available
commands. This is followed by a written description of
each command.
in Figure 5. The extended mode register is programmed
via the LOAD MODE REGISTER command to the mode
register (with BA0 = 1 and BA1 = 0) and will retain the
stored information until it is programmed again or the
device loses power. The enabling of the DLL should always
be followed by a LOAD MODE REGISTER command to the
mode register (BA0/BA1 both LOW) to reset the DLL.
DESELECT
The DESELECT function (CS# High) prevents new
commands from being executed by the DDR SDRAM. The
SDRAM is effectively deselected. Operations already in
progress are not affected.
The extended mode register must be loaded when all
banks are idle and no bursts are in progress, and the
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PRELIMINARY*
NO OPERATION (NOP)
ACTIVE
The NO OPERATION (NOP) command is used to perform
a NOP to the selected DDR SDRAM (CS# is LOW while
RAS#, CAS#, and WE# are high). This prevents unwanted
commands from being registered during idle or wait states.
Operations already in progress are not affected.
The ACTIVE command is used to open (or activate) a
row in a particular bank for a subsequent access. The
value on the BA0, BA1 inputs selects the bank, and
the address provided on inputs A0-12 selects the row.
This row remains active (or open) for accesses until
a PRECHARGE command is issued to that bank. A
PRECHARGE command must be issued before opening
a different row in the same bank.
LOAD MODE REGISTER
The Mode Registers are loaded via inputs A0-12. The
LOAD MODE REGISTER command can only be issued
when all banks are idle, and a subsequent executable
command cannot be issued until tMRD is met.
READ
The READ command is used to initiate a burst read access
to an active row. The value on the BA0, BA1 inputs selects
the bank, and the address provided on inputs A0-9 selects
the starting column location. The value on input A10
determines whether or not AUTO PRECHARGE is used. If
AUTO PRECHARGE is selected, the row being accessed
will be precharged at the end of the READ burst; if AUTO
PRECHARGE is not selected, the row will remain open
for subsequent accesses
FIGURE 3 – MODE REGISTER DEFINITION
BA1
A12 A11 A10 A9
BA0
14
13
0*
0*
12 11 10 9
A8
8 7
Operating Mode
A7
A6
6
A5
5
A3
A4
4
3
CAS Latency
BT
A2
2
A1
1
0
A0
Address Bus
Mode Register (Mx)
Burst Length
* M14 and M13
(BA0 and BA1 must be
"0, 0" to select
the base mode register
(vs. the extended
mode register).
Burst Length
M2 M1 M0
M3 = 1
M3 = 0
0
0 0
Reserved
0
0 1
2
2
0
1 0
4
4
0
1 1
8
8
1
0 0
Reserved
Reserved
1
0 1
Reserved
Reserved
1
1 0
Reserved
Reserved
1
1 1
Reserved
Reserved
WRITE
Reserved
The WRITE command is used to initiate a burst write
access to an active row. The value on the BA0, BA1 inputs
will be precharged at the end of the READ burst; if AUTO
PRECHARGE is not selected, the row will remain open
for subsequent accesses
PRECHARGE
Burst Type
M3
0
Sequential
1
Interleaved
M6 M5 M4
The PRECHARGE command is used to deactivate the
open row in a particular bank or the open row in all banks.
The bank(s) will be available for a subsequent row access
a specified time (tRP) after the PRECHARGE command is
issued. Except in the case of concurrent auto precharge,
where a READ or WRITE command to a different bank is
allowed as long as it does not interrupt the data transfer
in the current bank and does not violate any other timing
parameters. Input A10 determines whether one or all
banks are to be precharged, and in the case where only
one bank is to be precharged, inputs BA0, BA1 select the
bank. Otherwise BA0, BA1 are treated as “Don’t Care.”
Once a bank has been precharged, it is in the idle state and
must be activated prior to any READ or WRITE commands
being issued to that bank. A PRECHARGE command will
be treated as a NOP if there is no open row in that bank
(idle state), or if the previously open row is already in the
CAS Latency
0
0 0
Reserved
0
0 1
Reserved
0
1 0
2
0
1 1
Reserved
1
0 0
Reserved
1
0 1
Reserved
1
1 0
2.5
1
1 1
Reserved
M12
M11
M10
M9
M8
M7
M6-M0
0
0
0
0
0
0
Valid
Normal Operation
0
0
0
0
1
0
Valid
Normal Operation/Reset DLL
-
-
-
-
-
-
-
Operating Mode
All other states reserved
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December 2005
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TABLE 1 – BURST DEFINITION
Burst
Length
Starting Column
Address
FIGURE 4 – CAS LATENCY
Order of Accesses Within a Burst
Type = Sequential
Type = Interleaved
4
0
0-1
0-1
1
1-0
1-0
A0
0
0
0-1-2-3
0-1-2-3
0
1
1-2-3-0
1-0-3-2
1
0
2-3-0-1
2-3-0-1
1
1
3-0-1-2
3-2-1-0
COMMAND
8
A0
0
0
0
READ
NOP
NOP
T2n
T3
T3n
NOP
CL = 2
DQ
0-1-2-3-4-5-6-7
T0
T1
T2
READ
NOP
NOP
0
1
1-2-3-4-5-6-7-0
1-0-3-2-5-4-7-6
0
1
0
2-3-4-5-6-7-0-1
2-3-0-1-6-7-4-5
0
1
1
3-4-5-6-7-0-1-2
3-2-1-0-7-6-5-4
1
0
0
4-5-6-7-0-1-2-3
4-5-6-7-0-1-2-3
1
0
1
5-6-7-0-1-2-3-4
5-4-7-6-1-0-3-2
1
1
0
6-7-0-1-2-3-4-5
6-7-4-5-2-3-0-1
1
1
1
7-0-1-2-3-4-5-6
7-6-5-4-3-2-1-0
T3
T3n
CLK
NOP
CL = 2.5
0-1-2-3-4-5-6-7
0
T2n
CLK#
COMMAND
A1
T2
DQS
A1
A2
T1
CLK
A0
2
T0
CLK#
DQS
DQ
Burst Length = 4 in the cases shown
Shown with nominal tAC and nominal tDSDQ
DATA
TRANSITIONING DATA
DON'T CARE
process of precharging.
NOTES:
1. For a burst length of two, A1-Ai select two-data-element block; A0
selects the starting column within the block.
2. For a burst length of four, A2-Ai select four-data-element block; A0-1
select the starting column within the block.
3. For a burst length of eight, A3-Ai select eight-data-element block;
A0-2 select the starting column within the block.
4. Whenever a boundary of the block is reached within a given
sequence above, the following access wraps within the block.
AUTO PRECHARGE ensures that the precharge is
initiated at the earliest valid stage within a burst. This
“earliest valid stage” is determined as if an explicit
precharge command was issued at the earliest possible
time, without violating tRAS (MIN).The user must not issue
another command to the same bank until the precharge
time (tRP) is completed.
AUTO PRECHARGE
AUTO PRECHARGE is a feature which performs the
same individual-bank PRECHARGE function described
above, but without requiring an explicit command. This is
accomplished by using A10 to enable AUTO PRECHARGE
in conjunction with a specific READ or WRITE command.
A precharge of the bank/row that is addressed with the
READ or WRITE command is automatically performed
upon completion of the READ or WRITE burst. AUTO
PRECHARGE is nonpersistent in that it is either enabled
or disabled for each individual READ or WRITE command.
The device supports concurrent auto precharge if the
command to the other bank does not interrupt the data
transfer to the current bank.
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FIGURE 5 – EXTENDED MODE REGISTER
DEFINITION
BURST TERMINATE
The BURST TERMINATE command is used to truncate
READ bursts (with auto precharge disabled). The most
recently registered READ command prior to the BURST
TERMINATE command will be truncated. The open page
which the READ burst was terminated from remains
open.
BA1 BA0 A12 A11 A10 A9
A8
14 13 12 11 10 9 8
01
11
A7
7
A6
6
A3 A2
A5 A4
5
4
3
2
A1 A0
1
0
Extended Mode
Register (Ex)
DS DLL
Operating Mode
Address Bus
AUTO REFRESH
AUTO REFRESH is used during normal operation of the
DDR SDRAM and is analogous to CAS-BEFORE-RAS
(CBR) REFRESH in conventional DRAMs. This command
is nonpersistent, so it must be issued each time a refresh
is required. All banks must be idle before an AUTO
REFRESH command is issued.
E0
DLL
0
Enable
1
E1
Disable
Drive Strength
0
Normal
1
Reduced
The addressing is generated by the internal refresh
controller. This makes the address bits “Don’t Care”
E8
E7
E6
E5
E4
E3
E2
E1, E0
Operating Mode
0
0
0
0
0
0
0
0
0
0
0
Valid
Reserved
-
-
-
-
-
-
-
-
-
-
-
-
Reserved
E12 E11 E10 E9
1. E14 and E13 must be "0, 1" to select the Extended Mode Register (vs. the base Mode Register)
2. The QFC# function is not supported.
TRUTH TABLE – COMMANDS (NOTE 1)
NAME (FUNCTION)
CS#
RAS#
CAS#
WE#
ADDR
DESELECT (NOP) (9)
H
X
X
X
X
NO OPERATION (NOP) (9)
L
H
H
H
X
ACTIVE (Select bank and activate row) ( 3)
L
L
H
H
Bank/Row
READ (Select bank and column, and start READ burst) (4)
L
H
L
H
Bank/Col
WRITE (Select bank and column, and start WRITE burst) (4)
L
H
L
L
Bank/Col
BURST TERMINATE (8)
L
H
H
L
X
Code
PRECHARGE (Deactivate row in bank or banks) ( 5)
L
L
H
L
AUTO REFRESH or SELF REFRESH (Enter self refresh mode) (6, 7)
L
L
L
H
X
LOAD MODE REGISTER (2)
L
L
L
L
Op-Code
NOTES:
1. CKE is HIGH for all commands shown except SELF REFRESH.
2. A0-12 define the op-code to be written to the selected Mode Register. BA0, BA1
select either the mode register (0, 0) or the extended mode register (1, 0).
3. A0-12 provide row address, and BA0, BA1 provide bank address.
4. A0-9 provide column address; A10 HIGH enables the auto precharge feature (non
persistent), while A10 LOW disables the auto precharge feature; BA0, BA1 provide
bank address.
5. A10 LOW: BA0, BA1 determine the bank being precharged. A10 HIGH: All banks
precharged and BA0, BA1 are “Don’t Care.”
6.
This command is AUTO REFRESH if CKE is HIGH; SELF REFRESH if CKE is
LOW.
7. Internal refresh counter controls row addressing; all inputs and I/Os are “Don’t
Care” except for CKE.
8. Applies only to read bursts with auto precharge disabled; this command is
undefined (and should not be used) for READ bursts with auto precharge enabled
and for WRITE bursts.
9. DESELECT and NOP are functionally interchangeable.
10. Used to mask write data; provided coincident with the corresponding data.
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W3E232M16S-XSTX
PRELIMINARY*
TRUTH TABLE – DM OPERATION
NAME (FUNCTION)
DM
DQs
WRITE ENABLE (10)
L
Valid
WRITE INHIBIT (10)
H
X
The procedure for exiting self refresh requires a sequence
of commands. First, CK and CK# must be stable prior
to CKE going back HIGH. Once CKE is HIGH, the DDR
SDRAM must have NOP commands issued for tXSNR,
because time is required for the completion of any internal
refresh in progress.
during an AUTO REFRESH command. Each DDR SDRAM
requires AUTO REFRESH cycles at an average interval
of 7.8125µs (maximum).
To allow for improved efficiency in scheduling and
switching between tasks, some flexibility in the absolute
refresh interval is provided. A maximum of eight AUTO
REFRESH commands can be posted to any given DDR
SDRAM, meaning that the maximum absolute interval
between any AUTO REFRESH command and the next
AUTO REFRESH command is 9 x 7.8125µs (70.3µs). This
maximum absolute interval is to allow future support for
DLL updates internal to the DDR SDRAM to be restricted
to AUTO REFRESH cycles, without allowing excessive
drift in tAC between updates.
A simple algorithm for meeting both refresh and DLL
requirements is to apply NOPs for tXSNR time, then a DLL
Reset and NOPs for 200 additional clock cycles before
applying any other command.
Although not a JEDEC requirement, to provide for future
functionality features, CKE must be active (High) during
the AUTO REFRESH period. The AUTO REFRESH period
begins when the AUTO REFRESH command is registered
and ends tRFC later.
SELF REFRESH
The SELF REFRESH command can be used to retain
data in the DDR SDRAM, even if the rest of the system is
powered down. When in the self refresh mode, the DDR
SDRAM retains data without external clocking. The SELF
REFRESH command is initiated like an AUTO REFRESH
command except CKE is disabled (LOW). The DLL is
automatically disabled upon entering SELF REFRESH and
is automatically enabled upon exiting SELF REFRESH (A
DLL reset and 200 clock cycles must then occur before a
READ command can be issued). Input signals except CKE
are “Don’t Care” during SELF REFRESH. VREF voltage is
also required for the full duration of SELF REFRESH.
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W3E232M16S-XSTX
PRELIMINARY*
ABSOLUTE MAXIMUM RATINGS
Parameter
Unit
Voltage on VCC, VCCQ Supply relative to Vss
Voltage on I/O pins relative to Vss
-1 to 3.6
V
-0.5V to VCCQ +0.5V
V
Operating Temperature TA (Mil)
-55 to +125
°C
Operating Temperature TA (Ind)
-40 to +85
°C
Storage Temperature, Plastic
-55 to +125
°C
NOTE:Stress greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the
device at these or any other conditions greater than those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect reliability.
CAPACITANCE (NOTE 13)
Parameter
Symbol
Max
Input Capacitance: CK/CK#
CI1
6
Unit
pF
Addresses, BA0-1 Input Capacitance
CA
8
pF
Input Capacitance: All other input-only pins
CI2
6
pF
Input/Output Capacitance: I/Os
CIO
10
pF
DC ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS (NOTES 1-5, 16)
VCC, VCCQ = +2.5V ± 0.2V; -55°C ≤ TA ≤ +125°C
Parameter/Condition
Symbol
Min
Max
Units
Supply Voltage (36, 41)
VCC
2.3
2.7
V
I/O Supply Voltage (36, 41, 44)
VCCQ
2.3
2.7
V
Supply Voltage 400Mbs (36,40)
VCC
2.5
2.7
V
I/O Supply Voltage 400Mbs (36, 41, 44)
VCCQ
2.5
2.7
V
Input Leakage Current: Any input 0V ≤ VIN ≤ VCC (All other pins not under test = 0V)
II
-4
4
µA
Output Leakage Current: I/Os are disabled; 0V ≤ VOUT ≤ VCCQ
IOZ
-10
10
µA
Output Levels: Full drive option (37, 39)
High Current (VOUT = VCCQ - 0.373V, minimum VREF, minimum VTT)
Low Current (VOUT = 0.373V, maximum VREF, maximum VTT)
IOH
-12
-
mA
IOL
12
-
mA
Output Levels: Reduced drive option (38, 39)
High Current (VOUT = VCCQ - 0.763V, minimum VREF, minimum VTT)
Low Current (VOUT = 0.763V, maximum VREF, maximum VTT)
IOHR
-9
-
mA
IOLR
9
-
mA
I/O Reference Voltage (6,44)
VREF
0.49 x VCCQ
0.51 x VCCQ
V
I/O Termination Voltage (7, 44)
VTT
VREF - 0.04
VREF + 0.04
V
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W3E232M16S-XSTX
PRELIMINARY*
AC INPUT OPERATING CONDITIONS
VCC, VCCQ = +2.5V ± 0.2V; -55°C ≤ TA ≤ +125°C
Parameter/Condition
Symbol
Min
Max
Units
Input High (Logic 1) Voltage
VIH
VREF +0.310
—
V
Input Low (Logic 0) Voltage
VIL
—
VREF -0.310
V
IDD SPECIFICATIONS AND CONDITIONS
-40°C ≤ TA +85°C; VccQ = +2.6 ±0.1V, Vcc = +2.6V ±0.1V Notes: 1-5, 10, 12, 14, 46
Parameter/Condition
Symbol
Max
DDR400
Units
Notes
OPERATING CURRENT: One bank; Active-Precharge;
tRC=tRC (MIN); tCK=tCK (MIN); DQ, DM and DQS inputs changing once per clock cycle;
Address and control inputs changing once every two clock cycles
IDD0
310
mA
22, 47
OPERATING CURRENT: One bank; Active-Read-Precharge;
Burst = 4; tRC=tRC (MIN); tCK=tCK (MIN); IOUT = 0mA; Address and control inputs changing
once per clock cycle
IDD1
370
mA
22, 47
PRECHARGE POWER-DOWN STANDBY CURRENT: All banks idle; Power-down mode;
tCK=tCK (MIN); CKE = (LOW)
IDD2P
10
mA
23, 32, 49
IDLE STANDBY CURRENT: CS# = HIGH; All banks are idle;
tCK=tCK; CKE = HIGH; Address and other control inputs changing once per clock cycle. VIN
= VREF for DQ, DQS, and DM
IDD2F
110
mA
50
ACTIVE POWER-DOWN STANDBY CURRENT: One bank active;
Power-down mode; tCK=tCK (MIN); CKE = (LOW)
IDD3P
90
mA
23, 32, 49
ACTIVE STANDBY CURRENT: CS# = HIGH; CKE = HIGH;
One bank active; Address and control inputs changing once per clock cycle; tCK=tCK (MIN);
IOUT = 0mA
IDD3N
120
mA
22
OPERATING CURRENT: Burst = 2; Writes; Continuous burst;
One bank active; Address and control inputs changing once per clock cycle; tCK=tCK (MIN);
IOUT = 0mA
IDD4R
380
mA
22, 47
OPERATING CURRENT: Burst = 2; Writes; Continuous burst;
One bank active; Address and control inputs changing once per clock cycle; tCK=tCK (MIN)
DQ, DM, and DQS inputs changing twice per clock cycle
IDD4W
380
mA
22
tREFC = tRFC(MIN)
IDD5
690
mA
49
tREFC = 7.8us
IDD5A
22
mA
27, 47
Standard
IDD6
10
mA
11
OPERATING CURRENT: Four bank interleaving READs
(Burst = 4) with auto precharge, tRC = minimum tRC allowed:
tCK=tCK (MIN); Address and control inputs change only during Active READ, or WRITE
commands
IDD7
900
mA
22, 48
AUTO REFRESH BURST CURRENT:
SELF REFRESH CURRENT; CKE ≤0.2V
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W3E232M16S-XSTX
PRELIMINARY*
IDD SPECIFICATIONS AND CONDITIONS
-40°C ≤ TA +85°C; VccQ = +2.6 ±0.1V, Vcc = +2.6V ±0.1V Notes: 1-5, 10, 12, 14, 46
Parameter/Condition
Symbol
Max
DDR333
DDR266
DDR200
Units
Notes
OPERATING CURRENT: One bank; Active-Precharge;
tRC=tRC (MIN); tCK=tCK (MIN); DQ, DM and DQS inputs changing once per clock
cycle; Address and control inputs changing once every two clock cycles
IDD0
260
260
230
mA
22, 47,
53
OPERATING CURRENT: One bank; Active-Read-Precharge;
Burst = 4; tRC=tRC (MIN); tCK=tCK (MIN); IOUT = 0mA; Address and control inputs
changing once per clock cycle
IDD1
320
320
290
mA
22, 47,
53
PRECHARGE POWER-DOWN STANDBY CURRENT: All banks idle; Power-down
mode; tCK=tCK (MIN); CKE = (LOW)
IDD2P
10
10
10
mA
23, 32,
49
IDLE STANDBY CURRENT: CS# = HIGH; All banks are idle;
tCK=tCK; CKE = HIGH; Address and other control inputs changing once per clock
cycle. VIN = VREF for DQ, DQS, and DM
IDD2F
90
90
85
mA
50, 54
ACTIVE POWER-DOWN STANDBY CURRENT: One bank active;
Power-down mode; tCK=tCK (MIN); CKE = (LOW)
IDD3P
70
70
60
mA
23, 32,
49, 54
ACTIVE STANDBY CURRENT: CS# = HIGH; CKE = HIGH;
One bank active; Address and control inputs changing once per clock cycle; tCK=tCK
(MIN); IOUT = 0mA
IDD3N
100
100
90
mA
22, 54
OPERATING CURRENT: Burst = 2; Writes; Continuous burst;
One bank active; Address and control inputs changing once per clock cycle; tCK=tCK
(MIN); IOUT = 0mA
IDD4R
330
330
290
mA
22, 47,
53
OPERATING CURRENT: Burst = 2; Writes; Continuous burst;
One bank active; Address and control inputs changing once per clock cycle; tCK=tCK
(MIN) DQ, DM, and DQS inputs changing twice per clock cycle
IDD4W
350
310
270
mA
22, 53
tREFC = tRFC(MIN)
IDD5
580
580
560
mA
49, 54
tREFC = 7.8us
IDD5A
20
20
20
mA
27, 47,
54
Standard
IDD6
10
10
10
mA
11, 54
IDD7
810
800
700
mA
22, 48,
53
AUTO REFRESH BURST CURRENT:
SELF REFRESH CURRENT; CKE ≤0.2V
OPERATING CURRENT: Four bank interleaving READs
(Burst = 4) with auto precharge, tRC = minimum tRC allowed:
tCK=tCK (MIN); Address and control inputs change only during Active READ, or
WRITE commands
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December 2005
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W3E232M16S-XSTX
PRELIMINARY*
ELECTRICAL CHARACTERISTICS & RECOMMENDED AC OPERATING CONDITIONS DDR400
-40°C ≤ TA ≤ +85°C; VCCQ = +2.5V ±0.2V, VCC = +2.6V ±0.1V Notes: 1-5, 14-17. 33
AC Characteristics
DDR400
Parameter
Unit
Notes
Symbol
Min
Max
Access window of DQs from CK/CK#
tAC
-0.70
+0.70
ns
CK high-level width
tCH
0.45
0.55
tCK
CK low-level width
tCL
0.45
0.55
tCK
30
CL = 3
tCK (3)
5
7.5
ns
51
CL = 2.5
tCK (2.5)
7.5
13
ns
45, 51
CL = 2
tCK (2)
-
-
ns
45, 51
tDH
0.40
ns
26, 51
DQ and DM input setup time relative to DQS
tDS
0.40
ns
26, 51
DQ and DM input pulse width (for each input)
tDIPW
1.75
ns
31
Access window of DQS from CK/CK#
tDQSCK
-0.60
DQS input high pulse width
tDQSH
0.35
DQS input low pulse width
tDQSL
0.35
DQS–DQ skew, DQS to last DQ valid, per group, per access
tDQSQ
WRITE command to first DQS latching transition
tDQSS
0.72
DQS falling edge to CK rising – setup time
tDSS
0.2
tCK
DQS falling edge from CK rising – hold time
tDSH
0.2
tCK
Half clock period
tHP
tCH,tCL
Data-out high-impedance window from CK/CK#
tHZ
Clock cycle time
DQ and DM input hold time relative to DQS
Data-out low-impedance window from CK/CK#
+0.60
30
ns
tCK
tCK
0.40
ns
1.28
tCK
+0.70
25, 26
ns
34
ns
18, 42
tLZ
-0.7
ns
18, 42
Address and control input hold time (slew rate ≤0.5V/ns)
t
IHF
0.60
ns
14
Address and control setup time (slew rate ≤0.5V/ns)
t
ISF
0.60
ns
14
Address and Control input pulse width (for each input)
tIPW
2.2
ns
LOAD MODE REGISTER command cycle time
tMRD
10
ns
DQ–DQS hold, DQS to first DQ to go non-valid, per access
tQH
tHP-tQHS
ns
Data hold skew factor
tQHS
ACTIVE to PRECHARGE command
tRAS
40
ACTIVE to READ with auto precharge command
tRAP
15
ACTIVE to ACTIVE/AUTO REFRESH command period
tRC
55
ns
AUTO REFRESH command period
tRFC
70
ns
ACTIVE to READ or WRITE delay
tRCD
15
ns
0.50
ns
70,000
ns
25, 26
35
ns
49
tRP
15
DQS read preamble
tRPRE
0.9
1.1
tCK
43
DQS read postamble
tRPST
0.4
0.6
tCK
43
ACTIVE bank a to ACTIVE bank b command
tRRD
10
ns
tCK
PRECHARGE command period
DQS write preamble
tWPRE
0.25
DQS write preamble setup time
tWPRES
0
DQS write postamble
tWPST
0.4
tWR
15
Write recovery time
ns
0.6
ns
20, 21
tCK
19
ns
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December 2005
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White Electronic Designs
W3E232M16S-XSTX
PRELIMINARY*
ELECTRICAL CHARACTERISTICS & RECOMMENDED AC OPERATING CONDITIONS DDR400
-40°C ≤ TA ≤ +85°C; VCCQ = +2.5V ±0.2V, VCC = +2.6V ±0.1V Notes: 1-5, 14-17. 33
AC Characteristics
DDR400
Parameter
Symbol
Min
Data valid output window (DVW)
tWTR
2
REFRESH to REFRESH command interval
N/A
Average periodic refresh interval
tREFC
Max
Unit
tCK
tQH - tDQSQ
ns
25
70.3
µs
23
7.8
µs
23
Internal WRITE to READ command delay
tREFI
Terminating voltage delay to VDD
tVTD
Exit SELF REFRESH to non-READ command
tXSNR
70
ns
Exit SELF REFRESH to READ command
tXSRD
200
tCK
0
Notes
ns
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December 2005
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White Electronic Designs
W3E232M16S-XSTX
PRELIMINARY*
ELECTRICAL CHARACTERISTICS & RECOMMENDED AC OPERATING CONDITIONS
-40°C ≤ TA ≤ +85°C; VCCQ = +2.5V ±0.2V, VCC = +2.6V ±0.1V Notes: 1-5, 14-17. 33
AC Characteristics
Parameter
DDR333 CL 2.5
DDR266 CL 2
DDR266 CL 2.5
DDR200 CL 2
Symbol
Min
Max
Min
Max
Unit
Notes
Access window of DQs from CK/CK#
tAC
-0.70
+0.70
-0.70
+0.70
ns
CK high-level width
tCH
0.45
0.55
0.45
0.55
tCK
CK low-level width
tCL
0.45
0.55
0.45
0.55
tCK
30
CL = 2.5
tCK (3)
7.5
13
7.5
13
ns
51
CL = 2
tCK (2.5)
10
13
10
13
tDH
0.45
DQ and DM input setup time relative to DQS
tDS
0.45
DQ and DM input pulse width (for each input)
tDIPW
1.75
Access window of DQS from CK/CK#
tDQSCK
-0.6
DQS input high pulse width
tDQSH
0.35
0.35
DQS input low pulse width
tDQSL
0.35
0.35
DQS–DQ skew, DQS to last DQ valid, per group, per access
tDQSQ
WRITE command to first DQS latching transition
tDQSS
0.75
DQS falling edge to CK rising – setup time
tDSS
0.2
0.2
tCK
DQS falling edge from CK rising – hold time
tDSH
0.2
0.2
tCK
Half clock period
tHP
tCH,tCL
tCH,tCL
Data-out high-impedance window from CK/CK#
tHZ
Clock cycle time
DQ and DM input hold time relative to DQS
ns
45, 51
ns
26, 51
0.5
ns
26, 51
1.75
ns
31
0.5
+0.6
-0.75
0.4
1.25
30
0.75
+0.7
+0.75
ns
tCK
tCK
0.5
ns
1.25
tCK
+0.75
25, 26
ns
34
ns
18, 42
tLZ
-0.7
-0.75
ns
18, 42
Address and control input hold time (fast slew rate)
t
IHF
0.75
0.90
ns
14
Address and control setup time (fast slew rate)
t
0.75
0.90
ns
14
Address and control input hold time (slow slew rate)
t
IHs
0.8
1
Address and control setup time (slow slew rate)
t
ISs
0.8
1
Address and Control input pulse width (for each input)
tIPW
2.2
2.2
ns
LOAD MODE REGISTER command cycle time
tMRD
12
15
ns
DQ–DQS hold, DQS to first DQ to go non-valid, per access
tQH
tHP-tQHS
tHP-tQHS
Data hold skew factor
tQHS
ACTIVE to PRECHARGE command
tRAS
40
ACTIVE to READ with auto precharge command
tRAP
15
20
ns
ACTIVE to ACTIVE/AUTO REFRESH command period
tRC
60
65
ns
AUTO REFRESH command period
tRFC
72
75
ns
ACTIVE to READ or WRITE delay
tRCD
15
20
ns
Data-out low-impedance window from CK/CK#
ISF
0.55
70,000
40
ns
0.75
ns
120,000
ns
35
49
tRP
15
DQS read preamble
tRPRE
0.9
1.1
0.9
1.1
tCK
43
DQS read postamble
tRPST
0.4
0.6
0.4
0.6
tCK
43
ACTIVE bank a to ACTIVE bank b command
tRRD
12
15
ns
DQS write preamble
tWPRE
0.25
0.25
tCK
DQS write preamble setup time
tWPRES
0
0
ns
PRECHARGE command period
20
25, 26
ns
20, 21
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
December 2005
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16
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
White Electronic Designs
W3E232M16S-XSTX
PRELIMINARY*
ELECTRICAL CHARACTERISTICS & RECOMMENDED AC OPERATING CONDITIONS
-40°C ≤ TA ≤ +85°C; VCCQ = +2.5V ±0.2V, VCC = +2.6V ±0.1V Notes: 1-5, 14-17. 33
AC Characteristics
DDR333
Parameter
DQS write postamble
DDR266
Symbol
Min
Max
Min
Max
0.6
0.4
0.6
Unit
tWPST
0.4
Write recovery time
tWR
15
Internal WRITE to READ command delay
tWTR
1
Data valid output window (DVW)
N/A
REFRESH to REFRESH command interval (industrial)
tREFC
70.3
Average periodic refresh interval
tREFI
7.8
Terminating voltage delay to VDD
tVTD
19
Exit SELF REFRESH to non-READ command
tXSNR
75
75
ns
Exit SELF REFRESH to READ command
tXSRD
200
200
tCK
15
1
tQH - tDQSQ
0
Notes
µs
23
70.3
ns
25
7.8
µs
23
tQH - tDQSQ
0
ns
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December 2005
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White Electronic Designs
W3E232M16S-XSTX
PRELIMINARY*
NOTES:
1. All voltages referenced to VSS.
2. Tests for AC timing, ICC, and electrical AC and DC characteristics may be
conducted at nominal reference/supply voltage levels, but the related specifications
and device operation are guaranteed for the full voltage range specified.
3. Outputs measured with equivalent load:
15.
VTT
16.
50Ω
Output
(VOUT)
Reference
Point
30pF
17.
18.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
AC timing and ICC tests may use a VIL-to-VIH swing of up to 1.5V in the test
environment, but input timing is still referenced to VREF (or to the crossing point for
CK/CK#), and parameter specifications are guaranteed for the specified AC input
levels under normal use conditions. The minimum slew rate for the input signals
used to test the device is 1V/ns in the range between VIL(AC) and VIH(AC).
The AC and DC input level specifications are as defined in the SSTL_2 Standard
(i.e., the receiver will effectively switch as a result of the signal crossing the AC
input level, and will remain in that state as long as the signal does not ring back
above [below] the DC input LOW [HIGH] level).
VREF is expected to equal VCCQ/2 of the transmitting device and to track variations
in the DC level of the same. Peak-to-peak noise (noncommon mode) on VREF may
not exceed ±2 percent of the DC value. Thus, from VCCQ/2, VREF is allowed ±25mV
for DC error and an additional ±25mV for AC noise. This measurement is to be
taken at the nearest VREF by-pass capacitor.
VTT is not applied directly to the device. VTT is a system supply for signal
termination resistors, is expected to be set equal to VREF and must track variations
in the DC level of VREF.
VID is the magnitude of the difference between the input level on CK and the input
level on CK#.
The value of VIX and VMP are expected to equal VCCQ/2 of the transmitting device
and must track variations in the DC level of the same.
ICC is dependent on output loading and cycle rates. Specified values are obtained
with minimum cycle time with the outputs open.
Enables on-chip refresh and address counters.
ICC specifications are tested after the device is properly initialized, and is averaged
at the defined cycle rate.
This parameter is not tested but guaranteed by design. tA = 25°C, F= 1 MHz
For slew rates less than 1V/ns and greater than or equal to 0.5 V.ns. If the slew
rate is less than 0.5V/ns, timing must be derated: tIS has an additional 50 ps per
19.
20.
21.
22.
23.
24.
25.
FIGURE A – FULL DRIVE PULL-DOWN
CHARACTERISTICS
each 100mV/ns reduction in slew rate from the 500mV/ns. tIH has 0ps added, that
is, it remains constant. If the slew rate exceeds 4.5V/ns, functionality is uncertain.
The CK/CK# input reference level (for timing referenced to CK/CK#) is the point at
which CK# and CK# cross; the input reference level for signals other than CK/CK#
is VREF.
Inputs are not recognized as valid until VREF stabilizes. Once initialized, including
SELF REFRESH mode, VREF must be powered within specified range. Exception:
during the period before VREF stabilizes, CKE ≤ 0.3 x VCCQ is recognized as LOW.
The output timing reference level, as measured at the timing reference point
indicated in Note 3, is VTT.
tHZ and tLZ transitions occur in the same access time windows as valid data
transitions. These parameters are not referenced to a specific voltage level, but
specify when the device output is no longer driving (HZ) or begins driving (LZ).
The intent of the Don't Care state after completion of the postamble is the DQSdriven signal should either be high, low, or high-Z and that any signal transition
within the input switching region must follow valid input requirements. That is, if
DQS transitions high (above VIHDC(MIN) then it must not transition low (below
VIHDC) prior to tDQSH(MIN).
This is not a device limit. The device will operate with a negative value, but system
performance could be degraded due to bus turnaround.
It is recommended that DQS be valid (HIGH or LOW) on or before the WRITE
command. The case shown (DQS going from High-Z to logic LOW) applies when
no WRITEs were previously in progress on the bus. If a previous WRITE was in
progress, DQS could be HIGH during this time, depending on tDQSS.
MIN (tRC or tRFC) for ICC measurements is the smallest multiple of tCK that meets
the minimum absolute value for the respective parameter. tRAS (MAX) for ICC
measurements is the largest multiple of tCK that meets the maximum absolute
value for tRAS.
The refresh period 64ms. (32ms for Military grade) This equates to an average
refresh rate of 7.8125µs. However, an AUTO REFRESH command must be
asserted at least once every 70.3µs; (35µs for Military grade) burst refreshing or
posting by the DRAM controller greater than eight refresh cycles is not allowed.
The I/O capacitance per DQS and DQ byte/group will not differ by more than this
maximum amount for any given device.
The valid data window is derived by achieving other specifications - tHP (tCK/2),
tDQSQ, and tQH (tQH = tHP - tQHS). The data valid window derates directly porportional
with the clock duty cycle and a practical data valid window can be derived. The
clock is allowed a maximum duty cycle variation of 45/55. Functionality is uncertain
when operating beyond a 45/55 ratio. The data valid window derating curves are
provided below for duty cycles ranging between 50/50 and 45/55. 26.
Referenced to each output group: DQSL with DQ0-DQ7; and DQSH with DQ8-
FIGURE B – FULL DRIVE PULL-UP
CHARACTERISTICS
160
0
Maximum
140
-20
Minimum
-40
120
Nominal low
-60
Nominal high
IOUT (mA)
IOUT (mA)
100
80
Nominal low
60
Minimum
-80
-100
Nominal high
-120
-140
40
-160
20
-180
0
Maximum
-200
0.0
0.5
1.0
1.5
2.0
2.5
0.0
VOUT (V)
0.5
1.0
1.5
2.0
2.5
VCCQ - VOUT (V)
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37. Normal Output Drive Curves:
a) The full variation in driver pull-down current from minimum to maximum
process, temperature and voltage will lie within the outer bounding lines of the
V-I curve of Figure A.
b) The variation in driver pull-down current within nominal limits of voltage and
temperature is expected, but not guaranteed, to lie within the inner bounding
lines of the V-I curve of Figure A.
c) The full variation in driver pull-up current from minimum to maximum process,
temperature and voltage will lie within the outer bounding lines of the V-I curve
of Figure B.
d) The variation in driver pull-up current within nominal limits of voltage and
temperature is expected, but not guaranteed, to lie within the inner bounding
lines of the V-I curve of Figure B.
e) The full variation in the ratio of the maximum to minimum pull-up and pull-down
current should be between .71 and 1.4, for device drain-to-source voltages from
0.1V to 1.0 Volt, and at the same voltage and temperature.
f) The full variation in the ratio of the nominal pull-up to pull-down current should
be unity ±10%, for device drain-to-source voltages from 0.1V to 1.0 Volt.
38. Reduced Output Drive Curves:
a) The full variation in driver pull-down current from minimum to maximum
process, temperature and voltage will lie within the outer bounding lines of the
V-I curve of Figure C.
b) The variation in driver pull-down current within nominal limits of voltage and
temperature is expected, but not guaranteed, to lie within the inner bounding
lines of the V-I curve of Figure C.
c) The full variation in driver pull-up current from minimum to maximum process,
temperature and voltage will lie within the outer bounding lines of the V-I curve
of Figure D.
d) The variation in driver pull-up current within nominal limits of voltage and
temperature is expected, but not guaranteed, to lie within the inner bounding
lines of the V-I curve of Figure D.
e) The full variation in the ratio of the maximum to minimum pull-up and pull-down
current should be between .71 and 1.4, for device drain-to-source voltages from
0.1V to 1.0 V, and at the same voltage and temperature.
f) The full variation in the ratio of the nominal pull-up to pull-down current should
be unity ±10%, for device drain-to-source voltages from 0.1V to 1.0 V.
39. The voltage levels used are derived from a minimum VCC level and the referenced
test load. In practice, the voltage levels obtained from a properly terminated bus
will provide significantly different voltage values.
40. VIH overshoot: VIH(MAX) = VCCQ+1.5V for a pulse width ≤ 3ns and the pulse width
can not be greater than 1/3 of the cycle rate. VIL undershoot: VIL (MIN) = -1.5V for a
pulse width ≤ 3ns and the pulse width cannot be greater than 1/3 of the cycle rate.
41. VCC and VCCQ must track each other.
42. tHZ (MAX) will prevail over tDQSCK (MAX) + tRPST (MAX) condition. tLZ (MIN) will
prevail over tDQSCK (MIN) + tRPRE (MAX) condition.
43. tRPST end point and tRPRE begin point are not referenced to a specific voltage level
but specify when the device output is no longer driving (tRPST), or begins driving
(tRPRE).
44. During initialization, VCCQ, VTT, and VREF must be equal to or less than VCC + 0.3V.
Alternatively, VTT may be 1.35V maximum during power up, even if VCC/VCCQ are 0
volts, provided a minimum of 42 ohms of series resistance is used between the VTT
supply and the input pin.
45. The current part operates below the slowest JEDEC operating frequency of 83 MHz.
As such, future die may not reflect this option.
46. When an input signal is HIGH or LOW, it is defined as a steady state logic HIGH or
LOW.47.Random addressing changing: 50% of data changing at every transfer.
48. Random addressing changing: 100% of data changing at every transfer.
FIGURE C – REDUCED DRIVE PULL-DOWN
CHARACTERISTICS
FIGURE D – REDUCED DRIVE PULL-UP
CHARACTERISTICS
DQ15 of each chip.
27. This limit is actually a nominal value and does not result in a fail value. CKE is
HIGH during REFRESH command period (tRFC [MIN]) else CKE is LOW (i.e., during
standby).
28. To maintain a valid level, the transitioning edge of the input must:
a) Sustain a constant slew rate from the current AC level through to the target AC
level, VIL(AC) or VIH(AC).
b) Reach at least the target AC level.
c) After the AC target level is reached, continue to maintain at least the target DC
level, VIL(DC) or VIH(DC).
29. The Input capacitance per pin group will not differ by more than this maximum
amount for any given device.
30. CK and CK# input slew rate must be ≤ 1V/ns (≤2V/ns differentially).
31. DQ and DM input slew rates must not deviate from DQS by more than 10%. If the
DQ/DM/DQS slew rate is less than 0.5V/ns, timing must be derated: 50ps must be
added to tDS and tDH for each 100mV/ns reduction in slew rate. If slew rate exceeds
4V/ns, functionality is uncertain.
32. VCC must not vary more than 4% if CKE is not active while any bank is active.
33. The clock is allowed up to ±150ps of jitter. Each timing parameter is allowed to vary
by the same amount.
34. tHP min is the lesser of tCL minimum and tCH minimum actually applied to the device
CK and CK# inputs, collectively during bank active.
35. READs and WRITEs with auto precharge are not allowed to be issued until
tRAS(MIN) can be satisfied prior to the internal precharge command being issued.
36. Any positive glitch must be less than 1/3 of the clock and not more than +400mV or
2.9 volts, whichever is less. Any negative glitch must be less than
1/3 of the clock cycle and not exceed either -300mV or 2.2 volts, whichever is more
positive. The average cannot be below the 2.5V minimum.
0
80
Maximum
-10
70
60
Nominal high
40
IOUT (mA)
IOUT (mA)
50
Nominal low
30
-20
Minimum
-30
Nominal low
-40
-50
Minimum
Nominal high
20
-60
10
-70
0
-80
Maximum
0.0
0.5
1.0
1.5
2.0
0.0
2.5
0.5
1.0
1.5
2.0
2.5
VCCQ - VOUT (V)
VOUT (V)
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49. CKE must be active (high) during the entire time a refresh command is executed.
That is, from the time the AUTO REFRESH command is registered, CKE must be
active at each rising clock edge, until tRFC has been satisfied.
50. ICC2N specifies the DQ, DQS, and DQM to be driven to a valid high or low logic
level. ICC2Q is similar to ICC2F except ICC2Q specifies the address and control inputs
to remain stable. Although ICC2F, ICC2N, and ICC2Q are similar, ICC2F is “worst case.”
51. Whenever the operating frequency is altered, not including jitter, the DLL is
required to be reset followed by 200 clock cycles before any READ command.
52. This is the DC voltage supplied at the DRAM and is inclusive of all noise up to 20
MHz. Any noise above 20 MHz at the DRAM generated from any source other than
that of the DRAM itself may not exceed the DC coltage range of 2.6V ± 100mV.
53. One TSOP current mode, one TSOP in precharge power down standby mode
(IDD2P).
54. Both TSOPs in same current mode.
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W3E232M16S-XSTX
PRELIMINARY*
ORDERING INFORMATION
W 3E 232M 16 S - XXX ST X X
WHITE ELECTRONIC DESIGNS CORP.
DDR SDRAM
CONFIGURATION, 2x32M x 16
2.5V Power Supply
DATA RATE (MHz)
200 = DDR200
250 = DDR266
266 = DDR333
400 = DDR400
PACKAGE:
ST = Stacked TSOP
DEVICE GRADE:
I = Industrial
C = Commercial
-40°C to +85°C
0°C to +70°C
RoHS Compliance
Blank = Not RoHS compliant
G = RoHS compliant
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W3E232M16S-XSTX
PRELIMINARY*
Document Title
64Mx16bit DDR SDRAM
Revision History
Rev #
History
Release Date
Rev 0
Initial Release
February 2005
Advanced
Change (All pages)
December 2005
Preliminary
Rev 1
1.1 Add AC and DC electrical data
1.2 Add Product description and functionality
1.3 Add revision page
1.4 Change status to Preliminary
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
December 2005
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