Revised February 2005
74AC20
Dual 4-Input NAND Gate
General Description
Features
The AC20 contains four 4-input NAND gates.
■ ICC reduced by 50%
■ Outputs source/sink 24 mA
Ordering Code:
Order Number
Package
Package Description
Number
74AC20SC
M14A
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
74AC20SJ
M14D
Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74AC20MTC
MTC14
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74AC20MTC_NL
(Note 1)
MTC14
Pb-Free 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm
Wide
74AC20PC
N14A
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Pb-Free package per JEDEC J-STD-020B.
Note 1: “_NL” indicates Pb-Free package (per JEDEC J-STD-020B).
Logic Symbol
Connection Diagram
IEEE/IEC
Pin Descriptions
Pin Names
Description
An, Bn, Cn, Dn
Inputs
On
Outputs
FACT¥ is a trademark of Fairchild Semiconductor Corporation.
© 2005 Fairchild Semiconductor Corporation
DS009918
www.fairchildsemi.com
74AC20 Dual 4-Input NAND Gate
November 1988
74AC20
Absolute Maximum Ratings(Note 2)
Supply Voltage (VCC)
Recommended Operating
Conditions
0.5V to 7.0V
DC Input Diode Current (IIK)
VI
VI
0.5V
VCC 0.5V
DC Input Voltage (VI)
Supply Voltage (VCC)
20 mA
20 mA
0.5V to VCC 0.5V
VO
0.5V
VCC 0.5V
DC Output Voltage (VO)
0V to VCC
Output Voltage (VO)
0V to VCC
40qC to 85qC
Operating Temperature (TA)
Minimum Input Edge Rate ('V/'t)
DC Output Diode Current (IOK)
VO
2.0V to 6.0V
Input Voltage (VI)
20 mA
20 mA
0.5V to VCC 0.5V
125 mV/ns
VIN from 30% to 70% of VCC
VCC @ 3.3V, 4.5V, 5.5V
DC Output Source
r 50 mA
or Sink Current (IO)
DC VCC or Ground Current
per Output Pin (ICC or IGND)
Storage Temperature (TSTG)
r 50 mA
65qC to 150qC
Note 2: Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power
supply, temperature, and output/input loading variables. Fairchild does not
recommend operation of FACT¥ circuits outside databook specifications.
Junction Temperature (TJ)
140qC
PDIP
DC Electrical Characteristics
Symbol
Parameter
VCC
TA
(V)
VIH
VIL
VOH
VOL
25qC
Typ
TA
40qC to 85qC
Minimum HIGH Level
3.0
1.5
2.1
2.1
Input Voltage
4.5
2.25
3.15
3.15
5.5
2.75
3.85
3.85
Maximum LOW Level
3.0
1.5
0.9
0.9
Input Voltage
4.5
2.25
1.35
1.35
5.5
2.75
1.65
1.65
Minimum HIGH Level
3.0
2.99
2.9
2.9
Output Voltage
4.5
4.49
4.4
4.4
5.5
5.49
5.4
5.4
3.0
2.56
2.46
4.5
3.86
3.76
5.5
4.86
4.76
0.1
0.1
Maximum LOW Level
Output Voltage
3.0
Units
Conditions
Guaranteed Limits
0.002
VOUT
V
VOUT
or VCC 0.1V
V
IOUT
50 PA
V
4.5
0.001
0.1
0.1
0.001
0.1
0.1
V
3.0
0.36
0.44
4.5
0.36
0.44
5.5
0.36
0.44
5.5
r 0.1
r 1.0
PA
V
VIN
VIL or VIH
IOH
12 mA
IOH
24 mA
IOH
24 mA (Note 3)
50 PA
IOUT
VIN
VIL or VIH
IOL
12 mA
IOL
24 mA
IOL
VI
24 mA (Note 3)
IIN
Maximum Input
(Note 5)
Leakage Current
IOLD
Minimum Dynamic
5.5
75
mA
VOLD
IOHD
Output Current (Note 4)
5.5
75
mA
VOHD
ICC
Maximum Quiescent
5.5
20.0
PA
VIN
(Note 5)
Supply Current
VCC, GND
1.65V Max
3.85V Min
VCC
or GND
Note 3: All outputs loaded; thresholds on input associated with output under test.
Note 4: Maximum test duration 2.0 ms, one output loaded at a time.
Note 5: IIN and ICC @ 3.0V are guaranteed to be less than or equal to the respective limit @ 5.5V VCC.
www.fairchildsemi.com
0.1V
V
5.5
2.0
0.1V
or VCC 0.1V
2
Symbol
tPLH
Parameter
Propagation Delay
Propagation Delay
tPHL
VCC
TA
25qC
(V)
CL
50 pF
TA
40qC to 85qC
CL
50 pF
(Note 6)
Min
Typ
Max
Min
Max
3.3
2.0
6.0
8.5
1.5
10.0
5.0
1.5
5.0
7.0
1.0
8.0
3.3
1.5
5.0
7.0
1.0
9.0
5.0
1.5
4.0
6.0
1.0
7.0
Units
ns
ns
Note 6: Voltage Range 3.3 is 3.3V r 0.3V
Voltage Range 5.0 is 5.0V r 0.5V
Capacitance
Typ
Units
CIN
Symbol
Input Capacitance
Parameter
4.5
pF
VCC
OPEN
CPD
Power Dissipation Capacitance
40.0
pF
VCC
5.0V
3
Conditions
www.fairchildsemi.com
74AC20
AC Electrical Characteristics
74AC20
Physical Dimensions inches (millimeters) unless otherwise noted
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
Package Number M14A
www.fairchildsemi.com
4
74AC20
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M14D
5
www.fairchildsemi.com
74AC20
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Package Number MTC14
www.fairchildsemi.com
6
74AC20 Dual 4-Input NAND Gate
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Package Number N14A
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
2. A critical component in any component of a life support
device or system whose failure to perform can be reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the
user.
www.fairchildsemi.com
7
www.fairchildsemi.com