Revised November 1999 74AC86 Quad 2-Input Exclusive-OR Gate General Description Features The AC86 contains four, 2-input exclusive-OR gates. ■ ICC reduced by 50% ■ Outputs source/sink 24 mA Ordering Code: Order Number 74AC86SC 74AC86SJ 74AC86MTC 74AC86PC Package Number Package Description M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow Body M14D 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide MTC14 N14A 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Connection Diagram Logic Symbol IEEE/IEC Pin Descriptions Pin Names Description A0–A3 Inputs B0–B3 Inputs O0–O3 Outputs FACT is a trademark of Fairchild Semiconductor Corporation. © 1999 Fairchild Semiconductor Corporation DS009909 www.fairchildsemi.com 74AC86 Quad 2-Input Exclusive-OR Gate September 1988 74AC86 Absolute Maximum Ratings(Note 1) Supply Voltage (VCC) Recommended Operating Conditions −0.5V to +7.0V DC Input Diode Current (IIK) VI = 0.5V −20 mA VI = V CC +0.5V +20 mA DC Input Voltage (VI) Supply Voltage (VCC) 0V to VCC Output Voltage (VO) −0.5V to VCC +0.5V 0V to VCC −40°C to +85°C Operating Temperature (TA) DC Output Diode Current (IOK) Minimum Input Edge Rate (∆V/∆t) VO = −0.5V −20 mA VO = VCC +0.5V 125 mV/ns VIN from 30% to 70% of VCC +20 mA DC Output Voltage (VO) 2.0V to 6.0V Input Voltage (VI) VCC @ 3.3V, 4.5V, 5.5V −0.5V to VCC +0.5V ± 50 mA DC Output Source or Sink Current (IO) DC VCC or Ground Current ± 50 mA Per Output Pin (ICC or IGND) Storage Temperature (TSTG) −65°C to +150°C Note 1: Absolute maximum ratings are those values beyond which damage to the device may occur. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. Fairchild does not recommend operation of FACT circuits outside databook specifications. Junction Temperature (TJ) PDIP 140°C DC Electrical Characteristics Symbol VIH VIL VOH Parameter VCC (V) TA = −40°C to +85°C TA = 25°C Typ Guaranteed Limits Minimum HIGH Level 3.0 1.5 2.1 2.1 Input Voltage 4.5 2.25 3.15 3.15 5.5 2.75 3.85 3.85 Maximum LOW Level 3.0 1.5 0.9 0.9 Input Voltage 4.5 2.25 1.35 1.35 5.5 2.75 1.65 1.65 Minimum HIGH Level 3.0 2.99 2.9 2.9 Output Voltage 4.5 4.49 4.4 4.4 5.5 5.49 5.4 5.4 3.0 2.56 2.46 4.5 3.86 3.76 5.5 4.86 4.76 0.1 Units Conditions VOUT = 0.1V V or VCC − 0.1V VOUT = 0.1V V or VCC − 0.1V V IOUT = −50 µA VIN = VIL or VIH VOL Maximum LOW Level 3.0 0.002 0.1 Output Voltage 4.5 0.001 0.1 0.1 5.5 0.001 0.1 0.1 3.0 0.36 0.44 4.5 0.36 0.44 IOH = −12 mA V IOH = −24 mA IOH = −24 mA (Note 2) V IOUT = 50 µA VIN = VIL or VIH IOL = 12 mA V IOL = 24 mA 5.5 0.36 0.44 IIN (Note 4) Maximum Input Leakage Current 5.5 ±0.1 ±1.0 µA VI = VCC, GND IOLD Minimum Dynamic 5.5 75 mA VOLD = 1.65V Max IOHD Output Current (Note 3) 5.5 −75 mA ICC Maximum Quiescent (Note 4) Supply Current 5.5 2.0 20.0 Note 2: All outputs loaded; thresholds on input associated with output under test. Note 3: Maximum test duration 20 ms, one output loaded at a time. Note 4: IIN and ICC @ 3.0V are guaranteed to be less than or equal to the respective limit @ 5.5V VCC. www.fairchildsemi.com 2 IOL = 24 mA (Note 2) µA VOHD = 3.85V Min VIN = VCC or GND Symbol tPHL tPLH Parameter VCC TA = +25°C (V) CL = 50 pF (Note 5) Min Propagation Delay 3.3 Inputs to Outputs 5.0 Propagation Delay Inputs to Outputs TA = −40°C to +85°C CL 40 pF Typ Max 2.0 6.0 1.5 4.5 3.3 2.0 6.5 5.0 1.5 4.5 Units Min Max 11.5 1.5 12.5 8.5 1.0 9.5 11.5 1.5 12.5 8.5 1.0 9.0 ns ns Note 5: Voltage Range 3.3V is 3.3V ± 0.3V Voltage Range 5.0V is 5.0V ± 0.5V Capacitance Typ Units CIN Symbol Input Capacitance Parameter 4.5 pF VCC = OPEN CPD Power Dissipation Capacitance 35 pF VCC = 5.0V 3 Conditions www.fairchildsemi.com 74AC86 AC Electrical Characteristics 74AC86 Physical Dimensions inches (millimeters) unless otherwise noted 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow Body Package Number M14A www.fairchildsemi.com 4 74AC86 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M14D 5 www.fairchildsemi.com 74AC86 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC14 www.fairchildsemi.com 6 74AC86 Quad 2-Input Exclusive-OR Gate Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide Package Number N14A Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com 7 www.fairchildsemi.com