CYPRESS W164

W164
Spread Spectrum Desktop/Notebook System
Frequency Generator
Features
Key Specifications
• Maximized EMI suppression using Cypress’s Spread
Spectrum technology
• Reduces measured EMI by as much as 10 dB
• I2C programmable to 153 MHz (16 selectable
frequencies)
• Two skew-controlled copies of CPU output
• SEL100/66# selects CPU frequency (100 or 66.8 MHz)
• Seven copies of PCI output (synchronous w/CPU
output)
• One copy of 14.31818-MHz IOAPIC output
• One copy of 48-MHz USB output
• Selectable 24-/48-MHz output is determined by resistor
straps on power-up
• One high-drive output buffer that produces a copy of
the 14.318-MHz reference
• Isolated core VDD pin for noise reduction
Supply Voltages:....................................... VDDQ3 = 3.3V±5%
VDDQ2 = 2.5V±5%
CPU Cycle to Cycle Jitter: ...........................................200 ps
CPU, PCI Output Edge Rate:......................................... ≥1 V/ns
CPU0:1 Output Skew: ................................................175 ps
PCI_F, PCI1:6 Output Skew: .......................................500 ps
CPU to PCI Skew: .............................. 1 to 4 ns (CPU Leads)
REF2X/SEL48#, SCLOCK, SDATA................ 250-kΩ pull-up
Note: Internal pull-up resistors should not be relied upon for
setting I/O pins HIGH.
Table 1. Pin Selectable Frequency
Block Diagram
CPU(0:1)
PCI
1
100 MHz
33.3 MHz
0
66.8 MHz
33.4 MHz
Pin Configuration
VDDQ3
REF2X/SEL48#
GND
X1
X2
SEL100/66#
XTAL
OSC
VDDQ3
IOAPIC
PLL Ref Freq
VDDQ2
CPU0
X1
X2
GND
PCI_F
PCI1
PCI2
PCI3
PCI4
VDDQ3
PCI5
PCI6
VDDQ3
48MHz
24/48MHz
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
GND
REF2X/SEL48#
VDDQ3
VDDQ2
IOAPIC
VDDQ2
CPU0
CPU1
VDDQ3
GND
SDATA
SCLOCK
SEL100/66#
GND
CPU1
GND
100/66#_SEL
PLL 1
÷2/÷3/÷4
VDDQ3
PCI_F
PCI1
PCI2
PCI3
PCI4
SDATA
SCLOCK
PCI5
2
I C
LOGIC
PCI6
GND
VDDQ3
48MHz
PLL2
24/48MHz
GND
Cypress Semiconductor Corporation
Document #: 38-07169 Rev. *A
•
3901 North First Street
•
San Jose
•
CA 95134 • 408-943-2600
Revised December 15, 2002
W164
Pin Definitions
Pin
No.
Pin
Type
CPU0:1
22, 21
O
CPU Clock Outputs 0 through 1: These two CPU clocks run at a frequency set by
SEL100/66#. Output voltage swing is set by the voltage applied to VDDQ2.
PCI1:6
PCI_F
5, 6, 7, 8, 10,
11, 4
O
PCI Clock Outputs 1 through 6 and PCI_F: These seven PCI clock outputs run
synchronously to the CPU clock. Voltage swing is set by the power connection to
VDDQ3.
IOAPIC
24
O
I/O APIC Clock Output: Provides 14.318-MHz fixed frequency. The output voltage
swing is set by the power connection to VDDQ2.
48MHz
13
O
48-MHz Output: Fixed 48-MHz USB clock. Output voltage swing is controlled by
voltage applied to VDDQ3.
24/48MHz
14
O
24-MHz or 48-MHz Output: Frequency is set by the state of pin 27 on power-up.
REF2X/SEL48#
27
I/O
I/O Dual-Function REF2X and SEL48# pin: Upon power-up, the state of SEL48#
is latched. The initial state is set by either a 10K resistor to GND or to VDD. A 10K
resistor to GND causes pin 14 to output 48 MHz. If the pin is strapped to VDD, pin
14 will output 24 MHz. After 2 ms, the pin becomes a high-drive output that produces
a copy of 14.318 MHz.
SEL100/66#
16
I
Frequency Selection Input: Selects CPU clock frequency as shown in Table 1 on
page 1.
SDATA
18
I/O
I2C Data Pin: Data should be presented to this input as described in the I2C section
of this data sheet. Internal 250-kΩ pull-up resistor.
SCLOCK
17
I
I2C Clock Pin: The I2C data clock should be presented to this input as described in
the I2C section of this data sheet.
X1
1
I
Crystal Connection or External Reference Frequency Input: Connect to either
a 14.318-MHz crystal or other reference signal.
X2
2
I
Crystal Connection: An input connection for an external 14.318-MHz crystal. If
using an external reference, this pin must be left unconnected.
VDDQ3
9, 12, 20, 26
P
Power Connection: Power supply for core logic and PLL circuitry, PCI, 48-/24-MHz,
and Reference output buffers. Connect to 3.3V supply.
VDDQ2
23, 25
P
Power Connection: Power supply for IOAPIC and CPU output buffers. Connect to
2.5V supply.
3, 15, 19, 28
G
Ground Connections: Connect all ground pins to the common system ground
plane.
Pin Name
GND
Pin Description
Functional Description
I/O Pin Operation
Pin 27 is a dual-purpose l/O pin. Upon power-up this pin acts
as a logic input, allowing the determination of assigned device
functions. A short time after power-up, the logic state of the pin
is latched and the pin becomes a clock output. This feature
reduces device pin count by combining clock outputs with input select pins.
An external 10-kΩ “strapping” resistor is connected between
the l/O pin and ground or VDD. Connection to ground sets a
latch to “0,” connection to VDD sets a latch to “1.” Figure 1 and
Figure 2 show two suggested methods for strapping resistor
connections.
Upon W164 power-up, the first 2 ms of operation is used for
input logic selection. During this period, the Reference clock
output buffer is three-stated, allowing the output strapping resistor on the l/O pin to pull the pin and its associated capacitive
clock load to either a logic HIGH or LOW state. At the end of
the 2-ms period, the established logic “0” or “1” condition of the
Document #: 38-07169 Rev. *A
l/O pin is then latched. Next the output buffer is enabled which
converts the l/O pin into an operating clock output. The 2-ms
timer is started when VDD reaches 2.0V. The input bit can only
be reset by turning VDD off and then back on again.
It should be noted that the strapping resistor has no significant
effect on clock output signal integrity. The drive impedance of
clock output is 25Ω (nominal) which is minimally affected by
the 10-kΩ strap to ground or VDD. As with the series termination resistor, the output strapping resistor should be placed as
close to the l/O pin as possible in order to keep the interconnecting trace short. The trace from the resistor to ground or
VDD should be kept less than two inches in length to prevent
system noise coupling during input logic sampling.
When the clock output is enabled following the 2-ms input period, a 14.318-MHz output frequency is delivered on the pin,
assuming that VDD has stabilized. If VDD has not yet reached
full value, output frequency initially may be below target but will
increase to target once VDD voltage has stabilized. In either
case, a short output clock cycle may be produced from the
CPU clock outputs when the outputs are enabled.
Page 2 of 12
W164
VDD
Output Strapping Resistor
Series Termination Resistor
10 kΩ
(Load Option 1)
Clock Load
W164
Output
Buffer
Power-on
Reset
Timer
Hold
Output
Low
Output Three-state
Q
10 kΩ
(Load Option 0)
D
Data
Latch
Figure 1. Input Logic Selection Through Resistor Load Option
Jumper Options
Output Strapping Resistor
VDD
Series Termination Resistor
10 kΩ
W164
R
Output
Buffer
Power-on
Reset
Timer
Q
Resistor Value R
Hold
Output
Low
Output Three-state
Clock Load
D
Data
Latch
Figure 2. Input Logic Selection Through Jumper Option
Serial Data Interface
The W164 features a two-pin, serial data interface that can be
used to configure internal register settings that control particular device functions. Upon power-up, the W164 initializes
with default register settings. Therefore, the use of this serial
data interface is optional. The serial interface is write-only (to
the clock chip) and is the dedicated function of device pins
SDATA and SCLOCK. In motherboard applications, SDATA
and SCLOCK are typically driven by two logic outputs of the
chipset. Clock device register changes are normally made
upon system initialization, if required. The interface can also
be used during system operation for power management functions. Table 2 summarizes the control functions of the serial
data interface.
Operation
Data is written to the W164 in ten bytes of eight bits each.
Bytes are written in the order shown in Table 3.
Table 2. Serial Data Interface Control Functions Summary
Control Function
Description
Common Application
Clock Output Disable
Any individual clock output(s) can be disabled. Dis- Unused outputs are disabled to reduce EMI
abled outputs are actively held LOW.
and system power. Examples are clock outputs to unused PCI slots.
CPU Clock Frequency
Selection
Provides CPU/PCI frequency selections beyond the
100- and 66.6-MHz selections that are provided by
the SEL100/66# pin. Frequency is changed in a
smooth and controlled fashion.
For alternate microprocessors and power
management options. Smooth frequency transition allows CPU frequency change under
normal system operation.
Output Three-state
Puts all clock outputs into a high-impedance state. Production PCB testing.
Test Mode
All clock outputs toggle in relation to X1 input, inter- Production PCB testing.
nal PLL is bypassed. Refer to Table 4.
(Reserved)
Reserved function for future device revision or pro- No user application. Register bit must be writduction device testing.
ten as 0.
Document #: 38-07169 Rev. *A
Page 3 of 12
W164
Table 3. Byte Writing Sequence
Byte
Sequence
Byte Name
1
Slave Address
11010010
Commands the W164 to accept the bits in Data Bytes 3–6 for internal
register configuration. Since other devices may exist on the same common serial data bus, it is necessary to have a specific slave address for
each potential receiver. The slave receiver address for the W164 is
11010010. Register setting will not be made if the Slave Address is not
correct (or is for an alternate slave receiver).
2
Command
Code
Don’t Care
Unused by the W164, therefore bit values are ignored (“don’t care”). This
byte must be included in the data write sequence to maintain proper byte
allocation. The Command Code Byte is part of the standard serial communication protocol and may be used when writing to another addressed
slave receiver on the serial data bus.
3
Byte Count
Don’t Care
Unused by the W164, therefore bit values are ignored (“don’t care”). This
byte must be included in the data write sequence to maintain proper byte
allocation. The Byte Count Byte is part of the standard serial communication protocol and may be used when writing to another addressed slave
receiver on the serial data bus.
Don’t Care
Refer to Cypress SDRAM drivers.
Refer to Table 4
The data bits in these bytes set internal W164 registers that control device
operation. The data bits are only accepted when the Address Byte bit
sequence is 11010010, as noted above. For description of bit control
functions, refer to Table 4, Data Byte Serial Configuration Map.
4
Data Byte 0
5
Data Byte 1
6
Data Byte 2
7
Data Byte 3
8
Data Byte 4
9
Data Byte 5
10
Data Byte 6
Document #: 38-07169 Rev. *A
Bit Sequence
Byte Description
Page 4 of 12
W164
Writing Data Bytes
Each bit in the data bytes controls a particular device function
except for the “reserved” bits, which must be written as a logic
0. Bits are written MSB (most significant bit) first, which is bit
7. Table 4 gives the bit formats for registers located in Data
Bytes 3–6.
Table 5 details additional frequency selections that are available through the serial data interface.
Table 6 details the select functions for Byte 3, bits 1 and 0.
Table 4. Data Bytes 3–6 Serial Configuration Map
Affected Pin
Bit(s)
Pin No.
Pin Name
Data Byte 3
7
--6
--5
--4
--3
---
2
1–0
Data Byte 4
7
6
5
4
3
2
1
0
Data Byte 5
7
6
5
4
3
2
1
0
Data Byte 6
7
6
5
4
3
2
1
0
Bit Control
Control Function
SEL_3
SEL_2
SEL_1
SEL_0
Frequency Table
Selection
(Reserved)
Bit 1 Bit 0
0
0
0
1
1
0
1
1
0
1
--
-Refer to Table 5
Refer to Table 5
Refer to Table 5
Frequency Controlled Frequency Controlled
by external SEL100/
by BYT3 SEL_(3:0)
66# pin Table 1
Table 5
--Function (See Table 6 for function details)
Normal Operation
Test Mode
Spread Spectrum on
All Outputs Three-stated
Default
0
0
0
0
0
---
---
0
00
-14
---21
-22
-24/48MHz
---CPU1
-CPU0
(Reserved)
Clock output Disable
(Reserved)
(Reserved)
(Reserved)
Clock Output Disable
(Reserved)
Clock Output Disable
-Low
---Low
-Low
-Active
---Active
-Active
0
1
0
0
0
1
0
1
4
11
10
8
7
6
5
PCI_F
PCI6
PCI5
-PCI4
PCI3
PCI2
PCI1
Clock Output Disable
Clock Output Disable
Clock Output Disable
(Reserved)
Clock Output Disable
Clock Output Disable
Clock Output Disable
Clock Output Disable
Low
Low
Low
-Low
Low
Low
Low
Active
Active
Active
-Active
Active
Active
Active
1
1
1
0
1
1
1
1
--24
---27
27
--IOAPIC
---REF2X
REF2X
(Reserved)
(Reserved)
Clock Output Disable
(Reserved)
(Reserved)
(Reserved)
Clock Output Disable
Clock Output Disable
--Low
---Low
Low
--Active
---Active
Active
0
0
1
0
0
0
1[1]
1[1]
Note:
1. Both Bits 0 and 1 of Byte 6 in Table 4 must be programmed as the same value.
Document #: 38-07169 Rev. *A
Page 5 of 12
W164
Table 5. Additional Frequency Selections through Serial Data Interface Data Bytes
Input Conditions
Output Frequency
If Spread Is On
Data Byte 3, Bit 3 = 1
Bit 7
SEL_3
Bit 6
SEL_2
Bit 5
SEL_1
Bit 4
SEL_0
CPU, SDRAM
Clocks (MHz)
PCI Clocks
(MHz)
Spread Percentage
0
0
0
0
68.5
34.25
±0.5% Center
0
0
0
1
75
37.5
±0.5% Center
0
0
1
0
83.3
41.6
±0.5% Center
0
0
1
1
66.8
33.4
±0.5% Center
0
1
0
0
103
34.25
±0.5% Center
0
1
0
1
112
37.3
±0.5% Center
0
1
1
0
133.3
33.3
±0.5% Center
0
1
1
1
100
33.3
±0.5% Center
1
0
0
0
117
39.0
±0.5% Center
1
0
0
1
117
29.25
±0.5% Center
1
0
1
0
124
31.0
±0.5% Center
1
0
1
1
129
32.25
±0.5% Center
1
1
0
0
138
34.5
±0.5% Center
1
1
0
1
143
35.75
±0.5% Center
1
1
1
0
148
37.0
±0.5% Center
1
1
1
1
153
38.25
±0.5% Center
Table 6. Select Function for Data Byte 3, Bits 0:1
Input Conditions
Output Conditions
Data Byte 3
Bit 1
Bit 0
CPU0:1
PCI_F, PCI1:6
REF2X,
IOAPIC
48MHZ
24MHZ
Normal Operation
0
0
Note 2
Note 2
14.318 MHz
48 MHz
24 MHz
Test Mode
0
1
X1/2
CPU/2, 3, or 4
X1
X1/2
X1/4
Spread Spectrum
1
0
±0.5%
±0.5%
14.318 MHz
48 MHz
24 MHz
Three-state
1
1
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Function
Note:
2. CPU and PCI frequency selections are listed in Table 1 and Table 5.
Document #: 38-07169 Rev. *A
Page 6 of 12
W164
Absolute Maximum Ratings[3]
Stresses greater than those listed in this table may cause permanent damage to the device. These represent a stress rating
only. Operation of the device at these or any other conditions
Parameter
above those specified in the operating sections of this specification is not implied. Maximum conditions for extended periods may affect reliability.
Description
Rating
Unit
V
VDD, VIN
Voltage on any pin with respect to GND
–0.5 to +7.0
–65 to +150
°C
0 to +70
°C
–55 to +125
°C
2 (min.)
kV
TSTG
Storage Temperature
TA
Operating Temperature
TB
Ambient Temperature under Bias
ESDPROT
Input ESD Protection
DC Electrical Characteristics: TA = 0°C to +70°C, VDDQ3 = 3.3V±5%, VDDQ2 = 2.5V±5%
Parameter
Description
Test Condition
Min.
Typ.
Max.
Unit
Supply Current
IDDQ3
Combined 3.3V Supply Current
CPU0:1 =100 MHz
Outputs Loaded[4]
85
mA
IDDQ3
Combined 2.5V Supply Current
CPU0:1 =100 MHz
Outputs Loaded[4]
30
mA
Logic Inputs
VIL
Input Low Voltage
GND –
0.3
0.8
V
VIH
Input High Voltage
2.0
VDD +
0.3
V
IIL
Input Low Current[5]
–25
µA
IIH
Input High Current[5]
10
µA
IIL
Input Low Current (SEL100/66#)
–5
µA
IIH
Input High Current (SEL100/66#)
5
µA
50
mV
Clock Outputs
VOL
Output Low Voltage
IOL = 1 mA
VOH
Output High Voltage
IOH = –1 mA
3.1
V
VOH
Output High Voltage
CPU0:1/IOAPIC
IOH = –1 mA
2.2
V
IOL
Output Low Current
IOH
Output High Current
CPU0:1
VOL = 1.25V
50
70
100
mA
PCI_F, PCI1:6
VOL = 1.5V
60
80
120
mA
IOAPIC
VOL = 1.25V
40
85
140
mA
REF2X
VOL = 1.5V
100
130
152
mA
48MHz, 24MHz
VOL = 1.5V
40
50
76
mA
CPU0:1
VOH = 1.25V
50
70
100
mA
PCI_F, PCI1:6
VOH = 1.5V
60
70
120
mA
IOAPIC
VOH = 1.25V
40
87
155
mA
REF2X
VOH = 1.5V
100
130
150
mA
48MHz, 24MHz
VOH = 1.5V
40
50
94
mA
Notes:
3. Multiple Supplies: The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required.
4. All clock outputs loaded with maximum lump capacitance test load specified in the AC Electrical Characteristics section.
5. W164 logic inputs have internal pull-up resistors, except SEL100/66# (pull-ups not full CMOS level).
Document #: 38-07169 Rev. *A
Page 7 of 12
W164
DC Electrical Characteristics: TA = 0°C to +70°C, VDDQ3 = 3.3V±5%, VDDQ2 = 2.5V±5% (continued)
Parameter
Description
Test Condition
Min.
Typ.
Max.
Unit
Crystal Oscillator
VTH
X1 Input Threshold Voltage[6]
CLOAD
Load Capacitance, as seen by
External Crystal[7]
CIN,X1
X1 Input Capacitance[8]
VDDQ3 = 3.3V
1.65
V
13
pF
26
pF
Pin X2 unconnected
Pin Capacitance/Inductance
CIN
Input Pin Capacitance
Except X1 and X2
COUT
Output Pin Capacitance
LIN
Input Pin Inductance
pF
pF
7
nH
AC Electrical Characteristics
TA = 0°C to +70°C, VDDQ3 = 3.3V±5%,VDDQ2 = 2.5V± 5%, fXTL = 14.31818 MHz
AC clock parameters are tested and guaranteed over stated operating conditions using the stated lump capacitive load at the
clock output; Spread Spectrum clocking is disabled.
CPU Clock Outputs, CPU0:1 (Lump Capacitance Test Load = 20 pF)
CPU = 66.8 MHz
Parameter
Description
Test Condition/Comments
CPU = 100 MHz
Min. Typ. Max. Min.
15.5
Typ. Max. Unit
tP
Period
Measured on rising edge at 1.25V
15
tH
High Time
Duration of clock cycle above 2.0V
5.2
3.0
ns
tL
Low Time
Duration of clock cycle below 0.4V
5.0
2.8
ns
tR
Output Rise Edge Rate Measured from 0.4V to 2.0V
1
4
1
4
V/ns
tF
Output Fall Edge Rate
Measured from 2.0V to 0.4V
1
4
1
4
V/ns
tD
Duty Cycle
Measured on rising and falling edge at
1.25V
45
55
45
55
%
tJC
Jitter, Cycle-to-Cycle
Measured on rising edge at 1.25V. Maximum difference of cycle time between
two adjacent cycles.
200
250
ps
tSK
Output Skew
Measured on rising edge at 1.25V
175
175
ps
fST
Frequency Stabilization from Power-up
(cold start)
Assumes full supply voltage reached
within 1 ms from power-up. Short cycles
exist prior to frequency stabilization.
3
3
ms
Zo
AC Output Impedance
Average value during switching transition. Used for determining series termination value.
20
10
10.5
20
ns
Ω
Notes:
6. X1 input threshold voltage (typical) is VDD/2.
7. The W164 contains an internal crystal load capacitor between pin X1 and ground and another between pin X2 and ground. Total load placed on crystal is 14 pF;
this includes typical stray capacitance of short PCB traces to crystal.
8. X1 input capacitance is applicable when driving X1 with an external clock source (X2 is left unconnected).
Document #: 38-07169 Rev. *A
Page 8 of 12
W164
PCI Clock Outputs, PCI1:6 and PCI_F (Lump Capacitance Test Load = 30 pF
CPU = 66.8/100 MHz
Parameter
Description
Test Condition/Comments
Min.
Typ.
Max.
Unit
tP
Period
Measured on rising edge at 1.5V
30
ns
tH
High Time
Duration of clock cycle above 2.4V
12
ns
tL
Low Time
Duration of clock cycle below 0.4V
12
ns
tR
Output Rise Edge Rate
Measured from 0.4V to 2.4V
1
4
V/ns
tF
Output Fall Edge Rate
Measured from 2.4V to 0.4V
1
4
V/ns
tD
Duty Cycle
Measured on rising and falling edge at 1.5V
45
55
%
tJC
Jitter, Cycle-to-Cycle
Measured on rising edge at 1.5V. Maximum
difference of cycle time between two adjacent cycles.
250
ps
tSK
Output Skew
Measured on rising edge at 1.5V
500
ps
tO
CPU to PCI Clock Skew
Covers all CPU/PCI outputs. Measured on rising
edge at 1.5V. CPU leads PCI output.
4
ns
fST
Frequency Stabilization
from Power-up (cold
start)
Assumes full supply voltage reached within 1 ms
from power-up. Short cycles exist prior to frequency
stabilization.
3
ms
Zo
AC Output Impedance
Average value during switching transition. Used for
determining series termination value.
1
Ω
20
IOAPIC Clock Output (Lump Capacitance Test Load = 20 pF)
CPU = 66.8/100 MHz
Parameter
Description
Test Condition/Comments
Min.
Typ.
Max.
14.31818
Unit
f
Frequency, Actual
Frequency generated by crystal oscillator
MHz
tR
Output Rise Edge Rate
Measured from 0.4V to 2.0V
1
4
V/ns
tF
Output Fall Edge Rate
Measured from 2.0V to 0.4V
1
4
V/ns
tD
Duty Cycle
Measured on rising and falling edge at 1.25V
45
fST
Frequency Stabilization
from Power-up (cold start)
Assumes full supply voltage reached within
1 ms from power-up. Short cycles exist prior to
frequency stabilization.
Zo
AC Output Impedance
Average value during switching transition. Used
for determining series termination value.
55
%
1.5
ms
Ω
15
REF2X Clock Output (Lump Capacitance Test Load = 20 pF)
CPU = 66.8/100 MHz
Parameter
Description
Test Condition/Comments
Min.
Typ.
Max.
Frequency, Actual
Frequency generated by crystal oscillator
tR
Output Rise Edge Rate
Measured from 0.4V to 2.4V
0.5
2
V/ns
tF
Output Fall Edge Rate
Measured from 2.4V to 0.4V
0.5
2
V/ns
tD
Duty Cycle
Measured on rising and falling edge at 1.5V
45
55
%
fST
Frequency Stabilization from
Power-up (cold start)
Assumes full supply voltage reached within
1 ms from power-up. Short cycles exist prior to
frequency stabilization.
3
ms
Zo
AC Output Impedance
Average value during switching transition. Used
for determining series termination value.
Document #: 38-07169 Rev. *A
14.318
Unit
f
15
MHz
Ω
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W164
48-MHz and 24-MHz Clock Output (Lump Capacitance Test Load = 20 pF)
CPU = 66.8/100 MHz
Parameter
Description
Test Condition/Comments
Min.
Typ.
Max.
Unit
f
Frequency, Actual
Determined by PLL divider ratio (see m/n below)
48.008
24.004
MHz
fD
Deviation from 48 MHz
(48.008 – 48)/48
+167
ppm
m/n
PLL Ratio
(14.31818 MHz x 57/17 = 48.008 MHz)
tR
Output Rise Edge Rate
Measured from 0.4V to 2.4V
0.5
2
V/ns
tF
Output Fall Edge Rate
Measured from 2.4V to 0.4V
0.5
2
V/ns
tD
Duty Cycle
Measured on rising and falling edge at 1.5V
45
55
%
fST
Frequency Stabilization
from Power-up (cold start)
Assumes full supply voltage reached within 1 ms
from power-up. Short cycles exist prior to frequency stabilization.
3
ms
Zo
AC Output Impedance
Average value during switching transition. Used
for determining series termination value.
57/17, 57/34
25
Ω
Ordering Information
Ordering Code
Package
Name
W164
Document #: 38-07169 Rev. *A
G
Package Type
28-pin SOIC (300 mils)
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W164
Package Diagram
28-Pin Small Outline Integrated Circuit (SOIC, 300 mils)
Document #: 38-07169 Rev. *A
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© Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
W164
Document Title: W164 Spread Spectrum Desktop/Notebook System Frequency Generator
Document Number: 38-07169
REV.
ECN NO.
Issue
Date
Orig. of
Change
Description of Change
**
110279
11/05/01
SZV
Change from Spec number: 38-00841 to 38-07169
*A
122810
12/15/02
RBI
Add Power up Requirements to Operating Conditions Information
Document #: 38-07169 Rev. *A
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