W210 Spread Spectrum FTG for VIA K7 Chipset Features • Maximized EMI Suppression using Cypress’s Spread Spectrum technology • Single-chip system frequency synthesizer for VIA K7 chipset • One pair of differential CPU outputs for K7 Processor • One open-drain CPU output for VIA K7 chipset • Six copies of PCI output • One 48-MHz output for USB • One 24-MHz or 48-MHz output for SIO • Two buffered reference outputs • Thirteen SDRAM outputs provide support for 3 DIMMs • Supports frequencies up to 200 MHz • I2C™ interface for programming • Power management control inputs • Available in 48-pin SSOP Key Specifications CPU to CPU Output Skew: ......................................... 175 ps PCI to PCI Output Skew: ............................................ 500 ps VDDQ3: .................................................................... 3.3V±5% Table 1. Mode Input Table Mode Pin 2 0 1 CPU_STOP# REF0 Table 2. Pin Selectable Frequency Input Address CPU FS3 FS2 FS1 FS0 (MHz) 1 1 1 1 133.3 1 1 1 0 75 1 1 0 1 100.2 1 1 0 0 66.8 1 0 1 1 79 1 0 1 0 110 1 0 0 1 115 1 0 0 0 120 0 1 1 1 133.3 0 1 1 0 83.3 0 1 0 1 100.2 0 1 0 0 66.8 0 0 1 1 124 0 0 1 0 129 0 0 0 1 138 0 0 0 0 143 Block Diagram Pin Configuration PCI0:5 (MHz) 33.3 37.5 33.3 33.4 39.5 36.7 38.3 30 33.3 27.7 33.3 33.4 31.0 32.3 34.5 35.8 Spread Spectrum ±0.5% ±0.5% ±0.5% ±0.5% OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF [1] VDDQ3 REF0/(CPU_STOP#) X1 X2 PLL Ref Freq I/O Pin Control PWRDWN# CPUT_CS Stop Clock Control PLL 1 ÷2,3,4 CPUT0 CPUC0 VDDQ3 PCI0/MODE PCI1/FS1 PCI2 PCI3 PCI4 SDATA SCLK I2C Logic { PCI5 VDDQ3 48MHz/FS2 PLL2 ÷2 SDRAMIN 13 24_48MHz/FS3 VDDQ3 SDRAM0:12 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 W210 VDDQ3 REF0/(CPU_STOP#) GND X1 X2 VDDQ3 PCI0/MODE PCI1/FS1* GND PCI2 PCI3 PCI4 PCI5 VDDQ3 SDRAMIN GND SDRAM11 SDRAM10 VDDQ3 SDRAM9 SDRAM8 GND 2 SDATA I C SCLK REF1/FS0 XTAL OSC 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 REF1/FS0* GND CPUT_CS GND CPUC0 CPUT0 VDDQ3 PWRDWN#* SDRAM12 GND SDRAM0 SDRAM1 VDDQ3 SDRAM2 SDRAM3 GND SDRAM4 SDRAM5 VDDQ3 SDRAM6 SDRAM7 VDDQ3 48MHz/FS2* 24_48MHz/FS3^ Note: 1. Internal pull-up resistors should not be relied upon for setting I/O pins HIGH. Pin function with parentheses determined by MODE pin resistor strapping. Unlike other I/O pins, input FS3 has an internal pull-down resistor. I2C is a trademark of Philips Corporation. Cypress Semiconductor Corporation • Powered by ICminer.com Electronic-Library Service CopyRight 2003 3901 North First Street • San Jose • CA 95134 • 408-943-2600 April 11, 2000, rev. *C W210 Pin Definitions Pin Name Pin No. Pin Type Pin Description 43, 44, 46 O (opendrain) CPU Clock Output 0: CPUT0 and CPUC0 are the differential CPU clock outputs for the K7 processor. CPUT_CS is the open-drain clock output for the chipset. It has the same phase relationship as CPUT0. 10, 11, 12, 13 O PCI Clock Outputs 2 through 5: These four PCI clock outputs are controlled by the PWRDWN# control pin. Frequency is set by FS0:3 inputs or through serial input interface, see Tables 2 and 6 for details. Output voltage swing is controlled by voltage applied to VDDQ3. PCI1/FS1 8 I/O Fixed PCI Clock Output/Frequency Select 1: As an output, frequency is set by FS0:3 inputs or through serial input interface. This output is controlled by the PWRDWN# input. This pin also serves as a power-on strap option to determine device operating frequency as described in Table 2. PCI0/MODE 7 I/O Fixed PCI Clock Output/Mode: As an output, frequency is set by the FS0:3 inputs or through serial input interface, see Tables 2 and 6. This output is controlled by the PWRDWN# input. This pin also serves as a power-on strap option to determine the function of pin 2, see Table 1 for details. PWRDWN# 41 I PWRDWN# Input: LVTTL-compatible input that places the device in power-down mode when held LOW. In power-down mode,CPUC0 will be three-stated and all the other output clocks will be driven LOW. 48MHz/FS2 26 I/O 48-MHz Output/Frequency Select 2: 48 MHz is provided in normal operation. In standard PC systems, this output can be used as the reference for the Universal Serial Bus host controller. This pin also serves as a power-on strap option to determine device operating frequency as described in Table 2. 24_48MHz/ FS3 25 I/O 24_48-MHz Output/Frequency Select 3: In standard PC systems, this output can be used as the clock input for a Super I/O chip. The output frequency is controlled by Configuration Byte 3 bit[6]. The default output frequency is 24 MHz. This pin also serves as a power-on strap option to determine device operating frequency as described in Table 2. REF1/FS0 48 I/O Reference Clock Output 1/Frequency Select 2: 3.3V 14.318-MHz output clock. This pin also serves as a power-on strap option to determine device operating frequency as described in Table 2. Upon power-up, FS0 input will be latched, which will set clock frequencies as described in Table 2. REF0/ CPU_STOP# 2 I/O Reference Clock Output 0 or CPU_STOP# Input Pin: Function is determined by the MODE pin. When CPU_STOP# input is asserted LOW, it will drive CPUT0 and CPUT_CS to logic 0, and it will three-state CPUC0. When this pin is configured as an output, this pin becomes a 3.3V 14.318-MHz output clock. SDRAMIN 15 I Buffered Input Pin: The signal provided to this input pin is buffered to 13 outputs (SDRAM0:12). 38, 37, 35, 34, 32, 31, 29, 28, 21, 20, 18, 17, 40 O Buffered Outputs: These thirteen dedicated outputs provide copies of the signal provided at the SDRAMIN input. The swing is set by VDDQ3, and they are deactivated when PWRDWN# input is set LOW. SCLK 24 I Clock pin for I2C circuitry. SDATA 23 I/O Data pin for I2C circuitry. X1 4 I Crystal Connection or External Reference Frequency Input: This pin has dual functions. It can be used as an external 14.318-MHz crystal connection or as an external reference frequency input. X2 5 I Crystal Connection: An input connection for an external 14.318-MHz crystal. If using an external reference, this pin must be left unconnected. VDDQ3 1, 6, 14, 19, 27, 30, 36, 42 P Power Connection: Power supply for core logic, PLL circuitry, SDRAM outputs, PCI outputs, reference outputs, 48-MHz output, and 24_48-MHz output. Connect to 3.3V supply. GND 3, 9, 16, 22, 33, 39, 45, 47 G Ground Connections: Connect all ground pins to the common system ground plane. CPUT0, CPUC0, CPUT_CS PCI2:5 SDRAM0:12 Powered by ICminer.com Electronic-Library Service CopyRight 2003 2 W210 Upon W210 power-up, the first 2 ms of operation is used for input logic selection. During this period, the five I/O pins (7, 8, 25, 26, 48) are three-stated, allowing the output strapping resistor on the l/O pins to pull the pins and their associated capacitive clock load to either a logic HIGH or LOW state. At the end of the 2-ms period, the established logic “0” or “1” condition of the l/O pin is latched. Next the output buffer is enabled converting the l/O pins into operating clock outputs. The 2-ms timer starts when VDD reaches 2.0V. The input bits can only be reset by turning VDD off and then back on again. Overview The W210 was developed as a single-chip device to meet the clocking needs of VIA K7 core logic chip sets. In addition to the typical outputs provided by a standard FTG, the W210 adds a thirteenth output buffer, supporting SDRAM DIMM modules in conjunction with the chipset. Cypress’s proprietary spread spectrum frequency synthesis technique is a feature of the CPU and PCI outputs. When enabled, this feature reduces the peak EMI measurements of not only the output signals and their harmonics, but also of any other clock signals that are properly synchronized to them. It should be noted that the strapping resistors have no significant effect on clock output signal integrity. The drive impedance of clock outputs is <40Ω (nominal), which is minimally affected by the 10-kΩ strap to ground or VDD. As with the series termination resistor, the output strapping resistor should be placed as close to the l/O pin as possible in order to keep the interconnecting trace short. The trace from the resistor to ground or VDD should be kept less than two inches in length to prevent system noise coupling during input logic sampling. Functional Description I/O Pin Operation Pins 7, 8, 25, 26, and 48 are dual-purpose l/O pins. Upon power-up these pins act as logic inputs, allowing the determination of assigned device functions. A short time after powerup, the logic state of each pin is latched and the pins become clock outputs. This feature reduces device pin count by combining clock outputs with input select pins. When the clock outputs are enabled following the 2-ms input period, the specified output frequency is delivered on the pin, assuming that VDD has stabilized. If VDD has not yet reached full value, output frequency initially may be below target but will increase to target once VDD voltage has stabilized. In either case, a short output clock cycle may be produced from the CPU clock outputs when the outputs are enabled. An external 10-kΩ “strapping” resistor is connected between the l/O pin and ground or VDD. Connection to ground sets a latch to “0,” connection to VDD sets a latch to “1.” Figure 1 and Figure 2 show two suggested methods for strapping resistor connections. VDD Output Strapping Resistor Series Termination Resistor 10 kΩ (Load Option 1) W210 Power-on Reset Timer Hold Output Low Output Three-state Q Clock Load R Output Buffer 10 kΩ (Load Option 0) D Data Latch Figure 1. Input Logic Selection Through Resistor Load Option Jumper Options Output Strapping Resistor VDD Series Termination Resistor 10 kΩ W210 R Output Buffer Power-on Reset Timer Q Resistor Value R Hold Output Low Output Three-state D Data Latch Figure 2. Input Logic Selection Through Jumper Option Powered by ICminer.com Electronic-Library Service CopyRight 2003 3 Clock Load W210 Spread Spectrum Frequency Timing Generator Where P is the percentage of deviation and F is the frequency in MHz where the reduction is measured. The device generates a clock that is frequency modulated in order to increase the bandwidth that it occupies. By increasing the bandwidth of the fundamental and its harmonics, the amplitudes of the radiated electromagnetic emissions are reduced. This effect is depicted in Figure 3. The output clock is modulated with a waveform depicted in Figure 4. This waveform, as discussed in “Spread Spectrum Clock Generation for the Reduction of Radiated Emissions” by Bush, Fessler, and Hardin produces the maximum reduction in the amplitude of radiated electromagnetic emissions. The deviation selected for this chip is specified in Table 6. Figure 4 details the Cypress spreading pattern. Cypress does offer options with more spread and greater EMI reduction. Contact your local Sales representative for details on these devices. As shown in Figure 3, a harmonic of a modulated clock has a much lower amplitude than that of an unmodulated signal. The reduction in amplitude is dependent on the harmonic number and the frequency deviation or spread. The equation for the reduction is: Spread Spectrum clocking is activated or deactivated by selecting the appropriate values for bits 1–0 in data byte 0 of the I2C data stream. Refer to Table 6 for more details. dB = 6.5 + 9*log10(P) + 9*log10(F) 5 dB /div Typical Clo ck Amplitude (dB) SSFT G Freq uency S pan (M Hz) -S S% +SS % Figure 3. Clock Harmonic with and without SSCG Modulation Frequency Domain Representation MIN (–0.5%) Figure 4. Typical Modulation Profile Powered by ICminer.com Electronic-Library Service CopyRight 2003 4 100% 90% 80% 70% 60% 50% 40% 30% 20% 10% 100% 90% 80% 70% 60% 50% 40% 30% 20% 10% FREQUENCY MAX (0%) W210 chipset. Clock device register changes are normally made upon system initialization, if any are required. The interface can also be used during system operation for power management functions. Table 3 summarizes the control functions of the serial data interface. Serial Data Interface The W210 features a two-pin, serial data interface that can be used to configure internal register settings that control particular device functions. Upon power-up, the W210 initializes with default register settings, therefore the use of this serial data interface is optional. The serial interface is write-only (to the clock chip) and is the dedicated function of device pins SDATA and SCLOCK. In motherboard applications, SDATA and SCLOCK are typically driven by two logic outputs of the Operation Data is written to the W210 in eleven bytes of eight bits each. Bytes are written in the order shown in Table 4. Table 3. Serial Data Interface Control Functions Summary Control Function Description Common Application Clock Output Disable Any individual clock output(s) can be disabled. Dis- Unused outputs are disabled to reduce EMI abled outputs are actively held LOW. and system power. Examples are clock outputs to unused PCI slots. CPU Clock Frequency Selection Provides CPU/PCI frequency selections through software. Frequency is changed in a smooth and controlled fashion. For alternate microprocessors and power management options. Smooth frequency transition allows CPU frequency change under normal system operation. Spread Spectrum Enabling Enables or disables spread spectrum clocking. For EMI reduction. Output Three-state Puts clock output into a high impedance state. Production PCB testing. (Reserved) Reserved function for future device revision or pro- No user application. Register bit must be writduction device testing. ten as 0. Table 4. Byte Writing Sequence Byte Sequence Byte Name 1 Slave Address 11010010 Bit Sequence Commands the W210 to accept the bits in Data Bytes 0–6 for internal register configuration. Since other devices may exist on the same common serial data bus, it is necessary to have a specific slave address for each potential receiver. The slave receiver address for the W210 is 11010010. Register setting will not be made if the Slave Address is not correct (or is for an alternate slave receiver). 2 Command Code Don’t Care Unused by the W210, therefore bit values are ignored (“Don’t Care”). This byte must be included in the data write sequence to maintain proper byte allocation. The Command Code Byte is part of the standard serial communication protocol and may be used when writing to another addressed slave receiver on the serial data bus. 3 Byte Count Don’t Care Unused by the W210, therefore bit values are ignored (“Don’t Care”). This byte must be included in the data write sequence to maintain proper byte allocation. The Byte Count Byte is part of the standard serial communication protocol and may be used when writing to another addressed slave receiver on the serial data bus. 4 Data Byte 0 Refer to Table 5 5 Data Byte 1 6 Data Byte 2 The data bits in Data Bytes 0–7 set internal W210 registers that control device operation. The data bits are only accepted when the Address Byte bit sequence is 11010010, as noted above. For description of bit control functions, refer to Table 5, Data Byte Serial Configuration Map. 7 Data Byte 3 8 Data Byte 4 9 Data Byte 5 10 Data Byte 6 11 Data Byte 7 Powered by ICminer.com Electronic-Library Service CopyRight 2003 Byte Description 5 W210 Writing Data Bytes 7. Table 5 gives the bit formats for registers located in Data Bytes 0–7. Each bit in the data bytes controls a particular device function except for the “reserved” bits, which must be written as a logic 0. Bits are written MSB (most significant bit) first, which is bit Table 6 details additional frequency selections that are available through the serial data interface. Table 5. Data Bytes 0–7 Serial Configuration Map Affected Pin Bit(s) Pin No. Bit Control Pin Name Control Function 0 1 Default -- -- 0 Data Byte 0 7 -- -- (Reserved) 6 -- -- SEL_2 See Table 6 0 5 -- -- SEL_1 See Table 6 0 4 -- -- SEL_0 3 -- -- Hardware/Software Frequency Select See Table 6 Hardware 0 Software 0 2 -- -- SEL_4 See Table 6 1 1 -- -- SEL_3 See Table 6 0 0 -- -- (Reserved) Normal Three-stated 0 7 -- -- (Reserved) -- -- 0 6 -- -- (Reserved) -- -- 0 5 -- -- (Reserved) -- -- 0 4 -- -- (Reserved) -- -- 0 3 -- -- (Reserved) Write to ‘1’ -- -- 1 2 -- -- (Reserved) Write to ‘1’ -- -- 1 1 -- -- (Reserved) Write to ‘1’ -- -- 1 -- (Reserved) Write to ‘1’ -- -- 1 (Reserved) -- -- 0 Low Active 1 -- -- 0 Data Byte 1 0 Data Byte 2 7 -- -- 6 7 PCI0 5 -- -- 4 13 PCI5 Clock Output Disable Low Active 1 3 12 PCI4 Clock Output Disable Low Active 1 2 11 PCI3 Clock Output Disable Low Active 1 1 10 PCI2 Clock Output Disable Low Active 1 0 8 PCI1 Clock Output Disable Low Active 1 7 -- -- -- -- 0 6 -- 24 MHz 48 MHz 0 5 26 48MHz Clock Output Disable Low Active 1 4 25 24_48MHz Clock Output Disable Low Active 1 Clock Output Disable (Reserved) Data Byte 3 3 -- 2 21, 20, 18, 17 (Reserved) SEL_48MHz SEL_48MHz as the output frequency for 24_48MHz -- (Reserved) SDRAM8:11 Clock Output Disable Powered by ICminer.com Electronic-Library Service CopyRight 2003 6 -- -- 0 Low Active 1 W210 Table 5. Data Bytes 0–7 Serial Configuration Map (continued) Affected Pin Bit(s) Pin No. Pin Name 1 32, 31, 29, 28 SDRAM4:7 0 38, 37, 35, 34 SDRAM0:3 Bit Control Control Function 0 1 Default Clock Output Disable Low Active 1 Clock Output Disable Low Active 1 Data Byte 4 7 -- -- (Reserved) -- -- 0 6 -- -- (Reserved) -- -- 0 5 -- -- (Reserved) -- -- 0 4 -- -- (Reserved) -- -- 0 3 -- -- (Reserved) -- -- 0 2 -- -- (Reserved) -- -- 0 1 -- -- (Reserved) -- -- 0 0 -- -- (Reserved) -- -- 0 7 -- -- (Reserved) -- -- 0 6 -- -- (Reserved) -- -- 0 5 -- -- (Reserved) -- -- 0 4 -- -- (Reserved) -- -- 1 3 -- -- (Reserved) -- -- 0 (Reserved) Data Byte 5 2 -- -- -- -- 0 1 48 REF1 Clock Output Disable Low Active 1 0 2 REF0 Clock Output Disable Low Active 1 7 -- -- (Reserved) -- -- 0 6 -- -- (Reserved) -- -- 0 5 -- -- (Reserved) -- -- 0 4 -- -- (Reserved) -- -- 0 3 -- -- (Reserved) -- -- 0 2 -- -- (Reserved) -- -- 0 1 -- -- (Reserved) -- -- 0 0 -- -- (Reserved) -- -- 0 7 -- -- (Reserved) -- -- 0 6 -- -- (Reserved) -- -- 0 5 -- -- (Reserved) -- -- 0 4 -- -- (Reserved) -- -- 0 3 -- -- (Reserved) -- -- 0 2 -- -- (Reserved) -- -- 0 1 -- -- (Reserved) -- -- 0 0 -- -- (Reserved) -- -- 0 Data Byte 6 Data Byte 7 Powered by ICminer.com Electronic-Library Service CopyRight 2003 7 W210 Table 6. Additional Frequency Selections through Serial Data Interface Data Bytes Input Conditions Output Frequency Data Byte 0, Bit 3 = 1 Bit 2 SEL_4 Bit 1 SEL_3 Bit 6 SEL_2 Bit 5 SEL_1 Bit 4 SEL_0 CPU PCI Spread Spectrum 1 1 1 1 1 133.3 33.3 ±0.5% 1 1 1 1 0 75 37.5 ±0.5% 1 1 1 0 1 100.2 33.3 ±0.5% 1 1 1 0 0 66.8 33.4 ±0.5% 1 1 0 1 1 79 39.5 OFF 1 1 0 1 0 110 36.7 OFF 1 1 0 0 1 115 38.3 OFF 1 1 0 0 0 120 30 OFF 1 0 1 1 1 133.3 33.3 OFF 1 0 1 1 0 83.3 27.7 OFF 1 0 1 0 1 100.2 33.3 OFF 1 0 1 0 0 66.8 33.4 OFF 1 0 0 1 1 124 31.0 OFF 1 0 0 1 0 129 32.3 OFF 1 0 0 0 1 138 34.5 OFF 1 0 0 0 0 143 35.8 OFF 0 1 1 1 1 85 28.3 OFF 0 1 1 1 0 87.5 29.2 OFF 0 1 1 0 1 90 30 OFF 0 1 1 0 0 92.5 30.8 OFF 0 1 0 1 1 95 31.7 OFF 0 1 0 1 0 147 36.8 OFF 0 1 0 0 1 152 30.4 OFF 0 1 0 0 0 154 30.8 OFF 0 0 1 1 1 157 31.4 OFF 0 0 1 1 0 159 31.8 OFF 0 0 1 0 1 162 32.4 OFF 0 0 1 0 0 166 33.2 OFF 0 0 0 1 1 171 34.2 OFF 0 0 0 1 0 180 36 OFF 0 0 0 0 1 190 38 OFF 0 0 0 0 0 200 40 OFF Powered by ICminer.com Electronic-Library Service CopyRight 2003 8 W210 Absolute Maximum Ratings above those specified in the operating sections of this specification is not implied. Maximum conditions for extended periods may affect reliability. Stresses greater than those listed in this table may cause permanent damage to the device. These represent a stress rating only. Operation of the device at these or any other conditions . Parameter Description Rating Unit VDD, VIN Voltage on any pin with respect to GND –0.5 to +7.0 V TSTG Storage Temperature –65 to +150 °C TB Ambient Temperature under Bias –55 to +125 °C TA Operating Temperature 0 to +70 °C ESDPROT Input ESD Protection 2 (min.) kV DC Electrical Characteristics: TA = 0°C to +70°C, VDDQ3 = 3.3V±5% Parameter Description Test Condition Min. Typ. Max. Unit Supply Current IDD 3.3V Supply Current CPUT0, CPUC0, CPU_CS =100 MHz Outputs Loaded[2] 260 mA IDD 2.5V Supply Current CPUT0, CPUC0, CPU_CS =100 MHz Outputs Loaded[2] 25 mA Logic Inputs VIL Input Low Voltage GND – 0.3 0.8 2.0 V VIH Input High Voltage VDD + 0.3 V IIL Input Low Current[3] –25 µA IIH Input High Current[3] 10 µA 50 mV Clock Outputs VOL Output Low Voltage IOL = 1 mA VOH Output High Voltage IOH = –1 mA VOL Output Low Voltage CPUT_CS, CPUT0, CPUC0 Termination to V pull-up (external) 0 0.3 V VOH Output High Voltage CPUT_CS, CPUT0, CPUC0 Termination to V pull-up (external) 1.0 1.2 V IOL Output Low Current IOH Output High Current 3.1 V PCI0:5 VOL = 1.5V 70 110 135 mA REF0:1 VOL = 1.5V 50 70 100 mA 48 MHz VOL = 1.5V 50 70 100 mA 24 MHz VOL = 1.5V 50 70 100 mA SDRAM0:12 VOL = 1.5V 70 110 135 mA PCI0:5 VOH = 1.5V 70 110 135 mA REF0:1 VOH = 1.5V 50 70 100 mA 48 MHz VOH = 1.5V 50 70 100 mA 24 MHz VOH = 1.5V 50 70 100 mA SDRAM0:12 VOH = 1.5V 70 110 135 mA Notes: 2. All clock outputs loaded with 6" 60Ω transmission lines with 22-pF capacitors. 3. W210 logic inputs (except FS3) have internal pull-up devices (pull-ups not full CMOS level). Logic input FS3 has an internal pull-down device. Powered by ICminer.com Electronic-Library Service CopyRight 2003 9 W210 DC Electrical Characteristics: TA = 0°C to +70°C, VDDQ3 = 3.3V±5% (continued) Parameter Description Test Condition Min. Typ. Max. Unit Crystal Oscillator VTH X1 Input Threshold Voltage[4] CLOAD Load Capacitance, Imposed on External Crystal[5] CIN,X1 X1 Input Capacitance[6] VDDQ3 = 3.3V Pin X2 unconnected 1.65 V 14 pF 28 pF Pin Capacitance/Inductance CIN Input Pin Capacitance COUT Output Pin Capacitance 6 pF LIN Input Pin Inductance 7 nH Except X1 and X2 5 pF AC Electrical Characteristics TA = 0°C to +70°C, VDDQ3 = 3.3V±5% AC clock parameters are tested and guaranteed over stated operating conditions using the stated lump capacitive load at the clock output; Spread Spectrum is disabled. CPU Clock Outputs (CPUT0, CPUC0, CPUT_CS)[7] CPU = 100 MHz Parameter Description Test Condition/Comments Min. Typ. Max. CPU = 133 MHz Min. Typ. Max. Unit tR Output Rise Edge Rate 1.0 1.0 V/ns tF Output Fall Edge Rate 1.0 1.0 V/ns tD Duty Cycle 50 50 % tJC Jitter, Cycle to Cycle fST Frequency Stabilization from Power-up (cold start) Assumes full supply voltage reached within 1 ms from power-up. Short cycles exist prior to frequency stabilization. Zo AC Output Impedance VO = VX Measured at 50% point 250 250 3 50 ps 3 50 ms Ω Notes: 4. X1 input threshold voltage (typical) is VDD/2. 5. The W210 contains an internal crystal load capacitor between pin X1 and ground and another between pin X2 and ground. Total load placed on crystal is 14 pF; this includes typical stray capacitance of short PCB traces to crystal. 6. X1 input capacitance is applicable when driving X1 with an external clock source (X2 is left unconnected). 7. Refer to Figure 5 for K7 operation clock driver test circuit. Powered by ICminer.com Electronic-Library Service CopyRight 2003 10 W210 PCI Clock Outputs, PCI0:5 (Lump Capacitance Test Load = 30 pF Parameter Description Test Condition/Comments Min. Typ. Max. Unit tP Period Measured on rising edge at 1.5V 30 ns tH High Time Duration of clock cycle above 2.4V 12 ns tL Low Time Duration of clock cycle below 0.4V 12 ns tR Output Rise Edge Rate Measured from 0.4V to 2.4V 1 tF Output Fall Edge Rate Measured from 2.4V to 0.4V tD Duty Cycle Measured on rising and falling edge at 1.5V tJC Jitter, Cycle-to-Cycle tSK 4 V/ns 1 4 V/ns 45 55 % Measured on rising edge at 1.5V. Maximum difference of cycle time between two adjacent cycles. 250 ps Output Skew Measured on rising edge at 1.5V 500 ps tO CPU to PCI Clock Skew Covers all CPU/PCI outputs. Measured on rising edge at 1.5V. CPU leads PCI output. 4 ns fST Frequency Stabilization from Power-up (cold start) Assumes full supply voltage reached within 1 ms from power-up. Short cycles exist prior to frequency stabilization. 3 ms Zo AC Output Impedance Average value during switching transition. Used for determining series termination value. 1.5 Ω 30 REF0:1 Clock Outputs (Lump Capacitance Test Load = 20 pF) Parameter Description Test Condition/Comments Min. Typ. Max. 14.318 Unit f Frequency, Actual Frequency generated by crystal oscillator MHz tR Output Rise Edge Rate Measured from 0.4V to 2.4V 0.5 2 V/ns tF Output Fall Edge Rate Measured from 2.4V to 0.4V 0.5 2 V/ns tD Duty Cycle Measured on rising and falling edge at 1.5V 45 55 % fST Frequency Stabilization from Power-up (cold start) Assumes full supply voltage reached within 1 ms from power-up. Short cycles exist prior to frequency stabilization. 3 ms Zo AC Output Impedance Average value during switching transition. Used for determining series termination value. Ω 40 48-MHz Clock Output (Lump Capacitance Test Load = 20 pF) Parameter Description Test Condition/Comments Min. Typ. Max. Unit f Frequency, Actual Determined by PLL divider ratio (see m/n below) fD Deviation from 48 MHz (48.008 – 48)/48 m/n PLL Ratio (14.31818 MHz x 57/17 = 48.008 MHz) tR Output Rise Edge Rate Measured from 0.4V to 2.4V 0.5 2 V/ns tF Output Fall Edge Rate Measured from 2.4V to 0.4V 0.5 2 V/ns tD Duty Cycle Measured on rising and falling edge at 1.5V 45 55 % fST Frequency Stabilization from Power-up (cold start) Assumes full supply voltage reached within 1 ms from power-up. Short cycles exist prior to frequency stabilization. 3 ms Zo AC Output Impedance Average value during switching transition. Used for determining series termination value. Powered by ICminer.com Electronic-Library Service CopyRight 2003 11 48.008 MHz +167 ppm 57/17 40 Ω W210 24-MHz Clock Output (Lump Capacitance Test Load = 20 pF) Parameter Description Test Condition/Comments Min. Typ. Max. Unit f Frequency, Actual Determined by PLL divider ratio (see m/n below) fD Deviation from 24 MHz (24.004 – 24)/24 m/n PLL Ratio (14.31818 MHz x 57/34 = 24.004 MHz) tR Output Rise Edge Rate Measured from 0.4V to 2.4V 0.5 2 V/ns tF Output Fall Edge Rate Measured from 2.4V to 0.4V 0.5 2 V/ns tD Duty Cycle Measured on rising and falling edge at 1.5V 45 55 % fST Frequency Stabilization from Power-up (cold start) Assumes full supply voltage reached within 1 ms from power-up. Short cycles exist prior to frequency stabilization. 3 ms Zo AC Output Impedance Average value during switching transition. Used for determining series termination value. Z0 = 52Ω Length = 3 ” T2 R8 CPUCLK_T 47 20p Cl ip p 1.5V Clock Chip CPU Driver R3 68 Z0 = 52Ω Length = 3 ” T5 R9 CPUCLK_C 47 20p Figure 5. K7 Open Drain Clock Driver Test Circuit Ordering Information Ordering Code W210 Package Name H Package Type 48-pin SSOP (300 mils) Document #: 38-00846-C Powered by ICminer.com Electronic-Library Service CopyRight 2003 12 +167 ppm 40 R1 68 Z0 = 52Ω Length = 5” T4 MHz 57/34 1.5V Z0 = 52Ω Length = 5” T1 24.004 Ω W210 Layout Diagram +3.3V Supply FB VDDQ3 C4 0.005 µF 10 µF G G C3 µ VDDQ3 1 VCore G 2 3 G 4 5 G 6 V 7 G 8 9 G 10 11 12 13 G 14 V 15 G 16 17 18 G 19 V 20 G 21 22 G 23 24 G C1 G C2 G G W 210 G G 48 47 46 G 45 44 G 43 V 42 G 41 40 G 39 38 37 V 36 G 35 34 G 33 32 G 31 V 30 G 29 28 27 26 G 25 G G G G VDDQ3 5Ω C5 G G C6 FB = Dale ILB1206 - 300 (300Ω @ 100 MHz) C1 & C3 = 10–22 µF C2 & C4 = 0.005 µF C5 = 47 µF G = VIA to GND plane layer C6 = 0.1 µF V =VIA to respective supply plane layer Note: Each supply plane or strip should have a ferrite bead and capacitors. Powered by ICminer.com Electronic-Library Service CopyRight 2003 13 W210 Package Diagram 48-Pin Small Shrink Outline Package (SSOP, 300 mils) Summary of nominal dimensions in inches: Body Width: 0.296 Lead Pitch: 0.025 Body Length: 0.625 Body Height: 0.102 © Cypress Semiconductor Corporation, 2000. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. Powered by ICminer.com Electronic-Library Service CopyRight 2003