SST SST25VF032B-50-4I-SCF

32 Mbit SPI Serial Flash
SST25VF032B
SST25VF032B32Mb Serial Peripheral Interface (SPI) flash memory
Advance Information
FEATURES:
• Single Voltage Read and Write Operations
– 2.7-3.6V
• Serial Interface Architecture
– SPI Compatible: Mode 0 and Mode 3
• High Speed Clock Frequency
– 50 MHz Max
• Superior Reliability
– Endurance: 100,000 Cycles (typical)
– Greater than 100 years Data Retention
• Low Power Consumption:
– Active Read Current: 10 mA (typical)
– Standby Current: 5 µA (typical)
• Flexible Erase Capability
– Uniform 4 KByte sectors
– Uniform 32 KByte overlay blocks
– Uniform 64 KByte overlay blocks
• Fast Erase and Byte-Program:
– Chip-Erase Time: 35 ms (typical)
– Sector-/Block-Erase Time: 18 ms (typical)
– Byte-Program Time: 7 µs (typical)
• Auto Address Increment (AAI) Word Programming
– Decrease total chip programming time over
Byte-Program operations
• End-of-Write Detection
– Software polling the BUSY bit in Status Register
– Busy Status readout on SO pin
• Hold Pin (HOLD#)
– Suspends a serial sequence to the memory
without deselecting the device
• Write Protection (WP#)
– Enables/Disables the Lock-Down function of the
status register
• Software Write Protection
– Write protection through Block-Protection bits in
status register
• Temperature Range
– Commercial: 0°C to +70°C
– Industrial: -40°C to +85°C
• Packages Available
– 8-lead SOIC (200 mils)
– 16-lead SOIC (300 mils)
• All non-Pb (lead-free) devices are RoHS compliant
PRODUCT DESCRIPTION
The SST 25 series Serial Flash family features a four-wire,
SPI-compatible interface that allows for a low pin-count
package which occupies less board space and ultimately
lowers total system costs. SST25VF032B SPI serial flash
memories are manufactured with SST’s proprietary, highperformance CMOS SuperFlash technology. The split-gate
cell design and thick-oxide tunneling injector attain better
reliability and manufacturability compared with alternate
approaches.
The SST25VF032B devices significantly improve performance and reliability, while lowering power consumption.
The devices write (Program or Erase) with a single power
©2006 Silicon Storage Technology, Inc.
S71327-00-000
10/06
1
supply of 2.7-3.6V for SST25VF032B. The total energy
consumed is a function of the applied voltage, current, and
time of application. Since for any given voltage range, the
SuperFlash technology uses less current to program and
has a shorter erase time, the total energy consumed during
any Erase or Program operation is less than alternative
flash memory technologies.
The SST25VF032B device is offered in both 8-lead SOIC
(200 mils) and 16-lead SOIC (300 mils) packages. See Figures 2 and 3 for pin assignments.
The SST logo and SuperFlash are registered Trademarks of Silicon Storage Technology, Inc.
These specifications are subject to change without notice.
32 Mbit SPI Serial Flash
SST25VF032B
Advance Information
SuperFlash
Memory
X - Decoder
Address
Buffers
and
Latches
Y - Decoder
I/O Buffers
and
Data Latches
Control Logic
Serial Interface
CE#
SCK
SI
SO
WP#
HOLD#
1327 B1.0
Note: 1. In AAI mode, the SO pin can act as a RY/BY# pin when configured as a ready/busy status pin. See “End-ofWrite Detection” on page 12 for details
FIGURE 1: Functional Block Diagram
©2006 Silicon Storage Technology, Inc.
S71327-00-000
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10/06
32 Mbit SPI Serial Flash
SST25VF032B
Advance Information
PIN DESCRIPTION
CE#
1
SO
2
8
VDD
7
HOLD#
Top View
WP#
3
6
SCK
VSS
4
5
SI
1327 8-SOIC P1.0
Notes: 1. In AAI mode, the SO pin can act as a RY/BY# pin when configured as a ready/busy status pin. See “End-ofWrite Detection” on page 12 for details.
FIGURE 2: Pin Assignments for 8-Lead SOIC
SCK
HOLD#
VDD
SI
NC
NC
NC
NC
NC
NC
NC
NC
CE#
VSS
SO
WP#
1327 16-SOIC P1.0
Notes: 1. In AAI mode, the SO pin can act as a RY/BY# pin when configured as a ready/busy status pin. See “End-ofWrite Detection” on page 12 for details.
FIGURE 3: Pin Assignments for 16-Lead SOIC
©2006 Silicon Storage Technology, Inc.
S71327-00-000
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10/06
32 Mbit SPI Serial Flash
SST25VF032B
Advance Information
TABLE 1: Pin Description
Symbol
Pin Name
Functions
SCK
Serial Clock
To provide the timing of the serial interface.
Commands, addresses, or input data are latched on the rising edge of the clock input,
while output data is shifted out on the falling edge of the clock input.
SI
Serial Data Input
To transfer commands, addresses, or data serially into the device.
Inputs are latched on the rising edge of the serial clock.
SO
Serial Data Output
To transfer data serially out of the device.
Data is shifted out on the falling edge of the serial clock.
RY/BY#
Ready / Busy pin
Flash busy status pin in AAI mode if SO is configured as a hardware RY/BY# pin.
CE#
Chip Enable
The device is enabled by a high to low transition on CE#. CE# must remain low for the
duration of any command sequence.
WP#
Write Protect
The Write Protect (WP#) pin is used to enable/disable BPL bit in the status register.
HOLD#
Hold
To temporarily stop serial communication with SPI flash memory without resetting the
device.
VDD
Power Supply
To provide power supply voltage: 2.7-3.6V
VSS
Ground
T1.0 1327
©2006 Silicon Storage Technology, Inc.
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32 Mbit SPI Serial Flash
SST25VF032B
Advance Information
MEMORY ORGANIZATION
select the device, and data is accessed through the Serial
Data Input (SI), Serial Data Output (SO), and Serial Clock
(SCK).
The SST25VF032B SuperFlash memory array is organized in uniform 4 KByte erasable sectors with 32 KByte
overlay blocks and 64 KByte overlay erasable blocks.
The SST25VF032B supports both Mode 0 (0,0) and Mode
3 (1,1) of SPI bus operations. The difference between the
two modes, as shown in Figure 4, is the state of the SCK
signal when the bus master is in Stand-by mode and no
data is being transferred. The SCK signal is low for Mode 0
and SCK signal is high for Mode 3. For both modes, the
Serial Data In (SI) is sampled at the rising edge of the SCK
clock signal and the Serial Data Output (SO) is driven after
the falling edge of the SCK clock signal.
DEVICE OPERATION
The SST25VF032B is accessed through the SPI (Serial
Peripheral Interface) bus compatible protocol. The SPI bus
consist of four control lines; Chip Enable (CE#) is used to
CE#
SCK
SI
MODE 3
MODE 3
MODE 0
MODE 0
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
MSB
HIGH IMPEDANCE
DON'T CARE
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
SO
MSB
1327 F04.0
FIGURE 4: SPI Protocol
©2006 Silicon Storage Technology, Inc.
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32 Mbit SPI Serial Flash
SST25VF032B
Advance Information
Hold Operation
coincide with the SCK active low state, then the device
exits from Hold mode when the SCK next reaches the
active low state. See Figure 5 for Hold Condition waveform.
The HOLD# pin is used to pause a serial sequence using
the SPI flash memory, but without resetting the clocking
sequence. To activate the HOLD# mode, CE# must be in
active low state. The HOLD# mode begins when the SCK
active low state coincides with the falling edge of the
HOLD# signal. The HOLD mode ends when the HOLD#
signal’s rising edge coincides with the SCK active low state.
Once the device enters Hold mode, SO will be in highimpedance state while SI and SCK can be VIL or VIH.
If CE# is driven high during a Hold condition, the device
returns to Standby mode. As long as HOLD# signal is low,
the memory remains in the Hold condition. To resume
communication with the device, HOLD# must be driven
active high, and CE# must be driven active low. See Figure
5 for Hold timing.
If the falling edge of the HOLD# signal does not coincide
with the SCK active low state, then the device enters Hold
mode when the SCK next reaches the active low state.
Similarly, if the rising edge of the HOLD# signal does not
SCK
HOLD#
Active
Hold
Active
Hold
Active
1327 F05.0
FIGURE 5: Hold Condition Waveform
Write Protection
TABLE 2: Conditions to execute Write-StatusRegister (WRSR) Instruction
SST25VF032B provides software Write protection. The
Write Protect pin (WP#) enables or disables the lock-down
function of the status register. The Block-Protection bits
(BP3, BP2, BP1, BP0, and BPL) in the status register provide Write protection to the memory array and the status
register. See Table 4 for the Block-Protection description.
WP#
BPL
L
1
Execute WRSR Instruction
Not Allowed
L
0
Allowed
H
X
Allowed
T2.0 1327
Write Protect Pin (WP#)
The Write Protect (WP#) pin enables the lock-down function of the BPL bit (bit 7) in the status register. When WP#
is driven low, the execution of the Write-Status-Register
(WRSR) instruction is determined by the value of the BPL
bit (see Table 2). When WP# is high, the lock-down function of the BPL bit is disabled.
©2006 Silicon Storage Technology, Inc.
S71327-00-000
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10/06
32 Mbit SPI Serial Flash
SST25VF032B
Advance Information
Status Register
Program operation, the status register may be read only to
determine the completion of an operation in progress.
Table 3 describes the function of each bit in the software
status register.
The software status register provides status on whether the
flash memory array is available for any Read or Write operation, whether the device is Write enabled, and the state of
the Memory Write protection. During an internal Erase or
TABLE 3: Software Status Register
Default at
Power-up
Read/Write
1 = Internal Write operation is in progress
0 = No internal Write operation is in progress
0
R
WEL
1 = Device is memory Write enabled
0 = Device is not memory Write enabled
0
R
2
BP0
Indicate current level of block write protection (See Table 4)
1
R/W
3
BP1
Indicate current level of block write protection (See Table 4)
1
R/W
4
BP2
Indicate current level of block write protection (See Table 4)
1
R/W
5
BP3
Indicate current level of block write protection (See Table 4)
0
R/W
6
AAI
Auto Address Increment Programming status
1 = AAI programming mode
0 = Byte-Program mode
0
R
7
BPL
1 = BP3, BP2, BP1, BP0 are read-only bits
0 = BP3, BP2, BP1, BP0 are readable/writable
0
R/W
Bit
Name
Function
0
BUSY
1
T3.0 1327
Busy
Auto Address Increment (AAI)
The Busy bit determines whether there is an internal Erase
or Program operation in progress. A ‘1’ for the Busy bit indicates the device is busy with an operation in progress. A ‘0’
indicates the device is ready for the next valid operation.
The Auto Address Increment Programming-Status bit provides status on whether the device is in AAI programming
mode or Byte-Program mode. The default at power up is
Byte-Program mode.
Write Enable Latch (WEL)
The Write-Enable-Latch bit indicates the status of the internal memory Write Enable Latch. If the Write-Enable-Latch
bit is set to ‘1’, it indicates the device is Write enabled. If the
bit is set to ‘0’ (reset), it indicates the device is not Write
enabled and does not accept any memory Write (Program/
Erase) commands. The Write-Enable-Latch bit is automatically reset under the following conditions:
•
•
•
•
•
•
•
•
Power-up
Write-Disable (WRDI) instruction completion
Byte-Program instruction completion
Auto Address Increment (AAI) programming is
completed or reached its highest unprotected
memory address
Sector-Erase instruction completion
Block-Erase instruction completion
Chip-Erase instruction completion
Write-Status-Register instructions
©2006 Silicon Storage Technology, Inc.
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10/06
32 Mbit SPI Serial Flash
SST25VF032B
Advance Information
Block Protection (BP3,BP2, BP1, BP0)
Block Protection Lock-Down (BPL)
The Block-Protection (BP3, BP2, BP1, BP0) bits define the
size of the memory area, as shown in Table 4, to be software protected against any memory Write (Program or
Erase) operation. The Write-Status-Register (WRSR)
instruction is used to program the BP3, BP2, BP1 and BP0
bits as long as WP# is high or the Block-Protect-Lock
(BPL) bit is 0. Chip-Erase can only be executed if BlockProtection bits are all 0. After power-up, BP3, BP2, BP1
and BP0 are set to the defaults specified in Table 4.
WP# pin driven low (VIL), enables the Block-ProtectionLock-Down (BPL) bit. When BPL is set to 1, it prevents any
further alteration of the BPL, BP3, BP2, BP1, and BP0 bits.
When the WP# pin is driven high (VIH), the BPL bit has no
effect and its value is “Don’t Care”. After power-up, the BPL
bit is reset to 0.
TABLE 4: Software Status Register Block Protection FOR SST25VF032B1
Status Register Bit2
Protection Level
Protected Memory Address
BP3
BP2
BP1
BP0
32 Mbit
None
X
0
0
0
None
Upper 1/64
X
0
0
1
3F0000H-3FFFFFH
Upper 1/32
X
0
1
0
3E0000H-3FFFFFH
Upper 1/16
X
0
1
1
3C0000H-3FFFFFH
Upper 1/8
X
1
0
0
380000H-3FFFFFH
Upper 1/4
X
1
0
1
300000H-3FFFFFH
Upper 1/2
X
1
1
0
200000H-3FFFFFH
All Blocks
X
1
1
1
000000H-3FFFFFH
T4.0 1327
1. X = Don’t Care (RESERVED) default is “0
2. Default at power-up for BP2, BP1, and BP0 is ‘111’. (All Blocks Protected)
©2006 Silicon Storage Technology, Inc.
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10/06
32 Mbit SPI Serial Flash
SST25VF032B
Advance Information
INSTRUCTIONS
low before an instruction is entered and must be driven
high after the last bit of the instruction has been shifted in
(except for Read, Read-ID, and Read-Status-Register
instructions). Any low to high transition on CE#, before
receiving the last bit of an instruction bus cycle, will terminate the instruction in progress and return the device to
standby mode. Instruction commands (Op Code),
addresses, and data are all input from the most significant
bit (MSB) first.
Instructions are used to read, write (Erase and Program),
and configure the SST25VF032B. The instruction bus
cycles are 8 bits each for commands (Op Code), data, and
addresses. The Write-Enable (WREN) instruction must be
executed prior any Byte-Program, Auto Address Increment
(AAI) programming, Sector-Erase, Block-Erase, Write-Status-Register, or Chip-Erase instructions. The complete list
of instructions is provided in Table 5.
All instructions are synchronized off a high to low transition
of CE#. Inputs will be accepted on the rising edge of SCK
starting with the most significant bit. CE# must be driven
TABLE 5: Device Operation Instructions
Instruction
Description
Op Code Cycle1
Address
Cycle(s)2
Dummy
Data
Maximum
Cycle(s) Cycle(s) Frequency
Read
Read Memory
0000 0011b (03H)
3
0
1 to ∞
High-Speed Read
Read Memory at higher speed
25 MHz
0000 1011b (0BH)
3
1
1 to ∞
50 MHz
4 KByte Sector-Erase3 Erase 4 KByte of
memory array
0010 0000b (20H)
3
0
0
50 MHz
32 KByte Block-Erase4 Erase 32KByte block
of memory array
0101 0010b (52H)
3
0
0
50 MHz
64 KByte Block-Erase5 Erase 64 KByte block
of memory array
1101 1000b (D8H)
3
0
0
50 MHz
Chip-Erase
Erase Full Memory Array
0110 0000b (60H) or
1100 0111b (C7H)
0
0
0
50 MHz
Byte-Program
To Program One Data Byte
0000 0010b (02H)
3
0
1
50 MHz
AAI-Word-Program6
Auto Address Increment
Programming
1010 1101b (ADH)
3
0
2 to ∞
50 MHz
RDSR7
Read-Status-Register
0000 0101b (05H)
0
0
1 to ∞
50 MHz
EWSR
Enable-Write-Status-Register 0101 0000b (50H)
0
0
0
50 MHz
WRSR
Write-Status-Register
0000 0001b (01H)
0
0
1
50 MHz
WREN
Write-Enable
0000 0110b (06H)
0
0
0
50 MHz
WRDI
Write-Disable
0000 0100b (04H)
0
0
0
50 MHz
RDID8
Read-ID
1001 0000b (90H) or
1010 1011b (ABH)
3
0
1 to ∞
50 MHz
JEDEC-ID
JEDEC ID read
1001 1111b (9FH)
0
0
3 to ∞
50 MHz
EBSY
Enable SO as an output RY/BY# 0111 0000b (70H)
status during AAI programming
0
0
0
50 MHz
DBSY
Disable SO as an output RY/BY# 1000 0000b (80H)
status during AAI programming
0
0
0
50 MHz
T5.0
1327
1.
2.
3.
4.
5.
6.
One bus cycle is eight clock periods.
Address bits above the most significant bit can be either VIL or VIH.
4KByte Sector Erase addresses: use AMS-A12, remaining addresses are don’t care but must be set either at VIL or VIH.
32KByte Block Erase addresses: use AMS-A15, remaining addresses are don’t care but must be set either at VIL or VIH.
64KByte Block Erase addresses: use AMS-A16, remaining addresses are don’t care but must be set either at VIL or VIH.
To continue programming to the next sequential address location, enter the 8-bit command, ADH, followed by 2 bytes of data to be
programmed. Data Byte 0 will be programmed into the initial address [A23-A1] with A0=0, Data Byte 1 will be programmed into the
initial address [A23-A1] with A0 = 1.
7. The Read-Status-Register is continuous with ongoing clock cycles until terminated by a low to high transition on CE#.
8. Manufacturer’s ID is read with A0 = 0, and Device ID is read with A0 = 1. All other address bits are 00H. The Manufacturer’s ID and
device ID output stream is continuous until terminated by a low-to-high transition on CE#.
©2006 Silicon Storage Technology, Inc.
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32 Mbit SPI Serial Flash
SST25VF032B
Advance Information
Read (25 MHz)
ple, once the data from address location 3FFFFFH has
been read, the next output will be from address location
000000H.
The Read instruction, 03H, supports up to 25 MHz Read.
The device outputs the data starting from the specified
address location. The data output stream is continuous
through all addresses until terminated by a low to high transition on CE#. The internal address pointer will automatically increment until the highest memory address is
reached. Once the highest memory address is reached,
the address pointer will automatically increment to the
beginning (wrap-around) of the address space. For exam-
The Read instruction is initiated by executing an 8-bit command, 03H, followed by address bits [A23-A0]. CE# must
remain active low for the duration of the Read cycle. See
Figure 6 for the Read sequence.
CE#
MODE 3
SCK
0 1 2 3 4 5 6 7 8
23 24
15 16
31 32
39 40
47
48
55 56
63 64
70
MODE 0
ADD.
03
SI
ADD.
ADD.
MSB
MSB
N
DOUT
HIGH IMPEDANCE
SO
N+1
DOUT
N+2
DOUT
N+3
DOUT
N+4
DOUT
MSB
1327 F06.0
FIGURE 6: Read Sequence
High-Speed-Read (50 MHz)
addresses until terminated by a low to high transition on
CE#. The internal address pointer will automatically increment until the highest memory address is reached. Once
the highest memory address is reached, the address
pointer will automatically increment to the beginning (wraparound) of the address space. For example, once the data
from address location 3FFFFFH has been read, the next
output will be from address location 000000H.
The High-Speed-Read instruction supporting up to 50 MHz
Read is initiated by executing an 8-bit command, 0BH, followed by address bits [A23-A0] and a dummy byte. CE#
must remain active low for the duration of the High-SpeedRead cycle. See Figure 7 for the High-Speed-Read
sequence.
Following a dummy cycle, the High-Speed-Read instruction outputs the data starting from the specified address
location. The data output stream is continuous through all
CE#
MODE 3
SCK
0 1 2 3 4 5 6 7 8
15 16
23 24
31 32
39 40
47 48
55 56
63 64
80
71 72
MODE 0
SI
SO
0B
ADD.
ADD.
ADD.
X
N
DOUT
HIGH IMPEDANCE
MSB
N+1
DOUT
N+2
DOUT
N+3
DOUT
N+4
DOUT
1327 F07.0
FIGURE 7: High-Speed-Read Sequence
©2006 Silicon Storage Technology, Inc.
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10/06
32 Mbit SPI Serial Flash
SST25VF032B
Advance Information
Byte-Program
Program instruction is initiated by executing an 8-bit command, 02H, followed by address bits [A23-A0]. Following the
address, the data is input in order from MSB (bit 7) to LSB
(bit 0). CE# must be driven high before the instruction is
executed. The user may poll the Busy bit in the software
status register or wait TBP for the completion of the internal
self-timed Byte-Program operation. See Figure 8 for the
Byte-Program sequence.
The Byte-Program instruction programs the bits in the
selected byte to the desired data. The selected byte must
be in the erased state (FFH) when initiating a Program
operation. A Byte-Program instruction applied to a protected memory area will be ignored.
Prior to any Write operation, the Write-Enable (WREN)
instruction must be executed. CE# must remain active low
for the duration of the Byte-Program instruction. The Byte-
CE#
MODE 3
SCK
0 1 2 3 4 5
6 7 8
15 16
23 24
31 32
39
MODE 0
SI
02
ADD.
ADD.
ADD.
DIN
MSB LSB
HIGH IMPEDANCE
SO
1327 F08.0
FIGURE 8: Byte-Program Sequence
©2006 Silicon Storage Technology, Inc.
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10/06
32 Mbit SPI Serial Flash
SST25VF032B
Advance Information
Auto Address Increment (AAI) Word-Program
Hardware End-of-Write Detection
The AAI program instruction allows multiple bytes of data to
be programmed without re-issuing the next sequential
address location. This feature decreases total programming time when multiple bytes or entire memory array is to
be programmed. An AAI Word program instruction pointing
to a protected memory area will be ignored. The selected
address range must be in the erased state (FFH) when initiating an AAI Word Program operation. While within AAI
Word Programming sequence, the only valid instructions
are AAI Word (ADH), RDSR (05H), or WRDI (04H). Users
have three options to determine the completion of each
AAI Word program cycle: hardware detection by reading
the Serial Output, software detection by polling the BUSY
bit in the software status register or wait TBP. Refer to EndOf-Write Detection section for details.
The hardware end-of-write detection method eliminates the
overhead of polling the Busy bit in the Software Status
Register during an AAI Word program operation. The 8-bit
command, 70H, configures the Serial Output (SO) pin to
indicate Flash Busy status during AAI Word programming,
as shown in Figure 9. The 8-bit command, 70H, must be
executed prior to executing an AAI Word-Program instruction. Once an internal programming operation begins,
asserting CE# will immediately drive the status of the internal flash status on the SO pin. A ‘0’ indicates the device is
busy and a ‘1’ indicates the device is ready for the next
instruction. De-asserting CE# will return the SO pin to tristate.
The 8-bit command, 80H, prevents the Serial Output (SO)
pin from outputting Busy status during AAI-Word-program
operation and re-configures SO as an output pin. The
device can only accept the 80H command when the device
is not in AAI mode. Once SO is an output pin, in AAI mode
the device can accept both RDSR instruction for polling
and Software Status Register data outputs through the SO
pin. This is shown in Figure 10.
Prior to any write operation, the Write-Enable (WREN)
instruction must be executed. The AAI Word Program
instruction is initiated by executing an 8-bit command,
ADH, followed by address bits [A23-A0]. Following the
addresses, two bytes of data is input sequentially, each one
from MSB (Bit 7) to LSB (Bit 0). The first byte of data (D0)
will be programmed into the initial address [A23-A1] with A0
= 0, the second byte of Data (D1) will be programmed into
the initial address [A23-A1] with A0 = 1. CE# must be driven
high before the AAI Word Program instruction is executed.
The user must check the BUSY status before entering the
next valid command. Once the device indicates it is no
longer busy, data for the next two sequential addresses
may be programmed and so on. When the last desired
byte had been entered, check the busy status using the
hardware method or the RDSR instruction and execute the
Write-Disable (WRDI) instruction, 04H, to terminate AAI.
Check the busy status after WRDI to determine if the
device is ready for any command. See Figures 11 and 12
for AAI Word programming sequence.
CE#
MODE 3
SCK
0 1 2 3 4 5 6 7
MODE 0
70
SI
MSB
HIGH IMPEDANCE
SO
1327 F09.0
FIGURE 9: Enable SO as Hardware RY/BY#
during AAI Programming
There is no wrap mode during AAI programming; once the
highest unprotected memory address is reached, the
device will exit AAI operation and reset the Write-EnableLatch bit (WEL = 0) and the AAI bit (AAI = 0).
CE#
MODE 3
End-of-Write Detection
SCK
There are three methods to determine completion of a program cycle during AAI Word programming: hardware
detection by reading the Serial Output, software detection
by polling the BUSY bit in the Software Status Register or
wait TBP. The hardware end-of-write detection method is
described in the section below.
0 1 2 3 4 5 6 7
MODE 0
80
SI
MSB
SO
HIGH IMPEDANCE
1327 F10.0
FIGURE 10: Disable SO as Hardware RY/BY#
during AAI Programming
©2006 Silicon Storage Technology, Inc.
S71327-00-000
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10/06
32 Mbit SPI Serial Flash
SST25VF032B
Advance Information
CE#
8
0
8 0
16
8
32
24
48
40
0
16
8
24 0
16
8
24
8 0
0
8
16
SCK
SI
AD
WREN
A
A
A
D0
AD
D1
D2
D3
Dn-1
AD
Dn
WRDI
Last 2
Data Bytes
Load AAI command, Address, 2 bytes data
RDSR
WDRI to exit
AAI Mode
DOUT
SO
Check for Flash Busy Status to load next valid command
Note:
Output Status
Register Data
1. Valid commands during AAI programming: AAI command or WRDI command
2. User must configure the SO pin to output Flash Busy status during AAI programming
11327 AAI.HW.0
FIGURE 11: Auto Address Increment (AAI) Word-Program Sequence with
Hardware End-of-Write Detection
Check for Flash Busy Status to load next valid command
CE#
8
0
8 0
16
8
32
24
40
48
24 0
16
8
0
16
8
24
0
8
0
8
16
SCK
SI
AD
WREN
A
A
A
D0
D1
AD
D2
D3
AD
Dn-1
Load AAI command, Address, 2 bytes data
Dn
WRDI
Last 2
Data Bytes
WDRI to exit
AAI Mode
RDSR
DOUT
SO
Note:
1. Valid commands during AAI programming: AAI command or WRDI command
2. User must configure the SO pin to output Flash Busy status during AAI programming
Output Status
Register Data
1327 AAI.HW2.0
FIGURE 12: Auto Address Increment (AAI) Word-Program Sequence with
Software End-of-Write Detection
©2006 Silicon Storage Technology, Inc.
S71327-00-000
13
10/06
32 Mbit SPI Serial Flash
SST25VF032B
Advance Information
Sector-Erase
address bits [A23-A0]. Address bits [AMS-A12] (AMS = Most
Significant address) are used to determine the sector
address (SAX), remaining address bits can be VIL or VIH.
CE# must be driven high before the instruction is executed.
Poll the Busy bit in the software status register or wait TSE
for the completion of the internal self-timed Sector-Erase
cycle. See Figure 13 for the Sector-Erase sequence.
The Sector-Erase instruction clears all bits in the selected 4
KByte sector to FFH. A Sector-Erase instruction applied to
a protected memory area will be ignored. Prior to any Write
operation, the Write-Enable (WREN) instruction must be
executed. CE# must remain active low for the duration of
any command sequence. The Sector-Erase instruction is
initiated by executing an 8-bit command, 20H, followed by
CE#
MODE 3
SCK
0 1 2 3 4 5
6 7 8
15 16
23 24
31
MODE 0
SI
SO
ADD.
20
ADD.
ADD.
HIGH IMPEDANCE
1327 F13.0
FIGURE 13: Sector-Erase Sequence
©2006 Silicon Storage Technology, Inc.
S71327-00-000
14
10/06
32 Mbit SPI Serial Flash
SST25VF032B
Advance Information
32-KByte and 64-KByte Block-Erase
The 32-KByte Block-Erase instruction clears all bits in the
selected 32 KByte block to FFH. A Block-Erase instruction
applied to a protected memory area will be ignored. The
64-KByte Block-Erase instruction clears all bits in the
selected 64 KByte block to FFH. A Block-Erase instruction
applied to a protected memory area will be ignored. Prior to
any Write operation, the Write-Enable (WREN) instruction
must be executed. CE# must remain active low for the
duration of any command sequence. The 32-Kbyte BlockErase instruction is initiated by executing an 8-bit command, 52H, followed by address bits [A23-A0]. Address bits
[AMS-A15] (AMS = Most Significant Address) are used to
determine block address (BAX), remaining address bits can
be VIL or VIH. CE# must be driven high before the instruction
is executed. The 64-Kbyte Block-Erase instruction is initiated by executing an 8-bit command D8H, followed by
address bits [A23-A0]. Address bits [AMS-A15] are used to
determine block address (BAX), remaining address bits can
be VIL or VIH. CE# must be driven high before the instruction
is executed. Poll the Busy bit in the software status register
or wait TBE for the completion of the internal self-timed 32KByte Block-Erase or 64-KByte Block-Erase cycles. See
Figure 14 for the 32-KByte Block-Erase sequence and Figure 15 for the 64-KByte Block-Erase sequence.
CE#
MODE 3
SCK
0 1 2 3 4 5 6 7 8
15 16
23 24
31
MODE 0
ADDR
52
SI
MSB
ADDR
ADDR
MSB
HIGH IMPEDANCE
SO
1327 32KBklEr.0
FIGURE 14: 32-KByte Block-Erase Sequence
CE#
MODE 3
SCK
0 1 2 3 4 5 6 7 8
15 16
23 24
31
MODE 0
ADDR
D8
SI
MSB
SO
ADDR
ADDR
MSB
HIGH IMPEDANCE
1327 63KBlkEr.0
FIGURE 15: 64-KByte Block-Erase Sequence
©2006 Silicon Storage Technology, Inc.
S71327-00-000
15
10/06
32 Mbit SPI Serial Flash
SST25VF032B
Advance Information
Chip-Erase
executing an 8-bit command, 60H or C7H. CE# must be
driven high before the instruction is executed. Poll the Busy
bit in the software status register or wait TCE for the completion of the internal self-timed Chip-Erase cycle. See Figure
16 for the Chip-Erase sequence.
The Chip-Erase instruction clears all bits in the device to
FFH. A Chip-Erase instruction will be ignored if any of the
memory area is protected. Prior to any Write operation, the
Write-Enable (WREN) instruction must be executed. CE#
must remain active low for the duration of the Chip-Erase
instruction sequence. Initiate the Chip-Erase instruction by
CE#
MODE 3
SCK
0 1 2 3 4 5 6 7
MODE 0
60 or C7
SI
MSB
HIGH IMPEDANCE
SO
1327 F16.0
FIGURE 16: Chip-Erase Sequence
Read-Status-Register (RDSR)
CE# must be driven low before the RDSR instruction is
entered and remain low until the status data is read. ReadStatus-Register is continuous with ongoing clock cycles
until it is terminated by a low to high transition of the CE#.
See Figure 17 for the RDSR instruction sequence.
The Read-Status-Register (RDSR) instruction allows reading of the status register. The status register may be read at
any time even during a Write (Program/Erase) operation.
When a Write operation is in progress, the Busy bit may be
checked before sending any new commands to assure that
the new commands are properly received by the device.
CE#
MODE 3
SCK
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
MODE 0
SI
05
MSB
HIGH IMPEDANCE
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
SO
MSB
Status
Register Out
1327 F17.0
FIGURE 17: Read-Status-Register (RDSR) Sequence
©2006 Silicon Storage Technology, Inc.
S71327-00-000
16
10/06
32 Mbit SPI Serial Flash
SST25VF032B
Advance Information
Write-Enable (WREN)
the Write-Enable-Latch bit in the Status Register will be
cleared upon the rising edge CE# of the WRSR instruction.
CE# must be driven high before the WREN instruction is
executed.
The Write-Enable (WREN) instruction sets the WriteEnable-Latch bit in the Status Register to ‘1’ allowing Write
operations to occur. The WREN instruction must be executed prior to any Write (Program/Erase) operation. The
WREN instruction may also be used to allow execution of
the Write-Status-Register (WRSR) instruction; however,
CE#
MODE 3
SCK
0 1 2 3 4 5 6 7
MODE 0
06
SI
MSB
HIGH IMPEDANCE
SO
1327 F18.0
FIGURE 18: Write Enable (WREN) Sequence
Write-Disable (WRDI)
operation in progress may continue up to TBP after executing the WRDI instruction. CE# must be driven high before
the WRDI instruction is executed.
The Write-Disable (WRDI) instruction resets the WriteEnable-Latch bit and AAI bit to ‘0,’ therefore, preventing any
new Write operations. The WRDI instruction will not terminate any programming operation in progress. Any program
CE#
MODE 3
SCK
0 1 2 3 4 5 6 7
MODE 0
04
SI
MSB
SO
HIGH IMPEDANCE
1327 F19.0
FIGURE 19: Write Disable (WRDI) Sequence
Enable-Write-Status-Register (EWSR)
must be driven low before the EWSR instruction is entered
and must be driven high before the EWSR instruction is
executed.
The Enable-Write-Status-Register (EWSR) instruction
arms the Write-Status-Register (WRSR) instruction and
opens the status register for alteration. The Write-StatusRegister instruction must be executed immediately after the
execution of the Enable-Write-Status-Register instruction.
This two-step instruction sequence of the EWSR instruction followed by the WRSR instruction works like software
data protection (SDP) command structure which prevents
any accidental alteration of the status register values. CE#
©2006 Silicon Storage Technology, Inc.
S71327-00-000
17
10/06
32 Mbit SPI Serial Flash
SST25VF032B
Advance Information
Write-Status-Register (WRSR)
bit is disabled and the BPL, BP0, and BP1 and BP2 bits in
the status register can all be changed. As long as BPL bit is
set to ‘0’ or WP# pin is driven high (VIH) prior to the low-tohigh transition of the CE# pin at the end of the WRSR
instruction, the bits in the status register can all be altered
by the WRSR instruction. In this case, a single WRSR
instruction can set the BPL bit to ‘1’ to lock down the status
register as well as altering the BP0, BP1, and BP2 bits at
the same time. See Table 2 for a summary description of
WP# and BPL functions.
The Write-Status-Register instruction writes new values to
the BP3, BP2, BP1, BP0, and BPL bits of the status register. CE# must be driven low before the command
sequence of the WRSR instruction is entered and driven
high before the WRSR instruction is executed. See Figure
20 for EWSR or WREN and WRSR instruction sequences.
Executing the Write-Status-Register instruction will be
ignored when WP# is low and BPL bit is set to ‘1’. When
the WP# is low, the BPL bit can only be set from ‘0’ to ‘1’ to
lock-down the status register, but cannot be reset from ‘1’ to
‘0’. When WP# is high, the lock-down function of the BPL
CE#
MODE 3
SCK
0 1 2 3 4 5 6 7
MODE 0
MODE 3
01
50 or 06
SI
MSB
SO
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
MODE 0
MSB
STATUS
REGISTER IN
7 6 5 4 3 2 1 0
MSB
HIGH IMPEDANCE
1327 F20.0
FIGURE 20: Enable-Write-Status-Register (EWSR) or
Write-Enable (WREN) and Write-Status-Register (WRSR) Sequence
©2006 Silicon Storage Technology, Inc.
S71327-00-000
18
10/06
32 Mbit SPI Serial Flash
SST25VF032B
Advance Information
Read-ID (RDID)
00001H. Once the device is in Read-ID mode, the manufacturer’s and device ID output data toggles between
address 00000H and 00001H until terminated by a low to
high transition on CE#.
The Read-ID instruction (RDID) identifies the device as
SST25VF032B and manufacturer as SST. The device
information can be read from executing an 8-bit command,
90H or ABH, followed by address bits [A23-A0]. Following
the Read-ID instruction, the manufacturer’s ID is located in
address 00000H and the device ID is located in address
Refer to Tables 6 and 7 for device identification data.
CE#
MODE 3
SCK
0 1 2 3 4 5 6 7 8
23 24
15 16
31 32
39 40
47 48
55 56
63
MODE 0
90 or AB
SI
00
00
MSB
ADD1
MSB
HIGH IMPEDANCE
SO
BF
Device ID
BF
Device ID
HIGH
IMPEDANCE
MSB
Note: The manufacturer's and device ID output stream is continuous until terminated by a low to high transition on CE#.
1. 00H will output the manfacturer's ID first and 01H will output device ID first before toggling between the two.
1327 F21.0
FIGURE 21: Read-ID Sequence
TABLE 6: Product Identification
Manufacturer’s ID
Address
Data
00000H
BFH
00001H
4AH
Device ID
SST25VF032B
T6.0 1327
©2006 Silicon Storage Technology, Inc.
S71327-00-000
19
10/06
32 Mbit SPI Serial Flash
SST25VF032B
Advance Information
JEDEC Read-ID
BFH, identifies the manufacturer as SST. Byte 2, 25H, identifies the memory type as SPI Serial Flash. Byte 3, 4AH,
identifies the device as SST25VF032B. The instruction
sequence is shown in Figure 22. The JEDEC Read ID
instruction is terminated by a low to high transition on CE#
at any time during data output.
The JEDEC Read-ID instruction identifies the device as
SST25VF032B and the manufacturer as SST. The device
information can be read from executing the 8-bit command,
9FH. Following the JEDEC Read-ID instruction, the 8-bit
manufacturer’s ID, BFH, is output from the device. After
that, a 24-bit device ID is shifted out on the SO pin. Byte 1,
CE#
MODE 3
SCK
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
MODE 0
9F
SI
SO
HIGH IMPEDANCE
BF
25
MSB
4A
MSB
1327 F22.0
FIGURE 22: JEDEC Read-ID Sequence
TABLE 7: JEDEC Read-ID Data
Manufacturer’s ID
Device ID
Memory Type
Memory Capacity
Byte1
Byte 2
Byte 3
BFH
25H
4AH
T7.0 1327
©2006 Silicon Storage Technology, Inc.
S71327-00-000
20
10/06
32 Mbit SPI Serial Flash
SST25VF032B
Advance Information
ELECTRICAL SPECIFICATIONS
Absolute Maximum Stress Ratings Applied conditions greater than those listed under “Absolute Maximum
Stress Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation
of the device at these conditions or conditions greater than those defined in the operational sections of this data
sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.
Temperature Under Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55°C to +125°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +150°C
D. C. Voltage on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to VDD+0.5V
Transient Voltage (<20 ns) on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -2.0V to VDD+2.0V
Package Power Dissipation Capability (TA = 25°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0W
Surface Mount Solder Reflow Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C for 10 seconds
Output Short Circuit Current1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
1. Output shorted for no more than one second. No more than one output shorted at a time.
OPERATING RANGE
Range
AC CONDITIONS OF TEST
VDD
0°C to +70°C
2.7-3.6V
Output Load . . . . . . . . . . . . . . . . . . . . . CL = 30 pF
-40°C to +85°C
2.7-3.6V
See Figure 27
Commercial
Industrial
Input Rise/Fall Time . . . . . . . . . . . . . . . 5 ns
Ambient Temp
TABLE 8: DC Operating Characteristics (VDD = 2.7-3.6V)
Limits
Symbol
Parameter
IDDR
Read Current
Min
Max
Units
10
mA
Test Conditions
IDDR2
Read Current
15
mA
CE# = 0.1 VDD/0.9 VDD@50 MHz, SO = open
IDDW
Program and Erase Current
30
mA
CE# = VDD
ISB
Standby Current
20
µA
CE# = VDD, VIN = VDD or VSS
ILI
Input Leakage Current
1
µA
VIN = GND to VDD, VDD = VDD Max
ILO
Output Leakage Current
VIL
Input Low Voltage
VIH
Input High Voltage
VOL
Output Low Voltage
VOL2
Output Low Voltage
VOH
Output High Voltage
CE# = 0.1 VDD/0.9 VDD@25 MHz, SO = open
1
µA
VOUT = GND to VDD, VDD = VDD Max
0.8
V
VDD = VDD Min
V
VDD = VDD Max
0.2
V
IOL = 100 µA, VDD = VDD Min
0.4
V
IOL = 1.6 mA, VDD = VDD Min
V
IOH = -100 µA, VDD = VDD Min
0.7 VDD
VDD-0.2
T8.0 1327
TABLE 9: Recommended System Power-up Timings
Symbol
TPU-READ
Parameter
1
TPU-WRITE1
Minimum
Units
VDD Min to Read Operation
100
µs
VDD Min to Write Operation
100
µs
T9.0 1327
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
©2006 Silicon Storage Technology, Inc.
S71327-00-000
21
10/06
32 Mbit SPI Serial Flash
SST25VF032B
Advance Information
TABLE 10: Capacitance (TA = 25°C, f = 1 Mhz, other pins open)
Parameter
Description
COUT1
Output Pin Capacitance
CIN
1
Test Condition
Maximum
VOUT = 0V
12 pF
VIN = 0V
6 pF
Input Capacitance
T10.0 1327
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
TABLE 11: Reliability Characteristics
Symbol
Parameter
Minimum Specification
Units
Test Method
NEND1
Endurance
10,000
Cycles
JEDEC Standard A117
100
Years
JEDEC Standard A103
100 + IDD
mA
TDR
1
Data Retention
ILTH1
Latch Up
JEDEC Standard 78
T11.0 1327
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
TABLE 12: AC Operating Characteristics
25 MHz
Symbol
Parameter
Min
50 MHz
Max
Min
Max
Units
50
MHz
1
Serial Clock Frequency
TSCKH
Serial Clock High Time
TSCKL
Serial Clock Low Time
18
9
ns
TSCKR2
Serial Clock Rise Time (Slew Rate)
0.1
0.1
V/ns
TSCKF
Serial Clock Fall Time (Slew Rate)
0.1
0.1
V/ns
TCES3
CE# Active Setup Time
10
5
ns
CE# Active Hold Time
10
5
ns
CE# Not Active Setup Time
10
5
ns
FCLK
TCEH
3
TCHS3
TCHH
3
25
18
9
ns
CE# Not Active Hold Time
10
5
ns
TCPH
CE# High Time
100
50
ns
TCHZ
CE# High to High-Z Output
TCLZ
SCK Low to Low-Z Output
0
0
ns
TDS
Data In Setup Time
5
2
ns
TDH
Data In Hold Time
5
5
ns
THLS
HOLD# Low Setup Time
10
5
ns
THHS
HOLD# High Setup Time
10
5
ns
THLH
HOLD# Low Hold Time
10
5
ns
THHH
HOLD# High Hold Time
10
5
ns
THZ
HOLD# Low to High-Z Output
20
8
ns
TLZ
HOLD# High to Low-Z Output
15
8
ns
TOH
Output Hold from SCK Change
TV
Output Valid from SCK
15
8
ns
TSE
Sector-Erase
25
25
ms
TBE
Block-Erase
25
25
ms
TSCE
Chip-Erase
50
50
ms
TBP4
Byte-Program
10
10
15
0
8
ns
0
ns
µs
T12.0 1327
1.
2.
3.
4.
Maximum clock frequency for Read Instruction, 03H, is 25 MHz
Maximum Rise and Fall time may be limited by TSCKH and TSCKL requirements
Relative to SCK.
TBP of AAI-Word Programming is also 10 µs maximum time.
©2006 Silicon Storage Technology, Inc.
S71327-00-000
22
10/06
32 Mbit SPI Serial Flash
SST25VF032B
Advance Information
TCPH
CE#
TCEH
TCES
TCHH
TCHS
SCK
TDS
TDH
TSCKR
TSCKF
LSB
MSB
SI
HIGH-Z
HIGH-Z
SO
1327 F23.0
FIGURE 23: Serial Input Timing Diagram
CE#
TSCKH
TSCKL
SCK
TCLZ
SO
TOH
TCHZ
MSB
LSB
TV
SI
1327 F24.0
FIGURE 24: Serial Output Timing Diagram
©2006 Silicon Storage Technology, Inc.
S71327-00-000
23
10/06
32 Mbit SPI Serial Flash
SST25VF032B
Advance Information
CE#
THHH
THLS
THHS
SCK
THLH
THZ
TLZ
SO
SI
HOLD#
1327 F25.0
FIGURE 25: Hold Timing Diagram
VDD
VDD Max
Chip selection is not allowed.
All commands are rejected by the device.
VDD Min
TPU-READ
TPU-WRITE
Device fully accessible
Time
1327 F26.0
FIGURE 26: Power-up Timing Diagram
©2006 Silicon Storage Technology, Inc.
S71327-00-000
24
10/06
32 Mbit SPI Serial Flash
SST25VF032B
Advance Information
VIHT
VHT
INPUT?
VHT
REFERENCE POINTS
OUTPUT
VLT
VLT
VILT
1327 IORef.0
AC test inputs are driven at VIHT (0.9VDD) for a logic “1” and VILT (0.1VDD) for a logic “0”. Measurement reference points
for inputs and outputs are VHT (0.6VDD) and VLT (0.4VDD). Input rise and fall times (10% ↔ 90%) are <5 ns.
Note: VHT - VHIGH Test
VLT - VLOW Test
VIHT - VINPUT HIGH Test
VILT - VINPUT LOW Test
FIGURE 27: AC Input/Output Reference Waveforms
©2006 Silicon Storage Technology, Inc.
S71327-00-000
25
10/06
32 Mbit SPI Serial Flash
SST25VF032B
Advance Information
PRODUCT ORDERING INFORMATION
SST
25
XX
VF
XX
032 B
XXX X
-
50
XX
- 4C - XX -
S2A F
XXX X
Environmental Attribute
F1 = non-Pb / non-Sn contact (lead) finish:
Nickel plating with Gold top (outer) layer
Package Modifier
A = 8 leads or contacts
C = 16 leads
Package Type
S = SOIC
S2 = SOIC 200 mil body width
Temperature Range
C = Commercial = 0°C to +70°C
I = Industrial = -40°C to +85°C
Minimum Endurance
4 = 10,000 cycles
Operating Frequency
50 = 50 MHz
Device Density
032 = 32 Mbit
Voltage
V = 2.7-3.6V
Product Series
25 = Serial Peripheral Interface flash memory
1. Environmental suffix “F” denotes non-Pb/non-SN solder.
SST non-Pb/non-Sn solder devices are “RoHS Compliant”.
Valid combinations for SST25VF032B
SST25VF032B-50-4C-S2AF
SST25VF032B-50-4C-SCF
SST25VF032B-50-4I-S2AF
SST25VF032B-50-4I-SCF
Note: Valid combinations are those products in mass production or will be in mass production. Consult your SST sales
representative to confirm availability of valid combinations and to determine availability of new combinations.
©2006 Silicon Storage Technology, Inc.
S71327-00-000
26
10/06
32 Mbit SPI Serial Flash
SST25VF032B
Advance Information
PACKAGING DIAGRAMS
7.40
7.60
10.00
10.65
Pin #1
Identifier
10.08 †
10.50
.020x45˚
7˚
4 places
7˚
4 places
2.35
2.65
.33
.51
Note:
1.27 BSC
.23
.32
.10
.30
.38 ‡
1.27
16.soic-SC-ILL.3
1. Complies with JEDEC publication 95 MS-013 AA dimensions (except as noted), although some dimensions may be more stringent.
† = JEDEC min is 10.10; SST min (10.08) is less stringent
‡ = JEDEC min is 0.40; SST min (0.38) is less stringent
2. All linear dimensions are in metric (min/max).
3. Coplanarity: 0.1 (±.05) mm.
4. Maximum allowable mold flash is 0.15mm at the package ends, and 0.25mm between leads.
FIGURE 28: 16-Lead Plastic Small Outline Integrated Circuit (SOIC)
SST Package Code SC
©2006 Silicon Storage Technology, Inc.
S71327-00-000
27
10/06
32 Mbit SPI Serial Flash
SST25VF032B
Advance Information
Pin #1
Identifier
TOP VIEW
SIDE VIEW
0.50
0.35
5.40
5.15
1.27 BSC
0.25
0.05
5.40
5.15
8.10
7.70
END VIEW
2.16
1.75
0˚
0.25
0.19
Note: 1. All linear dimensions are in millimeters (max/min).
2. Coplanarity: 0.1 mm
3. Maximum allowable mold flash is 0.15 mm at the package ends and 0.25 mm between leads.
8˚
08-soic-EIAJ-S2A-3
0.80
0.50
1mm
FIGURE 29: 8-lead Small Outline Integrated Circuit (SOIC) 200 mil body width (5.2mm x 8mm)
SST Package Code: S2A
TABLE 13: Revision History
Number
00
Description
•
Initial release of data sheet
Date
Oct 2006
Silicon Storage Technology, Inc. • 1171 Sonora Court • Sunnyvale, CA 94086 • Telephone 408-735-9110 • Fax 408-735-9036
www.SuperFlash.com or www.sst.com
©2006 Silicon Storage Technology, Inc.
S71327-00-000
28
10/06