CY29946 2.5V or 3.3V, 200-MHz, 1:10 Clock Distribution Buffer Features Description • 2.5V or 3.3V operation The CY29946 is a low-voltage 200-MHz clock distribution buffer with the capability to select one of two LVCMOS/LVTTL compatible input clocks. These clock sources can be used to provide for test clocks as well as the primary system clocks. All other control inputs are LVCMOS/LVTTL compatible. The 10 outputs are LVCMOS or LVTTL compatible and can drive 50Ω series or parallel terminated transmission lines. For series terminated transmission lines, each output can drive one or two traces giving the device an effective fanout of 1:20. • 200-MHz clock support • Two LVCMOS-/LVTTL-compatible inputs • Ten clock outputs: drive up to 20 clock lines • 1× or 1/2× configurable outputs • Output three-state control • 250-ps max. output-to-output skew • Pin-compatible with MPC946, MPC9446 • Available in commercial and industrial temperature range • 32-pin TQFP package The CY29946 is capable of generating 1× and 1/2× signals from a 1× source. These signals are generated and retimed internally to ensure minimal skew between the 1× and 1/2× signals. SEL(A:C) inputs allow flexibility in selecting the ratio of 1× to1/2× outputs. The CY29946 outputs can also be three-stated via MR/OE# input. When MR/OE# is set HIGH, it resets the internal flip-flops and three-states the outputs. Block Diagram Pin Configuration TCLK0 /1 0 /2 1 /1 0 3 TCLK1 R MR/OE# VSS QA0 VDDC QA1 VSS QA2 VDDC TCLK_SEL QA0:2 32 31 30 29 28 27 26 25 DSELA 3 R /2 1 /1 0 /2 1 TCLK_SEL VDD TCLK0 TCLK1 DSELA DSELB DSELC VSS QB0:2 DSELB VSS QB0 VDDC QB1 VSS QB2 VDDC VDDC QC0:3 VDDC QC0 VSS QC1 VDDC QC2 VSS QC3 DSELC MR/OE# Cypress Semiconductor Corporation Document #: 38-07286 Rev. *E CY29946 24 23 22 21 20 19 18 17 9 10 11 12 13 14 15 16 4 R 1 2 3 4 5 6 7 8 • 3901 North First Street • San Jose, CA 95134 • 408-943-2600 Revised April 22, 2004 CY29946 Pin Description[1] Pin 3, 4 26, 28, 30 Name PWR TCLK(0,1) QA(2:0) I/O Description I, PU External Reference/Test Clock Input VDDC O Clock Outputs 19, 21, 23 QB(2:0) VDDC O Clock Outputs 10, 12, 14, 16 QC(0:3) VDDC O Clock Outputs 5, 6, 7 DSEL(A:C) I, PD Divider Select Inputs. When HIGH, selects ÷2 input divider. When LOW, selects ÷1 input divider. 1 TCLK_SEL I, PD TCLK Select Input. When LOW, TCLK0 clock is selected and when HIGH TCLK1 is selected. 32 MR/OE# 9, 13, 17, 18, 22, 25, 29 VDDC I, PD Output Enable Input. When asserted LOW, the outputs are enabled and when asserted HIGH, internal flip-flops are reset and the outputs are three-stated. If more than 1 Bank is being used in /2 Mode, a reset must be performed (MR/OE# Asserted High) after power-up to ensure all internal flip-flops are set to the same state. 2.5V or 3.3V Power Supply for Output Clock Buffers 2 VDD 2.5V or 3.3V Power Supply 8, 11, 15, 20, 24, 27, 31 VSS Common Ground Note: 1. PD = Internal pull-down. PU = Internal pull-up. Document #: 38-07286 Rev. *E Page 2 of 6 CY29946 Absolute Maximum Conditions[2] Storage Temperature: ................................ –65°C to + 150°C This device contains circuitry to protect the inputs against damage due to high static voltages or electric field; however, precautions should be taken to avoid application of any voltage higher than the maximum rated voltages to this circuit. For proper operation, Vin and Vout should be constrained to the range: Operating Temperature: ................................ –40°C to +85°C VSS < (Vin or Vout) < VDD . Maximum ESD protection ............................................... 2 kV Unused inputs must always be tied to an appropriate logic voltage level (either VSS or VDD). Maximum Input Voltage Relative to VSS: ............ VSS – 0.3V Maximum Input Voltage Relative to VDD: ............. VDD + 0.3V Maximum Power Supply: ................................................5.5V Maximum Input Current: ...........................................± 20 mA DC Electrical Specifications: VDD = VDDC = 3.3V ±10% or 2.5V ±5%, over the specified temperature range Parameter Description Conditions Min. Typ. Max. Unit VIL Input Low Voltage VSS 0.8 V VIH Input High Voltage 2.0 VDD V [3] IIL Input Low Current –100 µA IIH Input High Current[3] 100 µA Voltage[4] VOL Output Low VOH Output High Voltage[4] IDDQ Quiescent Supply Current IDD Dynamic Supply Current ZOut Cin Output Impedance IOL = 20 mA 0.4 IOH = –20 mA, VDD = 3.3V 2.5 IOH = –20 mA, VDD = 2.5V 1.8 5 7 VDD = 3.3V, Outputs @ 100 MHz, CL = 30 pF 130 VDD = 3.3V, Outputs @ 160 MHz, CL = 30 pF 225 VDD = 2.5V, Outputs @ 100 MHz, CL = 30 pF 95 VDD = 2.5V, Outputs @ 160 MHz, CL = 30 pF 160 mA mA VDD = 3.3V 12 15 18 VDD = 2.5V 14 18 22 Input Capacitance V V 4 W pF AC Electrical Specifications VDD = VDDC = 3.3V ±10% or 2.5V ±5%, over the specified temperature range[5] Parameter Description Fmax Input Frequency[6] Tpd TTL_CLK To Q Delay[6] Conditions Min. Typ. VDD = 3.3V VDD = 2.5V [6, 7] Max. Unit 200 MHz 170 5.0 11.5 ns FoutDC Output Duty Cycle 45 55 % tpZL, tpZH Output enable time (all outputs) 2 10 ns tpLZ, tpHZ Output disable time (all outputs) 2 10 ns Tskew Output-to-Output Skew[6, 8] 250 ps Measured at VDD/2 150 Skew[9] Tskew(pp) Part-to-Part Tr/Tf Output Clocks Rise/Fall Time[8] 4.5 ns 0.8V to 2.0V, VDD = 3.3V 0.10 2.0 1.0 ns 0.6V to 1.8V, VDD = 2.5V 0.10 1.3 Notes: 2. Multiple Supplies: The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required. 3. Inputs have pull-up/pull-down resistors that effect input current. 4. Driving series or parallel terminated 50Ω (or 50Ω to VDD/2) transmission lines. 5. Parameters are guaranteed by design and characterization. Not 100% tested in production. All parameters specified with loaded outputs. 6. Outputs driving 50Ω transmission lines. 7. 50% input duty cycle. 8. See Figure 1. 9. Part-to-Part skew at a given temperature and voltage. Document #: 38-07286 Rev. *E Page 3 of 6 CY29946 CY29946 DUT Zo = 50 ohm Pulse Generator Z = 50 ohm Zo = 50 ohm RT = 50 ohm RT = 50 ohm VTT VTT Figure 1. LVCMOS_CLK CY29946 Test Reference for VCC = 3.3V and VCC = 2.5V VCC LVCMOS_CLK VCC /2 GND VCC Q VCC /2 tPD GND Figure 2. LVCMOS Propagation Delay (TPD) Test Reference VCC VCC /2 tP G ND T0 DC = tP / T0 x 100% Figure 3. Output Duty Cycle (FoutDC) VCC VCC /2 GND VCC VCC /2 tSK(0) GND Figure 4. Output-to-Output Skew tsk(0) Ordering Information Part Number Package Type Production Flow CY29946AXI 32-pin TQFP Industrial, –40°C to +85°C CY29946AIXT 32-pin TQFP – Tape and Reel Industrial, –40°C to +85°C CY29946AXC 32-pin TQFP Commercial, 0°C to +70°C CY29946AXCT 32-pin TQFP – Tape and Reel Commercial, 0°C to +70°C Document #: 38-07286 Rev. *E Page 4 of 6 CY29946 Package Drawing and Dimensions 32-Lead Thin Plastic Quad Flatpack 7 x 7 x 1.0mm A32 51-85063-*B All product and company names mentioned in this document may be the trademarks of their respective holders. Document #: 38-07286 Rev. *E Page 5 of 6 © Cypress Semiconductor Corporation, 2003. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. CY29946 Document History Page Document Title: CY29946 2.5V or 3.3V, 200-MHz, 1:10 Clock Distribution Buffer Document Number: 38-07286 REV. Orig. of Change ECN NO. Issue Date Description of Change ** 111097 02/07/02 BRK New data sheet *A 116780 08/15/02 HWT Added the commercial temperature range in the Ordering Information *B 122878 12/22/02 RBI Added power-up requirements to Maximum Ratings *C 130007 10/15/03 RGL Fixed the block diagram. Fixed the MK/OE# description in the pin description table. *D 131375 11/21/03 RGL Updated document history page (revision *C) to reflect changes that were not listed. *E 221587 See ECN RGL Minor Change: Moved up the word Block Diagram in the first page. Document #: 38-07286 Rev. *E Page 6 of 6