B9948 3.3V, 160MHz, 1:12 Clock Distribution Buffer Product Features • • • • • • • • • • Description 160MHz Clock Support LVPECL or LVCMOS/LVTTL Clock Input LVCMOS/LVTTL Compatible Inputs 12 Clock Outputs: Drive up to 24 Clock Lines Synchronous Output Enable Output Tri-state Control 350ps Maximum Output-to-Output Skew Pin Compatible with MPC948 Industrial Temp. Range: -40°C to +85°C 32-Pin TQFP Package The B9948 is a low voltage clock distribution buffer with the capability to select either a differential LVPECL or a LVCMOS/LVTTL compatible input clock. The two clock sources can be used to provide for a test clock as well as the primary system clock. All other control inputs are LVCMOS/LVTTL compatible. The twelve outputs are 3.3V LVCMOS or LVTTL compatible and can drive two series terminated 50Ω transmission lines. With this capability the B9948 has an effective fan-out of 1:24. The outputs can also be tri-stated via the tri-state input TS#. Low output-to-output skews make the B9948 an ideal clock distribution buffer for nested clock trees in the most demanding of synchronous systems. The B9948 also provides a synchronous output enable input for enabling or disabling the output clocks. Since this input is internally synchronized to the input clock, potential output glitching or runt pulse generation is eliminated. Block Diagram Pin Configuration VSS Q0 VDDC Q1 VSS Q2 VDDC Q3 30 29 28 27 26 25 13 14 15 16 Q9 VDDC Q8 VSS B9948 12 TS# 24 23 22 21 20 19 18 17 VSS SYNC_OE 1 2 3 4 5 6 7 8 11 TCLK_SEL TCLK PECL_CLK PECL_CLK# SYNC_OE TS# VDD VSS Q10 TCLK_SEL Q0-Q11 31 12 32 1 9 TCLK 10 0 Q11 PECL_CLK PECL_CLK# VDDC VDDC VDD VSS Q4 VDDC Q5 VSS Q6 VDDC Q7 Figure 1 Cypress Semiconductor Corporation 525 Los Coches St. Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571 http://www.cypress.com Document#: 38-07079 Rev. *A 06/18/2001 Page 1 of 7 B9948 3.3V, 160MHz, 1:12 Clock Distribution Buffer Pin Description PIN 3 4 2 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, 31 1 NAME PECL_CLK PECL_CLK# TCLK Q(11:0) PWR VDDC I/O I, PU I, PD I, PU O Description PECL Input Clock. PECL Input Clock. External Reference/Test Clock Input. Clock Outputs. TCLK_SEL I, PU Clock Select Input. When low, PECL clock is selected and when high TCLK is selected. 5 SYNC_OE I, PU 6 TS# I, PU 10, 14, 18, 22, 26, 30 7 8, 12, 16, 20, 24, 28, 32 VDDC Output Enable Input. When asserted high, the outputs are enabled and when set low the outputs are disabled in a low state. Tri-state Control Input. When asserted low, the output buffers are tri-stated. When set high, the output buffers are enabled. 3.3V Power Supply for Output Clock Buffers. VDD VSS 3.3V Power Supply Common Ground PD = Internal Pull-Down, PU = Internal Pull-Up. Cypress Semiconductor Corporation 525 Los Coches St. Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571 http://www.cypress.com Document#: 38-07079 Rev. *A 06/18/2001 Page 2 of 7 B9948 3.3V, 160MHz, 1:12 Clock Distribution Buffer Maximum Ratings This device contains circuitry to protect the inputs against damage due to high static voltages or electric field; however, precautions should be taken to avoid application of any voltage higher than the maximum rated voltages to this circuit. For proper operation, Vin and Vout should be constrained to the range: Maximum Input Voltage Relative to VSS: VSS - 0.3V Maximum Input Voltage Relative to VDD: VDD + 0.3V Storage Temperature: -65°C to + 150°C Operating Temperature: -40°C to +85°C Maximum ESD protection 2KV Maximum Power Supply: Maximum Input Current: VSS<(Vin or Vout)<VDD 5.5V ±20mA Unused inputs must always be tied to an appropriate logic voltage level (either VSS or VDD). DC Parameters Characteristic Symbol Input Low Voltage Min VIL 1.49 Input High Voltage VIH VSS 2.135 2.0 Input Low Current (@VIL = VSS) Input High Current (@VIL =VDD) Peak-to-Peak Input Voltage PECL_CLK IIL IIH VPP Common Mode Range PECL_CLK VCMR Typ Units Conditions V PECL_CLK, Single Ended All other inputs PECL_CLK, Single Ended - 1.825 - 0.8 2.42 VDD V -100 100 1000 µA µA mV VDD0.6 V 0.4 V IOL = 20mA, Note 3 V IOH = -20mA, VDDC = 3.3V Note 3 All VDDC and VDD 300 VDD2.0 Max - All other inputs Output Low Voltage VOL Output High Voltage VOH 2.5 Quiescent Supply Current IDD - 1 2 mA Input Capacitance Cin - - 4 pF Note 1 Note 2 VDDC = 3.3V ±10%, VDD = 3.3V ±10%, TA = -40°°C to +85°°C Note 1: Inputs have pull-up resistors that effect input current, PECL_CLK# has a pull-down resistor. Note 2: The VCMR is the difference from the most positive side of the differential input signal. Normal operation is obtained when the “High” input is within the VCMR range and the input lies within the VPP specification. Note 3: Driving series or parallel terminated 50Ω (or 50Ω to VDD/2) transmission lines. Cypress Semiconductor Corporation 525 Los Coches St. Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571 http://www.cypress.com Document#: 38-07079 Rev. *A 06/18/2001 Page 3 of 7 B9948 3.3V, 160MHz, 1:12 Clock Distribution Buffer AC Parameters1 SYMBOL PARAMETER Fmax Maximum Input Frequency MIN Tpd PECL_CLK to Q Delay 2 2 2 TCLK to Q Delay FoutDC Output Duty Cycle TYP MAX 160 2,3 CONDITIONS MHz 4.0 - 8.0 4.4 - 8.9 TCYCLE/2 – 800 UNITS TCYCLE/2 + 800 ns ps Measured at VDDC/2 tpZL, tpZH Output enable time (all outputs) 2 10 ns tpLZ, tpHZ Output disable time (all outputs) 2 10 ns 350 ps 1.5 ns PECL_CLK to Q ns SYNC_OE to PECL_CLK Tskew 2,5 Output-to-Output Skew 6 Tskew (pp) Part to Part Skew Ts Setup Time Th Hold Time Tr / Tf Output Clocks Rise / Fall Time 2.0 2,4 1.0 TCLK to Q 0.0 2,4 SYNC_OE to TCLK ns 0.0 1.0 5 0.2 PECL_CLK to SYNC_OE TCLK to SYNC_OE 1.0 ns 0.8V to 2.0V VDDC = 3.3V +/- 10%, VDD = 3.3V +/- 10%, TA = -40°°C to +85°°C Note 1: Parameters are guaranteed by design and characterization. Not 100% tested in production. All parameters specified with loaded outputs. Note 2: Outputs driving 50Ω transmission lines. Note 3: 50% input duty cycle. Note 4: Setup and Hold times are relative to the falling edge of the input clock Note 5: Outputs loaded with 30pF each Note 6: Part to Part Skew at a given temperature and voltage Cypress Semiconductor Corporation 525 Los Coches St. Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571 http://www.cypress.com Document#: 38-07079 Rev. *A 06/18/2001 Page 4 of 7 B9948 3.3V, 160MHz, 1:12 Clock Distribution Buffer Output Enable/ Disable The B9948 features a control input to enable or disable the outputs. This data is latched on the falling edge of the input clock. When SYNC_OE is asserted low, the outputs are disabled in a low state. When SYNC_OE is set high, the outputs are enabled as shown in Figure 2. TCLK SYNC_OE Q Figure 2. SYNC_OE Timing Diagram Package Drawing and Dimensions 32 Pin TQFP Outline Dimensions INCHES SYMBOL MIN NOM MILLIMETERS MAX MIN NOM MAX A - - 0.047 - - 1.20 A1 0.002 - 0.006 0.05 - 0.15 A2 0.037 - 0.041 0.95 - 1.05 D - 0.354 - - 9.00 - D1 - 0.276 - - 7.00 - b 0.012 - 0.018 0.30 - 0.45 D D1 e 12° L A1 0.031 BSC 0.018 - 0.80 BSC 0.030 0.45 - 0.75 A L e Cypress Semiconductor Corporation 525 Los Coches St. Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571 http://www.cypress.com b Document#: 38-07079 Rev. *A 06/18/2001 Page 5 of 7 B9948 3.3V, 160MHz, 1:12 Clock Distribution Buffer Ordering Information Part Number Package Type Production Flow B9948CA 32 PIN TQFP Industrial, -40°C to +85°C Note: The ordering part number is formed by a combination of device number, device revision, package style, and screening as shown below. Marking: Example: Cypress B9948CA Date Code, Lot # B9948CA Package A = TQFP Revision Device Number Notice Cypress Semiconductor Corporation reserves the right to make changes to its products in order to improve design, performance or reliability. Cypress Semiconductor Corporation assumes no responsibility for the use of its products in life supporting and medical applications where the failure or malfunction of the product could cause failure of the life supporting and medical systems. Products are not authorized for use in such applications unless a written approval is requested by the manufacturer and an approval is given in writing by Cypress Semiconductor Corporation for the use of its products in the life supporting and medical applications. Cypress Semiconductor Corporation 525 Los Coches St. Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571 http://www.cypress.com Document#: 38-07079 Rev. *A 06/18/2001 Page 6 of 7 B9948 3.3V, 160MHz, 1:12 Clock Distribution Buffer Document Title: B9948 3.3V, 160 MHz, 1:12 Clock Distribution Buffer Document Number: 38-07079 Rev. ** *A ECN No. 107115 108060 Issue Date 06/06/01 07/03/01 Orig. of Change IKA NDP Cypress Semiconductor Corporation 525 Los Coches St. Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571 http://www.cypress.com Description of Change Convert from IMI to Cypress Changed Commercial to Industrial (See page 6) Document#: 38-07079 Rev. *A 06/18/2001 Page 7 of 7